[U-Boot] [PATCH] net: phy: aquantia: wait for phy init sequence to finish
Aquantia quad-phys may take longer to initialize. This commit adds a polling mechanism for a global alarm bit that tells if phy init sequence is completed.
Signed-off-by: Florin Chiculita florinlaurentiu.chiculita@nxp.com --- drivers/net/phy/aquantia.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 465ec2d..ae3112c 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -37,6 +37,9 @@ #define GLOBAL_FAULT 0xc850 #define GLOBAL_RSTATUS_1 0xc885
+#define GLOBAL_ALARM_1 0xcc00 +#define SYSTEM_READY_BIT 0x40 + #define GLOBAL_STANDARD_CONTROL 0x0 #define SOFT_RESET BIT(15) #define LOW_POWER BIT(11) @@ -258,6 +261,17 @@ int aquantia_config(struct phy_device *phydev) { u32 val, id, rstatus, fault; u32 reg_val1 = 0; + int num_retries = 5; + + /* check if the system is out of reset and init sequence completed. + * chip-wide reset for gen1 quad phys takes longer + */ + while (--num_retries) { + rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1); + if (rstatus & SYSTEM_READY_BIT) + break; + mdelay(10); + }
id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID); rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
On Mon, Oct 14, 2019 at 9:27 AM Florin Chiculita florinlaurentiu.chiculita@nxp.com wrote:
Aquantia quad-phys may take longer to initialize. This commit adds a polling mechanism for a global alarm bit that tells if phy init sequence is completed.
Signed-off-by: Florin Chiculita florinlaurentiu.chiculita@nxp.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
drivers/net/phy/aquantia.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 465ec2d..ae3112c 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -37,6 +37,9 @@ #define GLOBAL_FAULT 0xc850 #define GLOBAL_RSTATUS_1 0xc885
+#define GLOBAL_ALARM_1 0xcc00 +#define SYSTEM_READY_BIT 0x40
#define GLOBAL_STANDARD_CONTROL 0x0 #define SOFT_RESET BIT(15) #define LOW_POWER BIT(11) @@ -258,6 +261,17 @@ int aquantia_config(struct phy_device *phydev) { u32 val, id, rstatus, fault; u32 reg_val1 = 0;
int num_retries = 5;/* check if the system is out of reset and init sequence completed.
I'll be fixing up this comment format.
* chip-wide reset for gen1 quad phys takes longer*/while (--num_retries) {rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);if (rstatus & SYSTEM_READY_BIT)break;mdelay(10);} id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID); rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);-- 1.9.3
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