[U-Boot] [PATCH] powerpc/corenet_ds: Update DDR timing for single-rank DIMMs
Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed 800, 900, 1000, 1200, 1300MT/s.
Signed-off-by: York Sun yorksun@freescale.com --- board/freescale/corenet_ds/ddr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 4a53b8d..da284cd 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -139,8 +139,8 @@ static const struct board_specific_parameters udimm0[] = { {2, 1250, 4, 6, 0xff, 2, 0}, {2, 1350, 5, 7, 0xff, 2, 0}, {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1250, 4, 6, 0xff, 2, 0}, + {1, 1335, 4, 7, 0xff, 2, 0}, {1, 1666, 4, 8, 0xff, 2, 0}, {} };
P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet connector. It is necessary to use the same base address for correct LAW address. An offset is added for NOR flash.
Signed-off-by: York Sun yorksun@freescale.com --- include/configs/P2041RDB.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 7d69db3..8b9b0db 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -202,15 +202,21 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* Set the local bus clock 1/8 of platform clock */ #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
-#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ +/* + * This board doesn't have a promjet connector. + * However, it uses commone corenet board LAW and TLB. + * It is necessary to use the same start address with proper offset. + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull #else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif
#define CONFIG_SYS_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ + BR_PS_16 | BR_V) #define CONFIG_SYS_FLASH_OR_PRELIM \ ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) @@ -294,7 +300,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
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York Sun