Add a method for setting up the LPC device after it has been probed. This is needed because the device cannot fully init until other parts of the system are ready.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/lpc-uclass.c | 11 +++++++++++ include/lpc.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 include/lpc.h

diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c index c6e8f73..399e3db 100644 --- a/arch/x86/lib/lpc-uclass.c +++ b/arch/x86/lib/lpc-uclass.c @@ -7,10 +7,21 @@

#include <common.h> #include <dm.h> +#include <lpc.h> #include <dm/root.h>

DECLARE_GLOBAL_DATA_PTR;

+int lpc_init(struct udevice *dev) +{ + struct lpc_ops *ops = lpc_get_ops(dev); + + if (!ops->init) + return -ENOSYS; + + return ops->init(dev); +} + static int lpc_uclass_post_bind(struct udevice *bus) { /* diff --git a/include/lpc.h b/include/lpc.h new file mode 100644 index 0000000..9bd2c72 --- /dev/null +++ b/include/lpc.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __lpc_h +#define __lpc_h + +struct lpc_ops { + /** + * init() - set up the LPC device + * + * Complete any init needed to bring the LPC fully into operation. + */ + int (*init)(struct udevice *dev); +}; + +#define lpc_get_ops(dev) ((struct lpc_ops *)(dev)->driver->ops) + +/** + * lpc_init() - init a LPC + * + * Complete any init needed to bring the LPC fully into operation. + * + * @dev: LPC device to init + * @return 0 if OK, -ve on error + */ +int lpc_init(struct udevice *dev); + +#endif

This is often -96 (-EEPFNOSUPPORT) which indicates that the uclass is not compiled in. Display the error number to make this easier to spot.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/core/lists.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/core/lists.c b/drivers/core/lists.c index a1c9478..c4fc216 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -172,7 +172,8 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, dm_dbg(" - found match at '%s'\n", entry->name); ret = device_bind(parent, entry, name, NULL, offset, &dev); if (ret) { - dm_warn("Error binding driver '%s'\n", entry->name); + dm_warn("Error binding driver '%s': %d\n", entry->name, + ret); return ret; } else { dev->driver_data = id->data;

Add a compatible string to allow this to be specified in the device tree if needed.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/usb/host/ehci-pci.c | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index cda1c6d..4d77c61 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -137,6 +137,11 @@ static int ehci_pci_remove(struct udevice *dev) return 0; }

+static const struct udevice_id ehci_pci_ids[] = { + { .compatible = "ehci-pci" }, + { } +}; + U_BOOT_DRIVER(ehci_pci) = { .name = "ehci_pci", .id = UCLASS_USB,

Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/cpu.c | 9 --------- arch/x86/cpu/ivybridge/lpc.c | 32 ++++++++++++++++++++++++------- arch/x86/dts/chromebook_link.dts | 2 +- arch/x86/include/asm/arch-ivybridge/pch.h | 10 ---------- 4 files changed, 26 insertions(+), 27 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index fd7e1fc..73c9929 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -124,10 +124,8 @@ int arch_cpu_init(void)

int arch_cpu_init_dm(void) { - const void *blob = gd->fdt_blob; struct pci_controller *hose; struct udevice *bus, *dev; - int node; int ret;

post_code(0x70); @@ -145,13 +143,6 @@ int arch_cpu_init_dm(void) if (!dev) return -ENODEV;

- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); - if (node < 0) - return -ENOENT; - ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); - if (ret) - return ret; - enable_spi_prefetch(hose, PCH_LPC_DEV);

/* This is already done in start.S, but let's do it in C */ diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 04a7451..e6f25e1 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -463,7 +463,13 @@ static void pch_fixups(pci_dev_t dev) setbits_le32(RCB_REG(0x21a8), 0x3); }

-int lpc_early_init(const void *blob, int node, pci_dev_t dev) +/** + * lpc_early_init() - set up LPC serial ports and other early things + * + * @dev: LPC device + * @return 0 if OK, -ve on error + */ +static int lpc_early_init(struct udevice *dev) { struct reg_info { u32 base; @@ -472,17 +478,18 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) int count; int i;

- count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec", - (u32 *)values, sizeof(values) / sizeof(u32)); + count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, + "intel,gen-dec", (u32 *)values, + sizeof(values) / sizeof(u32)); if (count < 0) return -EINVAL;

/* Set COM1/COM2 decode range */ - x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010); + dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010);

/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ - x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN | - GAMEL_LPC_EN | COMA_LPC_EN); + dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + GAMEL_LPC_EN | COMA_LPC_EN);

/* Write all registers but use 0 if we run out of data */ count = count * sizeof(u32) / sizeof(values[0]); @@ -491,7 +498,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)

if (i < count) reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); - x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg); + dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg); }

return 0; @@ -570,6 +577,17 @@ void lpc_enable(pci_dev_t dev)

static int bd82x6x_lpc_probe(struct udevice *dev) { + int ret; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + ret = lpc_early_init(dev); + if (ret) { + debug("%s: lpc_early_init() failed\n", __func__); + return ret; + } + return 0; }

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 7a009db..144442d 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -193,7 +193,6 @@ #address-cells = <1>; #size-cells = <1>; gen-dec = <0x800 0xfc 0x900 0xfc>; - intel,gen-dec = <0x800 0xfc 0x900 0xfc>; intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b 0x80 0x80 0x80 0x80>; intel,gpi-routing = <0 0 0 0 0 0 0 2 @@ -224,6 +223,7 @@ #address-cells = <1>; #size-cells = <0>; u-boot,dm-pre-reloc; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; cros-ec@200 { compatible = "google,cros-ec"; reg = <0x204 1 0x200 1 0x880 0x80>; diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 21df083..73309be 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -463,14 +463,4 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); int lpc_init(struct pci_controller *hose, pci_dev_t dev); void lpc_enable(pci_dev_t dev);

-/** - * lpc_early_init() - set up LPC serial ports and other early things - * - * @blob: Device tree blob - * @node: Offset of LPC node - * @dev: PCH PCI device containing the LPC - * @return 0 if OK, -ve on error - */ -int lpc_early_init(const void *blob, int node, pci_dev_t dev); - #endif

Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/cpu.c | 43 ------------------------------------------- arch/x86/cpu/ivybridge/lpc.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 73c9929..5f4683c 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -30,26 +30,6 @@

DECLARE_GLOBAL_DATA_PTR;

-static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev) -{ - /* Enable port 80 POST on LPC */ - pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); - clrbits_le32(RCB_REG(GCS), 4); -} - -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev) -{ - u8 reg8; - - pci_hose_read_config_byte(hose, dev, 0xdc, &reg8); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_hose_write_config_byte(hose, dev, 0xdc, reg8); -} - static int set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; @@ -99,22 +79,6 @@ static int set_flex_ratio_to_tdp_nominal(void) return -EINVAL; }

-static void set_spi_speed(void) -{ - u32 fdod; - - /* Observe SPI Descriptor Component Section 0 */ - writel(0x1000, RCB_REG(SPI_DESC_COMP0)); - - /* Extract the1 Write/Erase SPI Frequency from descriptor */ - fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); - fdod >>= 24; - fdod &= 7; - - /* Set Software Sequence frequency to match */ - clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); -} - int arch_cpu_init(void) { post_code(POST_CPU_INIT); @@ -143,13 +107,6 @@ int arch_cpu_init_dm(void) if (!dev) return -ENODEV;

- enable_spi_prefetch(hose, PCH_LPC_DEV); - - /* This is already done in start.S, but let's do it in C */ - enable_port80_on_lpc(hose, PCH_LPC_DEV); - - set_spi_speed(); - /* * We should do as little as possible before the serial console is * up. Perhaps this should move to later. Our next lot of init diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index e6f25e1..b3cc32d 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -463,6 +463,42 @@ static void pch_fixups(pci_dev_t dev) setbits_le32(RCB_REG(0x21a8), 0x3); }

+/* + * Enable Prefetching and Caching. + */ +static void enable_spi_prefetch(struct udevice *pch) +{ + u8 reg8; + + dm_pci_read_config8(pch, 0xdc, &reg8); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + dm_pci_write_config8(pch, 0xdc, reg8); +} + +static void enable_port80_on_lpc(struct udevice *pch) +{ + /* Enable port 80 POST on LPC */ + dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + clrbits_le32(RCB_REG(GCS), 4); +} + +static void set_spi_speed(void) +{ + u32 fdod; + + /* Observe SPI Descriptor Component Section 0 */ + writel(0x1000, RCB_REG(SPI_DESC_COMP0)); + + /* Extract the1 Write/Erase SPI Frequency from descriptor */ + fdod = readl(RCB_REG(SPI_FREQ_WR_ERA)); + fdod >>= 24; + fdod &= 7; + + /* Set Software Sequence frequency to match */ + clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); +} + /** * lpc_early_init() - set up LPC serial ports and other early things * @@ -501,6 +537,13 @@ static int lpc_early_init(struct udevice *dev) dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg); }

+ enable_spi_prefetch(dev->parent); + + /* This is already done in start.S, but let's do it in C */ + enable_port80_on_lpc(dev->parent); + + set_spi_speed(); + return 0; }

Set up a PCH init() method where we will put init code. Rename the existing bd82x6x_init() to bd82x6x_init_extra().

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/bd82x6x.c | 8 +++++++- arch/x86/cpu/ivybridge/cpu.c | 11 +++++++++++ arch/x86/cpu/ivybridge/pci.c | 2 +- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 2 +- 4 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index be39bcd..fce6622 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -100,7 +100,7 @@ static int bd82x6x_probe(struct udevice *dev) return 0; }

-int bd82x6x_init(void) +int bd82x6x_init_extra(void) { const void *blob = gd->fdt_blob; int sata_node; @@ -125,7 +125,13 @@ static int bd82x6x_pch_get_version(struct udevice *dev) return 9; }

+static int bd82x6x_init(struct udevice *dev) +{ + return 0; +} + static const struct pch_ops bd82x6x_pch_ops = { + .init = bd82x6x_init, .get_version = bd82x6x_pch_get_version, };

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 5f4683c..c1f5ec9 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -15,6 +15,7 @@ #include <dm.h> #include <errno.h> #include <fdtdec.h> +#include <pch.h> #include <asm/cpu.h> #include <asm/io.h> #include <asm/lapic.h> @@ -211,6 +212,7 @@ int print_cpuinfo(void) { enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; char processor_name[CPU_MAX_NAME_LEN]; + struct udevice *dev; const char *name; uint32_t pm1_cnt; uint16_t pm1_sts; @@ -241,6 +243,15 @@ int print_cpuinfo(void) }

/* Early chipset init required before RAM init can work */ + ret = uclass_first_device(UCLASS_PCH, &dev); + if (ret) + return ret; + if (!dev) + return -ENODEV; + ret = pch_init(dev); + if (ret) + return ret; + sandybridge_early_init(SANDYBRIDGE_MOBILE);

/* Check PM1_STS[15] to see if we are waking from Sx */ diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c index 5e90f30..8af99b4 100644 --- a/arch/x86/cpu/ivybridge/pci.c +++ b/arch/x86/cpu/ivybridge/pci.c @@ -26,7 +26,7 @@ static int pci_ivybridge_probe(struct udevice *bus) if (!(gd->flags & GD_FLG_RELOC)) return 0; post_code(0x50); - bd82x6x_init(); + bd82x6x_init_extra(); post_code(0x51);

reg16 = 0xff; diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index fcdf6e2..d76cb8d 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -13,7 +13,7 @@ void bd82x6x_pci_init(pci_dev_t dev); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node); -int bd82x6x_init(void); +int bd82x6x_init_extra(void);

/** * struct x86_cpu_priv - Information about a single CPU

Add a uclass for the northbridge / SDRAM controller found on some older Intel chipsets.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/Makefile | 1 + arch/x86/lib/northbridge-uclass.c | 17 +++++++++++++++++ include/dm/uclass-id.h | 1 + 3 files changed, 19 insertions(+) create mode 100644 arch/x86/lib/northbridge-uclass.c

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 43792bc..d9fc296 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -19,6 +19,7 @@ obj-y += lpc-uclass.o obj-y += mpspec.o obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o obj-y += cmd_mtrr.o +obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o ifndef CONFIG_DM_PCI diff --git a/arch/x86/lib/northbridge-uclass.c b/arch/x86/lib/northbridge-uclass.c new file mode 100644 index 0000000..2ff3730 --- /dev/null +++ b/arch/x86/lib/northbridge-uclass.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/root.h> + +DECLARE_GLOBAL_DATA_PTR; + +UCLASS_DRIVER(northbridge) = { + .id = UCLASS_NORTHBRIDGE, + .name = "northbridge", +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index ef145af..4a6827b 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -46,6 +46,7 @@ enum uclass_id { UCLASS_MMC, /* SD / MMC card or chip */ UCLASS_MOD_EXP, /* RSA Mod Exp device */ UCLASS_MTD, /* Memory Technology Device (MTD) device */ + UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */ UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */

Add a driver with an empty probe function where we can move init code in follow-on patches.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/early_init.c | 18 ++++++++++++++++++ arch/x86/dts/chromebook_link.dts | 7 +++++++ 2 files changed, 25 insertions(+)

diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 9ca008e..945ae2d 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -8,6 +8,7 @@ */

#include <common.h> +#include <dm.h> #include <asm/io.h> #include <asm/pci.h> #include <asm/arch/pch.h> @@ -145,3 +146,20 @@ void sandybridge_early_init(int chipset_type)

sandybridge_setup_graphics(pch_dev, video_dev); } + +static int bd82x6x_northbridge_probe(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id bd82x6x_northbridge_ids[] = { + { .compatible = "intel,bd82x6x-northbridge" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { + .name = "bd82x6x_northbridge", + .id = UCLASS_NORTHBRIDGE, + .of_match = bd82x6x_northbridge_ids, + .probe = bd82x6x_northbridge_probe, +}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 144442d..ff19153 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -166,6 +166,13 @@ ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x1000 0x1000 0 0xefff>; + + northbridge@0,0 { + reg = <0x00000000 0 0 0 0>; + compatible = "intel,bd82x6x-northbridge"; + u-boot,dm-pre-reloc; + }; + sata { compatible = "intel,pantherpoint-ahci"; intel,sata-mode = "ahci";

Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/cpu.c | 2 ++ arch/x86/cpu/ivybridge/early_init.c | 33 +++++++++++++++++++-------------- 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index c1f5ec9..b7cdae1 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -243,6 +243,8 @@ int print_cpuinfo(void) }

/* Early chipset init required before RAM init can work */ + uclass_first_device(UCLASS_NORTHBRIDGE, &dev); + ret = uclass_first_device(UCLASS_PCH, &dev); if (ret) return ret; diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 945ae2d..c629f5b 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -123,20 +123,6 @@ void sandybridge_early_init(int chipset_type) pci_dev_t pch_dev = PCH_DEV; pci_dev_t video_dev = PCH_VIDEO_DEV; pci_dev_t lpc_dev = PCH_LPC_DEV; - u32 capid0_a; - u8 reg8; - - /* Device ID Override Enable should be done very early */ - capid0_a = x86_pci_read_config32(pch_dev, 0xe4); - if (capid0_a & (1 << 10)) { - reg8 = x86_pci_read_config8(pch_dev, 0xf3); - reg8 &= ~7; /* Clear 2:0 */ - - if (chipset_type == SANDYBRIDGE_MOBILE) - reg8 |= 1; /* Set bit 0 */ - - x86_pci_write_config8(pch_dev, 0xf3, reg8); - }

/* Setup all BARs required for early PCIe and raminit */ sandybridge_setup_bars(pch_dev, lpc_dev); @@ -149,6 +135,25 @@ void sandybridge_early_init(int chipset_type)

static int bd82x6x_northbridge_probe(struct udevice *dev) { + const int chipset_type = SANDYBRIDGE_MOBILE; + u32 capid0_a; + u8 reg8; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + /* Device ID Override Enable should be done very early */ + dm_pci_read_config32(dev, 0xe4, &capid0_a); + if (capid0_a & (1 << 10)) { + dm_pci_read_config8(dev, 0xf3, &reg8); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == SANDYBRIDGE_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + dm_pci_write_config8(dev, 0xf3, reg8); + } + return 0; }

Move more code into the northbridge probe() function.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/early_init.c | 47 +++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 23 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index c629f5b..029f5ef 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -14,7 +14,7 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h>

-static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev) +static void sandybridge_setup_lpc_bars(pci_dev_t lpc_dev) { /* Setting up Southbridge. In the northbridge code. */ debug("Setting up static southbridge registers\n"); @@ -26,30 +26,31 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev) debug("Disabling watchdog reboot\n"); setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ +}

+static void sandybridge_setup_northbridge_bars(struct udevice *dev) +{ /* Set up all hardcoded northbridge BARs */ debug("Setting up static registers\n"); - x86_pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1); - x86_pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - x86_pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1); - x86_pci_write_config32(pch_dev, MCHBAR + 4, - (0LL + DEFAULT_MCHBAR) >> 32); + dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); + dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); + dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); /* 64MB - busses 0-63 */ - x86_pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); - x86_pci_write_config32(pch_dev, PCIEXBAR + 4, - (0LL + DEFAULT_PCIEXBAR) >> 32); - x86_pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1); - x86_pci_write_config32(pch_dev, DMIBAR + 4, - (0LL + DEFAULT_DMIBAR) >> 32); + dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); + dm_pci_write_config32(dev, PCIEXBAR + 4, + (0LL + DEFAULT_PCIEXBAR) >> 32); + dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); + dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);

/* Set C0000-FFFFF to access RAM on both reads and writes */ - x86_pci_write_config8(pch_dev, PAM0, 0x30); - x86_pci_write_config8(pch_dev, PAM1, 0x33); - x86_pci_write_config8(pch_dev, PAM2, 0x33); - x86_pci_write_config8(pch_dev, PAM3, 0x33); - x86_pci_write_config8(pch_dev, PAM4, 0x33); - x86_pci_write_config8(pch_dev, PAM5, 0x33); - x86_pci_write_config8(pch_dev, PAM6, 0x33); + dm_pci_write_config8(dev, PAM0, 0x30); + dm_pci_write_config8(dev, PAM1, 0x33); + dm_pci_write_config8(dev, PAM2, 0x33); + dm_pci_write_config8(dev, PAM3, 0x33); + dm_pci_write_config8(dev, PAM4, 0x33); + dm_pci_write_config8(dev, PAM5, 0x33); + dm_pci_write_config8(dev, PAM6, 0x33); }

static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) @@ -122,10 +123,6 @@ void sandybridge_early_init(int chipset_type) { pci_dev_t pch_dev = PCH_DEV; pci_dev_t video_dev = PCH_VIDEO_DEV; - pci_dev_t lpc_dev = PCH_LPC_DEV; - - /* Setup all BARs required for early PCIe and raminit */ - sandybridge_setup_bars(pch_dev, lpc_dev);

/* Device Enable */ x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD); @@ -154,6 +151,10 @@ static int bd82x6x_northbridge_probe(struct udevice *dev) dm_pci_write_config8(dev, 0xf3, reg8); }

+ sandybridge_setup_lpc_bars(PCH_LPC_DEV); + + sandybridge_setup_northbridge_bars(dev); + return 0; }

In preparation for adding an init() method to the LPC uclass, rename this existing function so that it will not conflict.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/bd82x6x.c | 2 +- arch/x86/cpu/ivybridge/lpc.c | 2 +- arch/x86/include/asm/arch-ivybridge/pch.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index fce6622..2222fb5 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -69,7 +69,7 @@ static int bd82x6x_probe(struct udevice *dev)

hose = pci_bus_to_hose(0); lpc_enable(PCH_LPC_DEV); - lpc_init(hose, PCH_LPC_DEV); + lpc_init_extra(hose, PCH_LPC_DEV); sata_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PANTHERPOINT_AHCI); if (sata_node < 0) { diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index b3cc32d..f124de6 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -547,7 +547,7 @@ static int lpc_early_init(struct udevice *dev) return 0; }

-int lpc_init(struct pci_controller *hose, pci_dev_t dev) +int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev) { const void *blob = gd->fdt_blob; int node; diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 73309be..76d3c58 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -460,7 +460,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66

-int lpc_init(struct pci_controller *hose, pci_dev_t dev); +int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev); void lpc_enable(pci_dev_t dev);

#endif

Add an empty method for now. We will add more to it in future patches.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/cpu.c | 11 ++++++++++- arch/x86/cpu/ivybridge/lpc.c | 11 +++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index b7cdae1..276ae50 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -15,6 +15,7 @@ #include <dm.h> #include <errno.h> #include <fdtdec.h> +#include <lpc.h> #include <pch.h> #include <asm/cpu.h> #include <asm/io.h> @@ -212,7 +213,7 @@ int print_cpuinfo(void) { enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; char processor_name[CPU_MAX_NAME_LEN]; - struct udevice *dev; + struct udevice *dev, *lpc; const char *name; uint32_t pm1_cnt; uint16_t pm1_sts; @@ -254,6 +255,14 @@ int print_cpuinfo(void) if (ret) return ret;

+ ret = uclass_first_device(UCLASS_LPC, &lpc); + if (ret) + return ret; + if (!dev) + return -ENODEV; + ret = lpc_init(lpc); + if (ret) + return ret; sandybridge_early_init(SANDYBRIDGE_MOBILE);

/* Check PM1_STS[15] to see if we are waking from Sx */ diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index f124de6..dd7b788 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -10,6 +10,7 @@ #include <dm.h> #include <errno.h> #include <fdtdec.h> +#include <lpc.h> #include <rtc.h> #include <pci.h> #include <asm/acpi.h> @@ -618,6 +619,11 @@ void lpc_enable(pci_dev_t dev) setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); }

+static int bd82x6x_lpc_init(struct udevice *dev) +{ + return 0; +} + static int bd82x6x_lpc_probe(struct udevice *dev) { int ret; @@ -634,6 +640,10 @@ static int bd82x6x_lpc_probe(struct udevice *dev) return 0; }

+static struct lpc_ops bd82x6x_lpc_ops = { + .init = bd82x6x_lpc_init, +}; + static const struct udevice_id bd82x6x_lpc_ids[] = { { .compatible = "intel,bd82x6x-lpc" }, { } @@ -644,4 +654,5 @@ U_BOOT_DRIVER(bd82x6x_lpc_drv) = { .id = UCLASS_LPC, .of_match = bd82x6x_lpc_ids, .probe = bd82x6x_lpc_probe, + .ops = &bd82x6x_lpc_ops, };

We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/ivybridge/early_init.c | 80 ++----------------------------------- arch/x86/cpu/ivybridge/gma.c | 73 +++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 78 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 276ae50..8827c2c 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -263,7 +263,6 @@ int print_cpuinfo(void) ret = lpc_init(lpc); if (ret) return ret; - sandybridge_early_init(SANDYBRIDGE_MOBILE);

/* Check PM1_STS[15] to see if we are waking from Sx */ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 029f5ef..83ef7b7 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -53,83 +53,6 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev) dm_pci_write_config8(dev, PAM6, 0x33); }

-static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) -{ - u32 reg32; - u16 reg16; - u8 reg8; - - reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID); - switch (reg16) { - case 0x0102: /* GT1 Desktop */ - case 0x0106: /* GT1 Mobile */ - case 0x010a: /* GT1 Server */ - case 0x0112: /* GT2 Desktop */ - case 0x0116: /* GT2 Mobile */ - case 0x0122: /* GT2 Desktop >=1.3GHz */ - case 0x0126: /* GT2 Mobile >=1.3GHz */ - case 0x0156: /* IvyBridge */ - case 0x0166: /* IvyBridge */ - break; - default: - debug("Graphics not supported by this CPU/chipset\n"); - return; - } - - debug("Initialising Graphics\n"); - - /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ - reg16 = x86_pci_read_config16(pch_dev, GGC); - reg16 &= ~0x00f8; - reg16 |= 1 << 3; - /* Program GTT memory by setting GGC[9:8] = 2MB */ - reg16 &= ~0x0300; - reg16 |= 2 << 8; - /* Enable VGA decode */ - reg16 &= ~0x0002; - x86_pci_write_config16(pch_dev, GGC, reg16); - - /* Enable 256MB aperture */ - reg8 = x86_pci_read_config8(video_dev, MSAC); - reg8 &= ~0x06; - reg8 |= 0x02; - x86_pci_write_config8(video_dev, MSAC, reg8); - - /* Erratum workarounds */ - reg32 = readl(MCHBAR_REG(0x5f00)); - reg32 |= (1 << 9) | (1 << 10); - writel(reg32, MCHBAR_REG(0x5f00)); - - /* Enable SA Clock Gating */ - reg32 = readl(MCHBAR_REG(0x5f00)); - writel(reg32 | 1, MCHBAR_REG(0x5f00)); - - /* GPU RC6 workaround for sighting 366252 */ - reg32 = readl(MCHBAR_REG(0x5d14)); - reg32 |= (1 << 31); - writel(reg32, MCHBAR_REG(0x5d14)); - - /* VLW */ - reg32 = readl(MCHBAR_REG(0x6120)); - reg32 &= ~(1 << 0); - writel(reg32, MCHBAR_REG(0x6120)); - - reg32 = readl(MCHBAR_REG(0x5418)); - reg32 |= (1 << 4) | (1 << 5); - writel(reg32, MCHBAR_REG(0x5418)); -} - -void sandybridge_early_init(int chipset_type) -{ - pci_dev_t pch_dev = PCH_DEV; - pci_dev_t video_dev = PCH_VIDEO_DEV; - - /* Device Enable */ - x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD); - - sandybridge_setup_graphics(pch_dev, video_dev); -} - static int bd82x6x_northbridge_probe(struct udevice *dev) { const int chipset_type = SANDYBRIDGE_MOBILE; @@ -155,6 +78,9 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)

sandybridge_setup_northbridge_bars(dev);

+ /* Device Enable */ + dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); + return 0; }

diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 85a09c6..1748f7f 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -8,6 +8,7 @@

#include <common.h> #include <bios_emul.h> +#include <dm.h> #include <errno.h> #include <fdtdec.h> #include <pci_rom.h> @@ -728,16 +729,88 @@ static int int15_handler(void) return res; }

+void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev) +{ + u32 reg32; + u16 reg16; + u8 reg8; + + dm_pci_read_config16(video_dev, PCI_DEVICE_ID, &reg16); + switch (reg16) { + case 0x0102: /* GT1 Desktop */ + case 0x0106: /* GT1 Mobile */ + case 0x010a: /* GT1 Server */ + case 0x0112: /* GT2 Desktop */ + case 0x0116: /* GT2 Mobile */ + case 0x0122: /* GT2 Desktop >=1.3GHz */ + case 0x0126: /* GT2 Mobile >=1.3GHz */ + case 0x0156: /* IvyBridge */ + case 0x0166: /* IvyBridge */ + break; + default: + debug("Graphics not supported by this CPU/chipset\n"); + return; + } + + debug("Initialising Graphics\n"); + + /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + dm_pci_read_config16(dev, GGC, &reg16); + reg16 &= ~0x00f8; + reg16 |= 1 << 3; + /* Program GTT memory by setting GGC[9:8] = 2MB */ + reg16 &= ~0x0300; + reg16 |= 2 << 8; + /* Enable VGA decode */ + reg16 &= ~0x0002; + dm_pci_write_config16(dev, GGC, reg16); + + /* Enable 256MB aperture */ + dm_pci_read_config8(video_dev, MSAC, &reg8); + reg8 &= ~0x06; + reg8 |= 0x02; + dm_pci_write_config8(video_dev, MSAC, reg8); + + /* Erratum workarounds */ + reg32 = readl(MCHBAR_REG(0x5f00)); + reg32 |= (1 << 9) | (1 << 10); + writel(reg32, MCHBAR_REG(0x5f00)); + + /* Enable SA Clock Gating */ + reg32 = readl(MCHBAR_REG(0x5f00)); + writel(reg32 | 1, MCHBAR_REG(0x5f00)); + + /* GPU RC6 workaround for sighting 366252 */ + reg32 = readl(MCHBAR_REG(0x5d14)); + reg32 |= (1 << 31); + writel(reg32, MCHBAR_REG(0x5d14)); + + /* VLW */ + reg32 = readl(MCHBAR_REG(0x6120)); + reg32 &= ~(1 << 0); + writel(reg32, MCHBAR_REG(0x6120)); + + reg32 = readl(MCHBAR_REG(0x5418)); + reg32 |= (1 << 4) | (1 << 5); + writel(reg32, MCHBAR_REG(0x5418)); +} + int gma_func0_init(struct udevice *dev, const void *blob, int node) { #ifdef CONFIG_VIDEO ulong start; #endif + struct udevice *nbridge; void *gtt_bar; ulong base; u32 reg32; int ret;

+ ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge); + if (!nbridge) + return -ENODEV; + sandybridge_setup_graphics(nbridge, dev); + /* IGD needs to be Bus Master */ dm_pci_read_config32(dev, PCI_COMMAND, &reg32); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;

The watchdog can be reset later in the LPC init() call. Move it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/early_init.c | 16 ---------------- arch/x86/cpu/ivybridge/lpc.c | 12 ++++++++++++ 2 files changed, 12 insertions(+), 16 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 83ef7b7..5b16abc 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -14,20 +14,6 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h>

-static void sandybridge_setup_lpc_bars(pci_dev_t lpc_dev) -{ - /* Setting up Southbridge. In the northbridge code. */ - debug("Setting up static southbridge registers\n"); - x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); - - x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1); - x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ - - debug("Disabling watchdog reboot\n"); - setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ - outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ -} - static void sandybridge_setup_northbridge_bars(struct udevice *dev) { /* Set up all hardcoded northbridge BARs */ @@ -74,8 +60,6 @@ static int bd82x6x_northbridge_probe(struct udevice *dev) dm_pci_write_config8(dev, 0xf3, reg8); }

- sandybridge_setup_lpc_bars(PCH_LPC_DEV); - sandybridge_setup_northbridge_bars(dev);

/* Device Enable */ diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index dd7b788..a445b03 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -621,6 +621,18 @@ void lpc_enable(pci_dev_t dev)

static int bd82x6x_lpc_init(struct udevice *dev) { + /* Setting up Southbridge. In the northbridge code. */ + debug("Setting up static southbridge registers\n"); + dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1); + + /* Enable ACPI BAR */ + dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80); + + debug("Disabling watchdog reboot\n"); + setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ + outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + return 0; }

This init can happen in the driver also. Move it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/cpu.c | 4 ---- arch/x86/cpu/ivybridge/lpc.c | 3 +++ 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 8827c2c..849b058 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -300,10 +300,6 @@ int print_cpuinfo(void)

gd->arch.pei_boot_mode = boot_mode;

- /* TODO: Move this to the board or driver */ - x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10); - /* Print processor name */ name = cpu_get_name(processor_name); printf("CPU: %s\n", name); diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index a445b03..d24aac6 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -633,6 +633,9 @@ static int bd82x6x_lpc_init(struct udevice *dev) setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */

+ dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1); + dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10); + return 0; }

The existing ivybridge code predates the normal multi-core CPU init, and it is not used. Remove it and add CPU nodes to the device tree so that all four CPUs are set up. Also enable the 'cpu' command.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/model_206ax.c | 94 ++++++++++++++++-------------------- arch/x86/dts/chromebook_link.dts | 34 +++++++++++++ configs/chromebook_link_defconfig | 3 ++ 3 files changed, 79 insertions(+), 52 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index fd7db97..9fa1226 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -8,10 +8,13 @@ */

#include <common.h> +#include <cpu.h> +#include <dm.h> #include <fdtdec.h> #include <malloc.h> #include <asm/acpi.h> #include <asm/cpu.h> +#include <asm/cpu_x86.h> #include <asm/lapic.h> #include <asm/msr.h> #include <asm/mtrr.h> @@ -400,55 +403,6 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif

-/* - * Initialize any extra cores/threads in this package. - */ -static int intel_cores_init(struct x86_cpu_priv *cpu) -{ - struct cpuid_result result; - unsigned threads_per_package, threads_per_core, i; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - debug("CPU: %u has %u cores, %u threads per core\n", - cpu->apic_id, threads_per_package / threads_per_core, - threads_per_core); - - for (i = 1; i < threads_per_package; ++i) { - struct x86_cpu_priv *new_cpu; - - new_cpu = calloc(1, sizeof(*new_cpu)); - if (!new_cpu) - return -ENOMEM; - - new_cpu->apic_id = cpu->apic_id + i; - - /* Update APIC ID if no hyperthreading */ - if (threads_per_core == 1) - new_cpu->apic_id <<= 1; - - debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id); - -#if 0 && CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* TODO(sjg@chromium.org): Start the new cpu */ - if (!start_cpu(new_cpu)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new_cpu->apic_id); - new_cpu->start_err = 1; - } -#endif - } - - return 0; -} - int model_206ax_init(struct x86_cpu_priv *cpu) { int ret; @@ -492,8 +446,10 @@ int model_206ax_init(struct x86_cpu_priv *cpu)

/* Thermal throttle activation offset */ ret = configure_thermal_target(); - if (ret) + if (ret) { + debug("Cannot set thermal target\n"); return ret; + }

/* Enable Direct Cache Access */ configure_dca_cap(); @@ -507,8 +463,42 @@ int model_206ax_init(struct x86_cpu_priv *cpu) /* Enable Turbo */ turbo_enable();

- /* Start up extra cores */ - intel_cores_init(cpu); + return 0; +} + +static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info) +{ + info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU; + + return 0; +} + +static int model_206ax_get_count(struct udevice *dev) +{ + return 4; +}

+static int cpu_x86_model_206ax_probe(struct udevice *dev) +{ return 0; } + +static const struct cpu_ops cpu_x86_model_206ax_ops = { + .get_desc = cpu_x86_get_desc, + .get_info = model_206ax_get_info, + .get_count = model_206ax_get_count, +}; + +static const struct udevice_id cpu_x86_model_206ax_ids[] = { + { .compatible = "intel,core-gen3" }, + { } +}; + +U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = { + .name = "cpu_x86_model_206ax", + .id = UCLASS_CPU, + .of_match = cpu_x86_model_206ax_ids, + .bind = cpu_x86_bind, + .probe = cpu_x86_model_206ax_probe, + .ops = &cpu_x86_model_206ax_ops, +}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index ff19153..1df2e69 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -18,6 +18,40 @@ silent_console = <0>; };

+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <1>; + intel,apic-id = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <2>; + intel,apic-id = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <3>; + intel,apic-id = <3>; + }; + + }; + gpioa { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index dbfbb97..06e4ce6 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -5,7 +5,9 @@ CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK=y CONFIG_HAVE_MRC=y CONFIG_ENABLE_MRC_CACHE=y +CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y +CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -17,6 +19,7 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_OF_CONTROL=y +CONFIG_CPU=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y

Use the CPU driver's probe() method to perform the CPU init. This will happen automatically when the first CPU is probed.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/bd82x6x.c | 6 ------ arch/x86/cpu/ivybridge/model_206ax.c | 5 ++++- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 15 --------------- 3 files changed, 4 insertions(+), 22 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 2222fb5..cf30a3a 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -60,7 +60,6 @@ static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; struct pci_controller *hose; - struct x86_cpu_priv *cpu; int sata_node, gma_node; int ret;

@@ -80,11 +79,6 @@ static int bd82x6x_probe(struct udevice *dev) bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);

- cpu = calloc(1, sizeof(*cpu)); - if (!cpu) - return -ENOMEM; - model_206ax_init(cpu); - gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); if (gma_node < 0) { debug("%s: Cannot find GMA node\n", __func__); diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 9fa1226..6ab6ede 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -403,7 +403,7 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif

-int model_206ax_init(struct x86_cpu_priv *cpu) +static int model_206ax_init(void) { int ret;

@@ -480,6 +480,9 @@ static int model_206ax_get_count(struct udevice *dev)

static int cpu_x86_model_206ax_probe(struct udevice *dev) { + if (dev->seq == 0) + model_206ax_init(); + return 0; }

diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index d76cb8d..fc7fc6d 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -15,19 +15,4 @@ void bd82x6x_usb_xhci_init(pci_dev_t dev); int gma_func0_init(struct udevice *dev, const void *blob, int node); int bd82x6x_init_extra(void);

-/** - * struct x86_cpu_priv - Information about a single CPU - * - * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is - * just a number representing the CPU core - * - * TODO: Move this to driver model once lifecycle is understood - */ -struct x86_cpu_priv { - int apic_id; - int start_err; -}; - -int model_206ax_init(struct x86_cpu_priv *cpu); - #endif

This uses a non-existent node at present. It should use the first CPU node. The referenced property does not exist (the correct value is the default of 0), but this allows the follow-on init to complete.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/model_206ax.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 6ab6ede..a217954 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -283,18 +283,13 @@ static void configure_c_states(void) msr_write(MSR_PP1_CURRENT_CONFIG, msr); }

-static int configure_thermal_target(void) +static int configure_thermal_target(struct udevice *dev) { int tcc_offset; msr_t msr; - int node;

- /* Find pointer to CPU configuration */ - node = fdtdec_next_compatible(gd->fdt_blob, 0, - COMPAT_INTEL_MODEL_206AX); - if (node < 0) - return -ENOENT; - tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0); + tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "tcc-offset", + 0);

/* Set TCC activaiton offset if supported */ msr = msr_read(MSR_PLATFORM_INFO); @@ -403,7 +398,7 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif

-static int model_206ax_init(void) +static int model_206ax_init(struct udevice *dev) { int ret;

@@ -445,7 +440,7 @@ static int model_206ax_init(void) configure_misc();

/* Thermal throttle activation offset */ - ret = configure_thermal_target(); + ret = configure_thermal_target(dev); if (ret) { debug("Cannot set thermal target\n"); return ret; @@ -468,6 +463,10 @@ static int model_206ax_init(void)

static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info) { + msr_t msr; + + msr = msr_read(IA32_PERF_CTL); + info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000; info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;

return 0; @@ -481,7 +480,7 @@ static int model_206ax_get_count(struct udevice *dev) static int cpu_x86_model_206ax_probe(struct udevice *dev) { if (dev->seq == 0) - model_206ax_init(); + model_206ax_init(dev);

return 0; }

This is not used and MTRRs are set up elsewhere now. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/model_206ax.c | 10 ---------- 1 file changed, 10 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index a217954..9654600 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -412,16 +412,6 @@ static int model_206ax_init(struct udevice *dev) set_ehci_debug(0); #endif

- /* Setup MTRRs based on physical address size */ -#if 0 /* TODO: Implement this */ - struct cpuid_result cpuid_regs; - - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); - x86_mtrr_check(); -#endif - #if CONFIG_USBDEBUG set_ehci_debug(ehci_debug_addr); #endif

This code is now part of the northbridge driver, so move it into the same place.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/early_init.c | 81 ------------------------------------ arch/x86/cpu/ivybridge/northbridge.c | 67 +++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 82 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/early_init.c

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 0c7efae..bdbd3fa 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,7 +7,6 @@ obj-y += bd82x6x.o obj-y += car.o obj-y += cpu.o -obj-y += early_init.o obj-y += early_me.o obj-y += gma.o obj-y += lpc.o diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c deleted file mode 100644 index 5b16abc..0000000 --- a/arch/x86/cpu/ivybridge/early_init.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * From Coreboot - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> -#include <asm/arch/sandybridge.h> - -static void sandybridge_setup_northbridge_bars(struct udevice *dev) -{ - /* Set up all hardcoded northbridge BARs */ - debug("Setting up static registers\n"); - dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); - dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); - dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); - /* 64MB - busses 0-63 */ - dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); - dm_pci_write_config32(dev, PCIEXBAR + 4, - (0LL + DEFAULT_PCIEXBAR) >> 32); - dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); - dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); - - /* Set C0000-FFFFF to access RAM on both reads and writes */ - dm_pci_write_config8(dev, PAM0, 0x30); - dm_pci_write_config8(dev, PAM1, 0x33); - dm_pci_write_config8(dev, PAM2, 0x33); - dm_pci_write_config8(dev, PAM3, 0x33); - dm_pci_write_config8(dev, PAM4, 0x33); - dm_pci_write_config8(dev, PAM5, 0x33); - dm_pci_write_config8(dev, PAM6, 0x33); -} - -static int bd82x6x_northbridge_probe(struct udevice *dev) -{ - const int chipset_type = SANDYBRIDGE_MOBILE; - u32 capid0_a; - u8 reg8; - - if (gd->flags & GD_FLG_RELOC) - return 0; - - /* Device ID Override Enable should be done very early */ - dm_pci_read_config32(dev, 0xe4, &capid0_a); - if (capid0_a & (1 << 10)) { - dm_pci_read_config8(dev, 0xf3, &reg8); - reg8 &= ~7; /* Clear 2:0 */ - - if (chipset_type == SANDYBRIDGE_MOBILE) - reg8 |= 1; /* Set bit 0 */ - - dm_pci_write_config8(dev, 0xf3, reg8); - } - - sandybridge_setup_northbridge_bars(dev); - - /* Device Enable */ - dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); - - return 0; -} - -static const struct udevice_id bd82x6x_northbridge_ids[] = { - { .compatible = "intel,bd82x6x-northbridge" }, - { } -}; - -U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { - .name = "bd82x6x_northbridge", - .id = UCLASS_NORTHBRIDGE, - .of_match = bd82x6x_northbridge_ids, - .probe = bd82x6x_northbridge_probe, -}; diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index e95e60e..48c8cd7 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -8,6 +8,7 @@ */

#include <common.h> +#include <dm.h> #include <asm/msr.h> #include <asm/acpi.h> #include <asm/cpu.h> @@ -186,3 +187,69 @@ void northbridge_enable(pci_dev_t dev) } #endif } + +static void sandybridge_setup_northbridge_bars(struct udevice *dev) +{ + /* Set up all hardcoded northbridge BARs */ + debug("Setting up static registers\n"); + dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); + dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); + dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + /* 64MB - busses 0-63 */ + dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); + dm_pci_write_config32(dev, PCIEXBAR + 4, + (0LL + DEFAULT_PCIEXBAR) >> 32); + dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); + dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + dm_pci_write_config8(dev, PAM0, 0x30); + dm_pci_write_config8(dev, PAM1, 0x33); + dm_pci_write_config8(dev, PAM2, 0x33); + dm_pci_write_config8(dev, PAM3, 0x33); + dm_pci_write_config8(dev, PAM4, 0x33); + dm_pci_write_config8(dev, PAM5, 0x33); + dm_pci_write_config8(dev, PAM6, 0x33); +} + +static int bd82x6x_northbridge_probe(struct udevice *dev) +{ + const int chipset_type = SANDYBRIDGE_MOBILE; + u32 capid0_a; + u8 reg8; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + /* Device ID Override Enable should be done very early */ + dm_pci_read_config32(dev, 0xe4, &capid0_a); + if (capid0_a & (1 << 10)) { + dm_pci_read_config8(dev, 0xf3, &reg8); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == SANDYBRIDGE_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + dm_pci_write_config8(dev, 0xf3, reg8); + } + + sandybridge_setup_northbridge_bars(dev); + + /* Device Enable */ + dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); + + return 0; +} + +static const struct udevice_id bd82x6x_northbridge_ids[] = { + { .compatible = "intel,bd82x6x-northbridge" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { + .name = "bd82x6x_northbridge", + .id = UCLASS_NORTHBRIDGE, + .of_match = bd82x6x_northbridge_ids, + .probe = bd82x6x_northbridge_probe, +};

There are no other implementations of this function, and baords that need it can implement a CPU driver.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/cpu.c | 2 +- arch/x86/include/asm/u-boot-x86.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 1707993..3cbed17 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -683,7 +683,7 @@ static int x86_mp_init(void) } #endif

-__weak int x86_init_cpus(void) +static int x86_init_cpus(void) { #ifdef CONFIG_SMP debug("Init additional CPUs\n"); diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index dbf8e95..9c143ca 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -77,8 +77,6 @@ uint64_t timer_get_tsc(void);

void quick_ram_check(void);

-int x86_init_cpus(void); - #define PCI_VGA_RAM_IMAGE_START 0xc0000

#endif /* _U_BOOT_I386_H_ */

When the final MRC cache record is the same as the one we want to write, we skip writing since there is no point. This is normal behaviour.

Avoiding printing an error when this happens.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/mrccache.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 53a1259..67bace4 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -243,8 +243,12 @@ int mrccache_save(void) goto err_entry; data = (struct mrc_data_container *)gd->arch.mrc_output; ret = mrccache_update(sf, &entry, data); - if (!ret) + if (!ret) { debug("Saved MRC data with checksum %04x\n", data->checksum); + } else if (ret == -EEXIST) { + debug("MRC data is the same as last time, skipping save\n"); + ret = 0; + }

err_entry: if (ret)

These devices currently need to be inited early in boot. Once we have the init in the right places (with each device doing its own init and no problems with ordering) we should be able to remove this. For now it is needed to keep things working.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/cpu.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 3cbed17..35fa046 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -704,8 +704,20 @@ static int x86_init_cpus(void)

int cpu_init_r(void) { - if (ll_boot_init()) - return x86_init_cpus(); + struct udevice *dev; + int ret; + + if (!ll_boot_init()) + return 0; + + ret = x86_init_cpus(); + if (ret) + return ret; + + /* Set up the northbridge, PCH and LPC if available */ + uclass_first_device(UCLASS_NORTHBRIDGE, &dev); + uclass_first_device(UCLASS_PCH, &dev); + uclass_first_device(UCLASS_LPC, &dev);

return 0; }

Adjust this code to use the driver model PCI API. This is all called through lpc_init_extra().

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/lpc.c | 129 ++++++++++++++++++++++--------------------- 1 file changed, 66 insertions(+), 63 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index b94d9f7..739f453 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -25,13 +25,13 @@ #define ENABLE_ACPI_MODE_IN_COREBOOT 0 #define TEST_SMM_FLASH_LOCKDOWN 0

-static int pch_enable_apic(pci_dev_t dev) +static int pch_enable_apic(struct udevice *pch) { u32 reg32; int i;

/* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */ - x86_pci_write_config8(dev, ACPI_CNTL, 0x80); + dm_pci_write_config8(pch, ACPI_CNTL, 0x80);

writel(0, IO_APIC_INDEX); writel(1 << 25, IO_APIC_DATA); @@ -67,36 +67,36 @@ static int pch_enable_apic(pci_dev_t dev) return 0; }

-static void pch_enable_serial_irqs(pci_dev_t dev) +static void pch_enable_serial_irqs(struct udevice *pch) { u32 value;

/* Set packet length and toggle silent mode bit for one frame. */ value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0); #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE - x86_pci_write_config8(dev, SERIRQ_CNTL, value); + dm_pci_write_config8(pch, SERIRQ_CNTL, value); #else - x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6)); + dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6)); #endif }

-static int pch_pirq_init(const void *blob, int node, pci_dev_t dev) +static int pch_pirq_init(struct udevice *pch) { uint8_t route[8], *ptr;

- if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route, - sizeof(route))) + if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset, + "intel,pirq-routing", route, sizeof(route))) return -EINVAL; ptr = route; - x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++);

- x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++); - x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++); + dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++);

/* * TODO(sjg@chromium.org): U-Boot does not set up the interrupts @@ -105,26 +105,28 @@ static int pch_pirq_init(const void *blob, int node, pci_dev_t dev) return 0; }

-static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev) +static int pch_gpi_routing(struct udevice *pch) { u8 route[16]; u32 reg; int gpi;

- if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route, - sizeof(route))) + if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset, + "intel,gpi-routing", route, sizeof(route))) return -EINVAL;

for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++) reg |= route[gpi] << (gpi * 2);

- x86_pci_write_config32(dev, 0xb8, reg); + dm_pci_write_config32(pch, 0xb8, reg);

return 0; }

-static int pch_power_options(const void *blob, int node, pci_dev_t dev) +static int pch_power_options(struct udevice *pch) { + const void *blob = gd->fdt_blob; + int node = pch->of_offset; u8 reg8; u16 reg16, pmbase; u32 reg32; @@ -143,7 +145,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) */ pwr_on = MAINBOARD_POWER_ON;

- reg16 = x86_pci_read_config16(dev, GEN_PMCON_3); + dm_pci_read_config16(pch, GEN_PMCON_3, &reg16); reg16 &= 0xfffe; switch (pwr_on) { case MAINBOARD_POWER_OFF: @@ -170,7 +172,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)

reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */

- x86_pci_write_config16(dev, GEN_PMCON_3, reg16); + dm_pci_write_config16(pch, GEN_PMCON_3, reg16); debug("Set power %s after power failure.\n", state);

/* Set up NMI on errors. */ @@ -194,21 +196,22 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) outb(reg8, 0x70);

/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ - reg16 = x86_pci_read_config16(dev, GEN_PMCON_1); + dm_pci_read_config16(pch, GEN_PMCON_1, &reg16); reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ #if DEBUG_PERIODIC_SMIS /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */ reg16 |= (3 << 0); /* Periodic SMI every 8s */ #endif - x86_pci_write_config16(dev, GEN_PMCON_1, reg16); + dm_pci_write_config16(pch, GEN_PMCON_1, reg16);

/* Set the board's GPI routing. */ - ret = pch_gpi_routing(blob, node, dev); + ret = pch_gpi_routing(pch); if (ret) return ret;

- pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe; + dm_pci_read_config16(pch, 0x40, &pmbase); + pmbase &= 0xfffe;

writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node, "intel,gpe0-enable", 0)); @@ -228,16 +231,16 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) return 0; }

-static void pch_rtc_init(pci_dev_t dev) +static void pch_rtc_init(struct udevice *pch) { int rtc_failed; u8 reg8;

- reg8 = x86_pci_read_config8(dev, GEN_PMCON_3); + dm_pci_read_config8(pch, GEN_PMCON_3, &reg8); rtc_failed = reg8 & RTC_BATTERY_DEAD; if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; - x86_pci_write_config8(dev, GEN_PMCON_3, reg8); + dm_pci_write_config8(pch, GEN_PMCON_3, reg8); } debug("rtc_failed = 0x%x\n", rtc_failed);

@@ -256,10 +259,10 @@ static void pch_rtc_init(pci_dev_t dev) }

/* CougarPoint PCH Power Management init */ -static void cpt_pm_init(pci_dev_t dev) +static void cpt_pm_init(struct udevice *pch) { debug("CougarPoint PM init\n"); - x86_pci_write_config8(dev, 0xa9, 0x47); + dm_pci_write_config8(pch, 0xa9, 0x47); setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));

setbits_le32(RCB_REG(0x228c), 1 << 0); @@ -300,10 +303,10 @@ static void cpt_pm_init(pci_dev_t dev) }

/* PantherPoint PCH Power Management init */ -static void ppt_pm_init(pci_dev_t dev) +static void ppt_pm_init(struct udevice *pch) { debug("PantherPoint PM init\n"); - x86_pci_write_config8(dev, 0xa9, 0x47); + dm_pci_write_config8(pch, 0xa9, 0x47); setbits_le32(RCB_REG(0x2238), 1 << 0); setbits_le32(RCB_REG(0x228c), 1 << 0); setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); @@ -350,16 +353,16 @@ static void enable_hpet(void) clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7); }

-static void enable_clock_gating(pci_dev_t dev) +static void enable_clock_gating(struct udevice *pch) { u32 reg32; u16 reg16;

setbits_le32(RCB_REG(0x2234), 0xf);

- reg16 = x86_pci_read_config16(dev, GEN_PMCON_1); + dm_pci_read_config16(pch, GEN_PMCON_1, &reg16); reg16 |= (1 << 2) | (1 << 11); - x86_pci_write_config16(dev, GEN_PMCON_1, reg16); + dm_pci_write_config16(pch, GEN_PMCON_1, reg16);

pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); @@ -439,24 +442,24 @@ static void pch_lock_smm(pci_dev_t dev) } #endif

-static void pch_disable_smm_only_flashing(pci_dev_t dev) +static void pch_disable_smm_only_flashing(struct udevice *pch) { u8 reg8;

debug("Enabling BIOS updates outside of SMM... "); - reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + dm_pci_read_config8(pch, 0xdc, &reg8); /* BIOS_CNTL */ reg8 &= ~(1 << 5); - x86_pci_write_config8(dev, 0xdc, reg8); + dm_pci_write_config8(pch, 0xdc, reg8); }

-static void pch_fixups(pci_dev_t dev) +static void pch_fixups(struct udevice *pch) { u8 gen_pmcon_2;

/* Indicate DRAM init done for MRC S3 to know it can resume */ - gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2); + dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2); gen_pmcon_2 |= (1 << 7); - x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); + dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2);

/* Enable DMI ASPM in the PCH */ clrbits_le32(RCB_REG(0x2304), 1 << 10); @@ -548,66 +551,66 @@ static int lpc_early_init(struct udevice *dev) return 0; }

-static int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev) +static int lpc_init_extra(struct udevice *dev) { + struct udevice *pch = dev->parent; const void *blob = gd->fdt_blob; int node;

debug("pch: lpc_init\n"); - pci_write_bar32(hose, dev, 0, 0); - pci_write_bar32(hose, dev, 1, 0xff800000); - pci_write_bar32(hose, dev, 2, 0xfec00000); - pci_write_bar32(hose, dev, 3, 0x800); - pci_write_bar32(hose, dev, 4, 0x900); + dm_pci_write_bar32(pch, 0, 0); + dm_pci_write_bar32(pch, 1, 0xff800000); + dm_pci_write_bar32(pch, 2, 0xfec00000); + dm_pci_write_bar32(pch, 3, 0x800); + dm_pci_write_bar32(pch, 4, 0x900);

node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); if (node < 0) return -ENOENT;

/* Set the value for PCI command register. */ - x86_pci_write_config16(dev, PCI_COMMAND, 0x000f); + dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);

/* IO APIC initialization. */ - pch_enable_apic(dev); + pch_enable_apic(pch);

- pch_enable_serial_irqs(dev); + pch_enable_serial_irqs(pch);

/* Setup the PIRQ. */ - pch_pirq_init(blob, node, dev); + pch_pirq_init(pch);

/* Setup power options. */ - pch_power_options(blob, node, dev); + pch_power_options(pch);

/* Initialize power management */ switch (pch_silicon_type()) { case PCH_TYPE_CPT: /* CougarPoint */ - cpt_pm_init(dev); + cpt_pm_init(pch); break; case PCH_TYPE_PPT: /* PantherPoint */ - ppt_pm_init(dev); + ppt_pm_init(pch); break; default: - printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev), - PCI_FUNC(dev)); + printf("Unknown Chipset: %s\n", pch->name); return -ENOSYS; }

/* Initialize the real time clock. */ - pch_rtc_init(dev); + pch_rtc_init(pch);

/* Initialize the High Precision Event Timers, if present. */ enable_hpet();

/* Initialize Clock Gating */ - enable_clock_gating(dev); + enable_clock_gating(pch);

- pch_disable_smm_only_flashing(dev); + pch_disable_smm_only_flashing(pch);

#if CONFIG_HAVE_SMI_HANDLER pch_lock_smm(dev); #endif

- pch_fixups(dev); + pch_fixups(pch);

return 0; } @@ -654,7 +657,7 @@ static int bd82x6x_lpc_probe(struct udevice *dev) return 0; }

- return lpc_init_extra(pci_bus_to_hose(0), PCH_LPC_DEV); + return lpc_init_extra(dev); }

static struct lpc_ops bd82x6x_lpc_ops = {

Move these two boards to use driver model for USB.

Signed-off-by: Simon Glass sjg@chromium.org ---

configs/chromebook_link_defconfig | 2 ++ configs/chromebox_panther_defconfig | 2 ++ 2 files changed, 4 insertions(+)

diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 06e4ce6..f367f81 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -37,6 +37,8 @@ CONFIG_SYS_NS16550=y CONFIG_ICH_SPI=y CONFIG_TIMER=y CONFIG_TPM_TIS_LPC=y +CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index ed4428f..4b78292 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -29,6 +29,8 @@ CONFIG_SYS_NS16550=y CONFIG_ICH_SPI=y CONFIG_TIMER=y CONFIG_TPM_TIS_LPC=y +CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y

This is used on most Intel platforms. We don't have a driver for it yet, but add a stub to handle the init. For now this targets ivybridge so we may want to add a device tree binding and generalise it when other platforms are supported.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/i2c/Kconfig | 7 +++++++ drivers/i2c/Makefile | 1 + drivers/i2c/intel_i2c.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100644 drivers/i2c/intel_i2c.c

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 14adda2..fe98557 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -58,6 +58,13 @@ config DM_I2C_GPIO bindings are supported. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt

+config SYS_I2C_INTEL + bool "Intel I2C/SMBUS driver" + depends on DM_I2C + help + Add support for the Intel SMBUS driver. So far this driver is just + a stub which perhaps some basic init. + config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" depends on DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 811ad9b..a2a956a 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o +obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c new file mode 100644 index 0000000..1082d1a --- /dev/null +++ b/drivers/i2c/intel_i2c.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <asm/io.h> + +int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + return -ENOSYS; +} + +int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, uint chip_flags) +{ + return -ENOSYS; +} + +int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + return 0; +} + +static int intel_i2c_probe(struct udevice *dev) +{ + return 0; +} + +static const struct dm_i2c_ops intel_i2c_ops = { + .xfer = intel_i2c_xfer, + .probe_chip = intel_i2c_probe_chip, + .set_bus_speed = intel_i2c_set_bus_speed, +}; + +static const struct udevice_id intel_i2c_ids[] = { + { .compatible = "intel,ich-i2c" }, + { } +}; + +U_BOOT_DRIVER(intel_i2c) = { + .name = "i2c_intel", + .id = UCLASS_I2C, + .of_match = intel_i2c_ids, + .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), + .ops = &intel_i2c_ops, + .probe = intel_i2c_probe, +};

Convert the top part of the DRAM init to use the driver model PCI API. Further work will complete the transformation.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/sdram.c | 39 +++++++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 4372a5c..5c1b788 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -495,8 +495,10 @@ static int add_memory_area(struct memory_info *info, * * This is a bit complicated since on x86 there are system memory holes all * over the place. We create a list of available memory blocks + * + * @dev: Northbridge device */ -static int sdram_find(pci_dev_t dev) +static int sdram_find(struct udevice *dev) { struct memory_info *info = &gd->arch.meminfo; uint32_t tseg_base, uma_size, tolud; @@ -505,6 +507,7 @@ static int sdram_find(pci_dev_t dev) uint64_t uma_memory_size; unsigned long long tomk; uint16_t ggc; + u32 val;

/* Total Memory 2GB example: * @@ -533,24 +536,27 @@ static int sdram_find(pci_dev_t dev) */

/* Top of Upper Usable DRAM, including remap */ - touud = x86_pci_read_config32(dev, TOUUD+4); - touud <<= 32; - touud |= x86_pci_read_config32(dev, TOUUD); + dm_pci_read_config32(dev, TOUUD + 4, &val); + touud = (uint64_t)val << 32; + dm_pci_read_config32(dev, TOUUD, &val); + touud |= val;

/* Top of Lower Usable DRAM */ - tolud = x86_pci_read_config32(dev, TOLUD); + dm_pci_read_config32(dev, TOLUD, &tolud);

/* Top of Memory - does not account for any UMA */ - tom = x86_pci_read_config32(dev, 0xa4); - tom <<= 32; - tom |= x86_pci_read_config32(dev, 0xa0); + dm_pci_read_config32(dev, 0xa4, &val); + tom = (uint64_t)val << 32; + dm_pci_read_config32(dev, 0xa0, &val); + tom |= val;

debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);

/* ME UMA needs excluding if total memory <4GB */ - me_base = x86_pci_read_config32(dev, 0x74); - me_base <<= 32; - me_base |= x86_pci_read_config32(dev, 0x70); + dm_pci_read_config32(dev, 0x74, &val); + me_base = (uint64_t)val << 32; + dm_pci_read_config32(dev, 0x70, &val); + me_base |= val;

debug("MEBASE %llx\n", me_base);

@@ -568,7 +574,7 @@ static int sdram_find(pci_dev_t dev) }

/* Graphics memory comes next */ - ggc = x86_pci_read_config16(dev, GGC); + dm_pci_read_config16(dev, GGC, &ggc); if (!(ggc & 2)) { debug("IGD decoded, subtracting ");

@@ -588,7 +594,7 @@ static int sdram_find(pci_dev_t dev) }

/* Calculate TSEG size from its base which must be below GTT */ - tseg_base = x86_pci_read_config32(dev, 0xb8); + dm_pci_read_config32(dev, 0xb8, &tseg_base); uma_size = (uma_memory_base - tseg_base) >> 10; tomk -= uma_size; uma_memory_base = tomk * 1024ULL; @@ -723,7 +729,7 @@ int dram_init(void) { 0, 4, 0x0000 }, /* P13= Empty */ }, }; - pci_dev_t dev = PCI_BDF(0, 0, 0); + struct udevice *dev; int ret;

debug("Boot mode %d\n", gd->arch.pei_boot_mode); @@ -742,6 +748,11 @@ int dram_init(void)

post_code(POST_DRAM);

+ ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); + if (ret) + return ret; + if (!dev) + return -ENODEV; ret = sdram_find(dev); if (ret) return ret;

Convert this function to use the the driver model PCI API. We just need to pass in the northbridge device.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/sdram.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 5c1b788..6105cc0 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -283,9 +283,10 @@ static int recovery_mode_enabled(void) /** * Find the PEI executable in the ROM and execute it. * - * @param pei_data: configuration data for UEFI PEI reference code + * @dev: Northbridge device + * @pei_data: configuration data for UEFI PEI reference code */ -int sdram_initialise(struct pei_data *pei_data) +int sdram_initialise(struct udevice *dev, struct pei_data *pei_data) { unsigned version; const char *data; @@ -374,7 +375,7 @@ int sdram_initialise(struct pei_data *pei_data) * Send ME init done for SandyBridge here. This is done inside the * SystemAgent binary on IvyBridge */ - done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID); + dm_pci_read_config16(dev, PCI_DEVICE_ID, &done); done &= BASE_REV_MASK; if (BASE_REV_SNB == done) intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); @@ -732,12 +733,17 @@ int dram_init(void) struct udevice *dev; int ret;

+ ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); + if (ret) + return ret; + if (!dev) + return -ENODEV; debug("Boot mode %d\n", gd->arch.pei_boot_mode); debug("mrc_input %p\n", pei_data.mrc_input); pei_data.boot_mode = gd->arch.pei_boot_mode; ret = copy_spd(&pei_data); if (!ret) - ret = sdram_initialise(&pei_data); + ret = sdram_initialise(dev, &pei_data); if (ret) return ret;

@@ -748,11 +754,6 @@ int dram_init(void)

post_code(POST_DRAM);

- ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); - if (ret) - return ret; - if (!dev) - return -ENODEV; ret = sdram_find(dev); if (ret) return ret;

We will use a system controller to model the Intel Management Engine. Enable this for link.

Signed-off-by: Simon Glass sjg@chromium.org ---

configs/chromebook_link_defconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index daa958e..f44bef7 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CPU=y CONFIG_SYS_I2C_INTEL=y CONFIG_CMD_CROS_EC=y

SDRAM init needs access to the Northbridge controller and the Intel Management Engine device. Add the latter to the device tree and convert all of this code to driver model.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/early_me.c | 68 ++++++++++++++++++++------------ arch/x86/cpu/ivybridge/sdram.c | 20 ++++++---- arch/x86/dts/chromebook_link.dts | 6 +++ arch/x86/include/asm/arch-ivybridge/me.h | 45 ++++++++++++++++++--- 4 files changed, 101 insertions(+), 38 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index 711470f..612c910 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -7,6 +7,7 @@ */

#include <common.h> +#include <dm.h> #include <errno.h> #include <asm/pci.h> #include <asm/processor.h> @@ -25,33 +26,36 @@ static const char *const me_ack_values[] = { [ME_HFS_ACK_CONTINUE] = "Continue to boot" };

-static inline void pci_read_dword_ptr(void *ptr, int offset) +static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr, + int offset) { u32 dword;

- dword = x86_pci_read_config32(PCH_ME_DEV, offset); + dm_pci_read_config32(me_dev, offset, &dword); memcpy(ptr, &dword, sizeof(dword)); }

-static inline void pci_write_dword_ptr(void *ptr, int offset) +static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr, + int offset) { u32 dword = 0; + memcpy(&dword, ptr, sizeof(dword)); - x86_pci_write_config32(PCH_ME_DEV, offset, dword); + dm_pci_write_config32(me_dev, offset, dword); }

-void intel_early_me_status(void) +void intel_early_me_status(struct udevice *me_dev) { struct me_hfs hfs; struct me_gmes gmes;

- pci_read_dword_ptr(&hfs, PCI_ME_HFS); - pci_read_dword_ptr(&gmes, PCI_ME_GMES); + pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); + pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);

intel_me_status(&hfs, &gmes); }

-int intel_early_me_init(void) +int intel_early_me_init(struct udevice *me_dev) { int count; struct me_uma uma; @@ -61,7 +65,7 @@ int intel_early_me_init(void)

/* Wait for ME UMA SIZE VALID bit to be set */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&uma, PCI_ME_UMA); + pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA); if (uma.valid) break; udelay(ME_DELAY); @@ -72,7 +76,7 @@ int intel_early_me_init(void) }

/* Check for valid firmware */ - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); if (hfs.fpt_bad) { printf("WARNING: ME has bad firmware\n"); return -EBADF; @@ -83,11 +87,11 @@ int intel_early_me_init(void) return 0; }

-int intel_early_me_uma_size(void) +int intel_early_me_uma_size(struct udevice *me_dev) { struct me_uma uma;

- pci_read_dword_ptr(&uma, PCI_ME_UMA); + pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA); if (uma.valid) { debug("ME: Requested %uMB UMA\n", uma.size); return uma.size; @@ -97,11 +101,11 @@ int intel_early_me_uma_size(void) return -EINVAL; }

-static inline void set_global_reset(int enable) +static inline void set_global_reset(struct udevice *dev, int enable) { u32 etr3;

- etr3 = x86_pci_read_config32(PCH_LPC_DEV, ETR3); + dm_pci_read_config32(dev, ETR3, &etr3);

/* Clear CF9 Without Resume Well Reset Enable */ etr3 &= ~ETR3_CWORWRE; @@ -112,10 +116,11 @@ static inline void set_global_reset(int enable) else etr3 &= ~ETR3_CF9GR;

- x86_pci_write_config32(PCH_LPC_DEV, ETR3, etr3); + dm_pci_write_config32(dev, ETR3, etr3); }

-int intel_early_me_init_done(u8 status) +int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, + uint status) { int count; u32 mebase_l, mebase_h; @@ -126,8 +131,8 @@ int intel_early_me_init_done(u8 status) };

/* MEBASE from MESEG_BASE[35:20] */ - mebase_l = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L); - mebase_h = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H); + dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l); + dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h); mebase_h &= 0xf; did.uma_base = (mebase_l >> 20) | (mebase_h << 12);

@@ -135,25 +140,25 @@ int intel_early_me_init_done(u8 status) debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n", status, did.uma_base);

- pci_write_dword_ptr(&did, PCI_ME_H_GS); + pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);

/* Must wait for ME acknowledgement */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); if (hfs.bios_msg_ack) break; udelay(ME_DELAY); } if (!count) { printf("ERROR: ME failed to respond\n"); - return -1; + return -ETIMEDOUT; }

/* Return the requested BIOS action */ debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);

/* Check status after acknowledgement */ - intel_early_me_status(); + intel_early_me_status(me_dev);

switch (hfs.ack_data) { case ME_HFS_ACK_CONTINUE: @@ -161,17 +166,17 @@ int intel_early_me_init_done(u8 status) return 0; case ME_HFS_ACK_RESET: /* Non-power cycle reset */ - set_global_reset(0); + set_global_reset(dev, 0); reset_cpu(0); break; case ME_HFS_ACK_PWR_CYCLE: /* Power cycle reset */ - set_global_reset(0); + set_global_reset(dev, 0); x86_full_reset(); break; case ME_HFS_ACK_GBL_RESET: /* Global reset */ - set_global_reset(1); + set_global_reset(dev, 1); x86_full_reset(); break; case ME_HFS_ACK_S3: @@ -180,5 +185,16 @@ int intel_early_me_init_done(u8 status) break; }

- return -1; + return -EINVAL; } + +static const struct udevice_id ivybridge_syscon_ids[] = { + { .compatible = "intel,me", }, + { } +}; + +U_BOOT_DRIVER(syscon_intel_me) = { + .name = "intel_me_syscon", + .id = UCLASS_SYSCON, + .of_match = ivybridge_syscon_ids, +}; diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 6105cc0..696351b 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -286,7 +286,8 @@ static int recovery_mode_enabled(void) * @dev: Northbridge device * @pei_data: configuration data for UEFI PEI reference code */ -int sdram_initialise(struct udevice *dev, struct pei_data *pei_data) +int sdram_initialise(struct udevice *dev, struct udevice *me_dev, + struct pei_data *pei_data) { unsigned version; const char *data; @@ -296,10 +297,10 @@ int sdram_initialise(struct udevice *dev, struct pei_data *pei_data) report_platform_info();

/* Wait for ME to be ready */ - ret = intel_early_me_init(); + ret = intel_early_me_init(me_dev); if (ret) return ret; - ret = intel_early_me_uma_size(); + ret = intel_early_me_uma_size(me_dev); if (ret < 0) return ret;

@@ -378,9 +379,9 @@ int sdram_initialise(struct udevice *dev, struct pei_data *pei_data) dm_pci_read_config16(dev, PCI_DEVICE_ID, &done); done &= BASE_REV_MASK; if (BASE_REV_SNB == done) - intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); + intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS); else - intel_early_me_status(); + intel_early_me_status(me_dev);

post_system_agent_init(pei_data); report_memory_config(); @@ -730,7 +731,7 @@ int dram_init(void) { 0, 4, 0x0000 }, /* P13= Empty */ }, }; - struct udevice *dev; + struct udevice *dev, *me_dev; int ret;

ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev); @@ -738,12 +739,17 @@ int dram_init(void) return ret; if (!dev) return -ENODEV; + ret = uclass_first_device(UCLASS_SYSCON, &me_dev); + if (ret) + return ret; + if (!me_dev) + return -ENODEV; debug("Boot mode %d\n", gd->arch.pei_boot_mode); debug("mrc_input %p\n", pei_data.mrc_input); pei_data.boot_mode = gd->arch.pei_boot_mode; ret = copy_spd(&pei_data); if (!ret) - ret = sdram_initialise(dev, &pei_data); + ret = sdram_initialise(dev, me_dev, &pei_data); if (ret) return ret;

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index a94d9de..b54a545 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -220,6 +220,12 @@ intel,pch-backlight = <0x04000000>; };

+ me@16,0 { + reg = <0x0000b000 0 0 0 0>; + compatible = "intel,me"; + u-boot,dm-pre-reloc; + }; + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,bd82x6x", "intel,pch"; diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h index 3a0809d..eb1b73f 100644 --- a/arch/x86/include/asm/arch-ivybridge/me.h +++ b/arch/x86/include/asm/arch-ivybridge/me.h @@ -345,12 +345,47 @@ struct __packed me_fwcaps { u8 reserved[3]; };

-/* Defined in me_status.c for both romstage and ramstage */ +/** + * intel_me_status() - Check Intel Management Engine status + * + * struct hfs: Firmware status + * struct gmes: Management engine status + */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);

-void intel_early_me_status(void); -int intel_early_me_init(void); -int intel_early_me_uma_size(void); -int intel_early_me_init_done(u8 status); +/** + * intel_early_me_status() - Check early Management Engine Status + * + * @me_dev: Management engine PCI device + */ +void intel_early_me_status(struct udevice *me_dev); + +/** + * intel_early_me_init() - Early Intel Management Engine init + * + * @me_dev: Management engine PCI device + * @return 0 if OK, -ve on error + */ +int intel_early_me_init(struct udevice *me_dev); + +/** + * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine + * + * @me_dev: Management engine PCI device + * @return UMA size if OK, -EINVAL on error + */ +int intel_early_me_uma_size(struct udevice *me_dev); + +/** + * intel_early_me_init_done() - Complete Intel Management Engine init + * + * @dev: Northbridge device + * @me_dev: Management engine PCI device + * @status: Status result (ME_INIT_...) + * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT + * if ME did not respond + */ +int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, + uint status);

#endif

Convert these functions to use the driver model PCI API.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/report_platform.c | 11 ++++++----- arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c index 4493870..c78322a 100644 --- a/arch/x86/cpu/ivybridge/report_platform.c +++ b/arch/x86/cpu/ivybridge/report_platform.c @@ -10,6 +10,7 @@ #include <asm/cpu.h> #include <asm/pci.h> #include <asm/arch/pch.h> +#include <asm/arch/sandybridge.h>

static void report_cpu_info(void) { @@ -63,27 +64,27 @@ static struct { {0x1E5F, "NM70"}, };

-static void report_pch_info(void) +static void report_pch_info(struct udevice *dev) { const char *pch_type = "Unknown"; int i; u16 dev_id; uint8_t rev_id;

- dev_id = x86_pci_read_config16(PCH_LPC_DEV, 2); + dm_pci_read_config16(dev, 2, &dev_id); for (i = 0; i < ARRAY_SIZE(pch_table); i++) { if (pch_table[i].dev_id == dev_id) { pch_type = pch_table[i].dev_name; break; } } - rev_id = x86_pci_read_config8(PCH_LPC_DEV, 8); + dm_pci_read_config8(dev, 8, &rev_id); debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id, rev_id); }

-void report_platform_info(void) +void report_platform_info(struct udevice *dev) { report_cpu_info(); - report_pch_info(); + report_pch_info(dev); } diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 696351b..3e5be4e 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -294,7 +294,7 @@ int sdram_initialise(struct udevice *dev, struct udevice *me_dev, uint16_t done; int ret;

- report_platform_info(); + report_platform_info(dev);

/* Wait for ME to be ready */ ret = intel_early_me_init(me_dev); diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index af8a9f7..ce8d030 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -110,7 +110,7 @@

int bridge_silicon_revision(void);

-void report_platform_info(void); +void report_platform_info(struct udevice *dev);

void sandybridge_early_init(int chipset_type);

Convert this file to use the driver model PCI API.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/lpc.c | 10 ++++---- arch/x86/cpu/ivybridge/pch.c | 35 ++++++++++++++------------ arch/x86/cpu/ivybridge/sata.c | 21 +++++++++++----- arch/x86/include/asm/arch-ivybridge/pch.h | 42 +++++++++++++++++++++++++++---- 4 files changed, 76 insertions(+), 32 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 739f453..60c7b98 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -364,10 +364,10 @@ static void enable_clock_gating(struct udevice *pch) reg16 |= (1 << 2) | (1 << 11); dm_pci_write_config16(pch, GEN_PMCON_1, reg16);

- pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31)); + pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7)); + pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31)); + pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));

reg32 = readl(RCB_REG(CG)); reg32 |= (1 << 31); @@ -583,7 +583,7 @@ static int lpc_init_extra(struct udevice *dev) pch_power_options(pch);

/* Initialize power management */ - switch (pch_silicon_type()) { + switch (pch_silicon_type(pch)) { case PCH_TYPE_CPT: /* CougarPoint */ cpt_pm_init(pch); break; diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c index bbab646..c7ce408 100644 --- a/arch/x86/cpu/ivybridge/pch.c +++ b/arch/x86/cpu/ivybridge/pch.c @@ -14,32 +14,34 @@ static int pch_revision_id = -1; static int pch_type = -1;

-int pch_silicon_revision(void) +int pch_silicon_revision(struct udevice *dev) { - pci_dev_t dev; + u8 val;

- dev = PCH_LPC_DEV; + if (pch_revision_id < 0) { + dm_pci_read_config8(dev, PCI_REVISION_ID, &val); + pch_revision_id = val; + }

- if (pch_revision_id < 0) - pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID); return pch_revision_id; }

-int pch_silicon_type(void) +int pch_silicon_type(struct udevice *dev) { - pci_dev_t dev; + u8 val;

- dev = PCH_LPC_DEV; + if (pch_type < 0) { + dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); + pch_type = val; + }

- if (pch_type < 0) - pch_type = x86_pci_read_config8(dev, PCI_DEVICE_ID + 1); return pch_type; }

-int pch_silicon_supported(int type, int rev) +int pch_silicon_supported(struct udevice *dev, int type, int rev) { - int cur_type = pch_silicon_type(); - int cur_rev = pch_silicon_revision(); + int cur_type = pch_silicon_type(dev); + int cur_rev = pch_silicon_revision(dev);

switch (type) { case PCH_TYPE_CPT: @@ -78,7 +80,8 @@ static inline int iobp_poll(void) return 0; }

-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue) { u32 data;

@@ -86,7 +89,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) writel(address, RCB_REG(IOBPIRI));

/* READ OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) writel(IOBPS_RW_BX, RCB_REG(IOBPS)); else writel(IOBPS_READ_AX, RCB_REG(IOBPS)); @@ -109,7 +112,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) data |= orvalue;

/* WRITE OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) writel(IOBPS_RW_BX, RCB_REG(IOBPS)); else writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index bf8724c..f7fe27e 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -51,7 +51,7 @@ static void common_sata_init(struct udevice *dev, unsigned int port_map) dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); }

-static void bd82x6x_sata_init(struct udevice *dev) +static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch) { unsigned int port_map, speed_support, port_tx; const void *blob = gd->fdt_blob; @@ -181,11 +181,11 @@ static void bd82x6x_sata_init(struct udevice *dev) /* Set Gen3 Transmitter settings if needed */ port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); if (port_tx) - pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx); + pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);

port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0); if (port_tx) - pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx); + pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);

/* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00001600); @@ -210,8 +210,8 @@ static void bd82x6x_sata_init(struct udevice *dev) sir_write(dev, 0xc8, 0x0c0c0c0c); sir_write(dev, 0xd4, 0x10000000);

- pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); - pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); + pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000); + pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100); }

static void bd82x6x_sata_enable(struct udevice *dev) @@ -237,10 +237,19 @@ static void bd82x6x_sata_enable(struct udevice *dev)

static int bd82x6x_sata_probe(struct udevice *dev) { + struct udevice *pch; + int ret; + + ret = uclass_first_device(UCLASS_PCH, &pch); + if (ret) + return ret; + if (!pch) + return -ENODEV; + if (!(gd->flags & GD_FLG_RELOC)) bd82x6x_sata_enable(dev); else - bd82x6x_sata_init(dev); + bd82x6x_sata_init(dev, pch);

return 0; } diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index f5def1c..810f55b 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -30,11 +30,6 @@

#define SMBUS_IO_BASE 0x0400

-int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); - #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 @@ -460,4 +455,41 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66

+/** + * pch_silicon_revision() - Read silicon revision ID from the PCH + * + * @dev: PCH device + * @return silicon revision ID + */ +int pch_silicon_revision(struct udevice *dev); + +/** + * pch_silicon_revision() - Read silicon device ID from the PCH + * + * @dev: PCH device + * @return silicon device ID + */ +int pch_silicon_type(struct udevice *dev); + +/** + * pch_silicon_supported() - Check if a certain revision is supported + * + * @dev: PCH device + * @type: PCH type + * @rev: Minimum required resion + * @return 0 if not supported, 1 if supported + */ +int pch_silicon_supported(struct udevice *dev, int type, int rev); + +/** + * pch_pch_iobp_update() - Update a pch register + * + * @dev: PCH device + * @address: Address to update + * @andvalue: Value to AND with existing value + * @orvalue: Value to OR with existing value + */ +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue); + #endif

This code relates to the PCH, so we should move it into the same file.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/bd82x6x.c | 129 ++++++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/pch.c | 126 ----------------------------- arch/x86/include/asm/arch-ivybridge/pch.h | 18 ----- 4 files changed, 129 insertions(+), 145 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/pch.c

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 259a5df..7007d5f 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -14,7 +14,6 @@ obj-y += me_status.o obj-y += model_206ax.o obj-y += microcode_intel.o obj-y += northbridge.o -obj-y += pch.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 94c41ef..ff6d485 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -10,6 +10,7 @@ #include <fdtdec.h> #include <malloc.h> #include <pch.h> +#include <asm/io.h> #include <asm/lapic.h> #include <asm/pci.h> #include <asm/arch/bd82x6x.h> @@ -17,6 +18,134 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h>

+static int pch_revision_id = -1; +static int pch_type = -1; + +/** + * pch_silicon_revision() - Read silicon revision ID from the PCH + * + * @dev: PCH device + * @return silicon revision ID + */ +static int pch_silicon_revision(struct udevice *dev) +{ + u8 val; + + if (pch_revision_id < 0) { + dm_pci_read_config8(dev, PCI_REVISION_ID, &val); + pch_revision_id = val; + } + + return pch_revision_id; +} + +int pch_silicon_type(struct udevice *dev) +{ + u8 val; + + if (pch_type < 0) { + dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); + pch_type = val; + } + + return pch_type; +} + +/** + * pch_silicon_supported() - Check if a certain revision is supported + * + * @dev: PCH device + * @type: PCH type + * @rev: Minimum required resion + * @return 0 if not supported, 1 if supported + */ +static int pch_silicon_supported(struct udevice *dev, int type, int rev) +{ + int cur_type = pch_silicon_type(dev); + int cur_rev = pch_silicon_revision(dev); + + switch (type) { + case PCH_TYPE_CPT: + /* CougarPoint minimum revision */ + if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) + return 1; + /* PantherPoint any revision */ + if (cur_type == PCH_TYPE_PPT) + return 1; + break; + + case PCH_TYPE_PPT: + /* PantherPoint minimum revision */ + if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) + return 1; + break; + } + + return 0; +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned try = IOBP_RETRY; + u32 data; + + while (try--) { + data = readl(RCB_REG(IOBPS)); + if ((data & 1) == 0) + return 1; + udelay(10); + } + + printf("IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue) +{ + u32 data; + + /* Set the address */ + writel(address, RCB_REG(IOBPIRI)); + + /* READ OPCODE */ + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_READ_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = readl(RCB_REG(IOBPD)); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { + printf("IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Write IOBP data */ + writel(data, RCB_REG(IOBPD)); + if (!iobp_poll()) + return; +} + static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c deleted file mode 100644 index c7ce408..0000000 --- a/arch/x86/cpu/ivybridge/pch.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * From Coreboot - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> - -static int pch_revision_id = -1; -static int pch_type = -1; - -int pch_silicon_revision(struct udevice *dev) -{ - u8 val; - - if (pch_revision_id < 0) { - dm_pci_read_config8(dev, PCI_REVISION_ID, &val); - pch_revision_id = val; - } - - return pch_revision_id; -} - -int pch_silicon_type(struct udevice *dev) -{ - u8 val; - - if (pch_type < 0) { - dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); - pch_type = val; - } - - return pch_type; -} - -int pch_silicon_supported(struct udevice *dev, int type, int rev) -{ - int cur_type = pch_silicon_type(dev); - int cur_rev = pch_silicon_revision(dev); - - switch (type) { - case PCH_TYPE_CPT: - /* CougarPoint minimum revision */ - if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) - return 1; - /* PantherPoint any revision */ - if (cur_type == PCH_TYPE_PPT) - return 1; - break; - - case PCH_TYPE_PPT: - /* PantherPoint minimum revision */ - if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) - return 1; - break; - } - - return 0; -} - -#define IOBP_RETRY 1000 -static inline int iobp_poll(void) -{ - unsigned try = IOBP_RETRY; - u32 data; - - while (try--) { - data = readl(RCB_REG(IOBPS)); - if ((data & 1) == 0) - return 1; - udelay(10); - } - - printf("IOBP timeout\n"); - return 0; -} - -void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, - u32 orvalue) -{ - u32 data; - - /* Set the address */ - writel(address, RCB_REG(IOBPIRI)); - - /* READ OPCODE */ - if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) - writel(IOBPS_RW_BX, RCB_REG(IOBPS)); - else - writel(IOBPS_READ_AX, RCB_REG(IOBPS)); - if (!iobp_poll()) - return; - - /* Read IOBP data */ - data = readl(RCB_REG(IOBPD)); - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { - printf("IOBP read 0x%08x failed\n", address); - return; - } - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - /* WRITE OPCODE */ - if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) - writel(IOBPS_RW_BX, RCB_REG(IOBPS)); - else - writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); - if (!iobp_poll()) - return; - - /* Write IOBP data */ - writel(data, RCB_REG(IOBPD)); - if (!iobp_poll()) - return; -} diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 810f55b..ae8840f 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -456,14 +456,6 @@ #define TCO2_STS 0x66

/** - * pch_silicon_revision() - Read silicon revision ID from the PCH - * - * @dev: PCH device - * @return silicon revision ID - */ -int pch_silicon_revision(struct udevice *dev); - -/** * pch_silicon_revision() - Read silicon device ID from the PCH * * @dev: PCH device @@ -472,16 +464,6 @@ int pch_silicon_revision(struct udevice *dev); int pch_silicon_type(struct udevice *dev);

/** - * pch_silicon_supported() - Check if a certain revision is supported - * - * @dev: PCH device - * @type: PCH type - * @rev: Minimum required resion - * @return 0 if not supported, 1 if supported - */ -int pch_silicon_supported(struct udevice *dev, int type, int rev); - -/** * pch_pch_iobp_update() - Update a pch register * * @dev: PCH device

This function is called all over the place. Convert it use the driver model PCI API, and rationalise the calls.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/gma.c | 33 ++++++++-------- arch/x86/cpu/ivybridge/northbridge.c | 46 +++++++++++------------ arch/x86/include/asm/arch-ivybridge/sandybridge.h | 8 +++- 3 files changed, 45 insertions(+), 42 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index b94536c..f9b03f2 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -353,14 +353,13 @@ static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value) return 0; }

-static int gma_pm_init_pre_vbios(void *gtt_bar) +static int gma_pm_init_pre_vbios(void *gtt_bar, int rev) { u32 reg32;

- debug("GT Power Management Init, silicon = %#x\n", - bridge_silicon_revision()); + debug("GT Power Management Init, silicon = %#x\n", rev);

- if (bridge_silicon_revision() < IVB_STEP_C0) { + if (rev < IVB_STEP_C0) { /* 1: Enable force wake */ gtt_write(gtt_bar, 0xa18c, 0x00000001); gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0)); @@ -370,14 +369,14 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0)); }

- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ reg32 = gtt_read(gtt_bar, 0x42004); reg32 |= (1 << 14) | (1 << 15); gtt_write(gtt_bar, 0x42004, reg32); }

- if (bridge_silicon_revision() >= IVB_STEP_A0) { + if (rev >= IVB_STEP_A0) { /* Display Reset Acknowledge Settings */ reg32 = gtt_read(gtt_bar, 0x45010); reg32 |= (1 << 1) | (1 << 0); @@ -386,7 +385,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)

/* 2: Get GT SKU from GTT+0x911c[13] */ reg32 = gtt_read(gtt_bar, 0x911c); - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { if (reg32 & (1 << 13)) { debug("SNB GT1 Power Meter Weights\n"); gtt_write_powermeter(gtt_bar, snb_pm_gt1); @@ -435,13 +434,13 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) reg32 = gtt_read(gtt_bar, 0xa180); reg32 |= (1 << 26) | (1 << 31); /* (bit 20=1 for SNB step D1+ / IVB A0+) */ - if (bridge_silicon_revision() >= SNB_STEP_D1) + if (rev >= SNB_STEP_D1) reg32 |= (1 << 20); gtt_write(gtt_bar, 0xa180, reg32);

/* 6a: for SnB step D2+ only */ - if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && - (bridge_silicon_revision() >= SNB_STEP_D2)) { + if (((rev & BASE_REV_MASK) == BASE_REV_SNB) && + (rev >= SNB_STEP_D2)) { reg32 = gtt_read(gtt_bar, 0x9400); reg32 |= (1 << 7); gtt_write(gtt_bar, 0x9400, reg32); @@ -453,7 +452,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1)); }

- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { reg32 = gtt_read(gtt_bar, 0x907c); reg32 |= (1 << 16); gtt_write(gtt_bar, 0x907c, reg32); @@ -505,7 +504,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */

/* 11a: Enable Render Standby (RC6) */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { /* * IvyBridge should also support DeepRenderStandby. * @@ -539,14 +538,14 @@ static int gma_pm_init_pre_vbios(void *gtt_bar) return 0; }

-int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node) +int gma_pm_init_post_vbios(int rev, void *gtt_bar, const void *blob, int node) { u32 reg32, cycle_delay;

debug("GT Power Management Init (post VBIOS)\n");

/* 15: Deassert Force Wake */ - if (bridge_silicon_revision() < IVB_STEP_C0) { + if (rev < IVB_STEP_C0) { gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1); gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0)); } else { @@ -805,6 +804,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node) ulong base; u32 reg32; int ret; + int rev;

/* Enable PCH Display Port */ writew(0x0010, RCB_REG(DISPBDF)); @@ -813,6 +813,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node) ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge); if (!nbridge) return -ENODEV; + rev = bridge_silicon_revision(nbridge); sandybridge_setup_graphics(nbridge, dev);

/* IGD needs to be Bus Master */ @@ -827,7 +828,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)

gtt_bar = (void *)dm_pci_read_bar32(dev, 0); debug("GT bar %p\n", gtt_bar); - ret = gma_pm_init_pre_vbios(gtt_bar); + ret = gma_pm_init_pre_vbios(gtt_bar, rev); if (ret) return ret;

@@ -838,7 +839,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node) debug("BIOS ran in %lums\n", get_timer(start)); #endif /* Post VBIOS init */ - ret = gma_pm_init_post_vbios(gtt_bar, blob, node); + ret = gma_pm_init_post_vbios(rev, gtt_bar, blob, node); if (ret) return ret;

diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index ee09103..6e31d63 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -20,8 +20,6 @@ #include <asm/arch/model_206ax.h> #include <asm/arch/sandybridge.h>

-static int bridge_revision_id = -1; - static void bd82x6x_pci_init(struct udevice *dev) { u16 reg16; @@ -61,21 +59,17 @@ static void bd82x6x_pci_init(struct udevice *dev) dm_pci_write_config16(dev, SECSTS, reg16); }

-int bridge_silicon_revision(void) +int bridge_silicon_revision(struct udevice *dev) { - if (bridge_revision_id < 0) { - struct cpuid_result result; - uint8_t stepping, bridge_id; - pci_dev_t dev; - - result = cpuid(1); - stepping = result.eax & 0xf; - dev = PCI_BDF(0, 0, 0); - bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0; - bridge_revision_id = bridge_id | stepping; - } - - return bridge_revision_id; + struct cpuid_result result; + u16 bridge_id; + u8 stepping; + + result = cpuid(1); + stepping = result.eax & 0xf; + dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id); + bridge_id &= 0xf0; + return bridge_id | stepping; }

/* @@ -131,45 +125,45 @@ static void add_fixed_resources(struct udevice *dev, int index) } }

-static void northbridge_dmi_init(struct udevice *dev) +static void northbridge_dmi_init(struct udevice *dev, int rev) { /* Clear error status bits */ writel(0xffffffff, DMIBAR_REG(0x1c4)); writel(0xffffffff, DMIBAR_REG(0x1d0));

/* Steps prior to DMI ASPM */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), 1 << 21); }

setbits_le32(DMIBAR_REG(0x238), 1 << 29);

- if (bridge_silicon_revision() >= SNB_STEP_D0) { + if (rev >= SNB_STEP_D0) { setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); - } else if (bridge_silicon_revision() >= SNB_STEP_D1) { + } else if (rev >= SNB_STEP_D1) { clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); }

/* Enable ASPM on SNB link, should happen before PCH link */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) setbits_le32(DMIBAR_REG(0xd04), 1 << 4);

setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); }

-static void northbridge_init(struct udevice *dev) +static void northbridge_init(struct udevice *dev, int rev) { u32 bridge_type;

add_fixed_resources(dev, 6); - northbridge_dmi_init(dev); + northbridge_dmi_init(dev, rev);

bridge_type = readl(MCHBAR_REG(0x5f10)); bridge_type &= ~0xff;

- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { /* Enable Power Aware Interrupt Routing - fixed priority */ clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);

@@ -285,6 +279,7 @@ static int bd82x6x_northbridge_early_init(struct udevice *dev) static int bd82x6x_northbridge_probe(struct udevice *dev) { u16 reg16; + int rev;

if (!(gd->flags & GD_FLG_RELOC)) return bd82x6x_northbridge_early_init(dev); @@ -305,7 +300,8 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)

bd82x6x_pci_init(dev); northbridge_enable(dev); - northbridge_init(dev); + rev = bridge_silicon_revision(dev); + northbridge_init(dev, rev);

return 0; } diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index ce8d030..e9d3271 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -108,7 +108,13 @@

#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x)

-int bridge_silicon_revision(void); +/** + * bridge_silicon_revision() - Get the Northbridge revision + * + * @dev: Northbridge device + * @return revision ID (bits 7:4) and bridge ID (bits 3:0) + */ +int bridge_silicon_revision(struct udevice *dev);

void report_platform_info(struct udevice *dev);