[U-Boot] [PATCH 1/4] rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0
Required to successfully probe the ehci generic driver
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
drivers/clk/rockchip/clk_rk3328.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index a89e2ecc4a..5957a00402 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -745,10 +745,22 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) return -ENOENT; }
+static int rk3328_clk_enable(struct clk *clk) +{ + switch (clk->id) { + case HCLK_HOST0: + /* Required to successfully probe the ehci generic driver */ + return 0; + } + + return -ENOENT; +} + static struct clk_ops rk3328_clk_ops = { .get_rate = rk3328_clk_get_rate, .set_rate = rk3328_clk_set_rate, .set_parent = rk3328_clk_set_parent, + .enable = rk3328_clk_enable, };
static int rk3328_clk_probe(struct udevice *dev)
Rock64 has a USB3.0 port, enable the controller so that we can use it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index dbcce6ac64..21c2afca3c 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -32,3 +32,7 @@ &sdmmc { u-boot,dm-pre-reloc; }; + +&usb_host0_xhci { + status = "okay"; +};
Hi Kever,
I've just tested the series on my Rock64 and I see the following issue. An USB pen-drive is not discovered by `usb start' when attached to the USB3 (blue) port. Attaching to USB2 port works fine.
чт, 15 авг. 2019 г. в 11:14, Kever Yang kever.yang@rock-chips.com:
Rock64 has a USB3.0 port, enable the controller so that we can use it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index dbcce6ac64..21c2afca3c 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -32,3 +32,7 @@ &sdmmc { u-boot,dm-pre-reloc; };
+&usb_host0_xhci {
status = "okay";+};
2.17.1
Hi Matwey,
On 2019/8/17 下午10:15, Matwey V. Kornilov wrote:
Hi Kever,
I've just tested the series on my Rock64 and I see the following issue. An USB pen-drive is not discovered by `usb start' when attached to the USB3 (blue) port.
The USB3 is not working correctly by the default code, and it works after I enable some debug
option in xHCI, maybe some more delay is needed for XHCI? I have no idea for which part of the xHCI
driver is not work correct now.
Thanks,
- Kever
Attaching to USB2 port works fine.
чт, 15 авг. 2019 г. в 11:14, Kever Yang kever.yang@rock-chips.com:
Rock64 has a USB3.0 port, enable the controller so that we can use it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index dbcce6ac64..21c2afca3c 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -32,3 +32,7 @@ &sdmmc { u-boot,dm-pre-reloc; };
+&usb_host0_xhci {
status = "okay";+};
2.17.1
пн, 19 авг. 2019 г. в 03:35, Kever Yang kever.yang@rock-chips.com:
Hi Matwey,
On 2019/8/17 下午10:15, Matwey V. Kornilov wrote:
Hi Kever,
I've just tested the series on my Rock64 and I see the following issue. An USB pen-drive is not discovered by `usb start' when attached to the USB3 (blue) port.
The USB3 is not working correctly by the default code, and it works after I enable some debug
option in xHCI, maybe some more delay is needed for XHCI? I have no idea for which part of the xHCI
driver is not work correct now.
Ok, now it is clear.
Thanks,
- Kever
Attaching to USB2 port works fine.
чт, 15 авг. 2019 г. в 11:14, Kever Yang kever.yang@rock-chips.com:
Rock64 has a USB3.0 port, enable the controller so that we can use it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index dbcce6ac64..21c2afca3c 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -32,3 +32,7 @@ &sdmmc { u-boot,dm-pre-reloc; };
+&usb_host0_xhci {
status = "okay";+};
2.17.1
чт, 15 авг. 2019 г. в 11:14, Kever Yang kever.yang@rock-chips.com:
Rock64 has a USB3.0 port, enable the controller so that we can use it.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Tested-by: Matwey V. Kornilov matwey.kornilov@gmail.com
arch/arm/dts/rk3328-rock64-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index dbcce6ac64..21c2afca3c 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -32,3 +32,7 @@ &sdmmc { u-boot,dm-pre-reloc; };
+&usb_host0_xhci {
status = "okay";+};
2.17.1
Move all the nodes only shown in u-boot to -u-boot.dtsi to make rk3328.dtsi clean.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
arch/arm/dts/rk3328-evb-u-boot.dtsi | 31 +++----------- arch/arm/dts/rk3328-evb.dts | 5 --- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 33 ++------------- arch/arm/dts/rk3328-u-boot.dtsi | 58 ++++++++++++++++++++++++++ arch/arm/dts/rk3328.dtsi | 24 ----------- 5 files changed, 66 insertions(+), 85 deletions(-) create mode 100644 arch/arm/dts/rk3328-u-boot.dtsi
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 58ebf52b4b..4a827063c5 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -1,33 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2016-2019 Rockchip Electronics Co., Ltd */
+#include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr3-666.dtsi"
-/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -}; - -&cru { - u-boot,dm-pre-reloc; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; +&usb_host0_xhci { + vbus-supply = <&vcc5v0_host_xhci>; + status = "okay"; }; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index ec594a8452..a2ee838fcd 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -116,11 +116,6 @@ status = "okay"; };
-&usb_host0_xhci { - vbus-supply = <&vcc5v0_host_xhci>; - status = "okay"; -}; - &i2c1 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 21c2afca3c..1d441f7124 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -1,38 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2018 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd */
+#include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-1600.dtsi"
-/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -}; - -&cru { - u-boot,dm-pre-reloc; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - &usb_host0_xhci { status = "okay"; }; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi new file mode 100644 index 0000000000..ffbd657e31 --- /dev/null +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; + + dmc: dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3328-dmc"; + reg = <0x0 0xff400000 0x0 0x1000 + 0x0 0xff780000 0x0 0x3000 + 0x0 0xff100000 0x0 0x1000 + 0x0 0xff440000 0x0 0x1000 + 0x0 0xff720000 0x0 0x1000 + 0x0 0xff798000 0x0 0x1000>; + }; + + usb_host0_xhci: usb@ff600000 { + compatible = "rockchip,rk3328-xhci"; + reg = <0x0 0xff600000 0x0 0x100000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + snps,dis-enblslpm-quirk; + snps,phyif-utmi-bits = <16>; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-u2-susphy-quirk; + status = "disabled"; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; + clock-frequency = <24000000>; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index a080ae8d69..060c84e6c0 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -186,7 +186,6 @@ };
grf: syscon@ff100000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; reg = <0x0 0xff100000 0x0 0x1000>;
@@ -232,7 +231,6 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - clock-frequency = <24000000>; reg-shift = <2>; reg-io-width = <4>; dmas = <&dmac 6>, <&dmac 7>; @@ -351,17 +349,6 @@ status = "disabled"; };
- dmc: dmc { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3328-dmc"; - reg = <0x0 0xff400000 0x0 0x1000 - 0x0 0xff780000 0x0 0x3000 - 0x0 0xff100000 0x0 0x1000 - 0x0 0xff440000 0x0 0x1000 - 0x0 0xff720000 0x0 0x1000 - 0x0 0xff798000 0x0 0x1000>; - }; - cru: clock-controller@ff440000 { compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; reg = <0x0 0xff440000 0x0 0x1000>; @@ -512,17 +499,6 @@ status = "disabled"; };
- usb_host0_xhci: usb@ff600000 { - compatible = "rockchip,rk3328-xhci"; - reg = <0x0 0xff600000 0x0 0x100000>; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - snps,dis-enblslpm-quirk; - snps,phyif-utmi-bits = <16>; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-u2-susphy-quirk; - status = "disabled"; - }; - gic: interrupt-controller@ffb70000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;
чт, 15 авг. 2019 г. в 11:14, Kever Yang kever.yang@rock-chips.com:
Move all the nodes only shown in u-boot to -u-boot.dtsi to make rk3328.dtsi clean.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Tested-by: Matwey V. Kornilov matwey.kornilov@gmail.com
arch/arm/dts/rk3328-evb-u-boot.dtsi | 31 +++----------- arch/arm/dts/rk3328-evb.dts | 5 --- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 33 ++------------- arch/arm/dts/rk3328-u-boot.dtsi | 58 ++++++++++++++++++++++++++ arch/arm/dts/rk3328.dtsi | 24 ----------- 5 files changed, 66 insertions(+), 85 deletions(-) create mode 100644 arch/arm/dts/rk3328-u-boot.dtsi
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 58ebf52b4b..4a827063c5 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -1,33 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /*
- (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
- (C) Copyright 2016-2019 Rockchip Electronics Co., Ltd
+#include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr3-666.dtsi"
-/ {
aliases {mmc0 = &emmc;mmc1 = &sdmmc;};chosen {u-boot,spl-boot-order = &emmc, &sdmmc;};-};
-&cru {
u-boot,dm-pre-reloc;-};
-&uart2 {
u-boot,dm-pre-reloc;-};
-&emmc {
u-boot,dm-pre-reloc;-};
-&sdmmc {
u-boot,dm-pre-reloc;+&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;status = "okay";}; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index ec594a8452..a2ee838fcd 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -116,11 +116,6 @@ status = "okay"; };
-&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;status = "okay";-};
&i2c1 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 21c2afca3c..1d441f7124 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -1,38 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ /*
- (C) Copyright 2018 Rockchip Electronics Co., Ltd
- SPDX-License-Identifier: GPL-2.0+
*/
- (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+#include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-1600.dtsi"
-/ {
aliases {mmc0 = &emmc;mmc1 = &sdmmc;};chosen {u-boot,spl-boot-order = &emmc, &sdmmc;};-};
-&cru {
u-boot,dm-pre-reloc;-};
-&uart2 {
u-boot,dm-pre-reloc;-};
-&emmc {
u-boot,dm-pre-reloc;-};
-&sdmmc {
u-boot,dm-pre-reloc;-};
&usb_host0_xhci { status = "okay"; }; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi new file mode 100644 index 0000000000..ffbd657e31 --- /dev/null +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- (C) Copyright 2019 Rockchip Electronics Co., Ltd
- */
+/ {
aliases {mmc0 = &emmc;mmc1 = &sdmmc;};chosen {u-boot,spl-boot-order = &emmc, &sdmmc;};dmc: dmc {u-boot,dm-pre-reloc;compatible = "rockchip,rk3328-dmc";reg = <0x0 0xff400000 0x0 0x10000x0 0xff780000 0x0 0x30000x0 0xff100000 0x0 0x10000x0 0xff440000 0x0 0x10000x0 0xff720000 0x0 0x10000x0 0xff798000 0x0 0x1000>;};usb_host0_xhci: usb@ff600000 {compatible = "rockchip,rk3328-xhci";reg = <0x0 0xff600000 0x0 0x100000>;interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;snps,dis-enblslpm-quirk;snps,phyif-utmi-bits = <16>;snps,dis-u2-freeclk-exists-quirk;snps,dis-u2-susphy-quirk;status = "disabled";};+};
+&cru {
u-boot,dm-pre-reloc;+};
+&grf {
u-boot,dm-pre-reloc;+};
+&uart2 {
u-boot,dm-pre-reloc;clock-frequency = <24000000>;+};
+&emmc {
u-boot,dm-pre-reloc;+};
+&sdmmc {
u-boot,dm-pre-reloc;+}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index a080ae8d69..060c84e6c0 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -186,7 +186,6 @@ };
grf: syscon@ff100000 {
u-boot,dm-pre-reloc; compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; reg = <0x0 0xff100000 0x0 0x1000>;@@ -232,7 +231,6 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk";
clock-frequency = <24000000>; reg-shift = <2>; reg-io-width = <4>; dmas = <&dmac 6>, <&dmac 7>;@@ -351,17 +349,6 @@ status = "disabled"; };
dmc: dmc {u-boot,dm-pre-reloc;compatible = "rockchip,rk3328-dmc";reg = <0x0 0xff400000 0x0 0x10000x0 0xff780000 0x0 0x30000x0 0xff100000 0x0 0x10000x0 0xff440000 0x0 0x10000x0 0xff720000 0x0 0x10000x0 0xff798000 0x0 0x1000>;};cru: clock-controller@ff440000 { compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; reg = <0x0 0xff440000 0x0 0x1000>;@@ -512,17 +499,6 @@ status = "disabled"; };
usb_host0_xhci: usb@ff600000 {compatible = "rockchip,rk3328-xhci";reg = <0x0 0xff600000 0x0 0x100000>;interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;snps,dis-enblslpm-quirk;snps,phyif-utmi-bits = <16>;snps,dis-u2-freeclk-exists-quirk;snps,dis-u2-susphy-quirk;status = "disabled";};gic: interrupt-controller@ffb70000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;-- 2.17.1
According to rock64 schemetic, both VCC_HOST1_5V and VCC_HOST_5V are controlled by USB20_HOST_DRV(GPIO0A2), fix it so that we can get correct power supply for USB HOST ports.
Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
arch/arm/dts/rk3328-rock64.dts | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-)
diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index 7bcc53fcce..a78eb4ac6f 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -34,23 +34,10 @@
vcc_host_5v: vcc-host-5v-regulator { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_host_drv>; - regulator-name = "vcc_host_5v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host1_5v"; + regulator-name = "vcc_host_5v"; regulator-always-on; regulator-boot-on; vin-supply = <&vcc_sys>; @@ -244,12 +231,6 @@ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - - usb3 { - usb30_host_drv: usb30-host-drv { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; };
&sdmmc {
чт, 15 авг. 2019 г. в 11:14, Kever Yang kever.yang@rock-chips.com:
According to rock64 schemetic, both VCC_HOST1_5V and VCC_HOST_5V are controlled by USB20_HOST_DRV(GPIO0A2), fix it so that we can get correct power supply for USB HOST ports.
Signed-off-by: Kever Yang kever.yang@rock-chips.com
Tested-by: Matwey V. Kornilov matwey.kornilov@gmail.com
arch/arm/dts/rk3328-rock64.dts | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-)
diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index 7bcc53fcce..a78eb4ac6f 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -34,23 +34,10 @@
vcc_host_5v: vcc-host-5v-regulator { compatible = "regulator-fixed";
enable-active-high;gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&usb30_host_drv>;regulator-name = "vcc_host_5v";regulator-always-on;regulator-boot-on;vin-supply = <&vcc_sys>;};vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {compatible = "regulator-fixed";enable-active-high;gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";
regulator-name = "vcc_host_5v"; regulator-always-on; regulator-boot-on; vin-supply = <&vcc_sys>;@@ -244,12 +231,6 @@ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; };
usb3 {usb30_host_drv: usb30-host-drv {rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;};};};
&sdmmc {
2.17.1
participants (2)
-
Kever Yang -
Matwey V. Kornilov