Add missing L2 cache entry in dts to avoid warning during Linux kernel boot.

Signed-off-by: Loic Devulder ldevulder@suse.com --- arch/arm/dts/rk3328.dtsi | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 060c84e6c0..7334eb124d 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -38,7 +38,10 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; -// clocks = <&cru ARMCLK>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + dynamic-power-coefficient = <120>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; cpu1: cpu@1 { @@ -46,19 +49,39 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + dynamic-power-coefficient = <120>; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + dynamic-power-coefficient = <120>; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + dynamic-power-coefficient = <120>; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; + + l2: l2-cache0 { + compatible = "cache"; + }; + };

cpu0_opp_table: opp_table0 {

ROC-RK3328-CC is a board made by Firefly/Libre Computer based on rk3328 SoC: - 2 USB2.0 Host port - 1 USB3.0 Host port - 1 HDMI port - 2 10/100M eth port - 1GB or 2GB DDR4 - UART to USB debug port

This port is based on evb-rk3328 already available in U-Boot.

Signed-off-by: Loic Devulder ldevulder@suse.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3328-roc-cc-u-boot.dtsi | 16 ++ arch/arm/dts/rk3328-roc-cc.dts | 260 +++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3328/Kconfig | 1 - board/rockchip/evb_rk3328/MAINTAINERS | 6 + configs/roc-cc-rk3328_defconfig | 95 +++++++++ doc/README.rockchip | 9 +- 7 files changed, 384 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/rk3328-roc-cc-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-roc-cc.dts create mode 100644 configs/roc-cc-rk3328_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4fee5cc489..db4b987c4c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -104,7 +104,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \

dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ - rk3328-rock64.dtb + rk3328-rock64.dtb \ + rk3328-roc-cc.dtb

dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi new file mode 100644 index 0000000000..cf3452ea94 --- /dev/null +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd + */ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-ddr4-666.dtsi" +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&usb_host0_xhci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts new file mode 100644 index 0000000000..2bfb261bad --- /dev/null +++ b/arch/arm/dts/rk3328-roc-cc.dts @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Firefly ROC-RK3328-CC"; + compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + + chosen { + stdout-path = &uart2; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc3v3_sdmmc: sdmmc-pwren { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_otg: vcc5v0-otg-drv { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc5v0_otg"; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host_xhci: vcc5v0-host-xhci-drv { + status = "disabled"; //usb host xhci and usb otg use the same gpio to enable power + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc5v0_host_xhci"; + gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + }; +}; + +&saradc { + status = "okay"; +}; + +&uart2 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + status = "okay"; +}; + +&emmc { + u-boot,dm-pre-reloc; + bus-width = <8>; + cap-mmc-highspeed; + supports-emmc; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac2io { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb20_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb_host0_xhci { + vbus-supply = <&vcc5v0_host_xhci>; + status = "okay"; + maximum-speed = "high-speed"; +}; + +&i2c1 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + status = "okay"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + gpio-controller; + #gpio-cells = <2>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + + pwrkey { + status = "okay"; + }; + + led1 { + label = "standby"; + }; + + led2 { + label = "power"; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio1_d0 */ + }; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index d13a169022..7fc4af9a4d 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -40,5 +40,4 @@ config TPL_STACK default 0xff098000

source "board/rockchip/evb_rk3328/Kconfig" - endif diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index c661d2e06a..86aefc801a 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -10,3 +10,9 @@ M: Matwey V. Kornilov matwey.kornilov@gmail.com S: Maintained F: configs/rock64-rk3328_defconfig F: arch/arm/dts/rk3328-rock64-u-boot.dtsi + +ROC-RK3328-CC +M: Loic Devulder ldevulder@suse.com +S: Maintained +F: configs/roc-rk3328-cc_defconfig +F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig new file mode 100644 index 0000000000..2ea4616401 --- /dev/null +++ b/configs/roc-cc-rk3328_defconfig @@ -0,0 +1,95 @@ +CONFIG_SMBIOS_MANUFACTURER="firefly" +CONFIG_SMBIOS_PRODUCT_NAME="roc-rk3328-cc" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 9b699b9ae5..9aeee37900 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -52,12 +52,13 @@ Two RK3308 boards are supported: - EVB RK3308 - use evb-rk3308 configuration - ROC-CC-RK3308 - use roc-cc-rk3308 configuration

-Two RK3328 board are supported: +Three RK3328 boards are supported:

- - EVB RK3328 - use evb-rk3328_defconfig - - Pine64 Rock64 board - use rock64-rk3328_defconfig + - EVB RK3328 - use evb_rk3328 configuration + - Pine64 Rock64 board - use rock64-rk3328 configuration + - ROC-RK3328-CC - use roc-cc-rk3328 configuration

-Size RK3399 boards are supported (aarch64): +Six RK3399 boards are supported (aarch64):

- EBV RK3399 - use evb_rk3399 configuration - Firefly RK3399 - use the firefly_rk3399 configuration