Signed-off-by: Heiko Schocher hs@denx.de

---

Changes in v2: - add comment from Jagan Teki: - remove spi_init_f() from board file - remove CONFIG_SYS_SPI_WRITE_TOUT from board config file instead define a default in the spi driver -> new patch for v2

board/siemens/taurus/taurus.c | 18 ++++++++++++++++++ include/configs/taurus.h | 10 ++++++++++ 2 files changed, 28 insertions(+)

diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 673b302..76609c7 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -22,6 +22,8 @@ #include <asm/arch/gpio.h> #include <asm/arch/at91sam9_sdramc.h> #include <atmel_mci.h> +#include <asm/arch/at91_spi.h> +#include <spi.h>

#include <net.h> #include <netdev.h> @@ -127,6 +129,21 @@ int board_early_init_f(void) return 0; }

+int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1); +} + int board_init(void) { /* adress of boot parameters */ @@ -139,6 +156,7 @@ int board_init(void) #ifdef CONFIG_MACB taurus_macb_hw_init(); #endif + at91_spi0_hw_init(TAURUS_SPI_MASK);

return 0; } diff --git a/include/configs/taurus.h b/include/configs/taurus.h index aadf4cd..ba9496f 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -127,6 +127,16 @@ #define CONFIG_USB_STORAGE #endif

+/* SPI EEPROM */ +#define CONFIG_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_ATMEL_SPI +#define CONFIG_SPI_FLASH_STMICRO +#define TAURUS_SPI_MASK (1 << 4) +#define TAURUS_SPI_CS_PIN AT91_PIN_PA3 + /* load address */ #define CONFIG_SYS_LOAD_ADDR 0x22000000

- compile mpddrc ram init code also for AT91SAM9M10G45 based boards. - in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED in the cr configuration

Signed-off-by: Heiko Schocher hs@denx.de Reviewed-by: Andreas Bießmann andreas.devel@googlemail.com

---

Changes in v2: add Reviewed-by: Andreas Bießmann andreas.devel@googlemail.com

arch/arm/cpu/at91-common/Makefile | 6 +++++- arch/arm/cpu/at91-common/mpddrc.c | 11 ++++++++++- 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile index 5b97838..f62863a 100644 --- a/arch/arm/cpu/at91-common/Makefile +++ b/arch/arm/cpu/at91-common/Makefile @@ -9,4 +9,8 @@ #

obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o -obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o +ifneq ($(CONFIG_SPL_BUILD),) +obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o +obj-$(CONFIG_SAMA5D3) += mpddrc.o +obj-y += spl.o +endif diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c index 76668d2..602e71e 100644 --- a/arch/arm/cpu/at91-common/mpddrc.c +++ b/arch/arm/cpu/at91-common/mpddrc.c @@ -17,6 +17,15 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address) writel(0, ram_address); }

+static int ddr2_decodtype_is_seq(u32 cr) +{ +#if defined(CONFIG_SAMA5D3) + if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) + return 0; +#endif + return 1; +} + int ddr2_init(const unsigned int ram_address, const struct atmel_mpddr *mpddr_value) { @@ -25,7 +34,7 @@ int ddr2_init(const unsigned int ram_address,

/* Compute bank offset according to NC in configuration register */ ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; - if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)) + if (ddr2_decodtype_is_seq(mpddr_value->cr)) ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;

enable to boot only a raw u-boot.bin image from nand with the CONFIG_SPL_NAND_RAW_ONLY define. This option saves space on boards where spl space is low.

Signed-off-by: Heiko Schocher hs@denx.de Reviewed-by: Andreas Bießmann andreas.devel@googlemail.com

--- on the siemens taurus board, this option saved 0x14d bytes

Changes in v2: add Reviewed-by: Andreas Bießmann andreas.devel@googlemail.com

README | 4 ++++ common/spl/spl.c | 15 ++++++++++----- common/spl/spl_nand.c | 13 +++++++++++++ include/spl.h | 1 + 4 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/README b/README index 7b5538e..a34902b 100644 --- a/README +++ b/README @@ -3605,6 +3605,10 @@ FIT uImage format: Support for the MTD subsystem within SPL. Useful for environment on NAND support within SPL.

+ CONFIG_SPL_NAND_RAW_ONLY + Support to boot only raw u-boot.bin images. Use this only + if you need to save space. + CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT Set for the SPL on PPC mpc8xxx targets, support for drivers/ddr/fsl/libddr.o in SPL binary. diff --git a/common/spl/spl.c b/common/spl/spl.c index d85bab3..f01a21c 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -62,6 +62,15 @@ __weak void spl_board_prepare_for_linux(void) /* Nothing to do! */ }

+void spl_set_header_raw_uboot(void) +{ + spl_image.size = CONFIG_SYS_MONITOR_LEN; + spl_image.entry_point = CONFIG_SYS_UBOOT_START; + spl_image.load_addr = CONFIG_SYS_TEXT_BASE; + spl_image.os = IH_OS_U_BOOT; + spl_image.name = "U-Boot"; +} + void spl_parse_image_header(const struct image_header *header) { u32 header_size = sizeof(struct image_header); @@ -93,11 +102,7 @@ void spl_parse_image_header(const struct image_header *header) /* Signature not found - assume u-boot.bin */ debug("mkimage signature not found - ih_magic = %x\n", header->ih_magic); - spl_image.size = CONFIG_SYS_MONITOR_LEN; - spl_image.entry_point = CONFIG_SYS_UBOOT_START; - spl_image.load_addr = CONFIG_SYS_TEXT_BASE; - spl_image.os = IH_OS_U_BOOT; - spl_image.name = "U-Boot"; + spl_set_header_raw_uboot(); } }

diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 9b200bc..b7801cb 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -10,6 +10,18 @@ #include <asm/io.h> #include <nand.h>

+#if defined(CONFIG_SPL_NAND_RAW_ONLY) +void spl_nand_load_image(void) +{ + nand_init(); + + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (void *)CONFIG_SYS_NAND_U_BOOT_DST); + spl_set_header_raw_uboot(); + nand_deselect(); +} +#else void spl_nand_load_image(void) { struct image_header *header; @@ -82,3 +94,4 @@ void spl_nand_load_image(void) spl_image.size, (void *)spl_image.load_addr); nand_deselect(); } +#endif diff --git a/include/spl.h b/include/spl.h index 16b3566..b2e5bf7 100644 --- a/include/spl.h +++ b/include/spl.h @@ -35,6 +35,7 @@ extern struct spl_image_info spl_image; void preloader_console_init(void); u32 spl_boot_device(void); u32 spl_boot_mode(void); +void spl_set_header_raw_uboot(void); void spl_parse_image_header(const struct image_header *header); void spl_board_prepare_for_linux(void); void __noreturn jump_to_image_linux(void *arg);

erase one nand block in spl code. keep it simple, as size matters This is used on the upcoming taurus spl support.

Signed-off-by: Heiko Schocher hs@denx.de

---

Changes in v2: add comment from scott wood: - move nand_erase_one into "include/nand.h" and rename it to spl_nand_erase_one

drivers/mtd/nand/atmel_nand.c | 33 +++++++++++++++++++++++++++++++++ include/nand.h | 1 + 2 files changed, 34 insertions(+)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index d506e42..d6d6f85 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1274,6 +1274,39 @@ static int nand_read_page(int block, int page, void *dst)

return 0; } + +int spl_nand_erase_one(int block, int page) +{ + struct nand_chip *this = mtd.priv; + void (*hwctrl)(struct mtd_info *mtd, int cmd, + unsigned int ctrl) = this->cmd_ctrl; + int page_addr; + + if (nand_chip.select_chip) + nand_chip.select_chip(&mtd, 0); + + page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + /* Row address */ + hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE); + hwctrl(&mtd, ((page_addr >> 8) & 0xff), + NAND_CTRL_ALE | NAND_CTRL_CHANGE); +#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE + /* One more address cycle for devices > 128MiB */ + hwctrl(&mtd, (page_addr >> 16) & 0x0f, + NAND_CTRL_ALE | NAND_CTRL_CHANGE); +#endif + + hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + udelay(2000); + + while (!this->dev_ready(&mtd)) + ; + + nand_deselect(); + + return 0; +} #else static int nand_read_page(int block, int page, void *dst) { diff --git a/include/nand.h b/include/nand.h index fc735d1..15e31ab 100644 --- a/include/nand.h +++ b/include/nand.h @@ -167,3 +167,4 @@ __attribute__((noreturn)) void nand_boot(void); #define ENV_OFFSET_SIZE 8 int get_nand_env_oob(nand_info_t *nand, unsigned long *result); #endif +int spl_nand_erase_one(int block, int page);

device ready pin is signalling that the device is ready on state 1 not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c

Signed-off-by: Heiko Schocher hs@denx.de Reviewed-by: Andreas Bießmann andreas.devel@googlemail.com

---

Changes in v2: add Reviewed-by: Andreas Bießmann andreas.devel@googlemail.com

drivers/mtd/nand/atmel_nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index d6d6f85..3b6093a 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1188,7 +1188,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl;

- while (this->dev_ready(&mtd)) + while (!this->dev_ready(&mtd)) ;

if (cmd == NAND_CMD_READOOB) { @@ -1213,7 +1213,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

- while (this->dev_ready(&mtd)) + while (!this->dev_ready(&mtd)) ;

return 0; @@ -1353,7 +1353,7 @@ int at91_nand_wait_ready(struct mtd_info *mtd)

udelay(this->chip_delay);

- return 0; + return 1; }

int board_nand_init(struct nand_chip *nand)

add support for using spl code on at91sam9260 and at91sam9g45 based boards.

Signed-off-by: Heiko Schocher hs@denx.de ---

Changes in v2: None

arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c | 22 +++ arch/arm/cpu/arm926ejs/at91/clock.c | 60 +++++++ arch/arm/cpu/armv7/at91/clock.c | 27 +++ arch/arm/cpu/at91-common/Makefile | 1 + arch/arm/cpu/at91-common/sdram.c | 77 +++++++++ arch/arm/cpu/at91-common/spl.c | 185 +++++++++++++++------ arch/arm/include/asm/arch-at91/at91_common.h | 4 + arch/arm/include/asm/arch-at91/at91_pmc.h | 5 +- arch/arm/include/asm/arch-at91/at91sam9260.h | 1 + .../arm/include/asm/arch-at91/at91sam9260_matrix.h | 5 + arch/arm/include/asm/arch-at91/at91sam9_sdramc.h | 22 ++- 11 files changed, 359 insertions(+), 50 deletions(-) create mode 100644 arch/arm/cpu/at91-common/sdram.c

diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index cae4abc..7a7fd7d 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -8,8 +8,10 @@

#include <common.h> #include <asm/io.h> +#include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91sam9_sdramc.h> #include <asm/arch/gpio.h>

/* @@ -207,3 +209,23 @@ void at91_mci_hw_init(void) #endif } #endif + +void at91_sdram_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); + at91_set_a_periph(AT91_PIO_PORTC, 17, 0); + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); + at91_set_a_periph(AT91_PIO_PORTC, 25, 0); + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); + at91_set_a_periph(AT91_PIO_PORTC, 28, 0); + at91_set_a_periph(AT91_PIO_PORTC, 29, 0); + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); + at91_set_a_periph(AT91_PIO_PORTC, 31, 0); +} diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index 31315b5..f363982 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -187,3 +187,63 @@ int at91_clock_init(unsigned long main_clock)

return 0; } + +#if !defined(AT91_PLL_LOCK_TIMEOUT) +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#endif + +void at91_plla_init(u32 pllar) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + + writel(pllar, &pmc->pllar); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) { + timeout--; + if (timeout == 0) + break; + } +} +void at91_pllb_init(u32 pllbr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + + writel(pllbr, &pmc->pllbr); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) { + timeout--; + if (timeout == 0) + break; + } +} + +void at91_mck_init(u32 mckr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + u32 tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~(AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_MASK | + AT91_PMC_MCKR_CSS_MASK); + tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_MASK | + AT91_PMC_MCKR_CSS_MASK); + writel(tmp, &pmc->mckr); + + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) { + timeout--; + if (timeout == 0) + break; + } +} + +void at91_periph_clk_enable(int id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(1 << id, &pmc->pcer); +} diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c index 36ed4a6..363081a 100644 --- a/arch/arm/cpu/armv7/at91/clock.c +++ b/arch/arm/cpu/armv7/at91/clock.c @@ -111,6 +111,33 @@ int at91_clock_init(unsigned long main_clock) return 0; }

+void at91_plla_init(u32 pllar) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(pllar, &pmc->pllar); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) + ; +} + +void at91_mck_init(u32 mckr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~(AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_2); + tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_2); + writel(tmp, &pmc->mckr); + + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; +} + void at91_periph_clk_enable(int id) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile index f62863a..5bdfb6a 100644 --- a/arch/arm/cpu/at91-common/Makefile +++ b/arch/arm/cpu/at91-common/Makefile @@ -10,6 +10,7 @@

obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o ifneq ($(CONFIG_SPL_BUILD),) +obj-$(CONFIG_AT91SAM9G20) += sdram.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o obj-$(CONFIG_SAMA5D3) += mpddrc.o obj-y += spl.o diff --git a/arch/arm/cpu/at91-common/sdram.c b/arch/arm/cpu/at91-common/sdram.c new file mode 100644 index 0000000..5758b06 --- /dev/null +++ b/arch/arm/cpu/at91-common/sdram.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * (C) Copyright 2007-2008 + * Stelian Pop stelian@popies.net + * Lead Tech Design <www.leadtechdesign.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91sam9_sdramc.h> +#include <asm/arch/gpio.h> + +int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p) +{ + struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC; + unsigned int i; + + /* SDRAM feature must be in the configuration register */ + writel(p->cr, &reg->cr); + + /* The SDRAM memory type must be set in the Memory Device Register */ + writel(p->mdr, &reg->mdr); + + /* + * The minimum pause of 200 us is provided to precede any single + * toggle + */ + for (i = 0; i < 1000; i++) + ; + + /* A NOP command is issued to the SDRAM devices */ + writel(AT91_SDRAMC_MODE_NOP, &reg->mr); + writel(0x00000000, sdram_address); + + /* An All Banks Precharge command is issued to the SDRAM devices */ + writel(AT91_SDRAMC_MODE_PRECHARGE, &reg->mr); + writel(0x00000000, sdram_address); + + for (i = 0; i < 10000; i++) + ; + + /* Eight auto-refresh cycles are provided */ + for (i = 0; i < 8; i++) { + writel(AT91_SDRAMC_MODE_REFRESH, &reg->mr); + writel(0x00000001 + i, sdram_address + 4 + 4 * i); + } + + /* + * A Mode Register set (MRS) cyscle is issued to program the + * SDRAM parameters(TCSR, PASR, DS) + */ + writel(AT91_SDRAMC_MODE_LMR, &reg->mr); + writel(0xcafedede, sdram_address + 0x24); + + /* + * The application must go into Normal Mode, setting Mode + * to 0 in the Mode Register and perform a write access at + * any location in the SDRAM. + */ + writel(AT91_SDRAMC_MODE_NORMAL, &reg->mr); + writel(0x00000000, sdram_address); /* Perform Normal mode */ + + /* + * Write the refresh rate into the count field in the SDRAMC + * Refresh Timer Rgister. + */ + writel(p->tr, &reg->tr); + + return 0; +} diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c index 674a470..5c9a3ad 100644 --- a/arch/arm/cpu/at91-common/spl.c +++ b/arch/arm/cpu/at91-common/spl.c @@ -8,11 +8,18 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> +#if !defined(CONFIG_SAMA5D3) +#include <asm/arch/at91sam9_matrix.h> +#endif +#include <asm/arch/at91_pit.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> #include <asm/arch/at91_wdt.h> #include <asm/arch/clk.h> #include <spl.h>

+DECLARE_GLOBAL_DATA_PTR; + static void at91_disable_wdt(void) { struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; @@ -20,6 +27,33 @@ static void at91_disable_wdt(void) writel(AT91_WDT_MR_WDDIS, &wdt->mr); }

+u32 spl_boot_device(void) +{ +#ifdef CONFIG_SYS_USE_MMC + return BOOT_DEVICE_MMC1; +#elif CONFIG_SYS_USE_NANDFLASH + return BOOT_DEVICE_NAND; +#elif CONFIG_SYS_USE_SERIALFLASH + return BOOT_DEVICE_SPI; +#endif + return BOOT_DEVICE_NONE; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { +#ifdef CONFIG_SYS_USE_MMC + case BOOT_DEVICE_MMC1: + return MMCSD_MODE_FS; + break; +#endif + case BOOT_DEVICE_NONE: + default: + hang(); + } +} + +#if defined(CONFIG_SAMA5D3) static void switch_to_main_crystal_osc(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; @@ -57,77 +91,134 @@ static void switch_to_main_crystal_osc(void) writel(tmp, &pmc->mor); }

-void at91_plla_init(u32 pllar) +void s_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + switch_to_main_crystal_osc();

- writel(pllar, &pmc->pllar); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) - ; -} + /* disable watchdog */ + at91_disable_wdt();

-void at91_mck_init(u32 mckr) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 tmp; + /* PMC configuration */ + at91_pmc_init();

- tmp = readl(&pmc->mckr); - tmp &= ~(AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_2); - tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_2); - writel(tmp, &pmc->mckr); + at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);

- while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) - ; -} + timer_init();

+ board_early_init_f();

-u32 spl_boot_device(void) + preloader_console_init(); + + mem_init(); +} +#else +static void enable_ext_reset(void) { -#ifdef CONFIG_SYS_USE_MMC - return BOOT_DEVICE_MMC1; -#elif CONFIG_SYS_USE_NANDFLASH - return BOOT_DEVICE_NAND; -#elif CONFIG_SYS_USE_SERIALFLASH - return BOOT_DEVICE_SPI; -#endif - return BOOT_DEVICE_NONE; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + + writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr); }

-u32 spl_boot_mode(void) +#if defined(CONFIG_ATMEL_MATRIX_INIT) +static void matrix_init(void) { - switch (spl_boot_device()) { -#ifdef CONFIG_SYS_USE_MMC - case BOOT_DEVICE_MMC1: - return MMCSD_MODE_FS; - break; + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; + + writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE)) + | AT91_MATRIX_SLOT_CYCLE_(0x40), + &mat->scfg[3]); +} #endif - case BOOT_DEVICE_NONE: - default: - hang(); + +void lowlevel_clock_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { + /* Enable Main Oscillator */ + writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); + + /* Wait until Main Oscillator is stable */ + while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) + ; } + + /* After stabilization, switch to Main Oscillator */ + if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { + unsigned long tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_CSS; + tmp |= AT91_PMC_CSS_MAIN; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + + tmp &= ~AT91_PMC_PRES; + tmp |= AT91_PMC_PRES_1; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + } + + return; }

-void s_init(void) +void __weak at91_spl_board_init(void) { - switch_to_main_crystal_osc(); +}

- /* disable watchdog */ +void spl_board_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + lowlevel_clock_init(); at91_disable_wdt();

- /* PMC configuration */ - at91_pmc_init(); + /* + * At this stage the main oscillator is supposed to be enabled + * PCK = MCK = MOSC + */ + writel(0x00, &pmc->pllicpr);

- at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ + at91_plla_init(CONFIG_SYS_AT91_PLLA);

- timer_init(); + /* PCK = PLLA = 2 * MCK */ + at91_mck_init(CONFIG_SYS_MCKR);

- board_early_init_f(); + /* Switch MCK on PLLA output */ + at91_mck_init(CONFIG_SYS_MCKR_CSS); + +#if defined(CONFIG_SYS_AT91_PLLB) + /* Configure PLLB */ + at91_pllb_init(CONFIG_SYS_AT91_PLLB); +#endif + + /* Enable External Reset */ + enable_ext_reset();

+#if defined(CONFIG_ATMEL_MATRIX_INIT) + /* Initialize matrix */ + matrix_init(); +#endif + + gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; + /* + * init timer long enough for using in spl. + */ + timer_init(); + + /* enable clocks for all PIOs */ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + /* init console */ + at91_seriald_hw_init(); preloader_console_init();

mem_init(); + + at91_spl_board_init(); } +#endif diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index 59e2f43..2d94090 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -23,9 +23,13 @@ void at91_udp_hw_init(void); void at91_uhp_hw_init(void); void at91_lcd_hw_init(void); void at91_plla_init(u32 pllar); +void at91_pllb_init(u32 pllar); void at91_mck_init(u32 mckr); void at91_pmc_init(void); void mem_init(void); void at91_phy_reset(void); +void at91_sdram_hw_init(void); +void at91_mck_init(u32 mckr); +void at91_spl_board_init(void);

#endif /* AT91_COMMON_H */ diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h index 27331ff..5f64583 100644 --- a/arch/arm/include/asm/arch-at91/at91_pmc.h +++ b/arch/arm/include/asm/arch-at91/at91_pmc.h @@ -95,7 +95,7 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_CSS_MAIN 0x00000001 #define AT91_PMC_MCKR_CSS_PLLA 0x00000002 #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 -#define AT91_PMC_MCKR_CSS_MASK 0x00000003 +#define AT91_PMC_MCKR_CSS_MASK 0x00000007

#ifdef CONFIG_SAMA5D3 #define AT91_PMC_MCKR_PRES_1 0x00000000 @@ -114,7 +114,7 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_PRES_16 0x00000010 #define AT91_PMC_MCKR_PRES_32 0x00000014 #define AT91_PMC_MCKR_PRES_64 0x00000018 -#define AT91_PMC_MCKR_PRES_MASK 0x0000001C +#define AT91_PMC_MCKR_PRES_MASK 0x0000003C #endif

#ifdef CONFIG_AT91RM9200 @@ -133,6 +133,7 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_MDIV_MASK 0x00000300 #endif

+#define AT91_PMC_MCKR_PLLADIV_MASK 0x00003000 #define AT91_PMC_MCKR_PLLADIV_1 0x00000000 #define AT91_PMC_MCKR_PLLADIV_2 0x00001000

diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index 2e902ee..1e613fa 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -95,6 +95,7 @@ #define ATMEL_BASE_SDRAMC 0xffffea00 #define ATMEL_BASE_SMC 0xffffec00 #define ATMEL_BASE_MATRIX 0xffffee00 +#define ATMEL_BASE_CCFG 0xffffef14 #define ATMEL_BASE_AIC 0xfffff000 #define ATMEL_BASE_DBGU 0xfffff200 #define ATMEL_BASE_PIOA 0xfffff400 diff --git a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h index 4755fa1..dc61f48 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h @@ -61,5 +61,10 @@ struct at91_matrix { #define AT91_MATRIX_DBPUC (1 << 8) #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_IOSR_SEL (1 << 17) + +/* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) +#define AT91_MATRIX_SLOT_CYCLE_(x) (x << 0)

#endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h index 5c98cc7..3a076c6 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h +++ b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h @@ -25,6 +25,21 @@ #define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) #define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24)

+#else +struct sdramc_reg { + u32 mr; + u32 tr; + u32 cr; + u32 lpr; + u32 ier; + u32 idr; + u32 imr; + u32 isr; + u32 mdr; +}; + +int sdramc_initialize(unsigned int sdram_address, + const struct sdramc_reg *p); #endif

/* SDRAM Controller (SDRAMC) registers */ @@ -62,11 +77,17 @@ #define AT91_SDRAMC_DBW_32 (0 << 7) #define AT91_SDRAMC_DBW_16 (1 << 7) #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ +#define AT91_SDRAMC_TWR_VAL(x) (x << 8) #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ +#define AT91_SDRAMC_TRC_VAL(x) (x << 12) #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ +#define AT91_SDRAMC_TRP_VAL(x) (x << 16) #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ +#define AT91_SDRAMC_TRCD_VAL(x) (x << 20) #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ +#define AT91_SDRAMC_TRAS_VAL(x) (x << 24) #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ +#define AT91_SDRAMC_TXSR_VAL(x) (x << 28)

#define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ @@ -93,5 +114,4 @@ #define AT91_SDRAMC_MD_SDRAM 0 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1

- #endif

replaces the at91bootstrap code with SPL code. make the spl image with: ./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin

this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader.

Signed-off-by: Heiko Schocher hs@denx.de

---

Changes in v2: - rename function "nand_erase_one" to "spl_nand_erase_one" as Scott Wood suggested - add comment from Andreas Biessmann: rename "MPDDRC_CR_EBISHARE" to "MPDDRC_CR_DQMS_SHARED"

arch/arm/Kconfig | 1 + board/siemens/corvus/board.c | 109 ++++++++++++++++++++++++++++++++++++++----- configs/corvus_defconfig | 5 +- include/configs/corvus.h | 54 +++++++++++++++++++-- 4 files changed, 151 insertions(+), 18 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index abe1317..ff2d84c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -125,6 +125,7 @@ config TARGET_PM9G45 bool "Support pm9g45"

config TARGET_CORVUS + select SUPPORT_SPL bool "Support corvus"

config TARGET_TAURUS diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index f1e93ef..0a11540 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -31,12 +31,10 @@

DECLARE_GLOBAL_DATA_PTR;

-#ifdef CONFIG_CMD_NAND static void corvus_nand_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa;

/* Enable CS3 */ @@ -63,22 +61,111 @@ static void corvus_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode);

- writel(1 << ATMEL_ID_PIOC, &pmc->pcer); - - /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_periph_clk_enable(ATMEL_ID_PIOC);

/* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void at91_spl_board_init(void) +{ + /* + * For on the sam9m10g45ek board, the chip wm9711 stay in the test + * mode, so it need do some action to exit mode. + */ + at91_set_gpio_output(AT91_PIN_PD7, 0); + at91_set_gpio_output(AT91_PIN_PD8, 0); + at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); + at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); + + corvus_nand_hw_init(); + + /* Configure recovery button PINs */ + at91_set_gpio_input(AT91_PIN_PB7, 1); + + /* check if button is pressed */ + if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { + u32 boot_device; + + debug("Recovery button pressed\n"); + boot_device = spl_boot_device(); + switch (boot_device) { +#ifdef CONFIG_SPL_NAND_SUPPORT + case BOOT_DEVICE_NAND: + nand_init(); + spl_nand_erase_one(0, 0); + break; #endif + } + } +}

-#ifdef CONFIG_CMD_USB -static void taurus_usb_hw_init(void) +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_DQMS_SHARED | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3); + ddr2->rtr = 0x24b; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ + 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ + 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddr ddr2; + unsigned long csa; + + ddr2_conf(&ddr2);

- writel(1 << ATMEL_ID_PIODE, &pmc->pcer); + /* enable DDR2 clock */ + writel(0x4, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&mat->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; + writel(csa, &mat->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_CS6, &ddr2); +} +#endif + +#ifdef CONFIG_CMD_USB +static void taurus_usb_hw_init(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIODE);

at91_set_gpio_output(AT91_PIN_PD1, 0); at91_set_gpio_output(AT91_PIN_PD3, 0); @@ -88,10 +175,8 @@ static void taurus_usb_hw_init(void) #ifdef CONFIG_MACB static void corvus_macb_hw_init(void) { - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - /* Enable clock */ - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC);

/* * Disable pull-up on: diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 3fc8edb..5d60847 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" -CONFIG_ARM=y -CONFIG_TARGET_CORVUS=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_CORVUS=y diff --git a/include/configs/corvus.h b/include/configs/corvus.h index eb1584d..5b50c1d 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -19,7 +19,6 @@ #define MACH_TYPE_CORVUS 2066

#define CONFIG_SYS_GENERIC_BOARD - /* * Warning: changing CONFIG_SYS_TEXT_BASE requires * adapting the initial boot program. @@ -27,7 +26,7 @@ * hex number here! */

-#define CONFIG_SYS_TEXT_BASE 0x73f00000 +#define CONFIG_SYS_TEXT_BASE 0x72000000

#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */

@@ -107,8 +106,6 @@ /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 - #endif

/* Ethernet */ @@ -159,5 +156,54 @@ */ #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ 128*1024, 0x1000) +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE (12 * 1024) +#define CONFIG_SPL_STACK (16 * 1024) + +#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_BSS_MAX_SIZE (2 * 1024) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_SIZE (256*1024*1024) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0

#endif