[U-Boot-Users] serial: polling or interrupt based?
Hi folks
I'm trying to set up the serial interface on my happy little board. Reading the CPU's manual (CPU is mpc852T), I'm at this section called SCC Initialization. I'm a bit confused, because the initialization procedure specifically says:
... 10. Write ones to SCCM register to enable interrupts 11. Write CICR to configure the SCC interrupt priority 12. Clear out any interrupts in CIPR 13. Write the CIMR to enable interrupts to the CPIC. ...
However, the u-boot code writes zeros to the SCCM and doesn't touch CIMR. So I guess it's polling based, yes?
Then the question is, do I simply skip steps 10-13? If I wanted to use interrupts instead of polling, what else would I need to change?
On a similar note, the manual for the MPC866, in appendix H which is specific for MPC852T, specifies that there is no BRG1 nor BRG2. The u-boot hard codes wiring BRG1 to the selected SCC. Why? Even more important: I have to obviously change it; is there more than one place I need to change (namely, replace cp_brgc1 with cp_brgc4)?
Thanks Ben
Wolfgang has repeatedly said on this list that u-boot is single-threaded and polled.
With u-boot as a single-threaded environment, I don't know what you buy with the interrupt other than knowledge on how to do it.
If you do want the experience, you have to create an interrupt routine that knows how to service the hardware and feed the u-boot COMM-port mechanism.
If you're looking for an example ISR for the hardware servicing, look in the Linux code. Cheers, T.mike
-----Original Message----- From: u-boot-users-admin@lists.sourceforge.net [mailto:u-boot-users-admin@lists.sourceforge.net]On Behalf Of Benjamin Collar Sent: Friday, September 24, 2004 4:55 AM To: ubootuser Subject: [U-Boot-Users] serial: polling or interrupt based?
Hi folks
I'm trying to set up the serial interface on my happy little board. Reading the CPU's manual (CPU is mpc852T), I'm at this section called SCC Initialization. I'm a bit confused, because the initialization procedure specifically says:
... 10. Write ones to SCCM register to enable interrupts 11. Write CICR to configure the SCC interrupt priority 12. Clear out any interrupts in CIPR 13. Write the CIMR to enable interrupts to the CPIC. ...
However, the u-boot code writes zeros to the SCCM and doesn't touch CIMR. So I guess it's polling based, yes?
Then the question is, do I simply skip steps 10-13? If I wanted to use interrupts instead of polling, what else would I need to change?
On a similar note, the manual for the MPC866, in appendix H which is specific for MPC852T, specifies that there is no BRG1 nor BRG2. The u-boot hard codes wiring BRG1 to the selected SCC. Why? Even more important: I have to obviously change it; is there more than one place I need to change (namely, replace cp_brgc1 with cp_brgc4)?
Thanks Ben
-- Benjamin Collar Siemens AG CT SE 2 Embedded Linux 089-636-53711
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In message 1096026889.3318.40.camel@mhpajh5c you wrote:
However, the u-boot code writes zeros to the SCCM and doesn't touch CIMR. So I guess it's polling based, yes?
SDon;t guess. Read the source code. This is what you get it for.
Then the question is, do I simply skip steps 10-13? If I wanted to use interrupts instead of polling, what else would I need to change?
I have no idea what you are worrying about. Is there any problem with the existing MPC8xx drivers you're trying to fix?
specific for MPC852T, specifies that there is no BRG1 nor BRG2. The u-boot hard codes wiring BRG1 to the selected SCC. Why? Even more
Why not?
important: I have to obviously change it; is there more than one place I need to change (namely, replace cp_brgc1 with cp_brgc4)?
Really? There are several MPC866 based boards which run the existing code just fine.
Best regards,
Wolfgang Denk
participants (3)
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Benjamin Collar -
T Michael Turney -
Wolfgang Denk