Drop in favour of dts/upstream. This is just the clock headers.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/qcom,camcc-sdm845.h | 116 -------- include/dt-bindings/clock/qcom,dispcc-sdm845.h | 56 ---- include/dt-bindings/clock/qcom,gcc-ipq4019.h | 169 ----------- include/dt-bindings/clock/qcom,gcc-msm8916.h | 179 ----------- include/dt-bindings/clock/qcom,gcc-msm8996.h | 362 ----------------------- include/dt-bindings/clock/qcom,gcc-qcs404.h | 180 ----------- include/dt-bindings/clock/qcom,gcc-sdm845.h | 246 --------------- include/dt-bindings/clock/qcom,gpucc-sdm845.h | 24 -- include/dt-bindings/clock/qcom,lpass-sdm845.h | 15 - include/dt-bindings/clock/qcom,mmcc-msm8996.h | 295 ------------------ include/dt-bindings/clock/qcom,rpmcc.h | 174 ----------- include/dt-bindings/clock/qcom,rpmh.h | 37 --- include/dt-bindings/clock/qcom,turingcc-qcs404.h | 15 - include/dt-bindings/clock/qcom,videocc-sdm845.h | 35 --- 14 files changed, 1903 deletions(-)

diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h deleted file mode 100644 index 4f7a2d2320bf..000000000000 --- a/include/dt-bindings/clock/qcom,camcc-sdm845.h +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H - -/* CAM_CC clock registers */ -#define CAM_CC_BPS_AHB_CLK 0 -#define CAM_CC_BPS_AREG_CLK 1 -#define CAM_CC_BPS_AXI_CLK 2 -#define CAM_CC_BPS_CLK 3 -#define CAM_CC_BPS_CLK_SRC 4 -#define CAM_CC_CAMNOC_ATB_CLK 5 -#define CAM_CC_CAMNOC_AXI_CLK 6 -#define CAM_CC_CCI_CLK 7 -#define CAM_CC_CCI_CLK_SRC 8 -#define CAM_CC_CPAS_AHB_CLK 9 -#define CAM_CC_CPHY_RX_CLK_SRC 10 -#define CAM_CC_CSI0PHYTIMER_CLK 11 -#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12 -#define CAM_CC_CSI1PHYTIMER_CLK 13 -#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14 -#define CAM_CC_CSI2PHYTIMER_CLK 15 -#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16 -#define CAM_CC_CSI3PHYTIMER_CLK 17 -#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18 -#define CAM_CC_CSIPHY0_CLK 19 -#define CAM_CC_CSIPHY1_CLK 20 -#define CAM_CC_CSIPHY2_CLK 21 -#define CAM_CC_CSIPHY3_CLK 22 -#define CAM_CC_FAST_AHB_CLK_SRC 23 -#define CAM_CC_FD_CORE_CLK 24 -#define CAM_CC_FD_CORE_CLK_SRC 25 -#define CAM_CC_FD_CORE_UAR_CLK 26 -#define CAM_CC_ICP_APB_CLK 27 -#define CAM_CC_ICP_ATB_CLK 28 -#define CAM_CC_ICP_CLK 29 -#define CAM_CC_ICP_CLK_SRC 30 -#define CAM_CC_ICP_CTI_CLK 31 -#define CAM_CC_ICP_TS_CLK 32 -#define CAM_CC_IFE_0_AXI_CLK 33 -#define CAM_CC_IFE_0_CLK 34 -#define CAM_CC_IFE_0_CLK_SRC 35 -#define CAM_CC_IFE_0_CPHY_RX_CLK 36 -#define CAM_CC_IFE_0_CSID_CLK 37 -#define CAM_CC_IFE_0_CSID_CLK_SRC 38 -#define CAM_CC_IFE_0_DSP_CLK 39 -#define CAM_CC_IFE_1_AXI_CLK 40 -#define CAM_CC_IFE_1_CLK 41 -#define CAM_CC_IFE_1_CLK_SRC 42 -#define CAM_CC_IFE_1_CPHY_RX_CLK 43 -#define CAM_CC_IFE_1_CSID_CLK 44 -#define CAM_CC_IFE_1_CSID_CLK_SRC 45 -#define CAM_CC_IFE_1_DSP_CLK 46 -#define CAM_CC_IFE_LITE_CLK 47 -#define CAM_CC_IFE_LITE_CLK_SRC 48 -#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 -#define CAM_CC_IFE_LITE_CSID_CLK 50 -#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 -#define CAM_CC_IPE_0_AHB_CLK 52 -#define CAM_CC_IPE_0_AREG_CLK 53 -#define CAM_CC_IPE_0_AXI_CLK 54 -#define CAM_CC_IPE_0_CLK 55 -#define CAM_CC_IPE_0_CLK_SRC 56 -#define CAM_CC_IPE_1_AHB_CLK 57 -#define CAM_CC_IPE_1_AREG_CLK 58 -#define CAM_CC_IPE_1_AXI_CLK 59 -#define CAM_CC_IPE_1_CLK 60 -#define CAM_CC_IPE_1_CLK_SRC 61 -#define CAM_CC_JPEG_CLK 62 -#define CAM_CC_JPEG_CLK_SRC 63 -#define CAM_CC_LRME_CLK 64 -#define CAM_CC_LRME_CLK_SRC 65 -#define CAM_CC_MCLK0_CLK 66 -#define CAM_CC_MCLK0_CLK_SRC 67 -#define CAM_CC_MCLK1_CLK 68 -#define CAM_CC_MCLK1_CLK_SRC 69 -#define CAM_CC_MCLK2_CLK 70 -#define CAM_CC_MCLK2_CLK_SRC 71 -#define CAM_CC_MCLK3_CLK 72 -#define CAM_CC_MCLK3_CLK_SRC 73 -#define CAM_CC_PLL0 74 -#define CAM_CC_PLL0_OUT_EVEN 75 -#define CAM_CC_PLL1 76 -#define CAM_CC_PLL1_OUT_EVEN 77 -#define CAM_CC_PLL2 78 -#define CAM_CC_PLL2_OUT_EVEN 79 -#define CAM_CC_PLL3 80 -#define CAM_CC_PLL3_OUT_EVEN 81 -#define CAM_CC_SLOW_AHB_CLK_SRC 82 -#define CAM_CC_SOC_AHB_CLK 83 -#define CAM_CC_SYS_TMR_CLK 84 - -/* CAM_CC Resets */ -#define TITAN_CAM_CC_CCI_BCR 0 -#define TITAN_CAM_CC_CPAS_BCR 1 -#define TITAN_CAM_CC_CSI0PHY_BCR 2 -#define TITAN_CAM_CC_CSI1PHY_BCR 3 -#define TITAN_CAM_CC_CSI2PHY_BCR 4 -#define TITAN_CAM_CC_MCLK0_BCR 5 -#define TITAN_CAM_CC_MCLK1_BCR 6 -#define TITAN_CAM_CC_MCLK2_BCR 7 -#define TITAN_CAM_CC_MCLK3_BCR 8 -#define TITAN_CAM_CC_TITAN_TOP_BCR 9 - -/* CAM_CC GDSCRs */ -#define BPS_GDSC 0 -#define IPE_0_GDSC 1 -#define IPE_1_GDSC 2 -#define IFE_0_GDSC 3 -#define IFE_1_GDSC 4 -#define TITAN_TOP_GDSC 5 - -#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h deleted file mode 100644 index 4016fd1d5b46..000000000000 --- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H - -/* DISP_CC clock registers */ -#define DISP_CC_MDSS_AHB_CLK 0 -#define DISP_CC_MDSS_AXI_CLK 1 -#define DISP_CC_MDSS_BYTE0_CLK 2 -#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 -#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 -#define DISP_CC_MDSS_BYTE1_CLK 5 -#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 -#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 -#define DISP_CC_MDSS_ESC0_CLK 8 -#define DISP_CC_MDSS_ESC0_CLK_SRC 9 -#define DISP_CC_MDSS_ESC1_CLK 10 -#define DISP_CC_MDSS_ESC1_CLK_SRC 11 -#define DISP_CC_MDSS_MDP_CLK 12 -#define DISP_CC_MDSS_MDP_CLK_SRC 13 -#define DISP_CC_MDSS_MDP_LUT_CLK 14 -#define DISP_CC_MDSS_PCLK0_CLK 15 -#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 -#define DISP_CC_MDSS_PCLK1_CLK 17 -#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 -#define DISP_CC_MDSS_ROT_CLK 19 -#define DISP_CC_MDSS_ROT_CLK_SRC 20 -#define DISP_CC_MDSS_RSCC_AHB_CLK 21 -#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 -#define DISP_CC_MDSS_VSYNC_CLK 23 -#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 -#define DISP_CC_PLL0 25 -#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 -#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 -#define DISP_CC_MDSS_DP_AUX_CLK 28 -#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 -#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 -#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 -#define DISP_CC_MDSS_DP_LINK_CLK 32 -#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 -#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 -#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 -#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 -#define DISP_CC_MDSS_DP_PIXEL_CLK 37 -#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 - -/* DISP_CC Reset */ -#define DISP_CC_MDSS_RSCC_BCR 0 - -/* DISP_CC GDSCR */ -#define MDSS_GDSC 0 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h deleted file mode 100644 index 7e8a7be6dcda..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright (c) 2015 The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -#ifndef __QCOM_CLK_IPQ4019_H__ -#define __QCOM_CLK_IPQ4019_H__ - -#define GCC_DUMMY_CLK 0 -#define AUDIO_CLK_SRC 1 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5 -#define BLSP1_UART1_APPS_CLK_SRC 6 -#define BLSP1_UART2_APPS_CLK_SRC 7 -#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 -#define GCC_APPS_CLK_SRC 9 -#define GCC_APPS_AHB_CLK_SRC 10 -#define GP1_CLK_SRC 11 -#define GP2_CLK_SRC 12 -#define GP3_CLK_SRC 13 -#define SDCC1_APPS_CLK_SRC 14 -#define FEPHY_125M_DLY_CLK_SRC 15 -#define WCSS2G_CLK_SRC 16 -#define WCSS5G_CLK_SRC 17 -#define GCC_APSS_AHB_CLK 18 -#define GCC_AUDIO_AHB_CLK 19 -#define GCC_AUDIO_PWM_CLK 20 -#define GCC_BLSP1_AHB_CLK 21 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 -#define GCC_BLSP1_UART1_APPS_CLK 26 -#define GCC_BLSP1_UART2_APPS_CLK 27 -#define GCC_DCD_XO_CLK 28 -#define GCC_GP1_CLK 29 -#define GCC_GP2_CLK 30 -#define GCC_GP3_CLK 31 -#define GCC_BOOT_ROM_AHB_CLK 32 -#define GCC_CRYPTO_AHB_CLK 33 -#define GCC_CRYPTO_AXI_CLK 34 -#define GCC_CRYPTO_CLK 35 -#define GCC_ESS_CLK 36 -#define GCC_IMEM_AXI_CLK 37 -#define GCC_IMEM_CFG_AHB_CLK 38 -#define GCC_PCIE_AHB_CLK 39 -#define GCC_PCIE_AXI_M_CLK 40 -#define GCC_PCIE_AXI_S_CLK 41 -#define GCC_PCNOC_AHB_CLK 42 -#define GCC_PRNG_AHB_CLK 43 -#define GCC_QPIC_AHB_CLK 44 -#define GCC_QPIC_CLK 45 -#define GCC_SDCC1_AHB_CLK 46 -#define GCC_SDCC1_APPS_CLK 47 -#define GCC_SNOC_PCNOC_AHB_CLK 48 -#define GCC_SYS_NOC_125M_CLK 49 -#define GCC_SYS_NOC_AXI_CLK 50 -#define GCC_TCSR_AHB_CLK 51 -#define GCC_TLMM_AHB_CLK 52 -#define GCC_USB2_MASTER_CLK 53 -#define GCC_USB2_SLEEP_CLK 54 -#define GCC_USB2_MOCK_UTMI_CLK 55 -#define GCC_USB3_MASTER_CLK 56 -#define GCC_USB3_SLEEP_CLK 57 -#define GCC_USB3_MOCK_UTMI_CLK 58 -#define GCC_WCSS2G_CLK 59 -#define GCC_WCSS2G_REF_CLK 60 -#define GCC_WCSS2G_RTC_CLK 61 -#define GCC_WCSS5G_CLK 62 -#define GCC_WCSS5G_REF_CLK 63 -#define GCC_WCSS5G_RTC_CLK 64 -#define GCC_APSS_DDRPLL_VCO 65 -#define GCC_SDCC_PLLDIV_CLK 66 -#define GCC_FEPLL_VCO 67 -#define GCC_FEPLL125_CLK 68 -#define GCC_FEPLL125DLY_CLK 69 -#define GCC_FEPLL200_CLK 70 -#define GCC_FEPLL500_CLK 71 -#define GCC_FEPLL_WCSS2G_CLK 72 -#define GCC_FEPLL_WCSS5G_CLK 73 -#define GCC_APSS_CPU_PLLDIV_CLK 74 -#define GCC_PCNOC_AHB_CLK_SRC 75 - -#define WIFI0_CPU_INIT_RESET 0 -#define WIFI0_RADIO_SRIF_RESET 1 -#define WIFI0_RADIO_WARM_RESET 2 -#define WIFI0_RADIO_COLD_RESET 3 -#define WIFI0_CORE_WARM_RESET 4 -#define WIFI0_CORE_COLD_RESET 5 -#define WIFI1_CPU_INIT_RESET 6 -#define WIFI1_RADIO_SRIF_RESET 7 -#define WIFI1_RADIO_WARM_RESET 8 -#define WIFI1_RADIO_COLD_RESET 9 -#define WIFI1_CORE_WARM_RESET 10 -#define WIFI1_CORE_COLD_RESET 11 -#define USB3_UNIPHY_PHY_ARES 12 -#define USB3_HSPHY_POR_ARES 13 -#define USB3_HSPHY_S_ARES 14 -#define USB2_HSPHY_POR_ARES 15 -#define USB2_HSPHY_S_ARES 16 -#define PCIE_PHY_AHB_ARES 17 -#define PCIE_AHB_ARES 18 -#define PCIE_PWR_ARES 19 -#define PCIE_PIPE_STICKY_ARES 20 -#define PCIE_AXI_M_STICKY_ARES 21 -#define PCIE_PHY_ARES 22 -#define PCIE_PARF_XPU_ARES 23 -#define PCIE_AXI_S_XPU_ARES 24 -#define PCIE_AXI_M_VMIDMT_ARES 25 -#define PCIE_PIPE_ARES 26 -#define PCIE_AXI_S_ARES 27 -#define PCIE_AXI_M_ARES 28 -#define ESS_RESET 29 -#define GCC_BLSP1_BCR 30 -#define GCC_BLSP1_QUP1_BCR 31 -#define GCC_BLSP1_UART1_BCR 32 -#define GCC_BLSP1_QUP2_BCR 33 -#define GCC_BLSP1_UART2_BCR 34 -#define GCC_BIMC_BCR 35 -#define GCC_TLMM_BCR 36 -#define GCC_IMEM_BCR 37 -#define GCC_ESS_BCR 38 -#define GCC_PRNG_BCR 39 -#define GCC_BOOT_ROM_BCR 40 -#define GCC_CRYPTO_BCR 41 -#define GCC_SDCC1_BCR 42 -#define GCC_SEC_CTRL_BCR 43 -#define GCC_AUDIO_BCR 44 -#define GCC_QPIC_BCR 45 -#define GCC_PCIE_BCR 46 -#define GCC_USB2_BCR 47 -#define GCC_USB2_PHY_BCR 48 -#define GCC_USB3_BCR 49 -#define GCC_USB3_PHY_BCR 50 -#define GCC_SYSTEM_NOC_BCR 51 -#define GCC_PCNOC_BCR 52 -#define GCC_DCD_BCR 53 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 -#define GCC_TCSR_BCR 68 -#define GCC_QDSS_BCR 69 -#define GCC_MPM_BCR 70 -#define GCC_SPDM_BCR 71 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h deleted file mode 100644 index 563034406184..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-msm8916.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H -#define _DT_BINDINGS_CLK_MSM_GCC_8916_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define BIMC_PLL 2 -#define BIMC_PLL_VOTE 3 -#define GPLL1 4 -#define GPLL1_VOTE 5 -#define GPLL2 6 -#define GPLL2_VOTE 7 -#define PCNOC_BFDCD_CLK_SRC 8 -#define SYSTEM_NOC_BFDCD_CLK_SRC 9 -#define CAMSS_AHB_CLK_SRC 10 -#define APSS_AHB_CLK_SRC 11 -#define CSI0_CLK_SRC 12 -#define CSI1_CLK_SRC 13 -#define GFX3D_CLK_SRC 14 -#define VFE0_CLK_SRC 15 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 -#define BLSP1_UART1_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define CCI_CLK_SRC 30 -#define CAMSS_GP0_CLK_SRC 31 -#define CAMSS_GP1_CLK_SRC 32 -#define JPEG0_CLK_SRC 33 -#define MCLK0_CLK_SRC 34 -#define MCLK1_CLK_SRC 35 -#define CSI0PHYTIMER_CLK_SRC 36 -#define CSI1PHYTIMER_CLK_SRC 37 -#define CPP_CLK_SRC 38 -#define CRYPTO_CLK_SRC 39 -#define GP1_CLK_SRC 40 -#define GP2_CLK_SRC 41 -#define GP3_CLK_SRC 42 -#define BYTE0_CLK_SRC 43 -#define ESC0_CLK_SRC 44 -#define MDP_CLK_SRC 45 -#define PCLK0_CLK_SRC 46 -#define VSYNC_CLK_SRC 47 -#define PDM2_CLK_SRC 48 -#define SDCC1_APPS_CLK_SRC 49 -#define SDCC2_APPS_CLK_SRC 50 -#define APSS_TCU_CLK_SRC 51 -#define USB_HS_SYSTEM_CLK_SRC 52 -#define VCODEC0_CLK_SRC 53 -#define GCC_BLSP1_AHB_CLK 54 -#define GCC_BLSP1_SLEEP_CLK 55 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 -#define GCC_BLSP1_UART1_APPS_CLK 68 -#define GCC_BLSP1_UART2_APPS_CLK 69 -#define GCC_BOOT_ROM_AHB_CLK 70 -#define GCC_CAMSS_CCI_AHB_CLK 71 -#define GCC_CAMSS_CCI_CLK 72 -#define GCC_CAMSS_CSI0_AHB_CLK 73 -#define GCC_CAMSS_CSI0_CLK 74 -#define GCC_CAMSS_CSI0PHY_CLK 75 -#define GCC_CAMSS_CSI0PIX_CLK 76 -#define GCC_CAMSS_CSI0RDI_CLK 77 -#define GCC_CAMSS_CSI1_AHB_CLK 78 -#define GCC_CAMSS_CSI1_CLK 79 -#define GCC_CAMSS_CSI1PHY_CLK 80 -#define GCC_CAMSS_CSI1PIX_CLK 81 -#define GCC_CAMSS_CSI1RDI_CLK 82 -#define GCC_CAMSS_CSI_VFE0_CLK 83 -#define GCC_CAMSS_GP0_CLK 84 -#define GCC_CAMSS_GP1_CLK 85 -#define GCC_CAMSS_ISPIF_AHB_CLK 86 -#define GCC_CAMSS_JPEG0_CLK 87 -#define GCC_CAMSS_JPEG_AHB_CLK 88 -#define GCC_CAMSS_JPEG_AXI_CLK 89 -#define GCC_CAMSS_MCLK0_CLK 90 -#define GCC_CAMSS_MCLK1_CLK 91 -#define GCC_CAMSS_MICRO_AHB_CLK 92 -#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 -#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 -#define GCC_CAMSS_AHB_CLK 95 -#define GCC_CAMSS_TOP_AHB_CLK 96 -#define GCC_CAMSS_CPP_AHB_CLK 97 -#define GCC_CAMSS_CPP_CLK 98 -#define GCC_CAMSS_VFE0_CLK 99 -#define GCC_CAMSS_VFE_AHB_CLK 100 -#define GCC_CAMSS_VFE_AXI_CLK 101 -#define GCC_CRYPTO_AHB_CLK 102 -#define GCC_CRYPTO_AXI_CLK 103 -#define GCC_CRYPTO_CLK 104 -#define GCC_OXILI_GMEM_CLK 105 -#define GCC_GP1_CLK 106 -#define GCC_GP2_CLK 107 -#define GCC_GP3_CLK 108 -#define GCC_MDSS_AHB_CLK 109 -#define GCC_MDSS_AXI_CLK 110 -#define GCC_MDSS_BYTE0_CLK 111 -#define GCC_MDSS_ESC0_CLK 112 -#define GCC_MDSS_MDP_CLK 113 -#define GCC_MDSS_PCLK0_CLK 114 -#define GCC_MDSS_VSYNC_CLK 115 -#define GCC_MSS_CFG_AHB_CLK 116 -#define GCC_OXILI_AHB_CLK 117 -#define GCC_OXILI_GFX3D_CLK 118 -#define GCC_PDM2_CLK 119 -#define GCC_PDM_AHB_CLK 120 -#define GCC_PRNG_AHB_CLK 121 -#define GCC_SDCC1_AHB_CLK 122 -#define GCC_SDCC1_APPS_CLK 123 -#define GCC_SDCC2_AHB_CLK 124 -#define GCC_SDCC2_APPS_CLK 125 -#define GCC_GTCU_AHB_CLK 126 -#define GCC_JPEG_TBU_CLK 127 -#define GCC_MDP_TBU_CLK 128 -#define GCC_SMMU_CFG_CLK 129 -#define GCC_VENUS_TBU_CLK 130 -#define GCC_VFE_TBU_CLK 131 -#define GCC_USB2A_PHY_SLEEP_CLK 132 -#define GCC_USB_HS_AHB_CLK 133 -#define GCC_USB_HS_SYSTEM_CLK 134 -#define GCC_VENUS0_AHB_CLK 135 -#define GCC_VENUS0_AXI_CLK 136 -#define GCC_VENUS0_VCODEC0_CLK 137 -#define BIMC_DDR_CLK_SRC 138 -#define GCC_APSS_TCU_CLK 139 -#define GCC_GFX_TCU_CLK 140 -#define BIMC_GPU_CLK_SRC 141 -#define GCC_BIMC_GFX_CLK 142 -#define GCC_BIMC_GPU_CLK 143 -#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 -#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 -#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 -#define ULTAUDIO_XO_CLK_SRC 147 -#define ULTAUDIO_AHBFABRIC_CLK_SRC 148 -#define CODEC_DIGCODEC_CLK_SRC 149 -#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 -#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 -#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 -#define GCC_ULTAUDIO_STC_XO_CLK 153 -#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 -#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 -#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 -#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 -#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 -#define GCC_CODEC_DIGCODEC_CLK 159 -#define GCC_MSS_Q6_BIMC_AXI_CLK 160 - -/* Indexes for GDSCs */ -#define BIMC_GDSC 0 -#define VENUS_GDSC 1 -#define MDSS_GDSC 2 -#define JPEG_GDSC 3 -#define VFE_GDSC 4 -#define OXILI_GDSC 5 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h deleted file mode 100644 index ddfd6fd73081..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-msm8996.h +++ /dev/null @@ -1,362 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H -#define _DT_BINDINGS_CLK_MSM_GCC_8996_H - -#define GPLL0_EARLY 0 -#define GPLL0 1 -#define GPLL1_EARLY 2 -#define GPLL1 3 -#define GPLL2_EARLY 4 -#define GPLL2 5 -#define GPLL3_EARLY 6 -#define GPLL3 7 -#define GPLL4_EARLY 8 -#define GPLL4 9 -#define SYSTEM_NOC_CLK_SRC 10 -/* U-Boot: KConfig check in CI erroneously picks this up, it's unused - * anyway so comment it out for now - */ -//#define CONFIG _NOC_CLK_SRC 11 -#define PERIPH_NOC_CLK_SRC 12 -#define MMSS_BIMC_GFX_CLK_SRC 13 -#define USB30_MASTER_CLK_SRC 14 -#define USB30_MOCK_UTMI_CLK_SRC 15 -#define USB3_PHY_AUX_CLK_SRC 16 -#define USB20_MASTER_CLK_SRC 17 -#define USB20_MOCK_UTMI_CLK_SRC 18 -#define SDCC1_APPS_CLK_SRC 19 -#define SDCC1_ICE_CORE_CLK_SRC 20 -#define SDCC2_APPS_CLK_SRC 21 -#define SDCC3_APPS_CLK_SRC 22 -#define SDCC4_APPS_CLK_SRC 23 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 -#define BLSP1_UART1_APPS_CLK_SRC 26 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 -#define BLSP1_UART3_APPS_CLK_SRC 32 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 -#define BLSP1_UART4_APPS_CLK_SRC 35 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 -#define BLSP1_UART5_APPS_CLK_SRC 38 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 -#define BLSP1_UART6_APPS_CLK_SRC 41 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 -#define BLSP2_UART1_APPS_CLK_SRC 44 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 -#define BLSP2_UART2_APPS_CLK_SRC 47 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 -#define BLSP2_UART3_APPS_CLK_SRC 50 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 -#define BLSP2_UART4_APPS_CLK_SRC 53 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 -#define BLSP2_UART5_APPS_CLK_SRC 56 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 -#define BLSP2_UART6_APPS_CLK_SRC 59 -#define PDM2_CLK_SRC 60 -#define TSIF_REF_CLK_SRC 61 -#define CE1_CLK_SRC 62 -#define GCC_SLEEP_CLK_SRC 63 -#define BIMC_CLK_SRC 64 -#define HMSS_AHB_CLK_SRC 65 -#define BIMC_HMSS_AXI_CLK_SRC 66 -#define HMSS_RBCPR_CLK_SRC 67 -#define HMSS_GPLL0_CLK_SRC 68 -#define GP1_CLK_SRC 69 -#define GP2_CLK_SRC 70 -#define GP3_CLK_SRC 71 -#define PCIE_AUX_CLK_SRC 72 -#define UFS_AXI_CLK_SRC 73 -#define UFS_ICE_CORE_CLK_SRC 74 -#define QSPI_SER_CLK_SRC 75 -#define GCC_SYS_NOC_AXI_CLK 76 -#define GCC_SYS_NOC_HMSS_AHB_CLK 77 -#define GCC_SNOC_CNOC_AHB_CLK 78 -#define GCC_SNOC_PNOC_AHB_CLK 79 -#define GCC_SYS_NOC_AT_CLK 80 -#define GCC_SYS_NOC_USB3_AXI_CLK 81 -#define GCC_SYS_NOC_UFS_AXI_CLK 82 -#define GCC_CFG_NOC_AHB_CLK 83 -#define GCC_PERIPH_NOC_AHB_CLK 84 -#define GCC_PERIPH_NOC_USB20_AHB_CLK 85 -#define GCC_TIC_CLK 86 -#define GCC_IMEM_AXI_CLK 87 -#define GCC_MMSS_SYS_NOC_AXI_CLK 88 -#define GCC_MMSS_NOC_CFG_AHB_CLK 89 -#define GCC_MMSS_BIMC_GFX_CLK 90 -#define GCC_USB30_MASTER_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB30_MOCK_UTMI_CLK 93 -#define GCC_USB3_PHY_AUX_CLK 94 -#define GCC_USB3_PHY_PIPE_CLK 95 -#define GCC_USB20_MASTER_CLK 96 -#define GCC_USB20_SLEEP_CLK 97 -#define GCC_USB20_MOCK_UTMI_CLK 98 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 -#define GCC_SDCC1_APPS_CLK 100 -#define GCC_SDCC1_AHB_CLK 101 -#define GCC_SDCC1_ICE_CORE_CLK 102 -#define GCC_SDCC2_APPS_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC3_APPS_CLK 105 -#define GCC_SDCC3_AHB_CLK 106 -#define GCC_SDCC4_APPS_CLK 107 -#define GCC_SDCC4_AHB_CLK 108 -#define GCC_BLSP1_AHB_CLK 109 -#define GCC_BLSP1_SLEEP_CLK 110 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 -#define GCC_BLSP1_UART1_APPS_CLK 113 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 -#define GCC_BLSP1_UART2_APPS_CLK 116 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 -#define GCC_BLSP1_UART3_APPS_CLK 119 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 -#define GCC_BLSP1_UART4_APPS_CLK 122 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 -#define GCC_BLSP1_UART5_APPS_CLK 125 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 -#define GCC_BLSP1_UART6_APPS_CLK 128 -#define GCC_BLSP2_AHB_CLK 129 -#define GCC_BLSP2_SLEEP_CLK 130 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 -#define GCC_BLSP2_UART1_APPS_CLK 133 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 -#define GCC_BLSP2_UART2_APPS_CLK 136 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 -#define GCC_BLSP2_UART3_APPS_CLK 139 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 -#define GCC_BLSP2_UART4_APPS_CLK 142 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 -#define GCC_BLSP2_UART5_APPS_CLK 145 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 -#define GCC_BLSP2_UART6_APPS_CLK 148 -#define GCC_PDM_AHB_CLK 149 -#define GCC_PDM_XO4_CLK 150 -#define GCC_PDM2_CLK 151 -#define GCC_PRNG_AHB_CLK 152 -#define GCC_TSIF_AHB_CLK 153 -#define GCC_TSIF_REF_CLK 154 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 -#define GCC_TCSR_AHB_CLK 156 -#define GCC_BOOT_ROM_AHB_CLK 157 -#define GCC_MSG_RAM_AHB_CLK 158 -#define GCC_TLMM_AHB_CLK 159 -#define GCC_TLMM_CLK 160 -#define GCC_MPM_AHB_CLK 161 -#define GCC_SPMI_SER_CLK 162 -#define GCC_SPMI_CNOC_AHB_CLK 163 -#define GCC_CE1_CLK 164 -#define GCC_CE1_AXI_CLK 165 -#define GCC_CE1_AHB_CLK 166 -#define GCC_BIMC_HMSS_AXI_CLK 167 -#define GCC_BIMC_GFX_CLK 168 -#define GCC_HMSS_AHB_CLK 169 -#define GCC_HMSS_SLV_AXI_CLK 170 -#define GCC_HMSS_MSTR_AXI_CLK 171 -#define GCC_HMSS_RBCPR_CLK 172 -#define GCC_GP1_CLK 173 -#define GCC_GP2_CLK 174 -#define GCC_GP3_CLK 175 -#define GCC_PCIE_0_SLV_AXI_CLK 176 -#define GCC_PCIE_0_MSTR_AXI_CLK 177 -#define GCC_PCIE_0_CFG_AHB_CLK 178 -#define GCC_PCIE_0_AUX_CLK 179 -#define GCC_PCIE_0_PIPE_CLK 180 -#define GCC_PCIE_1_SLV_AXI_CLK 181 -#define GCC_PCIE_1_MSTR_AXI_CLK 182 -#define GCC_PCIE_1_CFG_AHB_CLK 183 -#define GCC_PCIE_1_AUX_CLK 184 -#define GCC_PCIE_1_PIPE_CLK 185 -#define GCC_PCIE_2_SLV_AXI_CLK 186 -#define GCC_PCIE_2_MSTR_AXI_CLK 187 -#define GCC_PCIE_2_CFG_AHB_CLK 188 -#define GCC_PCIE_2_AUX_CLK 189 -#define GCC_PCIE_2_PIPE_CLK 190 -#define GCC_PCIE_PHY_CFG_AHB_CLK 191 -#define GCC_PCIE_PHY_AUX_CLK 192 -#define GCC_UFS_AXI_CLK 193 -#define GCC_UFS_AHB_CLK 194 -#define GCC_UFS_TX_CFG_CLK 195 -#define GCC_UFS_RX_CFG_CLK 196 -#define GCC_UFS_TX_SYMBOL_0_CLK 197 -#define GCC_UFS_RX_SYMBOL_0_CLK 198 -#define GCC_UFS_RX_SYMBOL_1_CLK 199 -#define GCC_UFS_UNIPRO_CORE_CLK 200 -#define GCC_UFS_ICE_CORE_CLK 201 -#define GCC_UFS_SYS_CLK_CORE_CLK 202 -#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 -#define GCC_AGGRE0_SNOC_AXI_CLK 204 -#define GCC_AGGRE0_CNOC_AHB_CLK 205 -#define GCC_SMMU_AGGRE0_AXI_CLK 206 -#define GCC_SMMU_AGGRE0_AHB_CLK 207 -#define GCC_AGGRE1_PNOC_AHB_CLK 208 -#define GCC_AGGRE2_UFS_AXI_CLK 209 -#define GCC_AGGRE2_USB3_AXI_CLK 210 -#define GCC_QSPI_AHB_CLK 211 -#define GCC_QSPI_SER_CLK 212 -#define GCC_USB3_CLKREF_CLK 213 -#define GCC_HDMI_CLKREF_CLK 214 -#define GCC_UFS_CLKREF_CLK 215 -#define GCC_PCIE_CLKREF_CLK 216 -#define GCC_RX2_USB2_CLKREF_CLK 217 -#define GCC_RX1_USB2_CLKREF_CLK 218 -#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 -#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 -#define GCC_EDP_CLKREF_CLK 221 -#define GCC_MSS_CFG_AHB_CLK 222 -#define GCC_MSS_Q6_BIMC_AXI_CLK 223 -#define GCC_MSS_SNOC_AXI_CLK 224 -#define GCC_MSS_MNOC_BIMC_AXI_CLK 225 -#define GCC_DCC_AHB_CLK 226 -#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 -#define GCC_MMSS_GPLL0_DIV_CLK 228 -#define GCC_MSS_GPLL0_DIV_CLK 229 - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_PIMEM_BCR 5 -#define GCC_QDSS_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB_20_BCR 8 -#define GCC_QUSB2PHY_PRIM_BCR 9 -#define GCC_QUSB2PHY_SEC_BCR 10 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_PRNG_BCR 43 -#define GCC_TSIF_BCR 44 -#define GCC_TCSR_BCR 45 -#define GCC_BOOT_ROM_BCR 46 -#define GCC_MSG_RAM_BCR 47 -#define GCC_TLMM_BCR 48 -#define GCC_MPM_BCR 49 -#define GCC_SEC_CTRL_BCR 50 -#define GCC_SPMI_BCR 51 -#define GCC_SPDM_BCR 52 -#define GCC_CE1_BCR 53 -#define GCC_BIMC_BCR 54 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 55 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 57 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 -#define GCC_CNOC_BUS_TIMEOUT7_BCR 72 -#define GCC_CNOC_BUS_TIMEOUT8_BCR 73 -#define GCC_CNOC_BUS_TIMEOUT9_BCR 74 -#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 -#define GCC_APB2JTAG_BCR 76 -#define GCC_RBCPR_CX_BCR 77 -#define GCC_RBCPR_MX_BCR 78 -#define GCC_PCIE_0_BCR 79 -#define GCC_PCIE_0_PHY_BCR 80 -#define GCC_PCIE_1_BCR 81 -#define GCC_PCIE_1_PHY_BCR 82 -#define GCC_PCIE_2_BCR 83 -#define GCC_PCIE_2_PHY_BCR 84 -#define GCC_PCIE_PHY_BCR 85 -#define GCC_DCD_BCR 86 -#define GCC_OBT_ODT_BCR 87 -#define GCC_UFS_BCR 88 -#define GCC_SSC_BCR 89 -#define GCC_VS_BCR 90 -#define GCC_AGGRE0_NOC_BCR 91 -#define GCC_AGGRE1_NOC_BCR 92 -#define GCC_AGGRE2_NOC_BCR 93 -#define GCC_DCC_BCR 94 -#define GCC_IPA_BCR 95 -#define GCC_QSPI_BCR 96 -#define GCC_SKL_BCR 97 -#define GCC_MSMPU_BCR 98 -#define GCC_MSS_Q6_BCR 99 -#define GCC_QREFS_VBG_CAL_BCR 100 -#define GCC_PCIE_PHY_COM_BCR 101 -#define GCC_PCIE_PHY_COM_NOCSR_BCR 102 -#define GCC_USB3_PHY_BCR 103 -#define GCC_USB3PHY_PHY_BCR 104 -#define GCC_MSS_RESTART 105 - - -/* Indexes for GDSCs */ -#define AGGRE0_NOC_GDSC 0 -#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 -#define HLOS1_VOTE_LPASS_ADSP_GDSC 2 -#define HLOS1_VOTE_LPASS_CORE_GDSC 3 -#define USB30_GDSC 4 -#define PCIE0_GDSC 5 -#define PCIE1_GDSC 6 -#define PCIE2_GDSC 7 -#define UFS_GDSC 8 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h deleted file mode 100644 index bc3051543347..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H -#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H - -#define GCC_APSS_AHB_CLK_SRC 0 -#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 -#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 -#define GCC_BLSP1_UART0_APPS_CLK_SRC 11 -#define GCC_BLSP1_UART1_APPS_CLK_SRC 12 -#define GCC_BLSP1_UART2_APPS_CLK_SRC 13 -#define GCC_BLSP1_UART3_APPS_CLK_SRC 14 -#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 -#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 -#define GCC_BLSP2_UART0_APPS_CLK_SRC 17 -#define GCC_BYTE0_CLK_SRC 18 -#define GCC_EMAC_CLK_SRC 19 -#define GCC_EMAC_PTP_CLK_SRC 20 -#define GCC_ESC0_CLK_SRC 21 -#define GCC_APSS_AHB_CLK 22 -#define GCC_APSS_AXI_CLK 23 -#define GCC_BIMC_APSS_AXI_CLK 24 -#define GCC_BIMC_GFX_CLK 25 -#define GCC_BIMC_MDSS_CLK 26 -#define GCC_BLSP1_AHB_CLK 27 -#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 -#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 -#define GCC_BLSP1_UART0_APPS_CLK 38 -#define GCC_BLSP1_UART1_APPS_CLK 39 -#define GCC_BLSP1_UART2_APPS_CLK 40 -#define GCC_BLSP1_UART3_APPS_CLK 41 -#define GCC_BLSP2_AHB_CLK 42 -#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 -#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 -#define GCC_BLSP2_UART0_APPS_CLK 45 -#define GCC_BOOT_ROM_AHB_CLK 46 -#define GCC_DCC_CLK 47 -#define GCC_GENI_IR_H_CLK 48 -#define GCC_ETH_AXI_CLK 49 -#define GCC_ETH_PTP_CLK 50 -#define GCC_ETH_RGMII_CLK 51 -#define GCC_ETH_SLAVE_AHB_CLK 52 -#define GCC_GENI_IR_S_CLK 53 -#define GCC_GP1_CLK 54 -#define GCC_GP2_CLK 55 -#define GCC_GP3_CLK 56 -#define GCC_MDSS_AHB_CLK 57 -#define GCC_MDSS_AXI_CLK 58 -#define GCC_MDSS_BYTE0_CLK 59 -#define GCC_MDSS_ESC0_CLK 60 -#define GCC_MDSS_HDMI_APP_CLK 61 -#define GCC_MDSS_HDMI_PCLK_CLK 62 -#define GCC_MDSS_MDP_CLK 63 -#define GCC_MDSS_PCLK0_CLK 64 -#define GCC_MDSS_VSYNC_CLK 65 -#define GCC_OXILI_AHB_CLK 66 -#define GCC_OXILI_GFX3D_CLK 67 -#define GCC_PCIE_0_AUX_CLK 68 -#define GCC_PCIE_0_CFG_AHB_CLK 69 -#define GCC_PCIE_0_MSTR_AXI_CLK 70 -#define GCC_PCIE_0_PIPE_CLK 71 -#define GCC_PCIE_0_SLV_AXI_CLK 72 -#define GCC_PCNOC_USB2_CLK 73 -#define GCC_PCNOC_USB3_CLK 74 -#define GCC_PDM2_CLK 75 -#define GCC_PDM_AHB_CLK 76 -#define GCC_VSYNC_CLK_SRC 77 -#define GCC_PRNG_AHB_CLK 78 -#define GCC_PWM0_XO512_CLK 79 -#define GCC_PWM1_XO512_CLK 80 -#define GCC_PWM2_XO512_CLK 81 -#define GCC_SDCC1_AHB_CLK 82 -#define GCC_SDCC1_APPS_CLK 83 -#define GCC_SDCC1_ICE_CORE_CLK 84 -#define GCC_SDCC2_AHB_CLK 85 -#define GCC_SDCC2_APPS_CLK 86 -#define GCC_SYS_NOC_USB3_CLK 87 -#define GCC_USB20_MOCK_UTMI_CLK 88 -#define GCC_USB2A_PHY_SLEEP_CLK 89 -#define GCC_USB30_MASTER_CLK 90 -#define GCC_USB30_MOCK_UTMI_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB3_PHY_AUX_CLK 93 -#define GCC_USB3_PHY_PIPE_CLK 94 -#define GCC_USB_HS_PHY_CFG_AHB_CLK 95 -#define GCC_USB_HS_SYSTEM_CLK 96 -#define GCC_GFX3D_CLK_SRC 97 -#define GCC_GP1_CLK_SRC 98 -#define GCC_GP2_CLK_SRC 99 -#define GCC_GP3_CLK_SRC 100 -#define GCC_GPLL0_OUT_MAIN 101 -#define GCC_GPLL1_OUT_MAIN 102 -#define GCC_GPLL3_OUT_MAIN 103 -#define GCC_GPLL4_OUT_MAIN 104 -#define GCC_HDMI_APP_CLK_SRC 105 -#define GCC_HDMI_PCLK_CLK_SRC 106 -#define GCC_MDP_CLK_SRC 107 -#define GCC_PCIE_0_AUX_CLK_SRC 108 -#define GCC_PCIE_0_PIPE_CLK_SRC 109 -#define GCC_PCLK0_CLK_SRC 110 -#define GCC_PDM2_CLK_SRC 111 -#define GCC_SDCC1_APPS_CLK_SRC 112 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 113 -#define GCC_SDCC2_APPS_CLK_SRC 114 -#define GCC_USB20_MOCK_UTMI_CLK_SRC 115 -#define GCC_USB30_MASTER_CLK_SRC 116 -#define GCC_USB30_MOCK_UTMI_CLK_SRC 117 -#define GCC_USB3_PHY_AUX_CLK_SRC 118 -#define GCC_USB_HS_SYSTEM_CLK_SRC 119 -#define GCC_GPLL0_AO_CLK_SRC 120 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 -#define GCC_GPLL0_AO_OUT_MAIN 123 -#define GCC_GPLL0_SLEEP_CLK_SRC 124 -#define GCC_GPLL6 125 -#define GCC_GPLL6_OUT_AUX 126 -#define GCC_MDSS_MDP_VOTE_CLK 127 -#define GCC_MDSS_ROTATOR_VOTE_CLK 128 -#define GCC_BIMC_GPU_CLK 129 -#define GCC_GTCU_AHB_CLK 130 -#define GCC_GFX_TCU_CLK 131 -#define GCC_GFX_TBU_CLK 132 -#define GCC_SMMU_CFG_CLK 133 -#define GCC_APSS_TCU_CLK 134 -#define GCC_CRYPTO_AHB_CLK 135 -#define GCC_CRYPTO_AXI_CLK 136 -#define GCC_CRYPTO_CLK 137 -#define GCC_MDP_TBU_CLK 138 -#define GCC_QDSS_DAP_CLK 139 -#define GCC_DCC_XO_CLK 140 -#define GCC_WCSS_Q6_AHB_CLK 141 -#define GCC_WCSS_Q6_AXIM_CLK 142 -#define GCC_CDSP_CFG_AHB_CLK 143 -#define GCC_BIMC_CDSP_CLK 144 -#define GCC_CDSP_TBU_CLK 145 -#define GCC_CDSP_BIMC_CLK_SRC 146 - -#define GCC_GENI_IR_BCR 0 -#define GCC_USB_HS_BCR 1 -#define GCC_USB2_HS_PHY_ONLY_BCR 2 -#define GCC_QUSB2_PHY_BCR 3 -#define GCC_USB_HS_PHY_CFG_AHB_BCR 4 -#define GCC_USB2A_PHY_BCR 5 -#define GCC_USB3_PHY_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB3PHY_PHY_BCR 8 -#define GCC_PCIE_0_BCR 9 -#define GCC_PCIE_0_PHY_BCR 10 -#define GCC_PCIE_0_LINK_DOWN_BCR 11 -#define GCC_PCIEPHY_0_PHY_BCR 12 -#define GCC_EMAC_BCR 13 -#define GCC_CDSP_RESTART 14 -#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 -#define GCC_PCIE_0_AHB_ARES 16 -#define GCC_PCIE_0_AXI_SLAVE_ARES 17 -#define GCC_PCIE_0_AXI_MASTER_ARES 18 -#define GCC_PCIE_0_CORE_STICKY_ARES 19 -#define GCC_PCIE_0_SLEEP_ARES 20 -#define GCC_PCIE_0_PIPE_ARES 21 -#define GCC_WDSP_RESTART 22 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h deleted file mode 100644 index 968fa65b9c42..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-sdm845.h +++ /dev/null @@ -1,246 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H - -/* GCC clock registers */ -#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 -#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 -#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 -#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 -#define GCC_AGGRE_USB3_SEC_AXI_CLK 4 -#define GCC_BOOT_ROM_AHB_CLK 5 -#define GCC_CAMERA_AHB_CLK 6 -#define GCC_CAMERA_AXI_CLK 7 -#define GCC_CAMERA_XO_CLK 8 -#define GCC_CE1_AHB_CLK 9 -#define GCC_CE1_AXI_CLK 10 -#define GCC_CE1_CLK 11 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 -#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 -#define GCC_CPUSS_AHB_CLK 14 -#define GCC_CPUSS_AHB_CLK_SRC 15 -#define GCC_CPUSS_RBCPR_CLK 16 -#define GCC_CPUSS_RBCPR_CLK_SRC 17 -#define GCC_DDRSS_GPU_AXI_CLK 18 -#define GCC_DISP_AHB_CLK 19 -#define GCC_DISP_AXI_CLK 20 -#define GCC_DISP_GPLL0_CLK_SRC 21 -#define GCC_DISP_GPLL0_DIV_CLK_SRC 22 -#define GCC_DISP_XO_CLK 23 -#define GCC_GP1_CLK 24 -#define GCC_GP1_CLK_SRC 25 -#define GCC_GP2_CLK 26 -#define GCC_GP2_CLK_SRC 27 -#define GCC_GP3_CLK 28 -#define GCC_GP3_CLK_SRC 29 -#define GCC_GPU_CFG_AHB_CLK 30 -#define GCC_GPU_GPLL0_CLK_SRC 31 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 32 -#define GCC_GPU_MEMNOC_GFX_CLK 33 -#define GCC_GPU_SNOC_DVM_GFX_CLK 34 -#define GCC_MSS_AXIS2_CLK 35 -#define GCC_MSS_CFG_AHB_CLK 36 -#define GCC_MSS_GPLL0_DIV_CLK_SRC 37 -#define GCC_MSS_MFAB_AXIS_CLK 38 -#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 -#define GCC_MSS_SNOC_AXI_CLK 40 -#define GCC_PCIE_0_AUX_CLK 41 -#define GCC_PCIE_0_AUX_CLK_SRC 42 -#define GCC_PCIE_0_CFG_AHB_CLK 43 -#define GCC_PCIE_0_CLKREF_CLK 44 -#define GCC_PCIE_0_MSTR_AXI_CLK 45 -#define GCC_PCIE_0_PIPE_CLK 46 -#define GCC_PCIE_0_SLV_AXI_CLK 47 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 -#define GCC_PCIE_1_AUX_CLK 49 -#define GCC_PCIE_1_AUX_CLK_SRC 50 -#define GCC_PCIE_1_CFG_AHB_CLK 51 -#define GCC_PCIE_1_CLKREF_CLK 52 -#define GCC_PCIE_1_MSTR_AXI_CLK 53 -#define GCC_PCIE_1_PIPE_CLK 54 -#define GCC_PCIE_1_SLV_AXI_CLK 55 -#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 -#define GCC_PCIE_PHY_AUX_CLK 57 -#define GCC_PCIE_PHY_REFGEN_CLK 58 -#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 -#define GCC_PDM2_CLK 60 -#define GCC_PDM2_CLK_SRC 61 -#define GCC_PDM_AHB_CLK 62 -#define GCC_PDM_XO4_CLK 63 -#define GCC_PRNG_AHB_CLK 64 -#define GCC_QMIP_CAMERA_AHB_CLK 65 -#define GCC_QMIP_DISP_AHB_CLK 66 -#define GCC_QMIP_VIDEO_AHB_CLK 67 -#define GCC_QUPV3_WRAP0_S0_CLK 68 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 -#define GCC_QUPV3_WRAP0_S1_CLK 70 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 -#define GCC_QUPV3_WRAP0_S2_CLK 72 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 -#define GCC_QUPV3_WRAP0_S3_CLK 74 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 -#define GCC_QUPV3_WRAP0_S4_CLK 76 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 -#define GCC_QUPV3_WRAP0_S5_CLK 78 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 -#define GCC_QUPV3_WRAP0_S6_CLK 80 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 -#define GCC_QUPV3_WRAP0_S7_CLK 82 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 -#define GCC_QUPV3_WRAP1_S0_CLK 84 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 -#define GCC_QUPV3_WRAP1_S1_CLK 86 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 -#define GCC_QUPV3_WRAP1_S2_CLK 88 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 -#define GCC_QUPV3_WRAP1_S3_CLK 90 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 -#define GCC_QUPV3_WRAP1_S4_CLK 92 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 -#define GCC_QUPV3_WRAP1_S5_CLK 94 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 -#define GCC_QUPV3_WRAP1_S6_CLK 96 -#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 -#define GCC_QUPV3_WRAP1_S7_CLK 98 -#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC2_APPS_CLK 105 -#define GCC_SDCC2_APPS_CLK_SRC 106 -#define GCC_SDCC4_AHB_CLK 107 -#define GCC_SDCC4_APPS_CLK 108 -#define GCC_SDCC4_APPS_CLK_SRC 109 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 110 -#define GCC_TSIF_AHB_CLK 111 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 -#define GCC_TSIF_REF_CLK 113 -#define GCC_TSIF_REF_CLK_SRC 114 -#define GCC_UFS_CARD_AHB_CLK 115 -#define GCC_UFS_CARD_AXI_CLK 116 -#define GCC_UFS_CARD_AXI_CLK_SRC 117 -#define GCC_UFS_CARD_CLKREF_CLK 118 -#define GCC_UFS_CARD_ICE_CORE_CLK 119 -#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 -#define GCC_UFS_CARD_PHY_AUX_CLK 121 -#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 -#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 -#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 -#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 -#define GCC_UFS_MEM_CLKREF_CLK 128 -#define GCC_UFS_PHY_AHB_CLK 129 -#define GCC_UFS_PHY_AXI_CLK 130 -#define GCC_UFS_PHY_AXI_CLK_SRC 131 -#define GCC_UFS_PHY_ICE_CORE_CLK 132 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 -#define GCC_UFS_PHY_PHY_AUX_CLK 134 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 -#define GCC_USB30_PRIM_MASTER_CLK 141 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 142 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 -#define GCC_USB30_PRIM_SLEEP_CLK 145 -#define GCC_USB30_SEC_MASTER_CLK 146 -#define GCC_USB30_SEC_MASTER_CLK_SRC 147 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 148 -#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 -#define GCC_USB30_SEC_SLEEP_CLK 150 -#define GCC_USB3_PRIM_CLKREF_CLK 151 -#define GCC_USB3_PRIM_PHY_AUX_CLK 152 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 155 -#define GCC_USB3_SEC_CLKREF_CLK 156 -#define GCC_USB3_SEC_PHY_AUX_CLK 157 -#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 -#define GCC_USB3_SEC_PHY_PIPE_CLK 159 -#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 -#define GCC_VIDEO_AHB_CLK 162 -#define GCC_VIDEO_AXI_CLK 163 -#define GCC_VIDEO_XO_CLK 164 -#define GPLL0 165 -#define GPLL0_OUT_EVEN 166 -#define GPLL0_OUT_MAIN 167 -#define GCC_GPU_IREF_CLK 168 -#define GCC_SDCC1_AHB_CLK 169 -#define GCC_SDCC1_APPS_CLK 170 -#define GCC_SDCC1_ICE_CORE_CLK 171 -#define GCC_SDCC1_APPS_CLK_SRC 172 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 -#define GCC_APC_VS_CLK 174 -#define GCC_GPU_VS_CLK 175 -#define GCC_MSS_VS_CLK 176 -#define GCC_VDDA_VS_CLK 177 -#define GCC_VDDCX_VS_CLK 178 -#define GCC_VDDMX_VS_CLK 179 -#define GCC_VS_CTRL_AHB_CLK 180 -#define GCC_VS_CTRL_CLK 181 -#define GCC_VS_CTRL_CLK_SRC 182 -#define GCC_VSENSOR_CLK_SRC 183 -#define GPLL4 184 -#define GCC_CPUSS_DVM_BUS_CLK 185 -#define GCC_CPUSS_GNOC_CLK 186 -#define GCC_QSPI_CORE_CLK_SRC 187 -#define GCC_QSPI_CORE_CLK 188 -#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 -#define GCC_LPASS_Q6_AXI_CLK 190 -#define GCC_LPASS_SWAY_CLK 191 - -/* GCC Resets */ -#define GCC_MMSS_BCR 0 -#define GCC_PCIE_0_BCR 1 -#define GCC_PCIE_1_BCR 2 -#define GCC_PCIE_PHY_BCR 3 -#define GCC_PDM_BCR 4 -#define GCC_PRNG_BCR 5 -#define GCC_QUPV3_WRAPPER_0_BCR 6 -#define GCC_QUPV3_WRAPPER_1_BCR 7 -#define GCC_QUSB2PHY_PRIM_BCR 8 -#define GCC_QUSB2PHY_SEC_BCR 9 -#define GCC_SDCC2_BCR 10 -#define GCC_SDCC4_BCR 11 -#define GCC_TSIF_BCR 12 -#define GCC_UFS_CARD_BCR 13 -#define GCC_UFS_PHY_BCR 14 -#define GCC_USB30_PRIM_BCR 15 -#define GCC_USB30_SEC_BCR 16 -#define GCC_USB3_PHY_PRIM_BCR 17 -#define GCC_USB3PHY_PHY_PRIM_BCR 18 -#define GCC_USB3_DP_PHY_PRIM_BCR 19 -#define GCC_USB3_PHY_SEC_BCR 20 -#define GCC_USB3PHY_PHY_SEC_BCR 21 -#define GCC_USB3_DP_PHY_SEC_BCR 22 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 -#define GCC_PCIE_0_PHY_BCR 24 -#define GCC_PCIE_1_PHY_BCR 25 - -/* GCC GDSCRs */ -#define PCIE_0_GDSC 0 -#define PCIE_1_GDSC 1 -#define UFS_CARD_GDSC 2 -#define UFS_PHY_GDSC 3 -#define USB30_PRIM_GDSC 4 -#define USB30_SEC_GDSC 5 -#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6 -#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 -#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12 - -#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h deleted file mode 100644 index 9690d901b50a..000000000000 --- a/include/dt-bindings/clock/qcom,gpucc-sdm845.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H - -/* GPU_CC clock registers */ -#define GPU_CC_CX_GMU_CLK 0 -#define GPU_CC_CXO_CLK 1 -#define GPU_CC_GMU_CLK_SRC 2 -#define GPU_CC_PLL1 3 - -/* GPU_CC Resets */ -#define GPUCC_GPU_CC_CX_BCR 0 -#define GPUCC_GPU_CC_GMU_BCR 1 -#define GPUCC_GPU_CC_XO_BCR 2 - -/* GPU_CC GDSCRs */ -#define GPU_CX_GDSC 0 -#define GPU_GX_GDSC 1 - -#endif diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h deleted file mode 100644 index 659050846f61..000000000000 --- a/include/dt-bindings/clock/qcom,lpass-sdm845.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H -#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H - -#define LPASS_Q6SS_AHBM_AON_CLK 0 -#define LPASS_Q6SS_AHBS_AON_CLK 1 -#define LPASS_QDSP6SS_XO_CLK 2 -#define LPASS_QDSP6SS_SLEEP_CLK 3 -#define LPASS_QDSP6SS_CORE_CLK 4 - -#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h deleted file mode 100644 index d51f9ac70566..000000000000 --- a/include/dt-bindings/clock/qcom,mmcc-msm8996.h +++ /dev/null @@ -1,295 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H - -#define MMPLL0_EARLY 0 -#define MMPLL0_PLL 1 -#define MMPLL1_EARLY 2 -#define MMPLL1_PLL 3 -#define MMPLL2_EARLY 4 -#define MMPLL2_PLL 5 -#define MMPLL3_EARLY 6 -#define MMPLL3_PLL 7 -#define MMPLL4_EARLY 8 -#define MMPLL4_PLL 9 -#define MMPLL5_EARLY 10 -#define MMPLL5_PLL 11 -#define MMPLL8_EARLY 12 -#define MMPLL8_PLL 13 -#define MMPLL9_EARLY 14 -#define MMPLL9_PLL 15 -#define AHB_CLK_SRC 16 -#define AXI_CLK_SRC 17 -#define MAXI_CLK_SRC 18 -#define DSA_CORE_CLK_SRC 19 -#define GFX3D_CLK_SRC 20 -#define RBBMTIMER_CLK_SRC 21 -#define ISENSE_CLK_SRC 22 -#define RBCPR_CLK_SRC 23 -#define VIDEO_CORE_CLK_SRC 24 -#define VIDEO_SUBCORE0_CLK_SRC 25 -#define VIDEO_SUBCORE1_CLK_SRC 26 -#define PCLK0_CLK_SRC 27 -#define PCLK1_CLK_SRC 28 -#define MDP_CLK_SRC 29 -#define EXTPCLK_CLK_SRC 30 -#define VSYNC_CLK_SRC 31 -#define HDMI_CLK_SRC 32 -#define BYTE0_CLK_SRC 33 -#define BYTE1_CLK_SRC 34 -#define ESC0_CLK_SRC 35 -#define ESC1_CLK_SRC 36 -#define CAMSS_GP0_CLK_SRC 37 -#define CAMSS_GP1_CLK_SRC 38 -#define MCLK0_CLK_SRC 39 -#define MCLK1_CLK_SRC 40 -#define MCLK2_CLK_SRC 41 -#define MCLK3_CLK_SRC 42 -#define CCI_CLK_SRC 43 -#define CSI0PHYTIMER_CLK_SRC 44 -#define CSI1PHYTIMER_CLK_SRC 45 -#define CSI2PHYTIMER_CLK_SRC 46 -#define CSIPHY0_3P_CLK_SRC 47 -#define CSIPHY1_3P_CLK_SRC 48 -#define CSIPHY2_3P_CLK_SRC 49 -#define JPEG0_CLK_SRC 50 -#define JPEG2_CLK_SRC 51 -#define JPEG_DMA_CLK_SRC 52 -#define VFE0_CLK_SRC 53 -#define VFE1_CLK_SRC 54 -#define CPP_CLK_SRC 55 -#define CSI0_CLK_SRC 56 -#define CSI1_CLK_SRC 57 -#define CSI2_CLK_SRC 58 -#define CSI3_CLK_SRC 59 -#define FD_CORE_CLK_SRC 60 -#define MMSS_CXO_CLK 61 -#define MMSS_SLEEPCLK_CLK 62 -#define MMSS_MMAGIC_AHB_CLK 63 -#define MMSS_MMAGIC_CFG_AHB_CLK 64 -#define MMSS_MISC_AHB_CLK 65 -#define MMSS_MISC_CXO_CLK 66 -#define MMSS_BTO_AHB_CLK 67 -#define MMSS_MMAGIC_AXI_CLK 68 -#define MMSS_S0_AXI_CLK 69 -#define MMSS_MMAGIC_MAXI_CLK 70 -#define DSA_CORE_CLK 71 -#define DSA_NOC_CFG_AHB_CLK 72 -#define MMAGIC_CAMSS_AXI_CLK 73 -#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 -#define THROTTLE_CAMSS_CXO_CLK 75 -#define THROTTLE_CAMSS_AHB_CLK 76 -#define THROTTLE_CAMSS_AXI_CLK 77 -#define SMMU_VFE_AHB_CLK 78 -#define SMMU_VFE_AXI_CLK 79 -#define SMMU_CPP_AHB_CLK 80 -#define SMMU_CPP_AXI_CLK 81 -#define SMMU_JPEG_AHB_CLK 82 -#define SMMU_JPEG_AXI_CLK 83 -#define MMAGIC_MDSS_AXI_CLK 84 -#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 -#define THROTTLE_MDSS_CXO_CLK 86 -#define THROTTLE_MDSS_AHB_CLK 87 -#define THROTTLE_MDSS_AXI_CLK 88 -#define SMMU_ROT_AHB_CLK 89 -#define SMMU_ROT_AXI_CLK 90 -#define SMMU_MDP_AHB_CLK 91 -#define SMMU_MDP_AXI_CLK 92 -#define MMAGIC_VIDEO_AXI_CLK 93 -#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 -#define THROTTLE_VIDEO_CXO_CLK 95 -#define THROTTLE_VIDEO_AHB_CLK 96 -#define THROTTLE_VIDEO_AXI_CLK 97 -#define SMMU_VIDEO_AHB_CLK 98 -#define SMMU_VIDEO_AXI_CLK 99 -#define MMAGIC_BIMC_AXI_CLK 100 -#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 -#define GPU_GX_GFX3D_CLK 102 -#define GPU_GX_RBBMTIMER_CLK 103 -#define GPU_AHB_CLK 104 -#define GPU_AON_ISENSE_CLK 105 -#define VMEM_MAXI_CLK 106 -#define VMEM_AHB_CLK 107 -#define MMSS_RBCPR_CLK 108 -#define MMSS_RBCPR_AHB_CLK 109 -#define VIDEO_CORE_CLK 110 -#define VIDEO_AXI_CLK 111 -#define VIDEO_MAXI_CLK 112 -#define VIDEO_AHB_CLK 113 -#define VIDEO_SUBCORE0_CLK 114 -#define VIDEO_SUBCORE1_CLK 115 -#define MDSS_AHB_CLK 116 -#define MDSS_HDMI_AHB_CLK 117 -#define MDSS_AXI_CLK 118 -#define MDSS_PCLK0_CLK 119 -#define MDSS_PCLK1_CLK 120 -#define MDSS_MDP_CLK 121 -#define MDSS_EXTPCLK_CLK 122 -#define MDSS_VSYNC_CLK 123 -#define MDSS_HDMI_CLK 124 -#define MDSS_BYTE0_CLK 125 -#define MDSS_BYTE1_CLK 126 -#define MDSS_ESC0_CLK 127 -#define MDSS_ESC1_CLK 128 -#define CAMSS_TOP_AHB_CLK 129 -#define CAMSS_AHB_CLK 130 -#define CAMSS_MICRO_AHB_CLK 131 -#define CAMSS_GP0_CLK 132 -#define CAMSS_GP1_CLK 133 -#define CAMSS_MCLK0_CLK 134 -#define CAMSS_MCLK1_CLK 135 -#define CAMSS_MCLK2_CLK 136 -#define CAMSS_MCLK3_CLK 137 -#define CAMSS_CCI_CLK 138 -#define CAMSS_CCI_AHB_CLK 139 -#define CAMSS_CSI0PHYTIMER_CLK 140 -#define CAMSS_CSI1PHYTIMER_CLK 141 -#define CAMSS_CSI2PHYTIMER_CLK 142 -#define CAMSS_CSIPHY0_3P_CLK 143 -#define CAMSS_CSIPHY1_3P_CLK 144 -#define CAMSS_CSIPHY2_3P_CLK 145 -#define CAMSS_JPEG0_CLK 146 -#define CAMSS_JPEG2_CLK 147 -#define CAMSS_JPEG_DMA_CLK 148 -#define CAMSS_JPEG_AHB_CLK 149 -#define CAMSS_JPEG_AXI_CLK 150 -#define CAMSS_VFE_AHB_CLK 151 -#define CAMSS_VFE_AXI_CLK 152 -#define CAMSS_VFE0_CLK 153 -#define CAMSS_VFE0_STREAM_CLK 154 -#define CAMSS_VFE0_AHB_CLK 155 -#define CAMSS_VFE1_CLK 156 -#define CAMSS_VFE1_STREAM_CLK 157 -#define CAMSS_VFE1_AHB_CLK 158 -#define CAMSS_CSI_VFE0_CLK 159 -#define CAMSS_CSI_VFE1_CLK 160 -#define CAMSS_CPP_VBIF_AHB_CLK 161 -#define CAMSS_CPP_AXI_CLK 162 -#define CAMSS_CPP_CLK 163 -#define CAMSS_CPP_AHB_CLK 164 -#define CAMSS_CSI0_CLK 165 -#define CAMSS_CSI0_AHB_CLK 166 -#define CAMSS_CSI0PHY_CLK 167 -#define CAMSS_CSI0RDI_CLK 168 -#define CAMSS_CSI0PIX_CLK 169 -#define CAMSS_CSI1_CLK 170 -#define CAMSS_CSI1_AHB_CLK 171 -#define CAMSS_CSI1PHY_CLK 172 -#define CAMSS_CSI1RDI_CLK 173 -#define CAMSS_CSI1PIX_CLK 174 -#define CAMSS_CSI2_CLK 175 -#define CAMSS_CSI2_AHB_CLK 176 -#define CAMSS_CSI2PHY_CLK 177 -#define CAMSS_CSI2RDI_CLK 178 -#define CAMSS_CSI2PIX_CLK 179 -#define CAMSS_CSI3_CLK 180 -#define CAMSS_CSI3_AHB_CLK 181 -#define CAMSS_CSI3PHY_CLK 182 -#define CAMSS_CSI3RDI_CLK 183 -#define CAMSS_CSI3PIX_CLK 184 -#define CAMSS_ISPIF_AHB_CLK 185 -#define FD_CORE_CLK 186 -#define FD_CORE_UAR_CLK 187 -#define FD_AHB_CLK 188 -#define MMSS_SPDM_CSI0_CLK 189 -#define MMSS_SPDM_JPEG_DMA_CLK 190 -#define MMSS_SPDM_CPP_CLK 191 -#define MMSS_SPDM_PCLK0_CLK 192 -#define MMSS_SPDM_AHB_CLK 193 -#define MMSS_SPDM_GFX3D_CLK 194 -#define MMSS_SPDM_PCLK1_CLK 195 -#define MMSS_SPDM_JPEG2_CLK 196 -#define MMSS_SPDM_DEBUG_CLK 197 -#define MMSS_SPDM_VFE1_CLK 198 -#define MMSS_SPDM_VFE0_CLK 199 -#define MMSS_SPDM_VIDEO_CORE_CLK 200 -#define MMSS_SPDM_AXI_CLK 201 -#define MMSS_SPDM_MDP_CLK 202 -#define MMSS_SPDM_JPEG0_CLK 203 -#define MMSS_SPDM_RM_AXI_CLK 204 -#define MMSS_SPDM_RM_MAXI_CLK 205 - -#define MMAGICAHB_BCR 0 -#define MMAGIC_CFG_BCR 1 -#define MISC_BCR 2 -#define BTO_BCR 3 -#define MMAGICAXI_BCR 4 -#define MMAGICMAXI_BCR 5 -#define DSA_BCR 6 -#define MMAGIC_CAMSS_BCR 7 -#define THROTTLE_CAMSS_BCR 8 -#define SMMU_VFE_BCR 9 -#define SMMU_CPP_BCR 10 -#define SMMU_JPEG_BCR 11 -#define MMAGIC_MDSS_BCR 12 -#define THROTTLE_MDSS_BCR 13 -#define SMMU_ROT_BCR 14 -#define SMMU_MDP_BCR 15 -#define MMAGIC_VIDEO_BCR 16 -#define THROTTLE_VIDEO_BCR 17 -#define SMMU_VIDEO_BCR 18 -#define MMAGIC_BIMC_BCR 19 -#define GPU_GX_BCR 20 -#define GPU_BCR 21 -#define GPU_AON_BCR 22 -#define VMEM_BCR 23 -#define MMSS_RBCPR_BCR 24 -#define VIDEO_BCR 25 -#define MDSS_BCR 26 -#define CAMSS_TOP_BCR 27 -#define CAMSS_AHB_BCR 28 -#define CAMSS_MICRO_BCR 29 -#define CAMSS_CCI_BCR 30 -#define CAMSS_PHY0_BCR 31 -#define CAMSS_PHY1_BCR 32 -#define CAMSS_PHY2_BCR 33 -#define CAMSS_CSIPHY0_3P_BCR 34 -#define CAMSS_CSIPHY1_3P_BCR 35 -#define CAMSS_CSIPHY2_3P_BCR 36 -#define CAMSS_JPEG_BCR 37 -#define CAMSS_VFE_BCR 38 -#define CAMSS_VFE0_BCR 39 -#define CAMSS_VFE1_BCR 40 -#define CAMSS_CSI_VFE0_BCR 41 -#define CAMSS_CSI_VFE1_BCR 42 -#define CAMSS_CPP_TOP_BCR 43 -#define CAMSS_CPP_BCR 44 -#define CAMSS_CSI0_BCR 45 -#define CAMSS_CSI0RDI_BCR 46 -#define CAMSS_CSI0PIX_BCR 47 -#define CAMSS_CSI1_BCR 48 -#define CAMSS_CSI1RDI_BCR 49 -#define CAMSS_CSI1PIX_BCR 50 -#define CAMSS_CSI2_BCR 51 -#define CAMSS_CSI2RDI_BCR 52 -#define CAMSS_CSI2PIX_BCR 53 -#define CAMSS_CSI3_BCR 54 -#define CAMSS_CSI3RDI_BCR 55 -#define CAMSS_CSI3PIX_BCR 56 -#define CAMSS_ISPIF_BCR 57 -#define FD_BCR 58 -#define MMSS_SPDM_RM_BCR 59 - -/* Indexes for GDSCs */ -#define MMAGIC_VIDEO_GDSC 0 -#define MMAGIC_MDSS_GDSC 1 -#define MMAGIC_CAMSS_GDSC 2 -#define GPU_GDSC 3 -#define VENUS_GDSC 4 -#define VENUS_CORE0_GDSC 5 -#define VENUS_CORE1_GDSC 6 -#define CAMSS_GDSC 7 -#define VFE0_GDSC 8 -#define VFE1_GDSC 9 -#define JPEG_GDSC 10 -#define CPP_GDSC 11 -#define FD_GDSC 12 -#define MDSS_GDSC 13 -#define GPU_GX_GDSC 14 -#define MMAGIC_BIMC_GDSC 15 - -#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h deleted file mode 100644 index 46309c9953b2..000000000000 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H -#define _DT_BINDINGS_CLK_MSM_RPMCC_H - -/* RPM clocks */ -#define RPM_PXO_CLK 0 -#define RPM_PXO_A_CLK 1 -#define RPM_CXO_CLK 2 -#define RPM_CXO_A_CLK 3 -#define RPM_APPS_FABRIC_CLK 4 -#define RPM_APPS_FABRIC_A_CLK 5 -#define RPM_CFPB_CLK 6 -#define RPM_CFPB_A_CLK 7 -#define RPM_QDSS_CLK 8 -#define RPM_QDSS_A_CLK 9 -#define RPM_DAYTONA_FABRIC_CLK 10 -#define RPM_DAYTONA_FABRIC_A_CLK 11 -#define RPM_EBI1_CLK 12 -#define RPM_EBI1_A_CLK 13 -#define RPM_MM_FABRIC_CLK 14 -#define RPM_MM_FABRIC_A_CLK 15 -#define RPM_MMFPB_CLK 16 -#define RPM_MMFPB_A_CLK 17 -#define RPM_SYS_FABRIC_CLK 18 -#define RPM_SYS_FABRIC_A_CLK 19 -#define RPM_SFPB_CLK 20 -#define RPM_SFPB_A_CLK 21 -#define RPM_SMI_CLK 22 -#define RPM_SMI_A_CLK 23 -#define RPM_PLL4_CLK 24 -#define RPM_XO_D0 25 -#define RPM_XO_D1 26 -#define RPM_XO_A0 27 -#define RPM_XO_A1 28 -#define RPM_XO_A2 29 -#define RPM_NSS_FABRIC_0_CLK 30 -#define RPM_NSS_FABRIC_0_A_CLK 31 -#define RPM_NSS_FABRIC_1_CLK 32 -#define RPM_NSS_FABRIC_1_A_CLK 33 - -/* SMD RPM clocks */ -#define RPM_SMD_XO_CLK_SRC 0 -#define RPM_SMD_XO_A_CLK_SRC 1 -#define RPM_SMD_PCNOC_CLK 2 -#define RPM_SMD_PCNOC_A_CLK 3 -#define RPM_SMD_SNOC_CLK 4 -#define RPM_SMD_SNOC_A_CLK 5 -#define RPM_SMD_BIMC_CLK 6 -#define RPM_SMD_BIMC_A_CLK 7 -#define RPM_SMD_QDSS_CLK 8 -#define RPM_SMD_QDSS_A_CLK 9 -#define RPM_SMD_BB_CLK1 10 -#define RPM_SMD_BB_CLK1_A 11 -#define RPM_SMD_BB_CLK2 12 -#define RPM_SMD_BB_CLK2_A 13 -#define RPM_SMD_RF_CLK1 14 -#define RPM_SMD_RF_CLK1_A 15 -#define RPM_SMD_RF_CLK2 16 -#define RPM_SMD_RF_CLK2_A 17 -#define RPM_SMD_BB_CLK1_PIN 18 -#define RPM_SMD_BB_CLK1_A_PIN 19 -#define RPM_SMD_BB_CLK2_PIN 20 -#define RPM_SMD_BB_CLK2_A_PIN 21 -#define RPM_SMD_RF_CLK1_PIN 22 -#define RPM_SMD_RF_CLK1_A_PIN 23 -#define RPM_SMD_RF_CLK2_PIN 24 -#define RPM_SMD_RF_CLK2_A_PIN 25 -#define RPM_SMD_PNOC_CLK 26 -#define RPM_SMD_PNOC_A_CLK 27 -#define RPM_SMD_CNOC_CLK 28 -#define RPM_SMD_CNOC_A_CLK 29 -#define RPM_SMD_MMSSNOC_AHB_CLK 30 -#define RPM_SMD_MMSSNOC_AHB_A_CLK 31 -#define RPM_SMD_GFX3D_CLK_SRC 32 -#define RPM_SMD_GFX3D_A_CLK_SRC 33 -#define RPM_SMD_OCMEMGX_CLK 34 -#define RPM_SMD_OCMEMGX_A_CLK 35 -#define RPM_SMD_CXO_D0 36 -#define RPM_SMD_CXO_D0_A 37 -#define RPM_SMD_CXO_D1 38 -#define RPM_SMD_CXO_D1_A 39 -#define RPM_SMD_CXO_A0 40 -#define RPM_SMD_CXO_A0_A 41 -#define RPM_SMD_CXO_A1 42 -#define RPM_SMD_CXO_A1_A 43 -#define RPM_SMD_CXO_A2 44 -#define RPM_SMD_CXO_A2_A 45 -#define RPM_SMD_DIV_CLK1 46 -#define RPM_SMD_DIV_A_CLK1 47 -#define RPM_SMD_DIV_CLK2 48 -#define RPM_SMD_DIV_A_CLK2 49 -#define RPM_SMD_DIFF_CLK 50 -#define RPM_SMD_DIFF_A_CLK 51 -#define RPM_SMD_CXO_D0_PIN 52 -#define RPM_SMD_CXO_D0_A_PIN 53 -#define RPM_SMD_CXO_D1_PIN 54 -#define RPM_SMD_CXO_D1_A_PIN 55 -#define RPM_SMD_CXO_A0_PIN 56 -#define RPM_SMD_CXO_A0_A_PIN 57 -#define RPM_SMD_CXO_A1_PIN 58 -#define RPM_SMD_CXO_A1_A_PIN 59 -#define RPM_SMD_CXO_A2_PIN 60 -#define RPM_SMD_CXO_A2_A_PIN 61 -#define RPM_SMD_AGGR1_NOC_CLK 62 -#define RPM_SMD_AGGR1_NOC_A_CLK 63 -#define RPM_SMD_AGGR2_NOC_CLK 64 -#define RPM_SMD_AGGR2_NOC_A_CLK 65 -#define RPM_SMD_MMAXI_CLK 66 -#define RPM_SMD_MMAXI_A_CLK 67 -#define RPM_SMD_IPA_CLK 68 -#define RPM_SMD_IPA_A_CLK 69 -#define RPM_SMD_CE1_CLK 70 -#define RPM_SMD_CE1_A_CLK 71 -#define RPM_SMD_DIV_CLK3 72 -#define RPM_SMD_DIV_A_CLK3 73 -#define RPM_SMD_LN_BB_CLK 74 -#define RPM_SMD_LN_BB_A_CLK 75 -#define RPM_SMD_BIMC_GPU_CLK 76 -#define RPM_SMD_BIMC_GPU_A_CLK 77 -#define RPM_SMD_QPIC_CLK 78 -#define RPM_SMD_QPIC_CLK_A 79 -#define RPM_SMD_LN_BB_CLK1 80 -#define RPM_SMD_LN_BB_CLK1_A 81 -#define RPM_SMD_LN_BB_CLK2 82 -#define RPM_SMD_LN_BB_CLK2_A 83 -#define RPM_SMD_LN_BB_CLK3_PIN 84 -#define RPM_SMD_LN_BB_CLK3_A_PIN 85 -#define RPM_SMD_RF_CLK3 86 -#define RPM_SMD_RF_CLK3_A 87 -#define RPM_SMD_RF_CLK3_PIN 88 -#define RPM_SMD_RF_CLK3_A_PIN 89 -#define RPM_SMD_MMSSNOC_AXI_CLK 90 -#define RPM_SMD_MMSSNOC_AXI_CLK_A 91 -#define RPM_SMD_CNOC_PERIPH_CLK 92 -#define RPM_SMD_CNOC_PERIPH_A_CLK 93 -#define RPM_SMD_LN_BB_CLK3 94 -#define RPM_SMD_LN_BB_CLK3_A 95 -#define RPM_SMD_LN_BB_CLK1_PIN 96 -#define RPM_SMD_LN_BB_CLK1_A_PIN 97 -#define RPM_SMD_LN_BB_CLK2_PIN 98 -#define RPM_SMD_LN_BB_CLK2_A_PIN 99 -#define RPM_SMD_SYSMMNOC_CLK 100 -#define RPM_SMD_SYSMMNOC_A_CLK 101 -#define RPM_SMD_CE2_CLK 102 -#define RPM_SMD_CE2_A_CLK 103 -#define RPM_SMD_CE3_CLK 104 -#define RPM_SMD_CE3_A_CLK 105 -#define RPM_SMD_QUP_CLK 106 -#define RPM_SMD_QUP_A_CLK 107 -#define RPM_SMD_MMRT_CLK 108 -#define RPM_SMD_MMRT_A_CLK 109 -#define RPM_SMD_MMNRT_CLK 110 -#define RPM_SMD_MMNRT_A_CLK 111 -#define RPM_SMD_SNOC_PERIPH_CLK 112 -#define RPM_SMD_SNOC_PERIPH_A_CLK 113 -#define RPM_SMD_SNOC_LPASS_CLK 114 -#define RPM_SMD_SNOC_LPASS_A_CLK 115 -#define RPM_SMD_HWKM_CLK 116 -#define RPM_SMD_HWKM_A_CLK 117 -#define RPM_SMD_PKA_CLK 118 -#define RPM_SMD_PKA_A_CLK 119 -#define RPM_SMD_CPUSS_GNOC_CLK 120 -#define RPM_SMD_CPUSS_GNOC_A_CLK 121 -#define RPM_SMD_MSS_CFG_AHB_CLK 122 -#define RPM_SMD_MSS_CFG_AHB_A_CLK 123 -#define RPM_SMD_BIMC_FREQ_LOG 124 -#define RPM_SMD_LN_BB_CLK_PIN 125 -#define RPM_SMD_LN_BB_A_CLK_PIN 126 - -#endif diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h deleted file mode 100644 index 0a7d1be0d124..000000000000 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */ - - -#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H -#define _DT_BINDINGS_CLK_MSM_RPMH_H - -/* RPMh controlled clocks */ -#define RPMH_CXO_CLK 0 -#define RPMH_CXO_CLK_A 1 -#define RPMH_LN_BB_CLK2 2 -#define RPMH_LN_BB_CLK2_A 3 -#define RPMH_LN_BB_CLK3 4 -#define RPMH_LN_BB_CLK3_A 5 -#define RPMH_RF_CLK1 6 -#define RPMH_RF_CLK1_A 7 -#define RPMH_RF_CLK2 8 -#define RPMH_RF_CLK2_A 9 -#define RPMH_RF_CLK3 10 -#define RPMH_RF_CLK3_A 11 -#define RPMH_IPA_CLK 12 -#define RPMH_LN_BB_CLK1 13 -#define RPMH_LN_BB_CLK1_A 14 -#define RPMH_CE_CLK 15 -#define RPMH_QPIC_CLK 16 -#define RPMH_DIV_CLK1 17 -#define RPMH_DIV_CLK1_A 18 -#define RPMH_RF_CLK4 19 -#define RPMH_RF_CLK4_A 20 -#define RPMH_RF_CLK5 21 -#define RPMH_RF_CLK5_A 22 -#define RPMH_PKA_CLK 23 -#define RPMH_HWKM_CLK 24 -#define RPMH_QLINK_CLK 25 -#define RPMH_QLINK_CLK_A 26 - -#endif diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h deleted file mode 100644 index 838faef57c67..000000000000 --- a/include/dt-bindings/clock/qcom,turingcc-qcs404.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019, Linaro Ltd - */ - -#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H -#define _DT_BINDINGS_CLK_TURING_QCS404_H - -#define TURING_Q6SS_Q6_AXIM_CLK 0 -#define TURING_Q6SS_AHBM_AON_CLK 1 -#define TURING_WRAPPER_AON_CLK 2 -#define TURING_Q6SS_AHBS_AON_CLK 3 -#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4 - -#endif diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h deleted file mode 100644 index 1b868165e8ce..000000000000 --- a/include/dt-bindings/clock/qcom,videocc-sdm845.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H - -/* VIDEO_CC clock registers */ -#define VIDEO_CC_APB_CLK 0 -#define VIDEO_CC_AT_CLK 1 -#define VIDEO_CC_QDSS_TRIG_CLK 2 -#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3 -#define VIDEO_CC_VCODEC0_AXI_CLK 4 -#define VIDEO_CC_VCODEC0_CORE_CLK 5 -#define VIDEO_CC_VCODEC1_AXI_CLK 6 -#define VIDEO_CC_VCODEC1_CORE_CLK 7 -#define VIDEO_CC_VENUS_AHB_CLK 8 -#define VIDEO_CC_VENUS_CLK_SRC 9 -#define VIDEO_CC_VENUS_CTL_AXI_CLK 10 -#define VIDEO_CC_VENUS_CTL_CORE_CLK 11 -#define VIDEO_PLL0 12 - -/* VIDEO_CC Resets */ -#define VIDEO_CC_VENUS_BCR 0 -#define VIDEO_CC_VCODEC0_BCR 1 -#define VIDEO_CC_VCODEC1_BCR 2 -#define VIDEO_CC_INTERFACE_BCR 3 - -/* VIDEO_CC GDSCRs */ -#define VENUS_GDSC 0 -#define VCODEC0_GDSC 1 -#define VCODEC1_GDSC 2 - -#endif

Drop in favour of dts/upstream

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/sun20i-d1-ccu.h | 158 -------------------- include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 --- include/dt-bindings/clock/sun4i-a10-ccu.h | 202 -------------------------- include/dt-bindings/clock/sun4i-a10-pll2.h | 53 ------- include/dt-bindings/clock/sun50i-a64-ccu.h | 138 ------------------ include/dt-bindings/clock/sun50i-h6-ccu.h | 125 ---------------- include/dt-bindings/clock/sun50i-h6-r-ccu.h | 27 ---- include/dt-bindings/clock/sun50i-h616-ccu.h | 116 --------------- include/dt-bindings/clock/sun5i-ccu.h | 97 ------------- include/dt-bindings/clock/sun6i-a31-ccu.h | 193 ------------------------ include/dt-bindings/clock/sun6i-rtc.h | 10 -- include/dt-bindings/clock/sun7i-a20-ccu.h | 53 ------- include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 129 ---------------- include/dt-bindings/clock/sun8i-a83t-ccu.h | 140 ------------------ include/dt-bindings/clock/sun8i-de2.h | 21 --- include/dt-bindings/clock/sun8i-h3-ccu.h | 152 ------------------- include/dt-bindings/clock/sun8i-r-ccu.h | 59 -------- include/dt-bindings/clock/sun8i-r40-ccu.h | 191 ------------------------ include/dt-bindings/clock/sun8i-tcon-top.h | 11 -- include/dt-bindings/clock/sun8i-v3s-ccu.h | 111 -------------- include/dt-bindings/clock/sun9i-a80-ccu.h | 162 --------------------- include/dt-bindings/clock/sun9i-a80-de.h | 80 ---------- include/dt-bindings/clock/sun9i-a80-usb.h | 59 -------- include/dt-bindings/clock/suniv-ccu-f1c100s.h | 72 --------- 24 files changed, 2378 deletions(-)

diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h deleted file mode 100644 index fdbfb404f92a..000000000000 --- a/include/dt-bindings/clock/sun20i-d1-ccu.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2020 huangzhenwei@allwinnertech.com - * Copyright (C) 2021 Samuel Holland samuel@sholland.org - */ - -#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ -#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ - -#define CLK_PLL_CPUX 0 -#define CLK_PLL_DDR0 1 -#define CLK_PLL_PERIPH0_4X 2 -#define CLK_PLL_PERIPH0_2X 3 -#define CLK_PLL_PERIPH0_800M 4 -#define CLK_PLL_PERIPH0 5 -#define CLK_PLL_PERIPH0_DIV3 6 -#define CLK_PLL_VIDEO0_4X 7 -#define CLK_PLL_VIDEO0_2X 8 -#define CLK_PLL_VIDEO0 9 -#define CLK_PLL_VIDEO1_4X 10 -#define CLK_PLL_VIDEO1_2X 11 -#define CLK_PLL_VIDEO1 12 -#define CLK_PLL_VE 13 -#define CLK_PLL_AUDIO0_4X 14 -#define CLK_PLL_AUDIO0_2X 15 -#define CLK_PLL_AUDIO0 16 -#define CLK_PLL_AUDIO1 17 -#define CLK_PLL_AUDIO1_DIV2 18 -#define CLK_PLL_AUDIO1_DIV5 19 -#define CLK_CPUX 20 -#define CLK_CPUX_AXI 21 -#define CLK_CPUX_APB 22 -#define CLK_PSI_AHB 23 -#define CLK_APB0 24 -#define CLK_APB1 25 -#define CLK_MBUS 26 -#define CLK_DE 27 -#define CLK_BUS_DE 28 -#define CLK_DI 29 -#define CLK_BUS_DI 30 -#define CLK_G2D 31 -#define CLK_BUS_G2D 32 -#define CLK_CE 33 -#define CLK_BUS_CE 34 -#define CLK_VE 35 -#define CLK_BUS_VE 36 -#define CLK_BUS_DMA 37 -#define CLK_BUS_MSGBOX0 38 -#define CLK_BUS_MSGBOX1 39 -#define CLK_BUS_MSGBOX2 40 -#define CLK_BUS_SPINLOCK 41 -#define CLK_BUS_HSTIMER 42 -#define CLK_AVS 43 -#define CLK_BUS_DBG 44 -#define CLK_BUS_PWM 45 -#define CLK_BUS_IOMMU 46 -#define CLK_DRAM 47 -#define CLK_MBUS_DMA 48 -#define CLK_MBUS_VE 49 -#define CLK_MBUS_CE 50 -#define CLK_MBUS_TVIN 51 -#define CLK_MBUS_CSI 52 -#define CLK_MBUS_G2D 53 -#define CLK_MBUS_RISCV 54 -#define CLK_BUS_DRAM 55 -#define CLK_MMC0 56 -#define CLK_MMC1 57 -#define CLK_MMC2 58 -#define CLK_BUS_MMC0 59 -#define CLK_BUS_MMC1 60 -#define CLK_BUS_MMC2 61 -#define CLK_BUS_UART0 62 -#define CLK_BUS_UART1 63 -#define CLK_BUS_UART2 64 -#define CLK_BUS_UART3 65 -#define CLK_BUS_UART4 66 -#define CLK_BUS_UART5 67 -#define CLK_BUS_I2C0 68 -#define CLK_BUS_I2C1 69 -#define CLK_BUS_I2C2 70 -#define CLK_BUS_I2C3 71 -#define CLK_SPI0 72 -#define CLK_SPI1 73 -#define CLK_BUS_SPI0 74 -#define CLK_BUS_SPI1 75 -#define CLK_EMAC_25M 76 -#define CLK_BUS_EMAC 77 -#define CLK_IR_TX 78 -#define CLK_BUS_IR_TX 79 -#define CLK_BUS_GPADC 80 -#define CLK_BUS_THS 81 -#define CLK_I2S0 82 -#define CLK_I2S1 83 -#define CLK_I2S2 84 -#define CLK_I2S2_ASRC 85 -#define CLK_BUS_I2S0 86 -#define CLK_BUS_I2S1 87 -#define CLK_BUS_I2S2 88 -#define CLK_SPDIF_TX 89 -#define CLK_SPDIF_RX 90 -#define CLK_BUS_SPDIF 91 -#define CLK_DMIC 92 -#define CLK_BUS_DMIC 93 -#define CLK_AUDIO_DAC 94 -#define CLK_AUDIO_ADC 95 -#define CLK_BUS_AUDIO 96 -#define CLK_USB_OHCI0 97 -#define CLK_USB_OHCI1 98 -#define CLK_BUS_OHCI0 99 -#define CLK_BUS_OHCI1 100 -#define CLK_BUS_EHCI0 101 -#define CLK_BUS_EHCI1 102 -#define CLK_BUS_OTG 103 -#define CLK_BUS_LRADC 104 -#define CLK_BUS_DPSS_TOP 105 -#define CLK_HDMI_24M 106 -#define CLK_HDMI_CEC_32K 107 -#define CLK_HDMI_CEC 108 -#define CLK_BUS_HDMI 109 -#define CLK_MIPI_DSI 110 -#define CLK_BUS_MIPI_DSI 111 -#define CLK_TCON_LCD0 112 -#define CLK_BUS_TCON_LCD0 113 -#define CLK_TCON_TV 114 -#define CLK_BUS_TCON_TV 115 -#define CLK_TVE 116 -#define CLK_BUS_TVE_TOP 117 -#define CLK_BUS_TVE 118 -#define CLK_TVD 119 -#define CLK_BUS_TVD_TOP 120 -#define CLK_BUS_TVD 121 -#define CLK_LEDC 122 -#define CLK_BUS_LEDC 123 -#define CLK_CSI_TOP 124 -#define CLK_CSI_MCLK 125 -#define CLK_BUS_CSI 126 -#define CLK_TPADC 127 -#define CLK_BUS_TPADC 128 -#define CLK_BUS_TZMA 129 -#define CLK_DSP 130 -#define CLK_BUS_DSP_CFG 131 -#define CLK_RISCV 132 -#define CLK_RISCV_AXI 133 -#define CLK_BUS_RISCV_CFG 134 -#define CLK_FANOUT_24M 135 -#define CLK_FANOUT_12M 136 -#define CLK_FANOUT_16M 137 -#define CLK_FANOUT_25M 138 -#define CLK_FANOUT_32K 139 -#define CLK_FANOUT_27M 140 -#define CLK_FANOUT_PCLK 141 -#define CLK_FANOUT0 142 -#define CLK_FANOUT1 143 -#define CLK_FANOUT2 144 -#define CLK_BUS_CAN0 145 -#define CLK_BUS_CAN1 146 - -#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h deleted file mode 100644 index f95c170711e5..000000000000 --- a/include/dt-bindings/clock/sun20i-d1-r-ccu.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2021 Samuel Holland samuel@sholland.org - */ - -#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ - -#define CLK_R_AHB 0 - -#define CLK_BUS_R_TIMER 2 -#define CLK_BUS_R_TWD 3 -#define CLK_BUS_R_PPU 4 -#define CLK_R_IR_RX 5 -#define CLK_BUS_R_IR_RX 6 -#define CLK_BUS_R_RTC 7 -#define CLK_BUS_R_CPUCFG 8 - -#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h deleted file mode 100644 index e4fa61be5c75..000000000000 --- a/include/dt-bindings/clock/sun4i-a10-ccu.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes plaes@plaes.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_ -#define _DT_BINDINGS_CLK_SUN4I_A10_H_ - -#define CLK_HOSC 1 -#define CLK_PLL_VIDEO0_2X 9 -#define CLK_PLL_VIDEO1_2X 18 -#define CLK_CPU 20 - -/* AHB Gates */ -#define CLK_AHB_OTG 26 -#define CLK_AHB_EHCI0 27 -#define CLK_AHB_OHCI0 28 -#define CLK_AHB_EHCI1 29 -#define CLK_AHB_OHCI1 30 -#define CLK_AHB_SS 31 -#define CLK_AHB_DMA 32 -#define CLK_AHB_BIST 33 -#define CLK_AHB_MMC0 34 -#define CLK_AHB_MMC1 35 -#define CLK_AHB_MMC2 36 -#define CLK_AHB_MMC3 37 -#define CLK_AHB_MS 38 -#define CLK_AHB_NAND 39 -#define CLK_AHB_SDRAM 40 -#define CLK_AHB_ACE 41 -#define CLK_AHB_EMAC 42 -#define CLK_AHB_TS 43 -#define CLK_AHB_SPI0 44 -#define CLK_AHB_SPI1 45 -#define CLK_AHB_SPI2 46 -#define CLK_AHB_SPI3 47 -#define CLK_AHB_PATA 48 -#define CLK_AHB_SATA 49 -#define CLK_AHB_GPS 50 -#define CLK_AHB_HSTIMER 51 -#define CLK_AHB_VE 52 -#define CLK_AHB_TVD 53 -#define CLK_AHB_TVE0 54 -#define CLK_AHB_TVE1 55 -#define CLK_AHB_LCD0 56 -#define CLK_AHB_LCD1 57 -#define CLK_AHB_CSI0 58 -#define CLK_AHB_CSI1 59 -#define CLK_AHB_HDMI0 60 -#define CLK_AHB_HDMI1 61 -#define CLK_AHB_DE_BE0 62 -#define CLK_AHB_DE_BE1 63 -#define CLK_AHB_DE_FE0 64 -#define CLK_AHB_DE_FE1 65 -#define CLK_AHB_GMAC 66 -#define CLK_AHB_MP 67 -#define CLK_AHB_GPU 68 - -/* APB0 Gates */ -#define CLK_APB0_CODEC 69 -#define CLK_APB0_SPDIF 70 -#define CLK_APB0_I2S0 71 -#define CLK_APB0_AC97 72 -#define CLK_APB0_I2S1 73 -#define CLK_APB0_PIO 74 -#define CLK_APB0_IR0 75 -#define CLK_APB0_IR1 76 -#define CLK_APB0_I2S2 77 -#define CLK_APB0_KEYPAD 78 - -/* APB1 Gates */ -#define CLK_APB1_I2C0 79 -#define CLK_APB1_I2C1 80 -#define CLK_APB1_I2C2 81 -#define CLK_APB1_I2C3 82 -#define CLK_APB1_CAN 83 -#define CLK_APB1_SCR 84 -#define CLK_APB1_PS20 85 -#define CLK_APB1_PS21 86 -#define CLK_APB1_I2C4 87 -#define CLK_APB1_UART0 88 -#define CLK_APB1_UART1 89 -#define CLK_APB1_UART2 90 -#define CLK_APB1_UART3 91 -#define CLK_APB1_UART4 92 -#define CLK_APB1_UART5 93 -#define CLK_APB1_UART6 94 -#define CLK_APB1_UART7 95 - -/* IP clocks */ -#define CLK_NAND 96 -#define CLK_MS 97 -#define CLK_MMC0 98 -#define CLK_MMC0_OUTPUT 99 -#define CLK_MMC0_SAMPLE 100 -#define CLK_MMC1 101 -#define CLK_MMC1_OUTPUT 102 -#define CLK_MMC1_SAMPLE 103 -#define CLK_MMC2 104 -#define CLK_MMC2_OUTPUT 105 -#define CLK_MMC2_SAMPLE 106 -#define CLK_MMC3 107 -#define CLK_MMC3_OUTPUT 108 -#define CLK_MMC3_SAMPLE 109 -#define CLK_TS 110 -#define CLK_SS 111 -#define CLK_SPI0 112 -#define CLK_SPI1 113 -#define CLK_SPI2 114 -#define CLK_PATA 115 -#define CLK_IR0 116 -#define CLK_IR1 117 -#define CLK_I2S0 118 -#define CLK_AC97 119 -#define CLK_SPDIF 120 -#define CLK_KEYPAD 121 -#define CLK_SATA 122 -#define CLK_USB_OHCI0 123 -#define CLK_USB_OHCI1 124 -#define CLK_USB_PHY 125 -#define CLK_GPS 126 -#define CLK_SPI3 127 -#define CLK_I2S1 128 -#define CLK_I2S2 129 - -/* DRAM Gates */ -#define CLK_DRAM_VE 130 -#define CLK_DRAM_CSI0 131 -#define CLK_DRAM_CSI1 132 -#define CLK_DRAM_TS 133 -#define CLK_DRAM_TVD 134 -#define CLK_DRAM_TVE0 135 -#define CLK_DRAM_TVE1 136 -#define CLK_DRAM_OUT 137 -#define CLK_DRAM_DE_FE1 138 -#define CLK_DRAM_DE_FE0 139 -#define CLK_DRAM_DE_BE0 140 -#define CLK_DRAM_DE_BE1 141 -#define CLK_DRAM_MP 142 -#define CLK_DRAM_ACE 143 - -/* Display Engine Clocks */ -#define CLK_DE_BE0 144 -#define CLK_DE_BE1 145 -#define CLK_DE_FE0 146 -#define CLK_DE_FE1 147 -#define CLK_DE_MP 148 -#define CLK_TCON0_CH0 149 -#define CLK_TCON1_CH0 150 -#define CLK_CSI_SCLK 151 -#define CLK_TVD_SCLK2 152 -#define CLK_TVD 153 -#define CLK_TCON0_CH1_SCLK2 154 -#define CLK_TCON0_CH1 155 -#define CLK_TCON1_CH1_SCLK2 156 -#define CLK_TCON1_CH1 157 -#define CLK_CSI0 158 -#define CLK_CSI1 159 -#define CLK_CODEC 160 -#define CLK_VE 161 -#define CLK_AVS 162 -#define CLK_ACE 163 -#define CLK_HDMI 164 -#define CLK_GPU 165 - -#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */ diff --git a/include/dt-bindings/clock/sun4i-a10-pll2.h b/include/dt-bindings/clock/sun4i-a10-pll2.h deleted file mode 100644 index 071c8112d531..000000000000 --- a/include/dt-bindings/clock/sun4i-a10-pll2.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Maxime Ripard - * - * Maxime Ripard maxime.ripard@free-electrons.com - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ -#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ - -#define SUN4I_A10_PLL2_1X 0 -#define SUN4I_A10_PLL2_2X 1 -#define SUN4I_A10_PLL2_4X 2 -#define SUN4I_A10_PLL2_8X 3 - -#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h deleted file mode 100644 index 175892189e9d..000000000000 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard maxime.ripard@free-electrons.com - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ -#define _DT_BINDINGS_CLK_SUN50I_A64_H_ - -#define CLK_PLL_VIDEO0 7 -#define CLK_PLL_PERIPH0 11 - -#define CLK_CPUX 21 -#define CLK_BUS_MIPI_DSI 28 -#define CLK_BUS_CE 29 -#define CLK_BUS_DMA 30 -#define CLK_BUS_MMC0 31 -#define CLK_BUS_MMC1 32 -#define CLK_BUS_MMC2 33 -#define CLK_BUS_NAND 34 -#define CLK_BUS_DRAM 35 -#define CLK_BUS_EMAC 36 -#define CLK_BUS_TS 37 -#define CLK_BUS_HSTIMER 38 -#define CLK_BUS_SPI0 39 -#define CLK_BUS_SPI1 40 -#define CLK_BUS_OTG 41 -#define CLK_BUS_EHCI0 42 -#define CLK_BUS_EHCI1 43 -#define CLK_BUS_OHCI0 44 -#define CLK_BUS_OHCI1 45 -#define CLK_BUS_VE 46 -#define CLK_BUS_TCON0 47 -#define CLK_BUS_TCON1 48 -#define CLK_BUS_DEINTERLACE 49 -#define CLK_BUS_CSI 50 -#define CLK_BUS_HDMI 51 -#define CLK_BUS_DE 52 -#define CLK_BUS_GPU 53 -#define CLK_BUS_MSGBOX 54 -#define CLK_BUS_SPINLOCK 55 -#define CLK_BUS_CODEC 56 -#define CLK_BUS_SPDIF 57 -#define CLK_BUS_PIO 58 -#define CLK_BUS_THS 59 -#define CLK_BUS_I2S0 60 -#define CLK_BUS_I2S1 61 -#define CLK_BUS_I2S2 62 -#define CLK_BUS_I2C0 63 -#define CLK_BUS_I2C1 64 -#define CLK_BUS_I2C2 65 -#define CLK_BUS_SCR 66 -#define CLK_BUS_UART0 67 -#define CLK_BUS_UART1 68 -#define CLK_BUS_UART2 69 -#define CLK_BUS_UART3 70 -#define CLK_BUS_UART4 71 -#define CLK_BUS_DBG 72 -#define CLK_THS 73 -#define CLK_NAND 74 -#define CLK_MMC0 75 -#define CLK_MMC1 76 -#define CLK_MMC2 77 -#define CLK_TS 78 -#define CLK_CE 79 -#define CLK_SPI0 80 -#define CLK_SPI1 81 -#define CLK_I2S0 82 -#define CLK_I2S1 83 -#define CLK_I2S2 84 -#define CLK_SPDIF 85 -#define CLK_USB_PHY0 86 -#define CLK_USB_PHY1 87 -#define CLK_USB_HSIC 88 -#define CLK_USB_HSIC_12M 89 - -#define CLK_USB_OHCI0 91 - -#define CLK_USB_OHCI1 93 -#define CLK_DRAM 94 -#define CLK_DRAM_VE 95 -#define CLK_DRAM_CSI 96 -#define CLK_DRAM_DEINTERLACE 97 -#define CLK_DRAM_TS 98 -#define CLK_DE 99 -#define CLK_TCON0 100 -#define CLK_TCON1 101 -#define CLK_DEINTERLACE 102 -#define CLK_CSI_MISC 103 -#define CLK_CSI_SCLK 104 -#define CLK_CSI_MCLK 105 -#define CLK_VE 106 -#define CLK_AC_DIG 107 -#define CLK_AC_DIG_4X 108 -#define CLK_AVS 109 -#define CLK_HDMI 110 -#define CLK_HDMI_DDC 111 -#define CLK_MBUS 112 -#define CLK_DSI_DPHY 113 -#define CLK_GPU 114 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h deleted file mode 100644 index ef9123d81937..000000000000 --- a/include/dt-bindings/clock/sun50i-h6-ccu.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2017 Icenowy Zheng icenowy@aosc.io - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ -#define _DT_BINDINGS_CLK_SUN50I_H6_H_ - -#define CLK_PLL_PERIPH0 3 - -#define CLK_CPUX 21 - -#define CLK_APB1 26 - -#define CLK_DE 29 -#define CLK_BUS_DE 30 -#define CLK_DEINTERLACE 31 -#define CLK_BUS_DEINTERLACE 32 -#define CLK_GPU 33 -#define CLK_BUS_GPU 34 -#define CLK_CE 35 -#define CLK_BUS_CE 36 -#define CLK_VE 37 -#define CLK_BUS_VE 38 -#define CLK_EMCE 39 -#define CLK_BUS_EMCE 40 -#define CLK_VP9 41 -#define CLK_BUS_VP9 42 -#define CLK_BUS_DMA 43 -#define CLK_BUS_MSGBOX 44 -#define CLK_BUS_SPINLOCK 45 -#define CLK_BUS_HSTIMER 46 -#define CLK_AVS 47 -#define CLK_BUS_DBG 48 -#define CLK_BUS_PSI 49 -#define CLK_BUS_PWM 50 -#define CLK_BUS_IOMMU 51 - -#define CLK_MBUS_DMA 53 -#define CLK_MBUS_VE 54 -#define CLK_MBUS_CE 55 -#define CLK_MBUS_TS 56 -#define CLK_MBUS_NAND 57 -#define CLK_MBUS_CSI 58 -#define CLK_MBUS_DEINTERLACE 59 - -#define CLK_NAND0 61 -#define CLK_NAND1 62 -#define CLK_BUS_NAND 63 -#define CLK_MMC0 64 -#define CLK_MMC1 65 -#define CLK_MMC2 66 -#define CLK_BUS_MMC0 67 -#define CLK_BUS_MMC1 68 -#define CLK_BUS_MMC2 69 -#define CLK_BUS_UART0 70 -#define CLK_BUS_UART1 71 -#define CLK_BUS_UART2 72 -#define CLK_BUS_UART3 73 -#define CLK_BUS_I2C0 74 -#define CLK_BUS_I2C1 75 -#define CLK_BUS_I2C2 76 -#define CLK_BUS_I2C3 77 -#define CLK_BUS_SCR0 78 -#define CLK_BUS_SCR1 79 -#define CLK_SPI0 80 -#define CLK_SPI1 81 -#define CLK_BUS_SPI0 82 -#define CLK_BUS_SPI1 83 -#define CLK_BUS_EMAC 84 -#define CLK_TS 85 -#define CLK_BUS_TS 86 -#define CLK_IR_TX 87 -#define CLK_BUS_IR_TX 88 -#define CLK_BUS_THS 89 -#define CLK_I2S3 90 -#define CLK_I2S0 91 -#define CLK_I2S1 92 -#define CLK_I2S2 93 -#define CLK_BUS_I2S0 94 -#define CLK_BUS_I2S1 95 -#define CLK_BUS_I2S2 96 -#define CLK_BUS_I2S3 97 -#define CLK_SPDIF 98 -#define CLK_BUS_SPDIF 99 -#define CLK_DMIC 100 -#define CLK_BUS_DMIC 101 -#define CLK_AUDIO_HUB 102 -#define CLK_BUS_AUDIO_HUB 103 -#define CLK_USB_OHCI0 104 -#define CLK_USB_PHY0 105 -#define CLK_USB_PHY1 106 -#define CLK_USB_OHCI3 107 -#define CLK_USB_PHY3 108 -#define CLK_USB_HSIC_12M 109 -#define CLK_USB_HSIC 110 -#define CLK_BUS_OHCI0 111 -#define CLK_BUS_OHCI3 112 -#define CLK_BUS_EHCI0 113 -#define CLK_BUS_XHCI 114 -#define CLK_BUS_EHCI3 115 -#define CLK_BUS_OTG 116 -#define CLK_PCIE_REF_100M 117 -#define CLK_PCIE_REF 118 -#define CLK_PCIE_REF_OUT 119 -#define CLK_PCIE_MAXI 120 -#define CLK_PCIE_AUX 121 -#define CLK_BUS_PCIE 122 -#define CLK_HDMI 123 -#define CLK_HDMI_SLOW 124 -#define CLK_HDMI_CEC 125 -#define CLK_BUS_HDMI 126 -#define CLK_BUS_TCON_TOP 127 -#define CLK_TCON_LCD0 128 -#define CLK_BUS_TCON_LCD0 129 -#define CLK_TCON_TV0 130 -#define CLK_BUS_TCON_TV0 131 -#define CLK_CSI_CCI 132 -#define CLK_CSI_TOP 133 -#define CLK_CSI_MCLK 134 -#define CLK_BUS_CSI 135 -#define CLK_HDCP 136 -#define CLK_BUS_HDCP 137 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h deleted file mode 100644 index a96087abc86f..000000000000 --- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 Icenowy Zheng icenowy@aosc.xyz - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ - -#define CLK_AR100 0 - -#define CLK_R_APB1 2 - -#define CLK_R_APB1_TIMER 4 -#define CLK_R_APB1_TWD 5 -#define CLK_R_APB1_PWM 6 -#define CLK_R_APB2_UART 7 -#define CLK_R_APB2_I2C 8 -#define CLK_R_APB1_IR 9 -#define CLK_R_APB1_W1 10 - -#define CLK_IR 11 -#define CLK_W1 12 - -#define CLK_R_APB2_RSB 13 -#define CLK_R_APB1_RTC 14 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h deleted file mode 100644 index 6f8f01e67628..000000000000 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2020 Arm Ltd. - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_ -#define _DT_BINDINGS_CLK_SUN50I_H616_H_ - -#define CLK_PLL_PERIPH0 4 - -#define CLK_CPUX 21 - -#define CLK_APB1 26 - -#define CLK_DE 29 -#define CLK_BUS_DE 30 -#define CLK_DEINTERLACE 31 -#define CLK_BUS_DEINTERLACE 32 -#define CLK_G2D 33 -#define CLK_BUS_G2D 34 -#define CLK_GPU0 35 -#define CLK_BUS_GPU 36 -#define CLK_GPU1 37 -#define CLK_CE 38 -#define CLK_BUS_CE 39 -#define CLK_VE 40 -#define CLK_BUS_VE 41 -#define CLK_BUS_DMA 42 -#define CLK_BUS_HSTIMER 43 -#define CLK_AVS 44 -#define CLK_BUS_DBG 45 -#define CLK_BUS_PSI 46 -#define CLK_BUS_PWM 47 -#define CLK_BUS_IOMMU 48 - -#define CLK_MBUS_DMA 50 -#define CLK_MBUS_VE 51 -#define CLK_MBUS_CE 52 -#define CLK_MBUS_TS 53 -#define CLK_MBUS_NAND 54 -#define CLK_MBUS_G2D 55 - -#define CLK_NAND0 57 -#define CLK_NAND1 58 -#define CLK_BUS_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC1 61 -#define CLK_MMC2 62 -#define CLK_BUS_MMC0 63 -#define CLK_BUS_MMC1 64 -#define CLK_BUS_MMC2 65 -#define CLK_BUS_UART0 66 -#define CLK_BUS_UART1 67 -#define CLK_BUS_UART2 68 -#define CLK_BUS_UART3 69 -#define CLK_BUS_UART4 70 -#define CLK_BUS_UART5 71 -#define CLK_BUS_I2C0 72 -#define CLK_BUS_I2C1 73 -#define CLK_BUS_I2C2 74 -#define CLK_BUS_I2C3 75 -#define CLK_BUS_I2C4 76 -#define CLK_SPI0 77 -#define CLK_SPI1 78 -#define CLK_BUS_SPI0 79 -#define CLK_BUS_SPI1 80 -#define CLK_EMAC_25M 81 -#define CLK_BUS_EMAC0 82 -#define CLK_BUS_EMAC1 83 -#define CLK_TS 84 -#define CLK_BUS_TS 85 -#define CLK_BUS_THS 86 -#define CLK_SPDIF 87 -#define CLK_BUS_SPDIF 88 -#define CLK_DMIC 89 -#define CLK_BUS_DMIC 90 -#define CLK_AUDIO_CODEC_1X 91 -#define CLK_AUDIO_CODEC_4X 92 -#define CLK_BUS_AUDIO_CODEC 93 -#define CLK_AUDIO_HUB 94 -#define CLK_BUS_AUDIO_HUB 95 -#define CLK_USB_OHCI0 96 -#define CLK_USB_PHY0 97 -#define CLK_USB_OHCI1 98 -#define CLK_USB_PHY1 99 -#define CLK_USB_OHCI2 100 -#define CLK_USB_PHY2 101 -#define CLK_USB_OHCI3 102 -#define CLK_USB_PHY3 103 -#define CLK_BUS_OHCI0 104 -#define CLK_BUS_OHCI1 105 -#define CLK_BUS_OHCI2 106 -#define CLK_BUS_OHCI3 107 -#define CLK_BUS_EHCI0 108 -#define CLK_BUS_EHCI1 109 -#define CLK_BUS_EHCI2 110 -#define CLK_BUS_EHCI3 111 -#define CLK_BUS_OTG 112 -#define CLK_BUS_KEYADC 113 -#define CLK_HDMI 114 -#define CLK_HDMI_SLOW 115 -#define CLK_HDMI_CEC 116 -#define CLK_BUS_HDMI 117 -#define CLK_BUS_TCON_TOP 118 -#define CLK_TCON_TV0 119 -#define CLK_TCON_TV1 120 -#define CLK_BUS_TCON_TV0 121 -#define CLK_BUS_TCON_TV1 122 -#define CLK_TVE0 123 -#define CLK_BUS_TVE_TOP 124 -#define CLK_BUS_TVE0 125 -#define CLK_HDCP 126 -#define CLK_BUS_HDCP 127 -#define CLK_PLL_SYSTEM_32K 128 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h deleted file mode 100644 index 75fe5619c3d9..000000000000 --- a/include/dt-bindings/clock/sun5i-ccu.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2016 Maxime Ripard - * - * Maxime Ripard maxime.ripard@free-electrons.com - */ - -#ifndef _DT_BINDINGS_CLK_SUN5I_H_ -#define _DT_BINDINGS_CLK_SUN5I_H_ - -#define CLK_HOSC 1 - -#define CLK_PLL_VIDEO0_2X 9 - -#define CLK_PLL_VIDEO1_2X 16 -#define CLK_CPU 17 - -#define CLK_AHB_OTG 23 -#define CLK_AHB_EHCI 24 -#define CLK_AHB_OHCI 25 -#define CLK_AHB_SS 26 -#define CLK_AHB_DMA 27 -#define CLK_AHB_BIST 28 -#define CLK_AHB_MMC0 29 -#define CLK_AHB_MMC1 30 -#define CLK_AHB_MMC2 31 -#define CLK_AHB_NAND 32 -#define CLK_AHB_SDRAM 33 -#define CLK_AHB_EMAC 34 -#define CLK_AHB_TS 35 -#define CLK_AHB_SPI0 36 -#define CLK_AHB_SPI1 37 -#define CLK_AHB_SPI2 38 -#define CLK_AHB_GPS 39 -#define CLK_AHB_HSTIMER 40 -#define CLK_AHB_VE 41 -#define CLK_AHB_TVE 42 -#define CLK_AHB_LCD 43 -#define CLK_AHB_CSI 44 -#define CLK_AHB_HDMI 45 -#define CLK_AHB_DE_BE 46 -#define CLK_AHB_DE_FE 47 -#define CLK_AHB_IEP 48 -#define CLK_AHB_GPU 49 -#define CLK_APB0_CODEC 50 -#define CLK_APB0_SPDIF 51 -#define CLK_APB0_I2S 52 -#define CLK_APB0_PIO 53 -#define CLK_APB0_IR 54 -#define CLK_APB0_KEYPAD 55 -#define CLK_APB1_I2C0 56 -#define CLK_APB1_I2C1 57 -#define CLK_APB1_I2C2 58 -#define CLK_APB1_UART0 59 -#define CLK_APB1_UART1 60 -#define CLK_APB1_UART2 61 -#define CLK_APB1_UART3 62 -#define CLK_NAND 63 -#define CLK_MMC0 64 -#define CLK_MMC1 65 -#define CLK_MMC2 66 -#define CLK_TS 67 -#define CLK_SS 68 -#define CLK_SPI0 69 -#define CLK_SPI1 70 -#define CLK_SPI2 71 -#define CLK_IR 72 -#define CLK_I2S 73 -#define CLK_SPDIF 74 -#define CLK_KEYPAD 75 -#define CLK_USB_OHCI 76 -#define CLK_USB_PHY0 77 -#define CLK_USB_PHY1 78 -#define CLK_GPS 79 -#define CLK_DRAM_VE 80 -#define CLK_DRAM_CSI 81 -#define CLK_DRAM_TS 82 -#define CLK_DRAM_TVE 83 -#define CLK_DRAM_DE_FE 84 -#define CLK_DRAM_DE_BE 85 -#define CLK_DRAM_ACE 86 -#define CLK_DRAM_IEP 87 -#define CLK_DE_BE 88 -#define CLK_DE_FE 89 -#define CLK_TCON_CH0 90 - -#define CLK_TCON_CH1 92 -#define CLK_CSI 93 -#define CLK_VE 94 -#define CLK_CODEC 95 -#define CLK_AVS 96 -#define CLK_HDMI 97 -#define CLK_GPU 98 -#define CLK_MBUS 99 -#define CLK_IEP 100 - -#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h deleted file mode 100644 index 39878d9dce9f..000000000000 --- a/include/dt-bindings/clock/sun6i-a31-ccu.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai wens@csie.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ -#define _DT_BINDINGS_CLK_SUN6I_A31_H_ - -#define CLK_PLL_VIDEO0_2X 7 - -#define CLK_PLL_PERIPH 10 - -#define CLK_PLL_VIDEO1_2X 13 - -#define CLK_PLL_MIPI 15 - -#define CLK_CPU 18 - -#define CLK_AHB1_MIPIDSI 23 -#define CLK_AHB1_SS 24 -#define CLK_AHB1_DMA 25 -#define CLK_AHB1_MMC0 26 -#define CLK_AHB1_MMC1 27 -#define CLK_AHB1_MMC2 28 -#define CLK_AHB1_MMC3 29 -#define CLK_AHB1_NAND1 30 -#define CLK_AHB1_NAND0 31 -#define CLK_AHB1_SDRAM 32 -#define CLK_AHB1_EMAC 33 -#define CLK_AHB1_TS 34 -#define CLK_AHB1_HSTIMER 35 -#define CLK_AHB1_SPI0 36 -#define CLK_AHB1_SPI1 37 -#define CLK_AHB1_SPI2 38 -#define CLK_AHB1_SPI3 39 -#define CLK_AHB1_OTG 40 -#define CLK_AHB1_EHCI0 41 -#define CLK_AHB1_EHCI1 42 -#define CLK_AHB1_OHCI0 43 -#define CLK_AHB1_OHCI1 44 -#define CLK_AHB1_OHCI2 45 -#define CLK_AHB1_VE 46 -#define CLK_AHB1_LCD0 47 -#define CLK_AHB1_LCD1 48 -#define CLK_AHB1_CSI 49 -#define CLK_AHB1_HDMI 50 -#define CLK_AHB1_BE0 51 -#define CLK_AHB1_BE1 52 -#define CLK_AHB1_FE0 53 -#define CLK_AHB1_FE1 54 -#define CLK_AHB1_MP 55 -#define CLK_AHB1_GPU 56 -#define CLK_AHB1_DEU0 57 -#define CLK_AHB1_DEU1 58 -#define CLK_AHB1_DRC0 59 -#define CLK_AHB1_DRC1 60 - -#define CLK_APB1_CODEC 61 -#define CLK_APB1_SPDIF 62 -#define CLK_APB1_DIGITAL_MIC 63 -#define CLK_APB1_PIO 64 -#define CLK_APB1_DAUDIO0 65 -#define CLK_APB1_DAUDIO1 66 - -#define CLK_APB2_I2C0 67 -#define CLK_APB2_I2C1 68 -#define CLK_APB2_I2C2 69 -#define CLK_APB2_I2C3 70 -#define CLK_APB2_UART0 71 -#define CLK_APB2_UART1 72 -#define CLK_APB2_UART2 73 -#define CLK_APB2_UART3 74 -#define CLK_APB2_UART4 75 -#define CLK_APB2_UART5 76 - -#define CLK_NAND0 77 -#define CLK_NAND1 78 -#define CLK_MMC0 79 -#define CLK_MMC0_SAMPLE 80 -#define CLK_MMC0_OUTPUT 81 -#define CLK_MMC1 82 -#define CLK_MMC1_SAMPLE 83 -#define CLK_MMC1_OUTPUT 84 -#define CLK_MMC2 85 -#define CLK_MMC2_SAMPLE 86 -#define CLK_MMC2_OUTPUT 87 -#define CLK_MMC3 88 -#define CLK_MMC3_SAMPLE 89 -#define CLK_MMC3_OUTPUT 90 -#define CLK_TS 91 -#define CLK_SS 92 -#define CLK_SPI0 93 -#define CLK_SPI1 94 -#define CLK_SPI2 95 -#define CLK_SPI3 96 -#define CLK_DAUDIO0 97 -#define CLK_DAUDIO1 98 -#define CLK_SPDIF 99 -#define CLK_USB_PHY0 100 -#define CLK_USB_PHY1 101 -#define CLK_USB_PHY2 102 -#define CLK_USB_OHCI0 103 -#define CLK_USB_OHCI1 104 -#define CLK_USB_OHCI2 105 - -#define CLK_DRAM_VE 110 -#define CLK_DRAM_CSI_ISP 111 -#define CLK_DRAM_TS 112 -#define CLK_DRAM_DRC0 113 -#define CLK_DRAM_DRC1 114 -#define CLK_DRAM_DEU0 115 -#define CLK_DRAM_DEU1 116 -#define CLK_DRAM_FE0 117 -#define CLK_DRAM_FE1 118 -#define CLK_DRAM_BE0 119 -#define CLK_DRAM_BE1 120 -#define CLK_DRAM_MP 121 - -#define CLK_BE0 122 -#define CLK_BE1 123 -#define CLK_FE0 124 -#define CLK_FE1 125 -#define CLK_MP 126 -#define CLK_LCD0_CH0 127 -#define CLK_LCD1_CH0 128 -#define CLK_LCD0_CH1 129 -#define CLK_LCD1_CH1 130 -#define CLK_CSI0_SCLK 131 -#define CLK_CSI0_MCLK 132 -#define CLK_CSI1_MCLK 133 -#define CLK_VE 134 -#define CLK_CODEC 135 -#define CLK_AVS 136 -#define CLK_DIGITAL_MIC 137 -#define CLK_HDMI 138 -#define CLK_HDMI_DDC 139 -#define CLK_PS 140 - -#define CLK_MIPI_DSI 143 -#define CLK_MIPI_DSI_DPHY 144 -#define CLK_MIPI_CSI_DPHY 145 -#define CLK_IEP_DRC0 146 -#define CLK_IEP_DRC1 147 -#define CLK_IEP_DEU0 148 -#define CLK_IEP_DEU1 149 -#define CLK_GPU_CORE 150 -#define CLK_GPU_MEMORY 151 -#define CLK_GPU_HYD 152 -#define CLK_ATS 153 -#define CLK_TRACE 154 - -#define CLK_OUT_A 155 -#define CLK_OUT_B 156 -#define CLK_OUT_C 157 - -#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */ diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h deleted file mode 100644 index 3bd3aa3d57ce..000000000000 --- a/include/dt-bindings/clock/sun6i-rtc.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ -#define _DT_BINDINGS_CLK_SUN6I_RTC_H_ - -#define CLK_OSC32K 0 -#define CLK_OSC32K_FANOUT 1 -#define CLK_IOSC 2 - -#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */ diff --git a/include/dt-bindings/clock/sun7i-a20-ccu.h b/include/dt-bindings/clock/sun7i-a20-ccu.h deleted file mode 100644 index 045a5178da0c..000000000000 --- a/include/dt-bindings/clock/sun7i-a20-ccu.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes plaes@plaes.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_ -#define _DT_BINDINGS_CLK_SUN7I_A20_H_ - -#include <dt-bindings/clock/sun4i-a10-ccu.h> - -#define CLK_MBUS 166 -#define CLK_HDMI1_SLOW 167 -#define CLK_HDMI1 168 -#define CLK_OUT_A 169 -#define CLK_OUT_B 170 - -#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */ diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h deleted file mode 100644 index eb524d0bbd01..000000000000 --- a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard maxime.ripard@free-electrons.com - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ -#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ - -#define CLK_PLL_MIPI 13 - -#define CLK_CPUX 18 - -#define CLK_BUS_MIPI_DSI 23 -#define CLK_BUS_SS 24 -#define CLK_BUS_DMA 25 -#define CLK_BUS_MMC0 26 -#define CLK_BUS_MMC1 27 -#define CLK_BUS_MMC2 28 -#define CLK_BUS_NAND 29 -#define CLK_BUS_DRAM 30 -#define CLK_BUS_HSTIMER 31 -#define CLK_BUS_SPI0 32 -#define CLK_BUS_SPI1 33 -#define CLK_BUS_OTG 34 -#define CLK_BUS_EHCI 35 -#define CLK_BUS_OHCI 36 -#define CLK_BUS_VE 37 -#define CLK_BUS_LCD 38 -#define CLK_BUS_CSI 39 -#define CLK_BUS_DE_BE 40 -#define CLK_BUS_DE_FE 41 -#define CLK_BUS_GPU 42 -#define CLK_BUS_MSGBOX 43 -#define CLK_BUS_SPINLOCK 44 -#define CLK_BUS_DRC 45 -#define CLK_BUS_SAT 46 -#define CLK_BUS_CODEC 47 -#define CLK_BUS_PIO 48 -#define CLK_BUS_I2S0 49 -#define CLK_BUS_I2S1 50 -#define CLK_BUS_I2C0 51 -#define CLK_BUS_I2C1 52 -#define CLK_BUS_I2C2 53 -#define CLK_BUS_UART0 54 -#define CLK_BUS_UART1 55 -#define CLK_BUS_UART2 56 -#define CLK_BUS_UART3 57 -#define CLK_BUS_UART4 58 -#define CLK_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC0_SAMPLE 61 -#define CLK_MMC0_OUTPUT 62 -#define CLK_MMC1 63 -#define CLK_MMC1_SAMPLE 64 -#define CLK_MMC1_OUTPUT 65 -#define CLK_MMC2 66 -#define CLK_MMC2_SAMPLE 67 -#define CLK_MMC2_OUTPUT 68 -#define CLK_SS 69 -#define CLK_SPI0 70 -#define CLK_SPI1 71 -#define CLK_I2S0 72 -#define CLK_I2S1 73 -#define CLK_USB_PHY0 74 -#define CLK_USB_PHY1 75 -#define CLK_USB_HSIC 76 -#define CLK_USB_HSIC_12M 77 -#define CLK_USB_OHCI 78 - -#define CLK_DRAM_VE 80 -#define CLK_DRAM_CSI 81 -#define CLK_DRAM_DRC 82 -#define CLK_DRAM_DE_FE 83 -#define CLK_DRAM_DE_BE 84 -#define CLK_DE_BE 85 -#define CLK_DE_FE 86 -#define CLK_LCD_CH0 87 -#define CLK_LCD_CH1 88 -#define CLK_CSI_SCLK 89 -#define CLK_CSI_MCLK 90 -#define CLK_VE 91 -#define CLK_AC_DIG 92 -#define CLK_AC_DIG_4X 93 -#define CLK_AVS 94 - -#define CLK_DSI_SCLK 96 -#define CLK_DSI_DPHY 97 -#define CLK_DRC 98 -#define CLK_GPU 99 -#define CLK_ATS 100 - -#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */ diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h deleted file mode 100644 index 78af5085f630..000000000000 --- a/include/dt-bindings/clock/sun8i-a83t-ccu.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai wens@csie.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ - -#define CLK_PLL_PERIPH 6 - -#define CLK_PLL_DE 9 - -#define CLK_C0CPUX 11 -#define CLK_C1CPUX 12 - -#define CLK_BUS_MIPI_DSI 19 -#define CLK_BUS_SS 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_NAND 25 -#define CLK_BUS_DRAM 26 -#define CLK_BUS_EMAC 27 -#define CLK_BUS_HSTIMER 28 -#define CLK_BUS_SPI0 29 -#define CLK_BUS_SPI1 30 -#define CLK_BUS_OTG 31 -#define CLK_BUS_EHCI0 32 -#define CLK_BUS_EHCI1 33 -#define CLK_BUS_OHCI0 34 - -#define CLK_BUS_VE 35 -#define CLK_BUS_TCON0 36 -#define CLK_BUS_TCON1 37 -#define CLK_BUS_CSI 38 -#define CLK_BUS_HDMI 39 -#define CLK_BUS_DE 40 -#define CLK_BUS_GPU 41 -#define CLK_BUS_MSGBOX 42 -#define CLK_BUS_SPINLOCK 43 - -#define CLK_BUS_SPDIF 44 -#define CLK_BUS_PIO 45 -#define CLK_BUS_I2S0 46 -#define CLK_BUS_I2S1 47 -#define CLK_BUS_I2S2 48 -#define CLK_BUS_TDM 49 - -#define CLK_BUS_I2C0 50 -#define CLK_BUS_I2C1 51 -#define CLK_BUS_I2C2 52 -#define CLK_BUS_UART0 53 -#define CLK_BUS_UART1 54 -#define CLK_BUS_UART2 55 -#define CLK_BUS_UART3 56 -#define CLK_BUS_UART4 57 - -#define CLK_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC0_SAMPLE 61 -#define CLK_MMC0_OUTPUT 62 -#define CLK_MMC1 63 -#define CLK_MMC1_SAMPLE 64 -#define CLK_MMC1_OUTPUT 65 -#define CLK_MMC2 66 -#define CLK_MMC2_SAMPLE 67 -#define CLK_MMC2_OUTPUT 68 -#define CLK_SS 69 -#define CLK_SPI0 70 -#define CLK_SPI1 71 -#define CLK_I2S0 72 -#define CLK_I2S1 73 -#define CLK_I2S2 74 -#define CLK_TDM 75 -#define CLK_SPDIF 76 -#define CLK_USB_PHY0 77 -#define CLK_USB_PHY1 78 -#define CLK_USB_HSIC 79 -#define CLK_USB_HSIC_12M 80 -#define CLK_USB_OHCI0 81 - -#define CLK_DRAM_VE 83 -#define CLK_DRAM_CSI 84 - -#define CLK_TCON0 85 -#define CLK_TCON1 86 -#define CLK_CSI_MISC 87 -#define CLK_MIPI_CSI 88 -#define CLK_CSI_MCLK 89 -#define CLK_CSI_SCLK 90 -#define CLK_VE 91 -#define CLK_AVS 92 -#define CLK_HDMI 93 -#define CLK_HDMI_SLOW 94 - -#define CLK_MIPI_DSI0 96 -#define CLK_MIPI_DSI1 97 -#define CLK_GPU_CORE 98 -#define CLK_GPU_MEMORY 99 -#define CLK_GPU_HYD 100 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h deleted file mode 100644 index 7768f73b051e..000000000000 --- a/include/dt-bindings/clock/sun8i-de2.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng icenowy@aosc.io - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ - -#define CLK_BUS_MIXER0 0 -#define CLK_BUS_MIXER1 1 -#define CLK_BUS_WB 2 - -#define CLK_MIXER0 6 -#define CLK_MIXER1 7 -#define CLK_WB 8 - -#define CLK_BUS_ROT 9 -#define CLK_ROT 10 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h deleted file mode 100644 index 5d4ada2c22e6..000000000000 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard maxime.ripard@free-electrons.com - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ -#define _DT_BINDINGS_CLK_SUN8I_H3_H_ - -#define CLK_PLL_VIDEO 6 - -#define CLK_PLL_PERIPH0 9 - -#define CLK_CPUX 14 - -#define CLK_BUS_CE 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_NAND 25 -#define CLK_BUS_DRAM 26 -#define CLK_BUS_EMAC 27 -#define CLK_BUS_TS 28 -#define CLK_BUS_HSTIMER 29 -#define CLK_BUS_SPI0 30 -#define CLK_BUS_SPI1 31 -#define CLK_BUS_OTG 32 -#define CLK_BUS_EHCI0 33 -#define CLK_BUS_EHCI1 34 -#define CLK_BUS_EHCI2 35 -#define CLK_BUS_EHCI3 36 -#define CLK_BUS_OHCI0 37 -#define CLK_BUS_OHCI1 38 -#define CLK_BUS_OHCI2 39 -#define CLK_BUS_OHCI3 40 -#define CLK_BUS_VE 41 -#define CLK_BUS_TCON0 42 -#define CLK_BUS_TCON1 43 -#define CLK_BUS_DEINTERLACE 44 -#define CLK_BUS_CSI 45 -#define CLK_BUS_TVE 46 -#define CLK_BUS_HDMI 47 -#define CLK_BUS_DE 48 -#define CLK_BUS_GPU 49 -#define CLK_BUS_MSGBOX 50 -#define CLK_BUS_SPINLOCK 51 -#define CLK_BUS_CODEC 52 -#define CLK_BUS_SPDIF 53 -#define CLK_BUS_PIO 54 -#define CLK_BUS_THS 55 -#define CLK_BUS_I2S0 56 -#define CLK_BUS_I2S1 57 -#define CLK_BUS_I2S2 58 -#define CLK_BUS_I2C0 59 -#define CLK_BUS_I2C1 60 -#define CLK_BUS_I2C2 61 -#define CLK_BUS_UART0 62 -#define CLK_BUS_UART1 63 -#define CLK_BUS_UART2 64 -#define CLK_BUS_UART3 65 -#define CLK_BUS_SCR0 66 -#define CLK_BUS_EPHY 67 -#define CLK_BUS_DBG 68 - -#define CLK_THS 69 -#define CLK_NAND 70 -#define CLK_MMC0 71 -#define CLK_MMC0_SAMPLE 72 -#define CLK_MMC0_OUTPUT 73 -#define CLK_MMC1 74 -#define CLK_MMC1_SAMPLE 75 -#define CLK_MMC1_OUTPUT 76 -#define CLK_MMC2 77 -#define CLK_MMC2_SAMPLE 78 -#define CLK_MMC2_OUTPUT 79 -#define CLK_TS 80 -#define CLK_CE 81 -#define CLK_SPI0 82 -#define CLK_SPI1 83 -#define CLK_I2S0 84 -#define CLK_I2S1 85 -#define CLK_I2S2 86 -#define CLK_SPDIF 87 -#define CLK_USB_PHY0 88 -#define CLK_USB_PHY1 89 -#define CLK_USB_PHY2 90 -#define CLK_USB_PHY3 91 -#define CLK_USB_OHCI0 92 -#define CLK_USB_OHCI1 93 -#define CLK_USB_OHCI2 94 -#define CLK_USB_OHCI3 95 -#define CLK_DRAM 96 -#define CLK_DRAM_VE 97 -#define CLK_DRAM_CSI 98 -#define CLK_DRAM_DEINTERLACE 99 -#define CLK_DRAM_TS 100 -#define CLK_DE 101 -#define CLK_TCON0 102 -#define CLK_TVE 103 -#define CLK_DEINTERLACE 104 -#define CLK_CSI_MISC 105 -#define CLK_CSI_SCLK 106 -#define CLK_CSI_MCLK 107 -#define CLK_VE 108 -#define CLK_AC_DIG 109 -#define CLK_AVS 110 -#define CLK_HDMI 111 -#define CLK_HDMI_DDC 112 -#define CLK_MBUS 113 -#define CLK_GPU 114 - -/* New clocks imported in H5 */ -#define CLK_BUS_SCR1 115 - -#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h deleted file mode 100644 index 779d20aa0d05..000000000000 --- a/include/dt-bindings/clock/sun8i-r-ccu.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2016 Icenowy Zheng icenowy@aosc.xyz - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ - -#define CLK_AR100 0 - -#define CLK_APB0_PIO 3 -#define CLK_APB0_IR 4 -#define CLK_APB0_TIMER 5 -#define CLK_APB0_RSB 6 -#define CLK_APB0_UART 7 -/* 8 is reserved for CLK_APB0_W1 on A31 */ -#define CLK_APB0_I2C 9 -#define CLK_APB0_TWD 10 - -#define CLK_IR 11 - -#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h deleted file mode 100644 index d7337b55a4ef..000000000000 --- a/include/dt-bindings/clock/sun8i-r40-ccu.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng icenowy@aosc.io - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ -#define _DT_BINDINGS_CLK_SUN8I_R40_H_ - -#define CLK_PLL_VIDEO0 7 - -#define CLK_PLL_VIDEO1 16 - -#define CLK_CPU 24 - -#define CLK_BUS_MIPI_DSI 29 -#define CLK_BUS_CE 30 -#define CLK_BUS_DMA 31 -#define CLK_BUS_MMC0 32 -#define CLK_BUS_MMC1 33 -#define CLK_BUS_MMC2 34 -#define CLK_BUS_MMC3 35 -#define CLK_BUS_NAND 36 -#define CLK_BUS_DRAM 37 -#define CLK_BUS_EMAC 38 -#define CLK_BUS_TS 39 -#define CLK_BUS_HSTIMER 40 -#define CLK_BUS_SPI0 41 -#define CLK_BUS_SPI1 42 -#define CLK_BUS_SPI2 43 -#define CLK_BUS_SPI3 44 -#define CLK_BUS_SATA 45 -#define CLK_BUS_OTG 46 -#define CLK_BUS_EHCI0 47 -#define CLK_BUS_EHCI1 48 -#define CLK_BUS_EHCI2 49 -#define CLK_BUS_OHCI0 50 -#define CLK_BUS_OHCI1 51 -#define CLK_BUS_OHCI2 52 -#define CLK_BUS_VE 53 -#define CLK_BUS_MP 54 -#define CLK_BUS_DEINTERLACE 55 -#define CLK_BUS_CSI0 56 -#define CLK_BUS_CSI1 57 -#define CLK_BUS_HDMI1 58 -#define CLK_BUS_HDMI0 59 -#define CLK_BUS_DE 60 -#define CLK_BUS_TVE0 61 -#define CLK_BUS_TVE1 62 -#define CLK_BUS_TVE_TOP 63 -#define CLK_BUS_GMAC 64 -#define CLK_BUS_GPU 65 -#define CLK_BUS_TVD0 66 -#define CLK_BUS_TVD1 67 -#define CLK_BUS_TVD2 68 -#define CLK_BUS_TVD3 69 -#define CLK_BUS_TVD_TOP 70 -#define CLK_BUS_TCON_LCD0 71 -#define CLK_BUS_TCON_LCD1 72 -#define CLK_BUS_TCON_TV0 73 -#define CLK_BUS_TCON_TV1 74 -#define CLK_BUS_TCON_TOP 75 -#define CLK_BUS_CODEC 76 -#define CLK_BUS_SPDIF 77 -#define CLK_BUS_AC97 78 -#define CLK_BUS_PIO 79 -#define CLK_BUS_IR0 80 -#define CLK_BUS_IR1 81 -#define CLK_BUS_THS 82 -#define CLK_BUS_KEYPAD 83 -#define CLK_BUS_I2S0 84 -#define CLK_BUS_I2S1 85 -#define CLK_BUS_I2S2 86 -#define CLK_BUS_I2C0 87 -#define CLK_BUS_I2C1 88 -#define CLK_BUS_I2C2 89 -#define CLK_BUS_I2C3 90 -#define CLK_BUS_CAN 91 -#define CLK_BUS_SCR 92 -#define CLK_BUS_PS20 93 -#define CLK_BUS_PS21 94 -#define CLK_BUS_I2C4 95 -#define CLK_BUS_UART0 96 -#define CLK_BUS_UART1 97 -#define CLK_BUS_UART2 98 -#define CLK_BUS_UART3 99 -#define CLK_BUS_UART4 100 -#define CLK_BUS_UART5 101 -#define CLK_BUS_UART6 102 -#define CLK_BUS_UART7 103 -#define CLK_BUS_DBG 104 - -#define CLK_THS 105 -#define CLK_NAND 106 -#define CLK_MMC0 107 -#define CLK_MMC1 108 -#define CLK_MMC2 109 -#define CLK_MMC3 110 -#define CLK_TS 111 -#define CLK_CE 112 -#define CLK_SPI0 113 -#define CLK_SPI1 114 -#define CLK_SPI2 115 -#define CLK_SPI3 116 -#define CLK_I2S0 117 -#define CLK_I2S1 118 -#define CLK_I2S2 119 -#define CLK_AC97 120 -#define CLK_SPDIF 121 -#define CLK_KEYPAD 122 -#define CLK_SATA 123 -#define CLK_USB_PHY0 124 -#define CLK_USB_PHY1 125 -#define CLK_USB_PHY2 126 -#define CLK_USB_OHCI0 127 -#define CLK_USB_OHCI1 128 -#define CLK_USB_OHCI2 129 -#define CLK_IR0 130 -#define CLK_IR1 131 - -#define CLK_DRAM_VE 133 -#define CLK_DRAM_CSI0 134 -#define CLK_DRAM_CSI1 135 -#define CLK_DRAM_TS 136 -#define CLK_DRAM_TVD 137 -#define CLK_DRAM_MP 138 -#define CLK_DRAM_DEINTERLACE 139 -#define CLK_DE 140 -#define CLK_MP 141 -#define CLK_TCON_LCD0 142 -#define CLK_TCON_LCD1 143 -#define CLK_TCON_TV0 144 -#define CLK_TCON_TV1 145 -#define CLK_DEINTERLACE 146 -#define CLK_CSI1_MCLK 147 -#define CLK_CSI_SCLK 148 -#define CLK_CSI0_MCLK 149 -#define CLK_VE 150 -#define CLK_CODEC 151 -#define CLK_AVS 152 -#define CLK_HDMI 153 -#define CLK_HDMI_SLOW 154 -#define CLK_MBUS 155 -#define CLK_DSI_DPHY 156 -#define CLK_TVE0 157 -#define CLK_TVE1 158 -#define CLK_TVD0 159 -#define CLK_TVD1 160 -#define CLK_TVD2 161 -#define CLK_TVD3 162 -#define CLK_GPU 163 -#define CLK_OUTA 164 -#define CLK_OUTB 165 - -#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */ diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h deleted file mode 100644 index 25164d767835..000000000000 --- a/include/dt-bindings/clock/sun8i-tcon-top.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (C) 2018 Jernej Skrabec jernej.skrabec@siol.net */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ - -#define CLK_TCON_TOP_TV0 0 -#define CLK_TCON_TOP_TV1 1 -#define CLK_TCON_TOP_DSI 2 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h deleted file mode 100644 index 014ac6123d17..000000000000 --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2016 Icenowy Zheng icenowy@aosc.xyz - * - * Based on sun8i-h3-ccu.h, which is: - * Copyright (C) 2016 Maxime Ripard maxime.ripard@free-electrons.com - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_ -#define _DT_BINDINGS_CLK_SUN8I_V3S_H_ - -#define CLK_CPU 14 - -#define CLK_BUS_CE 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_DRAM 25 -#define CLK_BUS_EMAC 26 -#define CLK_BUS_HSTIMER 27 -#define CLK_BUS_SPI0 28 -#define CLK_BUS_OTG 29 -#define CLK_BUS_EHCI0 30 -#define CLK_BUS_OHCI0 31 -#define CLK_BUS_VE 32 -#define CLK_BUS_TCON0 33 -#define CLK_BUS_CSI 34 -#define CLK_BUS_DE 35 -#define CLK_BUS_CODEC 36 -#define CLK_BUS_PIO 37 -#define CLK_BUS_I2C0 38 -#define CLK_BUS_I2C1 39 -#define CLK_BUS_UART0 40 -#define CLK_BUS_UART1 41 -#define CLK_BUS_UART2 42 -#define CLK_BUS_EPHY 43 -#define CLK_BUS_DBG 44 - -#define CLK_MMC0 45 -#define CLK_MMC0_SAMPLE 46 -#define CLK_MMC0_OUTPUT 47 -#define CLK_MMC1 48 -#define CLK_MMC1_SAMPLE 49 -#define CLK_MMC1_OUTPUT 50 -#define CLK_MMC2 51 -#define CLK_MMC2_SAMPLE 52 -#define CLK_MMC2_OUTPUT 53 -#define CLK_CE 54 -#define CLK_SPI0 55 -#define CLK_USB_PHY0 56 -#define CLK_USB_OHCI0 57 - -#define CLK_DRAM_VE 59 -#define CLK_DRAM_CSI 60 -#define CLK_DRAM_EHCI 61 -#define CLK_DRAM_OHCI 62 -#define CLK_DE 63 -#define CLK_TCON0 64 -#define CLK_CSI_MISC 65 -#define CLK_CSI0_MCLK 66 -#define CLK_CSI1_SCLK 67 -#define CLK_CSI1_MCLK 68 -#define CLK_VE 69 -#define CLK_AC_DIG 70 -#define CLK_AVS 71 - -#define CLK_MIPI_CSI 73 - -/* Clocks not available on V3s */ -#define CLK_BUS_I2S0 75 -#define CLK_I2S0 76 - -#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-ccu.h b/include/dt-bindings/clock/sun9i-a80-ccu.h deleted file mode 100644 index 6ea1492a73a6..000000000000 --- a/include/dt-bindings/clock/sun9i-a80-ccu.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai wens@csie.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ - -#define CLK_PLL_AUDIO 2 -#define CLK_PLL_PERIPH0 3 - -#define CLK_C0CPUX 12 -#define CLK_C1CPUX 13 - -#define CLK_OUT_A 27 -#define CLK_OUT_B 28 - -#define CLK_NAND0_0 29 -#define CLK_NAND0_1 30 -#define CLK_NAND1_0 31 -#define CLK_NAND1_1 32 -#define CLK_MMC0 33 -#define CLK_MMC0_SAMPLE 34 -#define CLK_MMC0_OUTPUT 35 -#define CLK_MMC1 36 -#define CLK_MMC1_SAMPLE 37 -#define CLK_MMC1_OUTPUT 38 -#define CLK_MMC2 39 -#define CLK_MMC2_SAMPLE 40 -#define CLK_MMC2_OUTPUT 41 -#define CLK_MMC3 42 -#define CLK_MMC3_SAMPLE 43 -#define CLK_MMC3_OUTPUT 44 -#define CLK_TS 45 -#define CLK_SS 46 -#define CLK_SPI0 47 -#define CLK_SPI1 48 -#define CLK_SPI2 49 -#define CLK_SPI3 50 -#define CLK_I2S0 51 -#define CLK_I2S1 52 -#define CLK_SPDIF 53 -#define CLK_SDRAM 54 -#define CLK_DE 55 -#define CLK_EDP 56 -#define CLK_MP 57 -#define CLK_LCD0 58 -#define CLK_LCD1 59 -#define CLK_MIPI_DSI0 60 -#define CLK_MIPI_DSI1 61 -#define CLK_HDMI 62 -#define CLK_HDMI_SLOW 63 -#define CLK_MIPI_CSI 64 -#define CLK_CSI_ISP 65 -#define CLK_CSI_MISC 66 -#define CLK_CSI0_MCLK 67 -#define CLK_CSI1_MCLK 68 -#define CLK_FD 69 -#define CLK_VE 70 -#define CLK_AVS 71 -#define CLK_GPU_CORE 72 -#define CLK_GPU_MEMORY 73 -#define CLK_GPU_AXI 74 -#define CLK_SATA 75 -#define CLK_AC97 76 -#define CLK_MIPI_HSI 77 -#define CLK_GPADC 78 -#define CLK_CIR_TX 79 - -#define CLK_BUS_FD 80 -#define CLK_BUS_VE 81 -#define CLK_BUS_GPU_CTRL 82 -#define CLK_BUS_SS 83 -#define CLK_BUS_MMC 84 -#define CLK_BUS_NAND0 85 -#define CLK_BUS_NAND1 86 -#define CLK_BUS_SDRAM 87 -#define CLK_BUS_MIPI_HSI 88 -#define CLK_BUS_SATA 89 -#define CLK_BUS_TS 90 -#define CLK_BUS_SPI0 91 -#define CLK_BUS_SPI1 92 -#define CLK_BUS_SPI2 93 -#define CLK_BUS_SPI3 94 - -#define CLK_BUS_OTG 95 -#define CLK_BUS_USB 96 -#define CLK_BUS_GMAC 97 -#define CLK_BUS_MSGBOX 98 -#define CLK_BUS_SPINLOCK 99 -#define CLK_BUS_HSTIMER 100 -#define CLK_BUS_DMA 101 - -#define CLK_BUS_LCD0 102 -#define CLK_BUS_LCD1 103 -#define CLK_BUS_EDP 104 -#define CLK_BUS_CSI 105 -#define CLK_BUS_HDMI 106 -#define CLK_BUS_DE 107 -#define CLK_BUS_MP 108 -#define CLK_BUS_MIPI_DSI 109 - -#define CLK_BUS_SPDIF 110 -#define CLK_BUS_PIO 111 -#define CLK_BUS_AC97 112 -#define CLK_BUS_I2S0 113 -#define CLK_BUS_I2S1 114 -#define CLK_BUS_LRADC 115 -#define CLK_BUS_GPADC 116 -#define CLK_BUS_TWD 117 -#define CLK_BUS_CIR_TX 118 - -#define CLK_BUS_I2C0 119 -#define CLK_BUS_I2C1 120 -#define CLK_BUS_I2C2 121 -#define CLK_BUS_I2C3 122 -#define CLK_BUS_I2C4 123 -#define CLK_BUS_UART0 124 -#define CLK_BUS_UART1 125 -#define CLK_BUS_UART2 126 -#define CLK_BUS_UART3 127 -#define CLK_BUS_UART4 128 -#define CLK_BUS_UART5 129 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-de.h b/include/dt-bindings/clock/sun9i-a80-de.h deleted file mode 100644 index 3dad6c3cd131..000000000000 --- a/include/dt-bindings/clock/sun9i-a80-de.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai wens@csie.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ - -#define CLK_FE0 0 -#define CLK_FE1 1 -#define CLK_FE2 2 -#define CLK_IEP_DEU0 3 -#define CLK_IEP_DEU1 4 -#define CLK_BE0 5 -#define CLK_BE1 6 -#define CLK_BE2 7 -#define CLK_IEP_DRC0 8 -#define CLK_IEP_DRC1 9 -#define CLK_MERGE 10 - -#define CLK_DRAM_FE0 11 -#define CLK_DRAM_FE1 12 -#define CLK_DRAM_FE2 13 -#define CLK_DRAM_DEU0 14 -#define CLK_DRAM_DEU1 15 -#define CLK_DRAM_BE0 16 -#define CLK_DRAM_BE1 17 -#define CLK_DRAM_BE2 18 -#define CLK_DRAM_DRC0 19 -#define CLK_DRAM_DRC1 20 - -#define CLK_BUS_FE0 21 -#define CLK_BUS_FE1 22 -#define CLK_BUS_FE2 23 -#define CLK_BUS_DEU0 24 -#define CLK_BUS_DEU1 25 -#define CLK_BUS_BE0 26 -#define CLK_BUS_BE1 27 -#define CLK_BUS_BE2 28 -#define CLK_BUS_DRC0 29 -#define CLK_BUS_DRC1 30 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-usb.h b/include/dt-bindings/clock/sun9i-a80-usb.h deleted file mode 100644 index 783a60d2ccea..000000000000 --- a/include/dt-bindings/clock/sun9i-a80-usb.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai wens@csie.org - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ - -#define CLK_BUS_HCI0 0 -#define CLK_USB_OHCI0 1 -#define CLK_BUS_HCI1 2 -#define CLK_BUS_HCI2 3 -#define CLK_USB_OHCI2 4 - -#define CLK_USB0_PHY 5 -#define CLK_USB1_HSIC 6 -#define CLK_USB1_PHY 7 -#define CLK_USB2_HSIC 8 -#define CLK_USB2_PHY 9 -#define CLK_USB_HSIC 10 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */ diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h deleted file mode 100644 index d7570765f424..000000000000 --- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (c) 2018 Icenowy Zheng icenowy@aosc.xyz - * - */ - -#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ -#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ - -#define CLK_CPU 11 - -#define CLK_BUS_DMA 14 -#define CLK_BUS_MMC0 15 -#define CLK_BUS_MMC1 16 -#define CLK_BUS_DRAM 17 -#define CLK_BUS_SPI0 18 -#define CLK_BUS_SPI1 19 -#define CLK_BUS_OTG 20 -#define CLK_BUS_VE 21 -#define CLK_BUS_LCD 22 -#define CLK_BUS_DEINTERLACE 23 -#define CLK_BUS_CSI 24 -#define CLK_BUS_TVD 25 -#define CLK_BUS_TVE 26 -#define CLK_BUS_DE_BE 27 -#define CLK_BUS_DE_FE 28 -#define CLK_BUS_CODEC 29 -#define CLK_BUS_SPDIF 30 -#define CLK_BUS_IR 31 -#define CLK_BUS_RSB 32 -#define CLK_BUS_I2S0 33 -#define CLK_BUS_I2C0 34 -#define CLK_BUS_I2C1 35 -#define CLK_BUS_I2C2 36 -#define CLK_BUS_PIO 37 -#define CLK_BUS_UART0 38 -#define CLK_BUS_UART1 39 -#define CLK_BUS_UART2 40 - -#define CLK_MMC0 41 -#define CLK_MMC0_SAMPLE 42 -#define CLK_MMC0_OUTPUT 43 -#define CLK_MMC1 44 -#define CLK_MMC1_SAMPLE 45 -#define CLK_MMC1_OUTPUT 46 -#define CLK_I2S 47 -#define CLK_SPDIF 48 - -#define CLK_USB_PHY0 49 - -#define CLK_DRAM_VE 50 -#define CLK_DRAM_CSI 51 -#define CLK_DRAM_DEINTERLACE 52 -#define CLK_DRAM_TVD 53 -#define CLK_DRAM_DE_FE 54 -#define CLK_DRAM_DE_BE 55 - -#define CLK_DE_BE 56 -#define CLK_DE_FE 57 -#define CLK_TCON 58 -#define CLK_DEINTERLACE 59 -#define CLK_TVE2_CLK 60 -#define CLK_TVE1_CLK 61 -#define CLK_TVD 62 -#define CLK_CSI 63 -#define CLK_VE 64 -#define CLK_CODEC 65 -#define CLK_AVS 66 - -#define CLK_IR 67 - -#endif

Drop in favour of dts/upstream.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/imx5-clock.h | 219 ------------- include/dt-bindings/clock/imx6qdl-clock.h | 278 ----------------- include/dt-bindings/clock/imx6sl-clock.h | 178 ----------- include/dt-bindings/clock/imx6sll-clock.h | 210 ------------- include/dt-bindings/clock/imx6sx-clock.h | 281 ----------------- include/dt-bindings/clock/imx6ul-clock.h | 262 ---------------- include/dt-bindings/clock/imx7d-clock.h | 456 ---------------------------- include/dt-bindings/clock/imx7ulp-clock.h | 119 -------- include/dt-bindings/clock/imx8mm-clock.h | 286 ----------------- include/dt-bindings/clock/imx8mn-clock.h | 262 ---------------- include/dt-bindings/clock/imx8mp-clock.h | 401 ------------------------ include/dt-bindings/clock/imx8mq-clock.h | 431 -------------------------- include/dt-bindings/clock/imx8ulp-clock.h | 258 ---------------- include/dt-bindings/clock/imx93-clock.h | 208 ------------- include/dt-bindings/clock/imxrt1050-clock.h | 72 ----- 15 files changed, 3921 deletions(-)

diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h deleted file mode 100644 index d382fc71aa83..000000000000 --- a/include/dt-bindings/clock/imx5-clock.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright 2013 Lucas Stach, Pengutronix l.stach@pengutronix.de - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX5_H -#define __DT_BINDINGS_CLOCK_IMX5_H - -#define IMX5_CLK_DUMMY 0 -#define IMX5_CLK_CKIL 1 -#define IMX5_CLK_OSC 2 -#define IMX5_CLK_CKIH1 3 -#define IMX5_CLK_CKIH2 4 -#define IMX5_CLK_AHB 5 -#define IMX5_CLK_IPG 6 -#define IMX5_CLK_AXI_A 7 -#define IMX5_CLK_AXI_B 8 -#define IMX5_CLK_UART_PRED 9 -#define IMX5_CLK_UART_ROOT 10 -#define IMX5_CLK_ESDHC_A_PRED 11 -#define IMX5_CLK_ESDHC_B_PRED 12 -#define IMX5_CLK_ESDHC_C_SEL 13 -#define IMX5_CLK_ESDHC_D_SEL 14 -#define IMX5_CLK_EMI_SEL 15 -#define IMX5_CLK_EMI_SLOW_PODF 16 -#define IMX5_CLK_NFC_PODF 17 -#define IMX5_CLK_ECSPI_PRED 18 -#define IMX5_CLK_ECSPI_PODF 19 -#define IMX5_CLK_USBOH3_PRED 20 -#define IMX5_CLK_USBOH3_PODF 21 -#define IMX5_CLK_USB_PHY_PRED 22 -#define IMX5_CLK_USB_PHY_PODF 23 -#define IMX5_CLK_CPU_PODF 24 -#define IMX5_CLK_DI_PRED 25 -#define IMX5_CLK_TVE_SEL 27 -#define IMX5_CLK_UART1_IPG_GATE 28 -#define IMX5_CLK_UART1_PER_GATE 29 -#define IMX5_CLK_UART2_IPG_GATE 30 -#define IMX5_CLK_UART2_PER_GATE 31 -#define IMX5_CLK_UART3_IPG_GATE 32 -#define IMX5_CLK_UART3_PER_GATE 33 -#define IMX5_CLK_I2C1_GATE 34 -#define IMX5_CLK_I2C2_GATE 35 -#define IMX5_CLK_GPT_IPG_GATE 36 -#define IMX5_CLK_PWM1_IPG_GATE 37 -#define IMX5_CLK_PWM1_HF_GATE 38 -#define IMX5_CLK_PWM2_IPG_GATE 39 -#define IMX5_CLK_PWM2_HF_GATE 40 -#define IMX5_CLK_GPT_HF_GATE 41 -#define IMX5_CLK_FEC_GATE 42 -#define IMX5_CLK_USBOH3_PER_GATE 43 -#define IMX5_CLK_ESDHC1_IPG_GATE 44 -#define IMX5_CLK_ESDHC2_IPG_GATE 45 -#define IMX5_CLK_ESDHC3_IPG_GATE 46 -#define IMX5_CLK_ESDHC4_IPG_GATE 47 -#define IMX5_CLK_SSI1_IPG_GATE 48 -#define IMX5_CLK_SSI2_IPG_GATE 49 -#define IMX5_CLK_SSI3_IPG_GATE 50 -#define IMX5_CLK_ECSPI1_IPG_GATE 51 -#define IMX5_CLK_ECSPI1_PER_GATE 52 -#define IMX5_CLK_ECSPI2_IPG_GATE 53 -#define IMX5_CLK_ECSPI2_PER_GATE 54 -#define IMX5_CLK_CSPI_IPG_GATE 55 -#define IMX5_CLK_SDMA_GATE 56 -#define IMX5_CLK_EMI_SLOW_GATE 57 -#define IMX5_CLK_IPU_SEL 58 -#define IMX5_CLK_IPU_GATE 59 -#define IMX5_CLK_NFC_GATE 60 -#define IMX5_CLK_IPU_DI1_GATE 61 -#define IMX5_CLK_VPU_SEL 62 -#define IMX5_CLK_VPU_GATE 63 -#define IMX5_CLK_VPU_REFERENCE_GATE 64 -#define IMX5_CLK_UART4_IPG_GATE 65 -#define IMX5_CLK_UART4_PER_GATE 66 -#define IMX5_CLK_UART5_IPG_GATE 67 -#define IMX5_CLK_UART5_PER_GATE 68 -#define IMX5_CLK_TVE_GATE 69 -#define IMX5_CLK_TVE_PRED 70 -#define IMX5_CLK_ESDHC1_PER_GATE 71 -#define IMX5_CLK_ESDHC2_PER_GATE 72 -#define IMX5_CLK_ESDHC3_PER_GATE 73 -#define IMX5_CLK_ESDHC4_PER_GATE 74 -#define IMX5_CLK_USB_PHY_GATE 75 -#define IMX5_CLK_HSI2C_GATE 76 -#define IMX5_CLK_MIPI_HSC1_GATE 77 -#define IMX5_CLK_MIPI_HSC2_GATE 78 -#define IMX5_CLK_MIPI_ESC_GATE 79 -#define IMX5_CLK_MIPI_HSP_GATE 80 -#define IMX5_CLK_LDB_DI1_DIV_3_5 81 -#define IMX5_CLK_LDB_DI1_DIV 82 -#define IMX5_CLK_LDB_DI0_DIV_3_5 83 -#define IMX5_CLK_LDB_DI0_DIV 84 -#define IMX5_CLK_LDB_DI1_GATE 85 -#define IMX5_CLK_CAN2_SERIAL_GATE 86 -#define IMX5_CLK_CAN2_IPG_GATE 87 -#define IMX5_CLK_I2C3_GATE 88 -#define IMX5_CLK_LP_APM 89 -#define IMX5_CLK_PERIPH_APM 90 -#define IMX5_CLK_MAIN_BUS 91 -#define IMX5_CLK_AHB_MAX 92 -#define IMX5_CLK_AIPS_TZ1 93 -#define IMX5_CLK_AIPS_TZ2 94 -#define IMX5_CLK_TMAX1 95 -#define IMX5_CLK_TMAX2 96 -#define IMX5_CLK_TMAX3 97 -#define IMX5_CLK_SPBA 98 -#define IMX5_CLK_UART_SEL 99 -#define IMX5_CLK_ESDHC_A_SEL 100 -#define IMX5_CLK_ESDHC_B_SEL 101 -#define IMX5_CLK_ESDHC_A_PODF 102 -#define IMX5_CLK_ESDHC_B_PODF 103 -#define IMX5_CLK_ECSPI_SEL 104 -#define IMX5_CLK_USBOH3_SEL 105 -#define IMX5_CLK_USB_PHY_SEL 106 -#define IMX5_CLK_IIM_GATE 107 -#define IMX5_CLK_USBOH3_GATE 108 -#define IMX5_CLK_EMI_FAST_GATE 109 -#define IMX5_CLK_IPU_DI0_GATE 110 -#define IMX5_CLK_GPC_DVFS 111 -#define IMX5_CLK_PLL1_SW 112 -#define IMX5_CLK_PLL2_SW 113 -#define IMX5_CLK_PLL3_SW 114 -#define IMX5_CLK_IPU_DI0_SEL 115 -#define IMX5_CLK_IPU_DI1_SEL 116 -#define IMX5_CLK_TVE_EXT_SEL 117 -#define IMX5_CLK_MX51_MIPI 118 -#define IMX5_CLK_PLL4_SW 119 -#define IMX5_CLK_LDB_DI1_SEL 120 -#define IMX5_CLK_DI_PLL4_PODF 121 -#define IMX5_CLK_LDB_DI0_SEL 122 -#define IMX5_CLK_LDB_DI0_GATE 123 -#define IMX5_CLK_USB_PHY1_GATE 124 -#define IMX5_CLK_USB_PHY2_GATE 125 -#define IMX5_CLK_PER_LP_APM 126 -#define IMX5_CLK_PER_PRED1 127 -#define IMX5_CLK_PER_PRED2 128 -#define IMX5_CLK_PER_PODF 129 -#define IMX5_CLK_PER_ROOT 130 -#define IMX5_CLK_SSI_APM 131 -#define IMX5_CLK_SSI1_ROOT_SEL 132 -#define IMX5_CLK_SSI2_ROOT_SEL 133 -#define IMX5_CLK_SSI3_ROOT_SEL 134 -#define IMX5_CLK_SSI_EXT1_SEL 135 -#define IMX5_CLK_SSI_EXT2_SEL 136 -#define IMX5_CLK_SSI_EXT1_COM_SEL 137 -#define IMX5_CLK_SSI_EXT2_COM_SEL 138 -#define IMX5_CLK_SSI1_ROOT_PRED 139 -#define IMX5_CLK_SSI1_ROOT_PODF 140 -#define IMX5_CLK_SSI2_ROOT_PRED 141 -#define IMX5_CLK_SSI2_ROOT_PODF 142 -#define IMX5_CLK_SSI_EXT1_PRED 143 -#define IMX5_CLK_SSI_EXT1_PODF 144 -#define IMX5_CLK_SSI_EXT2_PRED 145 -#define IMX5_CLK_SSI_EXT2_PODF 146 -#define IMX5_CLK_SSI1_ROOT_GATE 147 -#define IMX5_CLK_SSI2_ROOT_GATE 148 -#define IMX5_CLK_SSI3_ROOT_GATE 149 -#define IMX5_CLK_SSI_EXT1_GATE 150 -#define IMX5_CLK_SSI_EXT2_GATE 151 -#define IMX5_CLK_EPIT1_IPG_GATE 152 -#define IMX5_CLK_EPIT1_HF_GATE 153 -#define IMX5_CLK_EPIT2_IPG_GATE 154 -#define IMX5_CLK_EPIT2_HF_GATE 155 -#define IMX5_CLK_CAN_SEL 156 -#define IMX5_CLK_CAN1_SERIAL_GATE 157 -#define IMX5_CLK_CAN1_IPG_GATE 158 -#define IMX5_CLK_OWIRE_GATE 159 -#define IMX5_CLK_GPU3D_SEL 160 -#define IMX5_CLK_GPU2D_SEL 161 -#define IMX5_CLK_GPU3D_GATE 162 -#define IMX5_CLK_GPU2D_GATE 163 -#define IMX5_CLK_GARB_GATE 164 -#define IMX5_CLK_CKO1_SEL 165 -#define IMX5_CLK_CKO1_PODF 166 -#define IMX5_CLK_CKO1 167 -#define IMX5_CLK_CKO2_SEL 168 -#define IMX5_CLK_CKO2_PODF 169 -#define IMX5_CLK_CKO2 170 -#define IMX5_CLK_SRTC_GATE 171 -#define IMX5_CLK_PATA_GATE 172 -#define IMX5_CLK_SATA_GATE 173 -#define IMX5_CLK_SPDIF_XTAL_SEL 174 -#define IMX5_CLK_SPDIF0_SEL 175 -#define IMX5_CLK_SPDIF1_SEL 176 -#define IMX5_CLK_SPDIF0_PRED 177 -#define IMX5_CLK_SPDIF0_PODF 178 -#define IMX5_CLK_SPDIF1_PRED 179 -#define IMX5_CLK_SPDIF1_PODF 180 -#define IMX5_CLK_SPDIF0_COM_SEL 181 -#define IMX5_CLK_SPDIF1_COM_SEL 182 -#define IMX5_CLK_SPDIF0_GATE 183 -#define IMX5_CLK_SPDIF1_GATE 184 -#define IMX5_CLK_SPDIF_IPG_GATE 185 -#define IMX5_CLK_OCRAM 186 -#define IMX5_CLK_SAHARA_IPG_GATE 187 -#define IMX5_CLK_SATA_REF 188 -#define IMX5_CLK_STEP_SEL 189 -#define IMX5_CLK_CPU_PODF_SEL 190 -#define IMX5_CLK_ARM 191 -#define IMX5_CLK_FIRI_PRED 192 -#define IMX5_CLK_FIRI_SEL 193 -#define IMX5_CLK_FIRI_PODF 194 -#define IMX5_CLK_FIRI_SERIAL_GATE 195 -#define IMX5_CLK_FIRI_IPG_GATE 196 -#define IMX5_CLK_CSI0_MCLK1_PRED 197 -#define IMX5_CLK_CSI0_MCLK1_SEL 198 -#define IMX5_CLK_CSI0_MCLK1_PODF 199 -#define IMX5_CLK_CSI0_MCLK1_GATE 200 -#define IMX5_CLK_IEEE1588_PRED 201 -#define IMX5_CLK_IEEE1588_SEL 202 -#define IMX5_CLK_IEEE1588_PODF 203 -#define IMX5_CLK_IEEE1588_GATE 204 -#define IMX5_CLK_END 205 - -#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h deleted file mode 100644 index e20c43cc36f6..000000000000 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ /dev/null @@ -1,278 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H -#define __DT_BINDINGS_CLOCK_IMX6QDL_H - -#define IMX6QDL_CLK_DUMMY 0 -#define IMX6QDL_CLK_CKIL 1 -#define IMX6QDL_CLK_CKIH 2 -#define IMX6QDL_CLK_OSC 3 -#define IMX6QDL_CLK_PLL2_PFD0_352M 4 -#define IMX6QDL_CLK_PLL2_PFD1_594M 5 -#define IMX6QDL_CLK_PLL2_PFD2_396M 6 -#define IMX6QDL_CLK_PLL3_PFD0_720M 7 -#define IMX6QDL_CLK_PLL3_PFD1_540M 8 -#define IMX6QDL_CLK_PLL3_PFD2_508M 9 -#define IMX6QDL_CLK_PLL3_PFD3_454M 10 -#define IMX6QDL_CLK_PLL2_198M 11 -#define IMX6QDL_CLK_PLL3_120M 12 -#define IMX6QDL_CLK_PLL3_80M 13 -#define IMX6QDL_CLK_PLL3_60M 14 -#define IMX6QDL_CLK_TWD 15 -#define IMX6QDL_CLK_STEP 16 -#define IMX6QDL_CLK_PLL1_SW 17 -#define IMX6QDL_CLK_PERIPH_PRE 18 -#define IMX6QDL_CLK_PERIPH2_PRE 19 -#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 -#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 -#define IMX6QDL_CLK_AXI_SEL 22 -#define IMX6QDL_CLK_ESAI_SEL 23 -#define IMX6QDL_CLK_ASRC_SEL 24 -#define IMX6QDL_CLK_SPDIF_SEL 25 -#define IMX6QDL_CLK_GPU2D_AXI 26 -#define IMX6QDL_CLK_GPU3D_AXI 27 -#define IMX6QDL_CLK_GPU2D_CORE_SEL 28 -#define IMX6QDL_CLK_GPU3D_CORE_SEL 29 -#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 -#define IMX6QDL_CLK_IPU1_SEL 31 -#define IMX6QDL_CLK_IPU2_SEL 32 -#define IMX6QDL_CLK_LDB_DI0_SEL 33 -#define IMX6QDL_CLK_LDB_DI1_SEL 34 -#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 -#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 -#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 -#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 -#define IMX6QDL_CLK_IPU1_DI0_SEL 39 -#define IMX6QDL_CLK_IPU1_DI1_SEL 40 -#define IMX6QDL_CLK_IPU2_DI0_SEL 41 -#define IMX6QDL_CLK_IPU2_DI1_SEL 42 -#define IMX6QDL_CLK_HSI_TX_SEL 43 -#define IMX6QDL_CLK_PCIE_AXI_SEL 44 -#define IMX6QDL_CLK_SSI1_SEL 45 -#define IMX6QDL_CLK_SSI2_SEL 46 -#define IMX6QDL_CLK_SSI3_SEL 47 -#define IMX6QDL_CLK_USDHC1_SEL 48 -#define IMX6QDL_CLK_USDHC2_SEL 49 -#define IMX6QDL_CLK_USDHC3_SEL 50 -#define IMX6QDL_CLK_USDHC4_SEL 51 -#define IMX6QDL_CLK_ENFC_SEL 52 -#define IMX6QDL_CLK_EIM_SEL 53 -#define IMX6QDL_CLK_EIM_SLOW_SEL 54 -#define IMX6QDL_CLK_VDO_AXI_SEL 55 -#define IMX6QDL_CLK_VPU_AXI_SEL 56 -#define IMX6QDL_CLK_CKO1_SEL 57 -#define IMX6QDL_CLK_PERIPH 58 -#define IMX6QDL_CLK_PERIPH2 59 -#define IMX6QDL_CLK_PERIPH_CLK2 60 -#define IMX6QDL_CLK_PERIPH2_CLK2 61 -#define IMX6QDL_CLK_IPG 62 -#define IMX6QDL_CLK_IPG_PER 63 -#define IMX6QDL_CLK_ESAI_PRED 64 -#define IMX6QDL_CLK_ESAI_PODF 65 -#define IMX6QDL_CLK_ASRC_PRED 66 -#define IMX6QDL_CLK_ASRC_PODF 67 -#define IMX6QDL_CLK_SPDIF_PRED 68 -#define IMX6QDL_CLK_SPDIF_PODF 69 -#define IMX6QDL_CLK_CAN_ROOT 70 -#define IMX6QDL_CLK_ECSPI_ROOT 71 -#define IMX6QDL_CLK_GPU2D_CORE_PODF 72 -#define IMX6QDL_CLK_GPU3D_CORE_PODF 73 -#define IMX6QDL_CLK_GPU3D_SHADER 74 -#define IMX6QDL_CLK_IPU1_PODF 75 -#define IMX6QDL_CLK_IPU2_PODF 76 -#define IMX6QDL_CLK_LDB_DI0_PODF 77 -#define IMX6QDL_CLK_LDB_DI1_PODF 78 -#define IMX6QDL_CLK_IPU1_DI0_PRE 79 -#define IMX6QDL_CLK_IPU1_DI1_PRE 80 -#define IMX6QDL_CLK_IPU2_DI0_PRE 81 -#define IMX6QDL_CLK_IPU2_DI1_PRE 82 -#define IMX6QDL_CLK_HSI_TX_PODF 83 -#define IMX6QDL_CLK_SSI1_PRED 84 -#define IMX6QDL_CLK_SSI1_PODF 85 -#define IMX6QDL_CLK_SSI2_PRED 86 -#define IMX6QDL_CLK_SSI2_PODF 87 -#define IMX6QDL_CLK_SSI3_PRED 88 -#define IMX6QDL_CLK_SSI3_PODF 89 -#define IMX6QDL_CLK_UART_SERIAL_PODF 90 -#define IMX6QDL_CLK_USDHC1_PODF 91 -#define IMX6QDL_CLK_USDHC2_PODF 92 -#define IMX6QDL_CLK_USDHC3_PODF 93 -#define IMX6QDL_CLK_USDHC4_PODF 94 -#define IMX6QDL_CLK_ENFC_PRED 95 -#define IMX6QDL_CLK_ENFC_PODF 96 -#define IMX6QDL_CLK_EIM_PODF 97 -#define IMX6QDL_CLK_EIM_SLOW_PODF 98 -#define IMX6QDL_CLK_VPU_AXI_PODF 99 -#define IMX6QDL_CLK_CKO1_PODF 100 -#define IMX6QDL_CLK_AXI 101 -#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 -#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 -#define IMX6QDL_CLK_ARM 104 -#define IMX6QDL_CLK_AHB 105 -#define IMX6QDL_CLK_APBH_DMA 106 -#define IMX6QDL_CLK_ASRC 107 -#define IMX6QDL_CLK_CAN1_IPG 108 -#define IMX6QDL_CLK_CAN1_SERIAL 109 -#define IMX6QDL_CLK_CAN2_IPG 110 -#define IMX6QDL_CLK_CAN2_SERIAL 111 -#define IMX6QDL_CLK_ECSPI1 112 -#define IMX6QDL_CLK_ECSPI2 113 -#define IMX6QDL_CLK_ECSPI3 114 -#define IMX6QDL_CLK_ECSPI4 115 -#define IMX6Q_CLK_ECSPI5 116 -#define IMX6DL_CLK_I2C4 116 -#define IMX6QDL_CLK_ENET 117 -#define IMX6QDL_CLK_ESAI_EXTAL 118 -#define IMX6QDL_CLK_GPT_IPG 119 -#define IMX6QDL_CLK_GPT_IPG_PER 120 -#define IMX6QDL_CLK_GPU2D_CORE 121 -#define IMX6QDL_CLK_GPU3D_CORE 122 -#define IMX6QDL_CLK_HDMI_IAHB 123 -#define IMX6QDL_CLK_HDMI_ISFR 124 -#define IMX6QDL_CLK_I2C1 125 -#define IMX6QDL_CLK_I2C2 126 -#define IMX6QDL_CLK_I2C3 127 -#define IMX6QDL_CLK_IIM 128 -#define IMX6QDL_CLK_ENFC 129 -#define IMX6QDL_CLK_IPU1 130 -#define IMX6QDL_CLK_IPU1_DI0 131 -#define IMX6QDL_CLK_IPU1_DI1 132 -#define IMX6QDL_CLK_IPU2 133 -#define IMX6QDL_CLK_IPU2_DI0 134 -#define IMX6QDL_CLK_LDB_DI0 135 -#define IMX6QDL_CLK_LDB_DI1 136 -#define IMX6QDL_CLK_IPU2_DI1 137 -#define IMX6QDL_CLK_HSI_TX 138 -#define IMX6QDL_CLK_MLB 139 -#define IMX6QDL_CLK_MMDC_CH0_AXI 140 -#define IMX6QDL_CLK_MMDC_CH1_AXI 141 -#define IMX6QDL_CLK_OCRAM 142 -#define IMX6QDL_CLK_OPENVG_AXI 143 -#define IMX6QDL_CLK_PCIE_AXI 144 -#define IMX6QDL_CLK_PWM1 145 -#define IMX6QDL_CLK_PWM2 146 -#define IMX6QDL_CLK_PWM3 147 -#define IMX6QDL_CLK_PWM4 148 -#define IMX6QDL_CLK_PER1_BCH 149 -#define IMX6QDL_CLK_GPMI_BCH_APB 150 -#define IMX6QDL_CLK_GPMI_BCH 151 -#define IMX6QDL_CLK_GPMI_IO 152 -#define IMX6QDL_CLK_GPMI_APB 153 -#define IMX6QDL_CLK_SATA 154 -#define IMX6QDL_CLK_SDMA 155 -#define IMX6QDL_CLK_SPBA 156 -#define IMX6QDL_CLK_SSI1 157 -#define IMX6QDL_CLK_SSI2 158 -#define IMX6QDL_CLK_SSI3 159 -#define IMX6QDL_CLK_UART_IPG 160 -#define IMX6QDL_CLK_UART_SERIAL 161 -#define IMX6QDL_CLK_USBOH3 162 -#define IMX6QDL_CLK_USDHC1 163 -#define IMX6QDL_CLK_USDHC2 164 -#define IMX6QDL_CLK_USDHC3 165 -#define IMX6QDL_CLK_USDHC4 166 -#define IMX6QDL_CLK_VDO_AXI 167 -#define IMX6QDL_CLK_VPU_AXI 168 -#define IMX6QDL_CLK_CKO1 169 -#define IMX6QDL_CLK_PLL1_SYS 170 -#define IMX6QDL_CLK_PLL2_BUS 171 -#define IMX6QDL_CLK_PLL3_USB_OTG 172 -#define IMX6QDL_CLK_PLL4_AUDIO 173 -#define IMX6QDL_CLK_PLL5_VIDEO 174 -#define IMX6QDL_CLK_PLL8_MLB 175 -#define IMX6QDL_CLK_PLL7_USB_HOST 176 -#define IMX6QDL_CLK_PLL6_ENET 177 -#define IMX6QDL_CLK_SSI1_IPG 178 -#define IMX6QDL_CLK_SSI2_IPG 179 -#define IMX6QDL_CLK_SSI3_IPG 180 -#define IMX6QDL_CLK_ROM 181 -#define IMX6QDL_CLK_USBPHY1 182 -#define IMX6QDL_CLK_USBPHY2 183 -#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 -#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 -#define IMX6QDL_CLK_SATA_REF 186 -#define IMX6QDL_CLK_SATA_REF_100M 187 -#define IMX6QDL_CLK_PCIE_REF 188 -#define IMX6QDL_CLK_PCIE_REF_125M 189 -#define IMX6QDL_CLK_ENET_REF 190 -#define IMX6QDL_CLK_USBPHY1_GATE 191 -#define IMX6QDL_CLK_USBPHY2_GATE 192 -#define IMX6QDL_CLK_PLL4_POST_DIV 193 -#define IMX6QDL_CLK_PLL5_POST_DIV 194 -#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 -#define IMX6QDL_CLK_EIM_SLOW 196 -#define IMX6QDL_CLK_SPDIF 197 -#define IMX6QDL_CLK_CKO2_SEL 198 -#define IMX6QDL_CLK_CKO2_PODF 199 -#define IMX6QDL_CLK_CKO2 200 -#define IMX6QDL_CLK_CKO 201 -#define IMX6QDL_CLK_VDOA 202 -#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 -#define IMX6QDL_CLK_LVDS1_SEL 204 -#define IMX6QDL_CLK_LVDS2_SEL 205 -#define IMX6QDL_CLK_LVDS1_GATE 206 -#define IMX6QDL_CLK_LVDS2_GATE 207 -#define IMX6QDL_CLK_ESAI_IPG 208 -#define IMX6QDL_CLK_ESAI_MEM 209 -#define IMX6QDL_CLK_ASRC_IPG 210 -#define IMX6QDL_CLK_ASRC_MEM 211 -#define IMX6QDL_CLK_LVDS1_IN 212 -#define IMX6QDL_CLK_LVDS2_IN 213 -#define IMX6QDL_CLK_ANACLK1 214 -#define IMX6QDL_CLK_ANACLK2 215 -#define IMX6QDL_PLL1_BYPASS_SRC 216 -#define IMX6QDL_PLL2_BYPASS_SRC 217 -#define IMX6QDL_PLL3_BYPASS_SRC 218 -#define IMX6QDL_PLL4_BYPASS_SRC 219 -#define IMX6QDL_PLL5_BYPASS_SRC 220 -#define IMX6QDL_PLL6_BYPASS_SRC 221 -#define IMX6QDL_PLL7_BYPASS_SRC 222 -#define IMX6QDL_CLK_PLL1 223 -#define IMX6QDL_CLK_PLL2 224 -#define IMX6QDL_CLK_PLL3 225 -#define IMX6QDL_CLK_PLL4 226 -#define IMX6QDL_CLK_PLL5 227 -#define IMX6QDL_CLK_PLL6 228 -#define IMX6QDL_CLK_PLL7 229 -#define IMX6QDL_PLL1_BYPASS 230 -#define IMX6QDL_PLL2_BYPASS 231 -#define IMX6QDL_PLL3_BYPASS 232 -#define IMX6QDL_PLL4_BYPASS 233 -#define IMX6QDL_PLL5_BYPASS 234 -#define IMX6QDL_PLL6_BYPASS 235 -#define IMX6QDL_PLL7_BYPASS 236 -#define IMX6QDL_CLK_GPT_3M 237 -#define IMX6QDL_CLK_VIDEO_27M 238 -#define IMX6QDL_CLK_MIPI_CORE_CFG 239 -#define IMX6QDL_CLK_MIPI_IPG 240 -#define IMX6QDL_CLK_CAAM_MEM 241 -#define IMX6QDL_CLK_CAAM_ACLK 242 -#define IMX6QDL_CLK_CAAM_IPG 243 -#define IMX6QDL_CLK_SPDIF_GCLK 244 -#define IMX6QDL_CLK_UART_SEL 245 -#define IMX6QDL_CLK_IPG_PER_SEL 246 -#define IMX6QDL_CLK_ECSPI_SEL 247 -#define IMX6QDL_CLK_CAN_SEL 248 -#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 -#define IMX6QDL_CLK_PRE0 250 -#define IMX6QDL_CLK_PRE1 251 -#define IMX6QDL_CLK_PRE2 252 -#define IMX6QDL_CLK_PRE3 253 -#define IMX6QDL_CLK_PRG0_AXI 254 -#define IMX6QDL_CLK_PRG1_AXI 255 -#define IMX6QDL_CLK_PRG0_APB 256 -#define IMX6QDL_CLK_PRG1_APB 257 -#define IMX6QDL_CLK_PRE_AXI 258 -#define IMX6QDL_CLK_MLB_SEL 259 -#define IMX6QDL_CLK_MLB_PODF 260 -#define IMX6QDL_CLK_EPIT1 261 -#define IMX6QDL_CLK_EPIT2 262 -#define IMX6QDL_CLK_MMDC_P0_IPG 263 -#define IMX6QDL_CLK_DCIC1 264 -#define IMX6QDL_CLK_DCIC2 265 -#define IMX6QDL_CLK_END 266 - -#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h deleted file mode 100644 index 31364d2caae6..000000000000 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H -#define __DT_BINDINGS_CLOCK_IMX6SL_H - -#define IMX6SL_CLK_DUMMY 0 -#define IMX6SL_CLK_CKIL 1 -#define IMX6SL_CLK_OSC 2 -#define IMX6SL_CLK_PLL1_SYS 3 -#define IMX6SL_CLK_PLL2_BUS 4 -#define IMX6SL_CLK_PLL3_USB_OTG 5 -#define IMX6SL_CLK_PLL4_AUDIO 6 -#define IMX6SL_CLK_PLL5_VIDEO 7 -#define IMX6SL_CLK_PLL6_ENET 8 -#define IMX6SL_CLK_PLL7_USB_HOST 9 -#define IMX6SL_CLK_USBPHY1 10 -#define IMX6SL_CLK_USBPHY2 11 -#define IMX6SL_CLK_USBPHY1_GATE 12 -#define IMX6SL_CLK_USBPHY2_GATE 13 -#define IMX6SL_CLK_PLL4_POST_DIV 14 -#define IMX6SL_CLK_PLL5_POST_DIV 15 -#define IMX6SL_CLK_PLL5_VIDEO_DIV 16 -#define IMX6SL_CLK_ENET_REF 17 -#define IMX6SL_CLK_PLL2_PFD0 18 -#define IMX6SL_CLK_PLL2_PFD1 19 -#define IMX6SL_CLK_PLL2_PFD2 20 -#define IMX6SL_CLK_PLL3_PFD0 21 -#define IMX6SL_CLK_PLL3_PFD1 22 -#define IMX6SL_CLK_PLL3_PFD2 23 -#define IMX6SL_CLK_PLL3_PFD3 24 -#define IMX6SL_CLK_PLL2_198M 25 -#define IMX6SL_CLK_PLL3_120M 26 -#define IMX6SL_CLK_PLL3_80M 27 -#define IMX6SL_CLK_PLL3_60M 28 -#define IMX6SL_CLK_STEP 29 -#define IMX6SL_CLK_PLL1_SW 30 -#define IMX6SL_CLK_OCRAM_ALT_SEL 31 -#define IMX6SL_CLK_OCRAM_SEL 32 -#define IMX6SL_CLK_PRE_PERIPH2_SEL 33 -#define IMX6SL_CLK_PRE_PERIPH_SEL 34 -#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35 -#define IMX6SL_CLK_PERIPH_CLK2_SEL 36 -#define IMX6SL_CLK_CSI_SEL 37 -#define IMX6SL_CLK_LCDIF_AXI_SEL 38 -#define IMX6SL_CLK_USDHC1_SEL 39 -#define IMX6SL_CLK_USDHC2_SEL 40 -#define IMX6SL_CLK_USDHC3_SEL 41 -#define IMX6SL_CLK_USDHC4_SEL 42 -#define IMX6SL_CLK_SSI1_SEL 43 -#define IMX6SL_CLK_SSI2_SEL 44 -#define IMX6SL_CLK_SSI3_SEL 45 -#define IMX6SL_CLK_PERCLK_SEL 46 -#define IMX6SL_CLK_PXP_AXI_SEL 47 -#define IMX6SL_CLK_EPDC_AXI_SEL 48 -#define IMX6SL_CLK_GPU2D_OVG_SEL 49 -#define IMX6SL_CLK_GPU2D_SEL 50 -#define IMX6SL_CLK_LCDIF_PIX_SEL 51 -#define IMX6SL_CLK_EPDC_PIX_SEL 52 -#define IMX6SL_CLK_SPDIF0_SEL 53 -#define IMX6SL_CLK_SPDIF1_SEL 54 -#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55 -#define IMX6SL_CLK_ECSPI_SEL 56 -#define IMX6SL_CLK_UART_SEL 57 -#define IMX6SL_CLK_PERIPH 58 -#define IMX6SL_CLK_PERIPH2 59 -#define IMX6SL_CLK_OCRAM_PODF 60 -#define IMX6SL_CLK_PERIPH_CLK2_PODF 61 -#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62 -#define IMX6SL_CLK_IPG 63 -#define IMX6SL_CLK_CSI_PODF 64 -#define IMX6SL_CLK_LCDIF_AXI_PODF 65 -#define IMX6SL_CLK_USDHC1_PODF 66 -#define IMX6SL_CLK_USDHC2_PODF 67 -#define IMX6SL_CLK_USDHC3_PODF 68 -#define IMX6SL_CLK_USDHC4_PODF 69 -#define IMX6SL_CLK_SSI1_PRED 70 -#define IMX6SL_CLK_SSI1_PODF 71 -#define IMX6SL_CLK_SSI2_PRED 72 -#define IMX6SL_CLK_SSI2_PODF 73 -#define IMX6SL_CLK_SSI3_PRED 74 -#define IMX6SL_CLK_SSI3_PODF 75 -#define IMX6SL_CLK_PERCLK 76 -#define IMX6SL_CLK_PXP_AXI_PODF 77 -#define IMX6SL_CLK_EPDC_AXI_PODF 78 -#define IMX6SL_CLK_GPU2D_OVG_PODF 79 -#define IMX6SL_CLK_GPU2D_PODF 80 -#define IMX6SL_CLK_LCDIF_PIX_PRED 81 -#define IMX6SL_CLK_EPDC_PIX_PRED 82 -#define IMX6SL_CLK_LCDIF_PIX_PODF 83 -#define IMX6SL_CLK_EPDC_PIX_PODF 84 -#define IMX6SL_CLK_SPDIF0_PRED 85 -#define IMX6SL_CLK_SPDIF0_PODF 86 -#define IMX6SL_CLK_SPDIF1_PRED 87 -#define IMX6SL_CLK_SPDIF1_PODF 88 -#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89 -#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90 -#define IMX6SL_CLK_ECSPI_ROOT 91 -#define IMX6SL_CLK_UART_ROOT 92 -#define IMX6SL_CLK_AHB 93 -#define IMX6SL_CLK_MMDC_ROOT 94 -#define IMX6SL_CLK_ARM 95 -#define IMX6SL_CLK_ECSPI1 96 -#define IMX6SL_CLK_ECSPI2 97 -#define IMX6SL_CLK_ECSPI3 98 -#define IMX6SL_CLK_ECSPI4 99 -#define IMX6SL_CLK_EPIT1 100 -#define IMX6SL_CLK_EPIT2 101 -#define IMX6SL_CLK_EXTERN_AUDIO 102 -#define IMX6SL_CLK_GPT 103 -#define IMX6SL_CLK_GPT_SERIAL 104 -#define IMX6SL_CLK_GPU2D_OVG 105 -#define IMX6SL_CLK_I2C1 106 -#define IMX6SL_CLK_I2C2 107 -#define IMX6SL_CLK_I2C3 108 -#define IMX6SL_CLK_OCOTP 109 -#define IMX6SL_CLK_CSI 110 -#define IMX6SL_CLK_PXP_AXI 111 -#define IMX6SL_CLK_EPDC_AXI 112 -#define IMX6SL_CLK_LCDIF_AXI 113 -#define IMX6SL_CLK_LCDIF_PIX 114 -#define IMX6SL_CLK_EPDC_PIX 115 -#define IMX6SL_CLK_OCRAM 116 -#define IMX6SL_CLK_PWM1 117 -#define IMX6SL_CLK_PWM2 118 -#define IMX6SL_CLK_PWM3 119 -#define IMX6SL_CLK_PWM4 120 -#define IMX6SL_CLK_SDMA 121 -#define IMX6SL_CLK_SPDIF 122 -#define IMX6SL_CLK_SSI1 123 -#define IMX6SL_CLK_SSI2 124 -#define IMX6SL_CLK_SSI3 125 -#define IMX6SL_CLK_UART 126 -#define IMX6SL_CLK_UART_SERIAL 127 -#define IMX6SL_CLK_USBOH3 128 -#define IMX6SL_CLK_USDHC1 129 -#define IMX6SL_CLK_USDHC2 130 -#define IMX6SL_CLK_USDHC3 131 -#define IMX6SL_CLK_USDHC4 132 -#define IMX6SL_CLK_PLL4_AUDIO_DIV 133 -#define IMX6SL_CLK_SPBA 134 -#define IMX6SL_CLK_ENET 135 -#define IMX6SL_CLK_LVDS1_SEL 136 -#define IMX6SL_CLK_LVDS1_OUT 137 -#define IMX6SL_CLK_LVDS1_IN 138 -#define IMX6SL_CLK_ANACLK1 139 -#define IMX6SL_PLL1_BYPASS_SRC 140 -#define IMX6SL_PLL2_BYPASS_SRC 141 -#define IMX6SL_PLL3_BYPASS_SRC 142 -#define IMX6SL_PLL4_BYPASS_SRC 143 -#define IMX6SL_PLL5_BYPASS_SRC 144 -#define IMX6SL_PLL6_BYPASS_SRC 145 -#define IMX6SL_PLL7_BYPASS_SRC 146 -#define IMX6SL_CLK_PLL1 147 -#define IMX6SL_CLK_PLL2 148 -#define IMX6SL_CLK_PLL3 149 -#define IMX6SL_CLK_PLL4 150 -#define IMX6SL_CLK_PLL5 151 -#define IMX6SL_CLK_PLL6 152 -#define IMX6SL_CLK_PLL7 153 -#define IMX6SL_PLL1_BYPASS 154 -#define IMX6SL_PLL2_BYPASS 155 -#define IMX6SL_PLL3_BYPASS 156 -#define IMX6SL_PLL4_BYPASS 157 -#define IMX6SL_PLL5_BYPASS 158 -#define IMX6SL_PLL6_BYPASS 159 -#define IMX6SL_PLL7_BYPASS 160 -#define IMX6SL_CLK_SSI1_IPG 161 -#define IMX6SL_CLK_SSI2_IPG 162 -#define IMX6SL_CLK_SSI3_IPG 163 -#define IMX6SL_CLK_SPDIF_GCLK 164 -#define IMX6SL_CLK_MMDC_P0_IPG 165 -#define IMX6SL_CLK_MMDC_P1_IPG 166 -#define IMX6SL_CLK_END 167 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h deleted file mode 100644 index 494fd0c37fb5..000000000000 --- a/include/dt-bindings/clock/imx6sll-clock.h +++ /dev/null @@ -1,210 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H -#define __DT_BINDINGS_CLOCK_IMX6SLL_H - -#define IMX6SLL_CLK_DUMMY 0 -#define IMX6SLL_CLK_CKIL 1 -#define IMX6SLL_CLK_OSC 2 -#define IMX6SLL_PLL1_BYPASS_SRC 3 -#define IMX6SLL_PLL2_BYPASS_SRC 4 -#define IMX6SLL_PLL3_BYPASS_SRC 5 -#define IMX6SLL_PLL4_BYPASS_SRC 6 -#define IMX6SLL_PLL5_BYPASS_SRC 7 -#define IMX6SLL_PLL6_BYPASS_SRC 8 -#define IMX6SLL_PLL7_BYPASS_SRC 9 -#define IMX6SLL_CLK_PLL1 10 -#define IMX6SLL_CLK_PLL2 11 -#define IMX6SLL_CLK_PLL3 12 -#define IMX6SLL_CLK_PLL4 13 -#define IMX6SLL_CLK_PLL5 14 -#define IMX6SLL_CLK_PLL6 15 -#define IMX6SLL_CLK_PLL7 16 -#define IMX6SLL_PLL1_BYPASS 17 -#define IMX6SLL_PLL2_BYPASS 18 -#define IMX6SLL_PLL3_BYPASS 19 -#define IMX6SLL_PLL4_BYPASS 20 -#define IMX6SLL_PLL5_BYPASS 21 -#define IMX6SLL_PLL6_BYPASS 22 -#define IMX6SLL_PLL7_BYPASS 23 -#define IMX6SLL_CLK_PLL1_SYS 24 -#define IMX6SLL_CLK_PLL2_BUS 25 -#define IMX6SLL_CLK_PLL3_USB_OTG 26 -#define IMX6SLL_CLK_PLL4_AUDIO 27 -#define IMX6SLL_CLK_PLL5_VIDEO 28 -#define IMX6SLL_CLK_PLL6_ENET 29 -#define IMX6SLL_CLK_PLL7_USB_HOST 30 -#define IMX6SLL_CLK_USBPHY1 31 -#define IMX6SLL_CLK_USBPHY2 32 -#define IMX6SLL_CLK_USBPHY1_GATE 33 -#define IMX6SLL_CLK_USBPHY2_GATE 34 -#define IMX6SLL_CLK_PLL2_PFD0 35 -#define IMX6SLL_CLK_PLL2_PFD1 36 -#define IMX6SLL_CLK_PLL2_PFD2 37 -#define IMX6SLL_CLK_PLL2_PFD3 38 -#define IMX6SLL_CLK_PLL3_PFD0 39 -#define IMX6SLL_CLK_PLL3_PFD1 40 -#define IMX6SLL_CLK_PLL3_PFD2 41 -#define IMX6SLL_CLK_PLL3_PFD3 42 -#define IMX6SLL_CLK_PLL4_POST_DIV 43 -#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 -#define IMX6SLL_CLK_PLL5_POST_DIV 45 -#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 -#define IMX6SLL_CLK_PLL2_198M 47 -#define IMX6SLL_CLK_PLL3_120M 48 -#define IMX6SLL_CLK_PLL3_80M 49 -#define IMX6SLL_CLK_PLL3_60M 50 -#define IMX6SLL_CLK_STEP 51 -#define IMX6SLL_CLK_PLL1_SW 52 -#define IMX6SLL_CLK_AXI_ALT_SEL 53 -#define IMX6SLL_CLK_AXI_SEL 54 -#define IMX6SLL_CLK_PERIPH_PRE 55 -#define IMX6SLL_CLK_PERIPH2_PRE 56 -#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 -#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 -#define IMX6SLL_CLK_PERCLK_SEL 59 -#define IMX6SLL_CLK_USDHC1_SEL 60 -#define IMX6SLL_CLK_USDHC2_SEL 61 -#define IMX6SLL_CLK_USDHC3_SEL 62 -#define IMX6SLL_CLK_SSI1_SEL 63 -#define IMX6SLL_CLK_SSI2_SEL 64 -#define IMX6SLL_CLK_SSI3_SEL 65 -#define IMX6SLL_CLK_PXP_SEL 66 -#define IMX6SLL_CLK_LCDIF_PRE_SEL 67 -#define IMX6SLL_CLK_LCDIF_SEL 68 -#define IMX6SLL_CLK_EPDC_PRE_SEL 69 -#define IMX6SLL_CLK_SPDIF_SEL 70 -#define IMX6SLL_CLK_ECSPI_SEL 71 -#define IMX6SLL_CLK_UART_SEL 72 -#define IMX6SLL_CLK_ARM 73 -#define IMX6SLL_CLK_PERIPH 74 -#define IMX6SLL_CLK_PERIPH2 75 -#define IMX6SLL_CLK_PERIPH2_CLK2 76 -#define IMX6SLL_CLK_PERIPH_CLK2 77 -#define IMX6SLL_CLK_MMDC_PODF 78 -#define IMX6SLL_CLK_AXI_PODF 79 -#define IMX6SLL_CLK_AHB 80 -#define IMX6SLL_CLK_IPG 81 -#define IMX6SLL_CLK_PERCLK 82 -#define IMX6SLL_CLK_USDHC1_PODF 83 -#define IMX6SLL_CLK_USDHC2_PODF 84 -#define IMX6SLL_CLK_USDHC3_PODF 85 -#define IMX6SLL_CLK_SSI1_PRED 86 -#define IMX6SLL_CLK_SSI2_PRED 87 -#define IMX6SLL_CLK_SSI3_PRED 88 -#define IMX6SLL_CLK_SSI1_PODF 89 -#define IMX6SLL_CLK_SSI2_PODF 90 -#define IMX6SLL_CLK_SSI3_PODF 91 -#define IMX6SLL_CLK_PXP_PODF 92 -#define IMX6SLL_CLK_LCDIF_PRED 93 -#define IMX6SLL_CLK_LCDIF_PODF 94 -#define IMX6SLL_CLK_EPDC_SEL 95 -#define IMX6SLL_CLK_EPDC_PODF 96 -#define IMX6SLL_CLK_SPDIF_PRED 97 -#define IMX6SLL_CLK_SPDIF_PODF 98 -#define IMX6SLL_CLK_ECSPI_PODF 99 -#define IMX6SLL_CLK_UART_PODF 100 - -/* CCGR 0 */ -#define IMX6SLL_CLK_AIPSTZ1 101 -#define IMX6SLL_CLK_AIPSTZ2 102 -#define IMX6SLL_CLK_DCP 103 -#define IMX6SLL_CLK_UART2_IPG 104 -#define IMX6SLL_CLK_UART2_SERIAL 105 - -/* CCGR 1 */ -#define IMX6SLL_CLK_ECSPI1 106 -#define IMX6SLL_CLK_ECSPI2 107 -#define IMX6SLL_CLK_ECSPI3 108 -#define IMX6SLL_CLK_ECSPI4 109 -#define IMX6SLL_CLK_UART3_IPG 110 -#define IMX6SLL_CLK_UART3_SERIAL 111 -#define IMX6SLL_CLK_UART4_IPG 112 -#define IMX6SLL_CLK_UART4_SERIAL 113 -#define IMX6SLL_CLK_EPIT1 114 -#define IMX6SLL_CLK_EPIT2 115 -#define IMX6SLL_CLK_GPT_BUS 116 -#define IMX6SLL_CLK_GPT_SERIAL 117 - -/* CCGR2 */ -#define IMX6SLL_CLK_CSI 118 -#define IMX6SLL_CLK_I2C1 119 -#define IMX6SLL_CLK_I2C2 120 -#define IMX6SLL_CLK_I2C3 121 -#define IMX6SLL_CLK_OCOTP 122 -#define IMX6SLL_CLK_LCDIF_APB 123 -#define IMX6SLL_CLK_PXP 124 - -/* CCGR3 */ -#define IMX6SLL_CLK_UART5_IPG 125 -#define IMX6SLL_CLK_UART5_SERIAL 126 -#define IMX6SLL_CLK_EPDC_AXI 127 -#define IMX6SLL_CLK_EPDC_PIX 128 -#define IMX6SLL_CLK_LCDIF_PIX 129 -#define IMX6SLL_CLK_WDOG1 130 -#define IMX6SLL_CLK_MMDC_P0_FAST 131 -#define IMX6SLL_CLK_MMDC_P0_IPG 132 -#define IMX6SLL_CLK_OCRAM 133 - -/* CCGR4 */ -#define IMX6SLL_CLK_PWM1 134 -#define IMX6SLL_CLK_PWM2 135 -#define IMX6SLL_CLK_PWM3 136 -#define IMX6SLL_CLK_PWM4 137 - -/* CCGR 5 */ -#define IMX6SLL_CLK_ROM 138 -#define IMX6SLL_CLK_SDMA 139 -#define IMX6SLL_CLK_KPP 140 -#define IMX6SLL_CLK_WDOG2 141 -#define IMX6SLL_CLK_SPBA 142 -#define IMX6SLL_CLK_SPDIF 143 -#define IMX6SLL_CLK_SPDIF_GCLK 144 -#define IMX6SLL_CLK_SSI1 145 -#define IMX6SLL_CLK_SSI1_IPG 146 -#define IMX6SLL_CLK_SSI2 147 -#define IMX6SLL_CLK_SSI2_IPG 148 -#define IMX6SLL_CLK_SSI3 149 -#define IMX6SLL_CLK_SSI3_IPG 150 -#define IMX6SLL_CLK_UART1_IPG 151 -#define IMX6SLL_CLK_UART1_SERIAL 152 - -/* CCGR 6 */ -#define IMX6SLL_CLK_USBOH3 153 -#define IMX6SLL_CLK_USDHC1 154 -#define IMX6SLL_CLK_USDHC2 155 -#define IMX6SLL_CLK_USDHC3 156 - -#define IMX6SLL_CLK_IPP_DI0 157 -#define IMX6SLL_CLK_IPP_DI1 158 -#define IMX6SLL_CLK_LDB_DI0_SEL 159 -#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 -#define IMX6SLL_CLK_LDB_DI0_DIV_7 161 -#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 -#define IMX6SLL_CLK_LDB_DI0 163 -#define IMX6SLL_CLK_LDB_DI1_SEL 164 -#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 -#define IMX6SLL_CLK_LDB_DI1_DIV_7 166 -#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 -#define IMX6SLL_CLK_LDB_DI1 168 -#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 -#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 -#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 -#define IMX6SLL_CLK_EXTERN_AUDIO 172 - -#define IMX6SLL_CLK_GPIO1 173 -#define IMX6SLL_CLK_GPIO2 174 -#define IMX6SLL_CLK_GPIO3 175 -#define IMX6SLL_CLK_GPIO4 176 -#define IMX6SLL_CLK_GPIO5 177 -#define IMX6SLL_CLK_GPIO6 178 -#define IMX6SLL_CLK_MMDC_P1_IPG 179 - -#define IMX6SLL_CLK_END 180 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h deleted file mode 100644 index 1c64997d6196..000000000000 --- a/include/dt-bindings/clock/imx6sx-clock.h +++ /dev/null @@ -1,281 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H -#define __DT_BINDINGS_CLOCK_IMX6SX_H - -#define IMX6SX_CLK_DUMMY 0 -#define IMX6SX_CLK_CKIL 1 -#define IMX6SX_CLK_CKIH 2 -#define IMX6SX_CLK_OSC 3 -#define IMX6SX_CLK_PLL1_SYS 4 -#define IMX6SX_CLK_PLL2_BUS 5 -#define IMX6SX_CLK_PLL3_USB_OTG 6 -#define IMX6SX_CLK_PLL4_AUDIO 7 -#define IMX6SX_CLK_PLL5_VIDEO 8 -#define IMX6SX_CLK_PLL6_ENET 9 -#define IMX6SX_CLK_PLL7_USB_HOST 10 -#define IMX6SX_CLK_USBPHY1 11 -#define IMX6SX_CLK_USBPHY2 12 -#define IMX6SX_CLK_USBPHY1_GATE 13 -#define IMX6SX_CLK_USBPHY2_GATE 14 -#define IMX6SX_CLK_PCIE_REF 15 -#define IMX6SX_CLK_PCIE_REF_125M 16 -#define IMX6SX_CLK_ENET_REF 17 -#define IMX6SX_CLK_PLL2_PFD0 18 -#define IMX6SX_CLK_PLL2_PFD1 19 -#define IMX6SX_CLK_PLL2_PFD2 20 -#define IMX6SX_CLK_PLL2_PFD3 21 -#define IMX6SX_CLK_PLL3_PFD0 22 -#define IMX6SX_CLK_PLL3_PFD1 23 -#define IMX6SX_CLK_PLL3_PFD2 24 -#define IMX6SX_CLK_PLL3_PFD3 25 -#define IMX6SX_CLK_PLL2_198M 26 -#define IMX6SX_CLK_PLL3_120M 27 -#define IMX6SX_CLK_PLL3_80M 28 -#define IMX6SX_CLK_PLL3_60M 29 -#define IMX6SX_CLK_TWD 30 -#define IMX6SX_CLK_PLL4_POST_DIV 31 -#define IMX6SX_CLK_PLL4_AUDIO_DIV 32 -#define IMX6SX_CLK_PLL5_POST_DIV 33 -#define IMX6SX_CLK_PLL5_VIDEO_DIV 34 -#define IMX6SX_CLK_STEP 35 -#define IMX6SX_CLK_PLL1_SW 36 -#define IMX6SX_CLK_OCRAM_SEL 37 -#define IMX6SX_CLK_PERIPH_PRE 38 -#define IMX6SX_CLK_PERIPH2_PRE 39 -#define IMX6SX_CLK_PERIPH_CLK2_SEL 40 -#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41 -#define IMX6SX_CLK_PCIE_AXI_SEL 42 -#define IMX6SX_CLK_GPU_AXI_SEL 43 -#define IMX6SX_CLK_GPU_CORE_SEL 44 -#define IMX6SX_CLK_EIM_SLOW_SEL 45 -#define IMX6SX_CLK_USDHC1_SEL 46 -#define IMX6SX_CLK_USDHC2_SEL 47 -#define IMX6SX_CLK_USDHC3_SEL 48 -#define IMX6SX_CLK_USDHC4_SEL 49 -#define IMX6SX_CLK_SSI1_SEL 50 -#define IMX6SX_CLK_SSI2_SEL 51 -#define IMX6SX_CLK_SSI3_SEL 52 -#define IMX6SX_CLK_QSPI1_SEL 53 -#define IMX6SX_CLK_PERCLK_SEL 54 -#define IMX6SX_CLK_VID_SEL 55 -#define IMX6SX_CLK_ESAI_SEL 56 -#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57 -#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58 -#define IMX6SX_CLK_CAN_SEL 59 -#define IMX6SX_CLK_UART_SEL 60 -#define IMX6SX_CLK_QSPI2_SEL 61 -#define IMX6SX_CLK_LDB_DI1_SEL 62 -#define IMX6SX_CLK_LDB_DI0_SEL 63 -#define IMX6SX_CLK_SPDIF_SEL 64 -#define IMX6SX_CLK_AUDIO_SEL 65 -#define IMX6SX_CLK_ENET_PRE_SEL 66 -#define IMX6SX_CLK_ENET_SEL 67 -#define IMX6SX_CLK_M4_PRE_SEL 68 -#define IMX6SX_CLK_M4_SEL 69 -#define IMX6SX_CLK_ECSPI_SEL 70 -#define IMX6SX_CLK_LCDIF1_PRE_SEL 71 -#define IMX6SX_CLK_LCDIF2_PRE_SEL 72 -#define IMX6SX_CLK_LCDIF1_SEL 73 -#define IMX6SX_CLK_LCDIF2_SEL 74 -#define IMX6SX_CLK_DISPLAY_SEL 75 -#define IMX6SX_CLK_CSI_SEL 76 -#define IMX6SX_CLK_CKO1_SEL 77 -#define IMX6SX_CLK_CKO2_SEL 78 -#define IMX6SX_CLK_CKO 79 -#define IMX6SX_CLK_PERIPH_CLK2 80 -#define IMX6SX_CLK_PERIPH2_CLK2 81 -#define IMX6SX_CLK_IPG 82 -#define IMX6SX_CLK_GPU_CORE_PODF 83 -#define IMX6SX_CLK_GPU_AXI_PODF 84 -#define IMX6SX_CLK_LCDIF1_PODF 85 -#define IMX6SX_CLK_QSPI1_PODF 86 -#define IMX6SX_CLK_EIM_SLOW_PODF 87 -#define IMX6SX_CLK_LCDIF2_PODF 88 -#define IMX6SX_CLK_PERCLK 89 -#define IMX6SX_CLK_VID_PODF 90 -#define IMX6SX_CLK_CAN_PODF 91 -#define IMX6SX_CLK_USDHC1_PODF 92 -#define IMX6SX_CLK_USDHC2_PODF 93 -#define IMX6SX_CLK_USDHC3_PODF 94 -#define IMX6SX_CLK_USDHC4_PODF 95 -#define IMX6SX_CLK_UART_PODF 96 -#define IMX6SX_CLK_ESAI_PRED 97 -#define IMX6SX_CLK_ESAI_PODF 98 -#define IMX6SX_CLK_SSI3_PRED 99 -#define IMX6SX_CLK_SSI3_PODF 100 -#define IMX6SX_CLK_SSI1_PRED 101 -#define IMX6SX_CLK_SSI1_PODF 102 -#define IMX6SX_CLK_QSPI2_PRED 103 -#define IMX6SX_CLK_QSPI2_PODF 104 -#define IMX6SX_CLK_SSI2_PRED 105 -#define IMX6SX_CLK_SSI2_PODF 106 -#define IMX6SX_CLK_SPDIF_PRED 107 -#define IMX6SX_CLK_SPDIF_PODF 108 -#define IMX6SX_CLK_AUDIO_PRED 109 -#define IMX6SX_CLK_AUDIO_PODF 110 -#define IMX6SX_CLK_ENET_PODF 111 -#define IMX6SX_CLK_M4_PODF 112 -#define IMX6SX_CLK_ECSPI_PODF 113 -#define IMX6SX_CLK_LCDIF1_PRED 114 -#define IMX6SX_CLK_LCDIF2_PRED 115 -#define IMX6SX_CLK_DISPLAY_PODF 116 -#define IMX6SX_CLK_CSI_PODF 117 -#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118 -#define IMX6SX_CLK_LDB_DI0_DIV_7 119 -#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120 -#define IMX6SX_CLK_LDB_DI1_DIV_7 121 -#define IMX6SX_CLK_CKO1_PODF 122 -#define IMX6SX_CLK_CKO2_PODF 123 -#define IMX6SX_CLK_PERIPH 124 -#define IMX6SX_CLK_PERIPH2 125 -#define IMX6SX_CLK_OCRAM 126 -#define IMX6SX_CLK_AHB 127 -#define IMX6SX_CLK_MMDC_PODF 128 -#define IMX6SX_CLK_ARM 129 -#define IMX6SX_CLK_AIPS_TZ1 130 -#define IMX6SX_CLK_AIPS_TZ2 131 -#define IMX6SX_CLK_APBH_DMA 132 -#define IMX6SX_CLK_ASRC_GATE 133 -#define IMX6SX_CLK_CAAM_MEM 134 -#define IMX6SX_CLK_CAAM_ACLK 135 -#define IMX6SX_CLK_CAAM_IPG 136 -#define IMX6SX_CLK_CAN1_IPG 137 -#define IMX6SX_CLK_CAN1_SERIAL 138 -#define IMX6SX_CLK_CAN2_IPG 139 -#define IMX6SX_CLK_CAN2_SERIAL 140 -#define IMX6SX_CLK_CPU_DEBUG 141 -#define IMX6SX_CLK_DCIC1 142 -#define IMX6SX_CLK_DCIC2 143 -#define IMX6SX_CLK_AIPS_TZ3 144 -#define IMX6SX_CLK_ECSPI1 145 -#define IMX6SX_CLK_ECSPI2 146 -#define IMX6SX_CLK_ECSPI3 147 -#define IMX6SX_CLK_ECSPI4 148 -#define IMX6SX_CLK_ECSPI5 149 -#define IMX6SX_CLK_EPIT1 150 -#define IMX6SX_CLK_EPIT2 151 -#define IMX6SX_CLK_ESAI_EXTAL 152 -#define IMX6SX_CLK_WAKEUP 153 -#define IMX6SX_CLK_GPT_BUS 154 -#define IMX6SX_CLK_GPT_SERIAL 155 -#define IMX6SX_CLK_GPU 156 -#define IMX6SX_CLK_OCRAM_S 157 -#define IMX6SX_CLK_CANFD 158 -#define IMX6SX_CLK_CSI 159 -#define IMX6SX_CLK_I2C1 160 -#define IMX6SX_CLK_I2C2 161 -#define IMX6SX_CLK_I2C3 162 -#define IMX6SX_CLK_OCOTP 163 -#define IMX6SX_CLK_IOMUXC 164 -#define IMX6SX_CLK_IPMUX1 165 -#define IMX6SX_CLK_IPMUX2 166 -#define IMX6SX_CLK_IPMUX3 167 -#define IMX6SX_CLK_TZASC1 168 -#define IMX6SX_CLK_LCDIF_APB 169 -#define IMX6SX_CLK_PXP_AXI 170 -#define IMX6SX_CLK_M4 171 -#define IMX6SX_CLK_ENET 172 -#define IMX6SX_CLK_DISPLAY_AXI 173 -#define IMX6SX_CLK_LCDIF2_PIX 174 -#define IMX6SX_CLK_LCDIF1_PIX 175 -#define IMX6SX_CLK_LDB_DI0 176 -#define IMX6SX_CLK_QSPI1 177 -#define IMX6SX_CLK_MLB 178 -#define IMX6SX_CLK_MMDC_P0_FAST 179 -#define IMX6SX_CLK_MMDC_P0_IPG 180 -#define IMX6SX_CLK_AXI 181 -#define IMX6SX_CLK_PCIE_AXI 182 -#define IMX6SX_CLK_QSPI2 183 -#define IMX6SX_CLK_PER1_BCH 184 -#define IMX6SX_CLK_PER2_MAIN 185 -#define IMX6SX_CLK_PWM1 186 -#define IMX6SX_CLK_PWM2 187 -#define IMX6SX_CLK_PWM3 188 -#define IMX6SX_CLK_PWM4 189 -#define IMX6SX_CLK_GPMI_BCH_APB 190 -#define IMX6SX_CLK_GPMI_BCH 191 -#define IMX6SX_CLK_GPMI_IO 192 -#define IMX6SX_CLK_GPMI_APB 193 -#define IMX6SX_CLK_ROM 194 -#define IMX6SX_CLK_SDMA 195 -#define IMX6SX_CLK_SPBA 196 -#define IMX6SX_CLK_SPDIF 197 -#define IMX6SX_CLK_SSI1_IPG 198 -#define IMX6SX_CLK_SSI2_IPG 199 -#define IMX6SX_CLK_SSI3_IPG 200 -#define IMX6SX_CLK_SSI1 201 -#define IMX6SX_CLK_SSI2 202 -#define IMX6SX_CLK_SSI3 203 -#define IMX6SX_CLK_UART_IPG 204 -#define IMX6SX_CLK_UART_SERIAL 205 -#define IMX6SX_CLK_SAI1 206 -#define IMX6SX_CLK_SAI2 207 -#define IMX6SX_CLK_USBOH3 208 -#define IMX6SX_CLK_USDHC1 209 -#define IMX6SX_CLK_USDHC2 210 -#define IMX6SX_CLK_USDHC3 211 -#define IMX6SX_CLK_USDHC4 212 -#define IMX6SX_CLK_EIM_SLOW 213 -#define IMX6SX_CLK_PWM8 214 -#define IMX6SX_CLK_VADC 215 -#define IMX6SX_CLK_GIS 216 -#define IMX6SX_CLK_I2C4 217 -#define IMX6SX_CLK_PWM5 218 -#define IMX6SX_CLK_PWM6 219 -#define IMX6SX_CLK_PWM7 220 -#define IMX6SX_CLK_CKO1 221 -#define IMX6SX_CLK_CKO2 222 -#define IMX6SX_CLK_IPP_DI0 223 -#define IMX6SX_CLK_IPP_DI1 224 -#define IMX6SX_CLK_ENET_AHB 225 -#define IMX6SX_CLK_OCRAM_PODF 226 -#define IMX6SX_CLK_GPT_3M 227 -#define IMX6SX_CLK_ENET_PTP 228 -#define IMX6SX_CLK_ENET_PTP_REF 229 -#define IMX6SX_CLK_ENET2_REF 230 -#define IMX6SX_CLK_ENET2_REF_125M 231 -#define IMX6SX_CLK_AUDIO 232 -#define IMX6SX_CLK_LVDS1_SEL 233 -#define IMX6SX_CLK_LVDS1_OUT 234 -#define IMX6SX_CLK_ASRC_IPG 235 -#define IMX6SX_CLK_ASRC_MEM 236 -#define IMX6SX_CLK_SAI1_IPG 237 -#define IMX6SX_CLK_SAI2_IPG 238 -#define IMX6SX_CLK_ESAI_IPG 239 -#define IMX6SX_CLK_ESAI_MEM 240 -#define IMX6SX_CLK_LVDS1_IN 241 -#define IMX6SX_CLK_ANACLK1 242 -#define IMX6SX_PLL1_BYPASS_SRC 243 -#define IMX6SX_PLL2_BYPASS_SRC 244 -#define IMX6SX_PLL3_BYPASS_SRC 245 -#define IMX6SX_PLL4_BYPASS_SRC 246 -#define IMX6SX_PLL5_BYPASS_SRC 247 -#define IMX6SX_PLL6_BYPASS_SRC 248 -#define IMX6SX_PLL7_BYPASS_SRC 249 -#define IMX6SX_CLK_PLL1 250 -#define IMX6SX_CLK_PLL2 251 -#define IMX6SX_CLK_PLL3 252 -#define IMX6SX_CLK_PLL4 253 -#define IMX6SX_CLK_PLL5 254 -#define IMX6SX_CLK_PLL6 255 -#define IMX6SX_CLK_PLL7 256 -#define IMX6SX_PLL1_BYPASS 257 -#define IMX6SX_PLL2_BYPASS 258 -#define IMX6SX_PLL3_BYPASS 259 -#define IMX6SX_PLL4_BYPASS 260 -#define IMX6SX_PLL5_BYPASS 261 -#define IMX6SX_PLL6_BYPASS 262 -#define IMX6SX_PLL7_BYPASS 263 -#define IMX6SX_CLK_SPDIF_GCLK 264 -#define IMX6SX_CLK_LVDS2_SEL 265 -#define IMX6SX_CLK_LVDS2_OUT 266 -#define IMX6SX_CLK_LVDS2_IN 267 -#define IMX6SX_CLK_ANACLK2 268 -#define IMX6SX_CLK_MMDC_P1_IPG 269 -#define IMX6SX_CLK_CLK_END 270 - -#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h deleted file mode 100644 index 79094338e6f1..000000000000 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H -#define __DT_BINDINGS_CLOCK_IMX6UL_H - -#define IMX6UL_CLK_DUMMY 0 -#define IMX6UL_CLK_CKIL 1 -#define IMX6UL_CLK_CKIH 2 -#define IMX6UL_CLK_OSC 3 -#define IMX6UL_PLL1_BYPASS_SRC 4 -#define IMX6UL_PLL2_BYPASS_SRC 5 -#define IMX6UL_PLL3_BYPASS_SRC 6 -#define IMX6UL_PLL4_BYPASS_SRC 7 -#define IMX6UL_PLL5_BYPASS_SRC 8 -#define IMX6UL_PLL6_BYPASS_SRC 9 -#define IMX6UL_PLL7_BYPASS_SRC 10 -#define IMX6UL_CLK_PLL1 11 -#define IMX6UL_CLK_PLL2 12 -#define IMX6UL_CLK_PLL3 13 -#define IMX6UL_CLK_PLL4 14 -#define IMX6UL_CLK_PLL5 15 -#define IMX6UL_CLK_PLL6 16 -#define IMX6UL_CLK_PLL7 17 -#define IMX6UL_PLL1_BYPASS 18 -#define IMX6UL_PLL2_BYPASS 19 -#define IMX6UL_PLL3_BYPASS 20 -#define IMX6UL_PLL4_BYPASS 21 -#define IMX6UL_PLL5_BYPASS 22 -#define IMX6UL_PLL6_BYPASS 23 -#define IMX6UL_PLL7_BYPASS 24 -#define IMX6UL_CLK_PLL1_SYS 25 -#define IMX6UL_CLK_PLL2_BUS 26 -#define IMX6UL_CLK_PLL3_USB_OTG 27 -#define IMX6UL_CLK_PLL4_AUDIO 28 -#define IMX6UL_CLK_PLL5_VIDEO 29 -#define IMX6UL_CLK_PLL6_ENET 30 -#define IMX6UL_CLK_PLL7_USB_HOST 31 -#define IMX6UL_CLK_USBPHY1 32 -#define IMX6UL_CLK_USBPHY2 33 -#define IMX6UL_CLK_USBPHY1_GATE 34 -#define IMX6UL_CLK_USBPHY2_GATE 35 -#define IMX6UL_CLK_PLL2_PFD0 36 -#define IMX6UL_CLK_PLL2_PFD1 37 -#define IMX6UL_CLK_PLL2_PFD2 38 -#define IMX6UL_CLK_PLL2_PFD3 39 -#define IMX6UL_CLK_PLL3_PFD0 40 -#define IMX6UL_CLK_PLL3_PFD1 41 -#define IMX6UL_CLK_PLL3_PFD2 42 -#define IMX6UL_CLK_PLL3_PFD3 43 -#define IMX6UL_CLK_ENET_REF 44 -#define IMX6UL_CLK_ENET2_REF 45 -#define IMX6UL_CLK_ENET2_REF_125M 46 -#define IMX6UL_CLK_ENET_PTP_REF 47 -#define IMX6UL_CLK_ENET_PTP 48 -#define IMX6UL_CLK_PLL4_POST_DIV 49 -#define IMX6UL_CLK_PLL4_AUDIO_DIV 50 -#define IMX6UL_CLK_PLL5_POST_DIV 51 -#define IMX6UL_CLK_PLL5_VIDEO_DIV 52 -#define IMX6UL_CLK_PLL2_198M 53 -#define IMX6UL_CLK_PLL3_80M 54 -#define IMX6UL_CLK_PLL3_60M 55 -#define IMX6UL_CLK_STEP 56 -#define IMX6UL_CLK_PLL1_SW 57 -#define IMX6UL_CLK_AXI_ALT_SEL 58 -#define IMX6UL_CLK_AXI_SEL 59 -#define IMX6UL_CLK_PERIPH_PRE 60 -#define IMX6UL_CLK_PERIPH2_PRE 61 -#define IMX6UL_CLK_PERIPH_CLK2_SEL 62 -#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 -#define IMX6UL_CLK_USDHC1_SEL 64 -#define IMX6UL_CLK_USDHC2_SEL 65 -#define IMX6UL_CLK_BCH_SEL 66 -#define IMX6UL_CLK_GPMI_SEL 67 -#define IMX6UL_CLK_EIM_SLOW_SEL 68 -#define IMX6UL_CLK_SPDIF_SEL 69 -#define IMX6UL_CLK_SAI1_SEL 70 -#define IMX6UL_CLK_SAI2_SEL 71 -#define IMX6UL_CLK_SAI3_SEL 72 -#define IMX6UL_CLK_LCDIF_PRE_SEL 73 -#define IMX6UL_CLK_SIM_PRE_SEL 74 -#define IMX6UL_CLK_LDB_DI0_SEL 75 -#define IMX6UL_CLK_LDB_DI1_SEL 76 -#define IMX6UL_CLK_ENFC_SEL 77 -#define IMX6UL_CLK_CAN_SEL 78 -#define IMX6UL_CLK_ECSPI_SEL 79 -#define IMX6UL_CLK_UART_SEL 80 -#define IMX6UL_CLK_QSPI1_SEL 81 -#define IMX6UL_CLK_PERCLK_SEL 82 -#define IMX6UL_CLK_LCDIF_SEL 83 -#define IMX6UL_CLK_SIM_SEL 84 -#define IMX6UL_CLK_PERIPH 85 -#define IMX6UL_CLK_PERIPH2 86 -#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 -#define IMX6UL_CLK_LDB_DI0_DIV_7 88 -#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 -#define IMX6UL_CLK_LDB_DI1_DIV_7 90 -#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 -#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 -#define IMX6UL_CLK_ARM 93 -#define IMX6UL_CLK_PERIPH_CLK2 94 -#define IMX6UL_CLK_PERIPH2_CLK2 95 -#define IMX6UL_CLK_AHB 96 -#define IMX6UL_CLK_MMDC_PODF 97 -#define IMX6UL_CLK_AXI_PODF 98 -#define IMX6UL_CLK_PERCLK 99 -#define IMX6UL_CLK_IPG 100 -#define IMX6UL_CLK_USDHC1_PODF 101 -#define IMX6UL_CLK_USDHC2_PODF 102 -#define IMX6UL_CLK_BCH_PODF 103 -#define IMX6UL_CLK_GPMI_PODF 104 -#define IMX6UL_CLK_EIM_SLOW_PODF 105 -#define IMX6UL_CLK_SPDIF_PRED 106 -#define IMX6UL_CLK_SPDIF_PODF 107 -#define IMX6UL_CLK_SAI1_PRED 108 -#define IMX6UL_CLK_SAI1_PODF 109 -#define IMX6UL_CLK_SAI2_PRED 110 -#define IMX6UL_CLK_SAI2_PODF 111 -#define IMX6UL_CLK_SAI3_PRED 112 -#define IMX6UL_CLK_SAI3_PODF 113 -#define IMX6UL_CLK_LCDIF_PRED 114 -#define IMX6UL_CLK_LCDIF_PODF 115 -#define IMX6UL_CLK_SIM_PODF 116 -#define IMX6UL_CLK_QSPI1_PDOF 117 -#define IMX6UL_CLK_ENFC_PRED 118 -#define IMX6UL_CLK_ENFC_PODF 119 -#define IMX6UL_CLK_CAN_PODF 120 -#define IMX6UL_CLK_ECSPI_PODF 121 -#define IMX6UL_CLK_UART_PODF 122 -#define IMX6UL_CLK_ADC1 123 -#define IMX6UL_CLK_ADC2 124 -#define IMX6UL_CLK_AIPSTZ1 125 -#define IMX6UL_CLK_AIPSTZ2 126 -#define IMX6UL_CLK_AIPSTZ3 127 -#define IMX6UL_CLK_APBHDMA 128 -#define IMX6UL_CLK_ASRC_IPG 129 -#define IMX6UL_CLK_ASRC_MEM 130 -#define IMX6UL_CLK_GPMI_BCH_APB 131 -#define IMX6UL_CLK_GPMI_BCH 132 -#define IMX6UL_CLK_GPMI_IO 133 -#define IMX6UL_CLK_GPMI_APB 134 -#define IMX6UL_CLK_CAAM_MEM 135 -#define IMX6UL_CLK_CAAM_ACLK 136 -#define IMX6UL_CLK_CAAM_IPG 137 -#define IMX6UL_CLK_CSI 138 -#define IMX6UL_CLK_ECSPI1 139 -#define IMX6UL_CLK_ECSPI2 140 -#define IMX6UL_CLK_ECSPI3 141 -#define IMX6UL_CLK_ECSPI4 142 -#define IMX6UL_CLK_EIM 143 -#define IMX6UL_CLK_ENET 144 -#define IMX6UL_CLK_ENET_AHB 145 -#define IMX6UL_CLK_EPIT1 146 -#define IMX6UL_CLK_EPIT2 147 -#define IMX6UL_CLK_CAN1_IPG 148 -#define IMX6UL_CLK_CAN1_SERIAL 149 -#define IMX6UL_CLK_CAN2_IPG 150 -#define IMX6UL_CLK_CAN2_SERIAL 151 -#define IMX6UL_CLK_GPT1_BUS 152 -#define IMX6UL_CLK_GPT1_SERIAL 153 -#define IMX6UL_CLK_GPT2_BUS 154 -#define IMX6UL_CLK_GPT2_SERIAL 155 -#define IMX6UL_CLK_I2C1 156 -#define IMX6UL_CLK_I2C2 157 -#define IMX6UL_CLK_I2C3 158 -#define IMX6UL_CLK_I2C4 159 -#define IMX6UL_CLK_IOMUXC 160 -#define IMX6UL_CLK_LCDIF_APB 161 -#define IMX6UL_CLK_LCDIF_PIX 162 -#define IMX6UL_CLK_MMDC_P0_FAST 163 -#define IMX6UL_CLK_MMDC_P0_IPG 164 -#define IMX6UL_CLK_OCOTP 165 -#define IMX6UL_CLK_OCRAM 166 -#define IMX6UL_CLK_PWM1 167 -#define IMX6UL_CLK_PWM2 168 -#define IMX6UL_CLK_PWM3 169 -#define IMX6UL_CLK_PWM4 170 -#define IMX6UL_CLK_PWM5 171 -#define IMX6UL_CLK_PWM6 172 -#define IMX6UL_CLK_PWM7 173 -#define IMX6UL_CLK_PWM8 174 -#define IMX6UL_CLK_PXP 175 -#define IMX6UL_CLK_QSPI 176 -#define IMX6UL_CLK_ROM 177 -#define IMX6UL_CLK_SAI1 178 -#define IMX6UL_CLK_SAI1_IPG 179 -#define IMX6UL_CLK_SAI2 180 -#define IMX6UL_CLK_SAI2_IPG 181 -#define IMX6UL_CLK_SAI3 182 -#define IMX6UL_CLK_SAI3_IPG 183 -#define IMX6UL_CLK_SDMA 184 -#define IMX6UL_CLK_SIM 185 -#define IMX6UL_CLK_SIM_S 186 -#define IMX6UL_CLK_SPBA 187 -#define IMX6UL_CLK_SPDIF 188 -#define IMX6UL_CLK_UART1_IPG 189 -#define IMX6UL_CLK_UART1_SERIAL 190 -#define IMX6UL_CLK_UART2_IPG 191 -#define IMX6UL_CLK_UART2_SERIAL 192 -#define IMX6UL_CLK_UART3_IPG 193 -#define IMX6UL_CLK_UART3_SERIAL 194 -#define IMX6UL_CLK_UART4_IPG 195 -#define IMX6UL_CLK_UART4_SERIAL 196 -#define IMX6UL_CLK_UART5_IPG 197 -#define IMX6UL_CLK_UART5_SERIAL 198 -#define IMX6UL_CLK_UART6_IPG 199 -#define IMX6UL_CLK_UART6_SERIAL 200 -#define IMX6UL_CLK_UART7_IPG 201 -#define IMX6UL_CLK_UART7_SERIAL 202 -#define IMX6UL_CLK_UART8_IPG 203 -#define IMX6UL_CLK_UART8_SERIAL 204 -#define IMX6UL_CLK_USBOH3 205 -#define IMX6UL_CLK_USDHC1 206 -#define IMX6UL_CLK_USDHC2 207 -#define IMX6UL_CLK_WDOG1 208 -#define IMX6UL_CLK_WDOG2 209 -#define IMX6UL_CLK_WDOG3 210 -#define IMX6UL_CLK_LDB_DI0 211 -#define IMX6UL_CLK_AXI 212 -#define IMX6UL_CLK_SPDIF_GCLK 213 -#define IMX6UL_CLK_GPT_3M 214 -#define IMX6UL_CLK_SIM2 215 -#define IMX6UL_CLK_SIM1 216 -#define IMX6UL_CLK_IPP_DI0 217 -#define IMX6UL_CLK_IPP_DI1 218 -#define IMX6UL_CA7_SECONDARY_SEL 219 -#define IMX6UL_CLK_PER_BCH 220 -#define IMX6UL_CLK_CSI_SEL 221 -#define IMX6UL_CLK_CSI_PODF 222 -#define IMX6UL_CLK_PLL3_120M 223 -#define IMX6UL_CLK_KPP 224 -#define IMX6ULL_CLK_ESAI_PRED 225 -#define IMX6ULL_CLK_ESAI_PODF 226 -#define IMX6ULL_CLK_ESAI_EXTAL 227 -#define IMX6ULL_CLK_ESAI_MEM 228 -#define IMX6ULL_CLK_ESAI_IPG 229 -#define IMX6ULL_CLK_DCP_CLK 230 -#define IMX6ULL_CLK_EPDC_PRE_SEL 231 -#define IMX6ULL_CLK_EPDC_SEL 232 -#define IMX6ULL_CLK_EPDC_PODF 233 -#define IMX6ULL_CLK_EPDC_ACLK 234 -#define IMX6ULL_CLK_EPDC_PIX 235 -#define IMX6ULL_CLK_ESAI_SEL 236 -#define IMX6UL_CLK_CKO1_SEL 237 -#define IMX6UL_CLK_CKO1_PODF 238 -#define IMX6UL_CLK_CKO1 239 -#define IMX6UL_CLK_CKO2_SEL 240 -#define IMX6UL_CLK_CKO2_PODF 241 -#define IMX6UL_CLK_CKO2 242 -#define IMX6UL_CLK_CKO 243 -#define IMX6UL_CLK_GPIO1 244 -#define IMX6UL_CLK_GPIO2 245 -#define IMX6UL_CLK_GPIO3 246 -#define IMX6UL_CLK_GPIO4 247 -#define IMX6UL_CLK_GPIO5 248 -#define IMX6UL_CLK_MMDC_P1_IPG 249 - -#define IMX6UL_CLK_END 250 - -#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h deleted file mode 100644 index 1d4c0dfe0202..000000000000 --- a/include/dt-bindings/clock/imx7d-clock.h +++ /dev/null @@ -1,456 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX7D_H -#define __DT_BINDINGS_CLOCK_IMX7D_H - -#define IMX7D_OSC_24M_CLK 0 -#define IMX7D_PLL_ARM_MAIN 1 -#define IMX7D_PLL_ARM_MAIN_CLK 2 -#define IMX7D_PLL_ARM_MAIN_SRC 3 -#define IMX7D_PLL_ARM_MAIN_BYPASS 4 -#define IMX7D_PLL_SYS_MAIN 5 -#define IMX7D_PLL_SYS_MAIN_CLK 6 -#define IMX7D_PLL_SYS_MAIN_SRC 7 -#define IMX7D_PLL_SYS_MAIN_BYPASS 8 -#define IMX7D_PLL_SYS_MAIN_480M 9 -#define IMX7D_PLL_SYS_MAIN_240M 10 -#define IMX7D_PLL_SYS_MAIN_120M 11 -#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 -#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 -#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 -#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 -#define IMX7D_PLL_SYS_PFD0_196M 16 -#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 -#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 -#define IMX7D_PLL_SYS_PFD1_166M 19 -#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 -#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 -#define IMX7D_PLL_SYS_PFD2_135M 22 -#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 -#define IMX7D_PLL_SYS_PFD3_CLK 24 -#define IMX7D_PLL_SYS_PFD4_CLK 25 -#define IMX7D_PLL_SYS_PFD5_CLK 26 -#define IMX7D_PLL_SYS_PFD6_CLK 27 -#define IMX7D_PLL_SYS_PFD7_CLK 28 -#define IMX7D_PLL_ENET_MAIN 29 -#define IMX7D_PLL_ENET_MAIN_CLK 30 -#define IMX7D_PLL_ENET_MAIN_SRC 31 -#define IMX7D_PLL_ENET_MAIN_BYPASS 32 -#define IMX7D_PLL_ENET_MAIN_500M 33 -#define IMX7D_PLL_ENET_MAIN_250M 34 -#define IMX7D_PLL_ENET_MAIN_125M 35 -#define IMX7D_PLL_ENET_MAIN_100M 36 -#define IMX7D_PLL_ENET_MAIN_50M 37 -#define IMX7D_PLL_ENET_MAIN_40M 38 -#define IMX7D_PLL_ENET_MAIN_25M 39 -#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 -#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 -#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 -#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 -#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 -#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 -#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 -#define IMX7D_PLL_DRAM_MAIN 47 -#define IMX7D_PLL_DRAM_MAIN_CLK 48 -#define IMX7D_PLL_DRAM_MAIN_SRC 49 -#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 -#define IMX7D_PLL_DRAM_MAIN_533M 51 -#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 -#define IMX7D_PLL_AUDIO_MAIN 53 -#define IMX7D_PLL_AUDIO_MAIN_CLK 54 -#define IMX7D_PLL_AUDIO_MAIN_SRC 55 -#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 -#define IMX7D_PLL_VIDEO_MAIN_CLK 57 -#define IMX7D_PLL_VIDEO_MAIN 58 -#define IMX7D_PLL_VIDEO_MAIN_SRC 59 -#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 -#define IMX7D_USB_MAIN_480M_CLK 61 -#define IMX7D_ARM_A7_ROOT_CLK 62 -#define IMX7D_ARM_A7_ROOT_SRC 63 -#define IMX7D_ARM_A7_ROOT_CG 64 -#define IMX7D_ARM_A7_ROOT_DIV 65 -#define IMX7D_ARM_M4_ROOT_CLK 66 -#define IMX7D_ARM_M4_ROOT_SRC 67 -#define IMX7D_ARM_M4_ROOT_CG 68 -#define IMX7D_ARM_M4_ROOT_DIV 69 -#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */ -#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */ -#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */ -#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */ -#define IMX7D_MAIN_AXI_ROOT_CLK 74 -#define IMX7D_MAIN_AXI_ROOT_SRC 75 -#define IMX7D_MAIN_AXI_ROOT_CG 76 -#define IMX7D_MAIN_AXI_ROOT_DIV 77 -#define IMX7D_DISP_AXI_ROOT_CLK 78 -#define IMX7D_DISP_AXI_ROOT_SRC 79 -#define IMX7D_DISP_AXI_ROOT_CG 80 -#define IMX7D_DISP_AXI_ROOT_DIV 81 -#define IMX7D_ENET_AXI_ROOT_CLK 82 -#define IMX7D_ENET_AXI_ROOT_SRC 83 -#define IMX7D_ENET_AXI_ROOT_CG 84 -#define IMX7D_ENET_AXI_ROOT_DIV 85 -#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 -#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 -#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 -#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 -#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 -#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 -#define IMX7D_AHB_CHANNEL_ROOT_CG 92 -#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 -#define IMX7D_DRAM_PHYM_ROOT_CLK 94 -#define IMX7D_DRAM_PHYM_ROOT_SRC 95 -#define IMX7D_DRAM_PHYM_ROOT_CG 96 -#define IMX7D_DRAM_PHYM_ROOT_DIV 97 -#define IMX7D_DRAM_ROOT_CLK 98 -#define IMX7D_DRAM_ROOT_SRC 99 -#define IMX7D_DRAM_ROOT_CG 100 -#define IMX7D_DRAM_ROOT_DIV 101 -#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 -#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 -#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 -#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 -#define IMX7D_DRAM_ALT_ROOT_CLK 106 -#define IMX7D_DRAM_ALT_ROOT_SRC 107 -#define IMX7D_DRAM_ALT_ROOT_CG 108 -#define IMX7D_DRAM_ALT_ROOT_DIV 109 -#define IMX7D_USB_HSIC_ROOT_CLK 110 -#define IMX7D_USB_HSIC_ROOT_SRC 111 -#define IMX7D_USB_HSIC_ROOT_CG 112 -#define IMX7D_USB_HSIC_ROOT_DIV 113 -#define IMX7D_PCIE_CTRL_ROOT_CLK 114 -#define IMX7D_PCIE_CTRL_ROOT_SRC 115 -#define IMX7D_PCIE_CTRL_ROOT_CG 116 -#define IMX7D_PCIE_CTRL_ROOT_DIV 117 -#define IMX7D_PCIE_PHY_ROOT_CLK 118 -#define IMX7D_PCIE_PHY_ROOT_SRC 119 -#define IMX7D_PCIE_PHY_ROOT_CG 120 -#define IMX7D_PCIE_PHY_ROOT_DIV 121 -#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 -#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 -#define IMX7D_EPDC_PIXEL_ROOT_CG 124 -#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 -#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 -#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 -#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 -#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 -#define IMX7D_MIPI_DSI_ROOT_CLK 130 -#define IMX7D_MIPI_DSI_ROOT_SRC 131 -#define IMX7D_MIPI_DSI_ROOT_CG 132 -#define IMX7D_MIPI_DSI_ROOT_DIV 133 -#define IMX7D_MIPI_CSI_ROOT_CLK 134 -#define IMX7D_MIPI_CSI_ROOT_SRC 135 -#define IMX7D_MIPI_CSI_ROOT_CG 136 -#define IMX7D_MIPI_CSI_ROOT_DIV 137 -#define IMX7D_MIPI_DPHY_ROOT_CLK 138 -#define IMX7D_MIPI_DPHY_ROOT_SRC 139 -#define IMX7D_MIPI_DPHY_ROOT_CG 140 -#define IMX7D_MIPI_DPHY_ROOT_DIV 141 -#define IMX7D_SAI1_ROOT_CLK 142 -#define IMX7D_SAI1_ROOT_SRC 143 -#define IMX7D_SAI1_ROOT_CG 144 -#define IMX7D_SAI1_ROOT_DIV 145 -#define IMX7D_SAI2_ROOT_CLK 146 -#define IMX7D_SAI2_ROOT_SRC 147 -#define IMX7D_SAI2_ROOT_CG 148 -#define IMX7D_SAI2_ROOT_DIV 149 -#define IMX7D_SAI3_ROOT_CLK 150 -#define IMX7D_SAI3_ROOT_SRC 151 -#define IMX7D_SAI3_ROOT_CG 152 -#define IMX7D_SAI3_ROOT_DIV 153 -#define IMX7D_SPDIF_ROOT_CLK 154 -#define IMX7D_SPDIF_ROOT_SRC 155 -#define IMX7D_SPDIF_ROOT_CG 156 -#define IMX7D_SPDIF_ROOT_DIV 157 -#define IMX7D_ENET1_IPG_ROOT_CLK 158 -#define IMX7D_ENET1_REF_ROOT_SRC 159 -#define IMX7D_ENET1_REF_ROOT_CG 160 -#define IMX7D_ENET1_REF_ROOT_DIV 161 -#define IMX7D_ENET1_TIME_ROOT_CLK 162 -#define IMX7D_ENET1_TIME_ROOT_SRC 163 -#define IMX7D_ENET1_TIME_ROOT_CG 164 -#define IMX7D_ENET1_TIME_ROOT_DIV 165 -#define IMX7D_ENET2_IPG_ROOT_CLK 166 -#define IMX7D_ENET2_REF_ROOT_SRC 167 -#define IMX7D_ENET2_REF_ROOT_CG 168 -#define IMX7D_ENET2_REF_ROOT_DIV 169 -#define IMX7D_ENET2_TIME_ROOT_CLK 170 -#define IMX7D_ENET2_TIME_ROOT_SRC 171 -#define IMX7D_ENET2_TIME_ROOT_CG 172 -#define IMX7D_ENET2_TIME_ROOT_DIV 173 -#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 -#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 -#define IMX7D_ENET_PHY_REF_ROOT_CG 176 -#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 -#define IMX7D_EIM_ROOT_CLK 178 -#define IMX7D_EIM_ROOT_SRC 179 -#define IMX7D_EIM_ROOT_CG 180 -#define IMX7D_EIM_ROOT_DIV 181 -#define IMX7D_NAND_ROOT_CLK 182 -#define IMX7D_NAND_ROOT_SRC 183 -#define IMX7D_NAND_ROOT_CG 184 -#define IMX7D_NAND_ROOT_DIV 185 -#define IMX7D_QSPI_ROOT_CLK 186 -#define IMX7D_QSPI_ROOT_SRC 187 -#define IMX7D_QSPI_ROOT_CG 188 -#define IMX7D_QSPI_ROOT_DIV 189 -#define IMX7D_USDHC1_ROOT_CLK 190 -#define IMX7D_USDHC1_ROOT_SRC 191 -#define IMX7D_USDHC1_ROOT_CG 192 -#define IMX7D_USDHC1_ROOT_DIV 193 -#define IMX7D_USDHC2_ROOT_CLK 194 -#define IMX7D_USDHC2_ROOT_SRC 195 -#define IMX7D_USDHC2_ROOT_CG 196 -#define IMX7D_USDHC2_ROOT_DIV 197 -#define IMX7D_USDHC3_ROOT_CLK 198 -#define IMX7D_USDHC3_ROOT_SRC 199 -#define IMX7D_USDHC3_ROOT_CG 200 -#define IMX7D_USDHC3_ROOT_DIV 201 -#define IMX7D_CAN1_ROOT_CLK 202 -#define IMX7D_CAN1_ROOT_SRC 203 -#define IMX7D_CAN1_ROOT_CG 204 -#define IMX7D_CAN1_ROOT_DIV 205 -#define IMX7D_CAN2_ROOT_CLK 206 -#define IMX7D_CAN2_ROOT_SRC 207 -#define IMX7D_CAN2_ROOT_CG 208 -#define IMX7D_CAN2_ROOT_DIV 209 -#define IMX7D_I2C1_ROOT_CLK 210 -#define IMX7D_I2C1_ROOT_SRC 211 -#define IMX7D_I2C1_ROOT_CG 212 -#define IMX7D_I2C1_ROOT_DIV 213 -#define IMX7D_I2C2_ROOT_CLK 214 -#define IMX7D_I2C2_ROOT_SRC 215 -#define IMX7D_I2C2_ROOT_CG 216 -#define IMX7D_I2C2_ROOT_DIV 217 -#define IMX7D_I2C3_ROOT_CLK 218 -#define IMX7D_I2C3_ROOT_SRC 219 -#define IMX7D_I2C3_ROOT_CG 220 -#define IMX7D_I2C3_ROOT_DIV 221 -#define IMX7D_I2C4_ROOT_CLK 222 -#define IMX7D_I2C4_ROOT_SRC 223 -#define IMX7D_I2C4_ROOT_CG 224 -#define IMX7D_I2C4_ROOT_DIV 225 -#define IMX7D_UART1_ROOT_CLK 226 -#define IMX7D_UART1_ROOT_SRC 227 -#define IMX7D_UART1_ROOT_CG 228 -#define IMX7D_UART1_ROOT_DIV 229 -#define IMX7D_UART2_ROOT_CLK 230 -#define IMX7D_UART2_ROOT_SRC 231 -#define IMX7D_UART2_ROOT_CG 232 -#define IMX7D_UART2_ROOT_DIV 233 -#define IMX7D_UART3_ROOT_CLK 234 -#define IMX7D_UART3_ROOT_SRC 235 -#define IMX7D_UART3_ROOT_CG 236 -#define IMX7D_UART3_ROOT_DIV 237 -#define IMX7D_UART4_ROOT_CLK 238 -#define IMX7D_UART4_ROOT_SRC 239 -#define IMX7D_UART4_ROOT_CG 240 -#define IMX7D_UART4_ROOT_DIV 241 -#define IMX7D_UART5_ROOT_CLK 242 -#define IMX7D_UART5_ROOT_SRC 243 -#define IMX7D_UART5_ROOT_CG 244 -#define IMX7D_UART5_ROOT_DIV 245 -#define IMX7D_UART6_ROOT_CLK 246 -#define IMX7D_UART6_ROOT_SRC 247 -#define IMX7D_UART6_ROOT_CG 248 -#define IMX7D_UART6_ROOT_DIV 249 -#define IMX7D_UART7_ROOT_CLK 250 -#define IMX7D_UART7_ROOT_SRC 251 -#define IMX7D_UART7_ROOT_CG 252 -#define IMX7D_UART7_ROOT_DIV 253 -#define IMX7D_ECSPI1_ROOT_CLK 254 -#define IMX7D_ECSPI1_ROOT_SRC 255 -#define IMX7D_ECSPI1_ROOT_CG 256 -#define IMX7D_ECSPI1_ROOT_DIV 257 -#define IMX7D_ECSPI2_ROOT_CLK 258 -#define IMX7D_ECSPI2_ROOT_SRC 259 -#define IMX7D_ECSPI2_ROOT_CG 260 -#define IMX7D_ECSPI2_ROOT_DIV 261 -#define IMX7D_ECSPI3_ROOT_CLK 262 -#define IMX7D_ECSPI3_ROOT_SRC 263 -#define IMX7D_ECSPI3_ROOT_CG 264 -#define IMX7D_ECSPI3_ROOT_DIV 265 -#define IMX7D_ECSPI4_ROOT_CLK 266 -#define IMX7D_ECSPI4_ROOT_SRC 267 -#define IMX7D_ECSPI4_ROOT_CG 268 -#define IMX7D_ECSPI4_ROOT_DIV 269 -#define IMX7D_PWM1_ROOT_CLK 270 -#define IMX7D_PWM1_ROOT_SRC 271 -#define IMX7D_PWM1_ROOT_CG 272 -#define IMX7D_PWM1_ROOT_DIV 273 -#define IMX7D_PWM2_ROOT_CLK 274 -#define IMX7D_PWM2_ROOT_SRC 275 -#define IMX7D_PWM2_ROOT_CG 276 -#define IMX7D_PWM2_ROOT_DIV 277 -#define IMX7D_PWM3_ROOT_CLK 278 -#define IMX7D_PWM3_ROOT_SRC 279 -#define IMX7D_PWM3_ROOT_CG 280 -#define IMX7D_PWM3_ROOT_DIV 281 -#define IMX7D_PWM4_ROOT_CLK 282 -#define IMX7D_PWM4_ROOT_SRC 283 -#define IMX7D_PWM4_ROOT_CG 284 -#define IMX7D_PWM4_ROOT_DIV 285 -#define IMX7D_FLEXTIMER1_ROOT_CLK 286 -#define IMX7D_FLEXTIMER1_ROOT_SRC 287 -#define IMX7D_FLEXTIMER1_ROOT_CG 288 -#define IMX7D_FLEXTIMER1_ROOT_DIV 289 -#define IMX7D_FLEXTIMER2_ROOT_CLK 290 -#define IMX7D_FLEXTIMER2_ROOT_SRC 291 -#define IMX7D_FLEXTIMER2_ROOT_CG 292 -#define IMX7D_FLEXTIMER2_ROOT_DIV 293 -#define IMX7D_SIM1_ROOT_CLK 294 -#define IMX7D_SIM1_ROOT_SRC 295 -#define IMX7D_SIM1_ROOT_CG 296 -#define IMX7D_SIM1_ROOT_DIV 297 -#define IMX7D_SIM2_ROOT_CLK 298 -#define IMX7D_SIM2_ROOT_SRC 299 -#define IMX7D_SIM2_ROOT_CG 300 -#define IMX7D_SIM2_ROOT_DIV 301 -#define IMX7D_GPT1_ROOT_CLK 302 -#define IMX7D_GPT1_ROOT_SRC 303 -#define IMX7D_GPT1_ROOT_CG 304 -#define IMX7D_GPT1_ROOT_DIV 305 -#define IMX7D_GPT2_ROOT_CLK 306 -#define IMX7D_GPT2_ROOT_SRC 307 -#define IMX7D_GPT2_ROOT_CG 308 -#define IMX7D_GPT2_ROOT_DIV 309 -#define IMX7D_GPT3_ROOT_CLK 310 -#define IMX7D_GPT3_ROOT_SRC 311 -#define IMX7D_GPT3_ROOT_CG 312 -#define IMX7D_GPT3_ROOT_DIV 313 -#define IMX7D_GPT4_ROOT_CLK 314 -#define IMX7D_GPT4_ROOT_SRC 315 -#define IMX7D_GPT4_ROOT_CG 316 -#define IMX7D_GPT4_ROOT_DIV 317 -#define IMX7D_TRACE_ROOT_CLK 318 -#define IMX7D_TRACE_ROOT_SRC 319 -#define IMX7D_TRACE_ROOT_CG 320 -#define IMX7D_TRACE_ROOT_DIV 321 -#define IMX7D_WDOG1_ROOT_CLK 322 -#define IMX7D_WDOG_ROOT_SRC 323 -#define IMX7D_WDOG_ROOT_CG 324 -#define IMX7D_WDOG_ROOT_DIV 325 -#define IMX7D_CSI_MCLK_ROOT_CLK 326 -#define IMX7D_CSI_MCLK_ROOT_SRC 327 -#define IMX7D_CSI_MCLK_ROOT_CG 328 -#define IMX7D_CSI_MCLK_ROOT_DIV 329 -#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 -#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 -#define IMX7D_AUDIO_MCLK_ROOT_CG 332 -#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 -#define IMX7D_WRCLK_ROOT_CLK 334 -#define IMX7D_WRCLK_ROOT_SRC 335 -#define IMX7D_WRCLK_ROOT_CG 336 -#define IMX7D_WRCLK_ROOT_DIV 337 -#define IMX7D_CLKO1_ROOT_SRC 338 -#define IMX7D_CLKO1_ROOT_CG 339 -#define IMX7D_CLKO1_ROOT_DIV 340 -#define IMX7D_CLKO2_ROOT_SRC 341 -#define IMX7D_CLKO2_ROOT_CG 342 -#define IMX7D_CLKO2_ROOT_DIV 343 -#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 -#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 -#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 -#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 -#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 -#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 -#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 -#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 -#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 -#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 -#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 -#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 -#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 -#define IMX7D_SAI1_ROOT_PRE_DIV 357 -#define IMX7D_SAI2_ROOT_PRE_DIV 358 -#define IMX7D_SAI3_ROOT_PRE_DIV 359 -#define IMX7D_SPDIF_ROOT_PRE_DIV 360 -#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 -#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 -#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 -#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 -#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 -#define IMX7D_EIM_ROOT_PRE_DIV 366 -#define IMX7D_NAND_ROOT_PRE_DIV 367 -#define IMX7D_QSPI_ROOT_PRE_DIV 368 -#define IMX7D_USDHC1_ROOT_PRE_DIV 369 -#define IMX7D_USDHC2_ROOT_PRE_DIV 370 -#define IMX7D_USDHC3_ROOT_PRE_DIV 371 -#define IMX7D_CAN1_ROOT_PRE_DIV 372 -#define IMX7D_CAN2_ROOT_PRE_DIV 373 -#define IMX7D_I2C1_ROOT_PRE_DIV 374 -#define IMX7D_I2C2_ROOT_PRE_DIV 375 -#define IMX7D_I2C3_ROOT_PRE_DIV 376 -#define IMX7D_I2C4_ROOT_PRE_DIV 377 -#define IMX7D_UART1_ROOT_PRE_DIV 378 -#define IMX7D_UART2_ROOT_PRE_DIV 379 -#define IMX7D_UART3_ROOT_PRE_DIV 380 -#define IMX7D_UART4_ROOT_PRE_DIV 381 -#define IMX7D_UART5_ROOT_PRE_DIV 382 -#define IMX7D_UART6_ROOT_PRE_DIV 383 -#define IMX7D_UART7_ROOT_PRE_DIV 384 -#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 -#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 -#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 -#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 -#define IMX7D_PWM1_ROOT_PRE_DIV 389 -#define IMX7D_PWM2_ROOT_PRE_DIV 390 -#define IMX7D_PWM3_ROOT_PRE_DIV 391 -#define IMX7D_PWM4_ROOT_PRE_DIV 392 -#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 -#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 -#define IMX7D_SIM1_ROOT_PRE_DIV 395 -#define IMX7D_SIM2_ROOT_PRE_DIV 396 -#define IMX7D_GPT1_ROOT_PRE_DIV 397 -#define IMX7D_GPT2_ROOT_PRE_DIV 398 -#define IMX7D_GPT3_ROOT_PRE_DIV 399 -#define IMX7D_GPT4_ROOT_PRE_DIV 400 -#define IMX7D_TRACE_ROOT_PRE_DIV 401 -#define IMX7D_WDOG_ROOT_PRE_DIV 402 -#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 -#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 -#define IMX7D_WRCLK_ROOT_PRE_DIV 405 -#define IMX7D_CLKO1_ROOT_PRE_DIV 406 -#define IMX7D_CLKO2_ROOT_PRE_DIV 407 -#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 -#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 -#define IMX7D_LVDS1_IN_CLK 410 -#define IMX7D_LVDS1_OUT_SEL 411 -#define IMX7D_LVDS1_OUT_CLK 412 -#define IMX7D_CLK_DUMMY 413 -#define IMX7D_GPT_3M_CLK 414 -#define IMX7D_OCRAM_CLK 415 -#define IMX7D_OCRAM_S_CLK 416 -#define IMX7D_WDOG2_ROOT_CLK 417 -#define IMX7D_WDOG3_ROOT_CLK 418 -#define IMX7D_WDOG4_ROOT_CLK 419 -#define IMX7D_SDMA_CORE_CLK 420 -#define IMX7D_USB1_MAIN_480M_CLK 421 -#define IMX7D_USB_CTRL_CLK 422 -#define IMX7D_USB_PHY1_CLK 423 -#define IMX7D_USB_PHY2_CLK 424 -#define IMX7D_IPG_ROOT_CLK 425 -#define IMX7D_SAI1_IPG_CLK 426 -#define IMX7D_SAI2_IPG_CLK 427 -#define IMX7D_SAI3_IPG_CLK 428 -#define IMX7D_PLL_AUDIO_TEST_DIV 429 -#define IMX7D_PLL_AUDIO_POST_DIV 430 -#define IMX7D_PLL_VIDEO_TEST_DIV 431 -#define IMX7D_PLL_VIDEO_POST_DIV 432 -#define IMX7D_MU_ROOT_CLK 433 -#define IMX7D_SEMA4_HS_ROOT_CLK 434 -#define IMX7D_PLL_DRAM_TEST_DIV 435 -#define IMX7D_ADC_ROOT_CLK 436 -#define IMX7D_CLK_ARM 437 -#define IMX7D_CKIL 438 -#define IMX7D_OCOTP_CLK 439 -#define IMX7D_NAND_RAWNAND_CLK 440 -#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 -#define IMX7D_SNVS_CLK 442 -#define IMX7D_CAAM_CLK 443 -#define IMX7D_KPP_ROOT_CLK 444 -#define IMX7D_PXP_CLK 445 -#define IMX7D_CLK_END 446 -#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h deleted file mode 100644 index b58370d146e2..000000000000 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017~2018 NXP - * - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H -#define __DT_BINDINGS_CLOCK_IMX7ULP_H - -/* SCG1 */ - -#define IMX7ULP_CLK_DUMMY 0 -#define IMX7ULP_CLK_ROSC 1 -#define IMX7ULP_CLK_SOSC 2 -#define IMX7ULP_CLK_FIRC 3 -#define IMX7ULP_CLK_SPLL_PRE_SEL 4 -#define IMX7ULP_CLK_SPLL_PRE_DIV 5 -#define IMX7ULP_CLK_SPLL 6 -#define IMX7ULP_CLK_SPLL_POST_DIV1 7 -#define IMX7ULP_CLK_SPLL_POST_DIV2 8 -#define IMX7ULP_CLK_SPLL_PFD0 9 -#define IMX7ULP_CLK_SPLL_PFD1 10 -#define IMX7ULP_CLK_SPLL_PFD2 11 -#define IMX7ULP_CLK_SPLL_PFD3 12 -#define IMX7ULP_CLK_SPLL_PFD_SEL 13 -#define IMX7ULP_CLK_SPLL_SEL 14 -#define IMX7ULP_CLK_APLL_PRE_SEL 15 -#define IMX7ULP_CLK_APLL_PRE_DIV 16 -#define IMX7ULP_CLK_APLL 17 -#define IMX7ULP_CLK_APLL_POST_DIV1 18 -#define IMX7ULP_CLK_APLL_POST_DIV2 19 -#define IMX7ULP_CLK_APLL_PFD0 20 -#define IMX7ULP_CLK_APLL_PFD1 21 -#define IMX7ULP_CLK_APLL_PFD2 22 -#define IMX7ULP_CLK_APLL_PFD3 23 -#define IMX7ULP_CLK_APLL_PFD_SEL 24 -#define IMX7ULP_CLK_APLL_SEL 25 -#define IMX7ULP_CLK_UPLL 26 -#define IMX7ULP_CLK_SYS_SEL 27 -#define IMX7ULP_CLK_CORE_DIV 28 -#define IMX7ULP_CLK_BUS_DIV 29 -#define IMX7ULP_CLK_PLAT_DIV 30 -#define IMX7ULP_CLK_DDR_SEL 31 -#define IMX7ULP_CLK_DDR_DIV 32 -#define IMX7ULP_CLK_NIC_SEL 33 -#define IMX7ULP_CLK_NIC0_DIV 34 -#define IMX7ULP_CLK_GPU_DIV 35 -#define IMX7ULP_CLK_NIC1_DIV 36 -#define IMX7ULP_CLK_NIC1_BUS_DIV 37 -#define IMX7ULP_CLK_NIC1_EXT_DIV 38 -/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */ -#define IMX7ULP_CLK_MIPI_PLL 39 -#define IMX7ULP_CLK_SIRC 40 -#define IMX7ULP_CLK_SOSC_BUS_CLK 41 -#define IMX7ULP_CLK_FIRC_BUS_CLK 42 -#define IMX7ULP_CLK_SPLL_BUS_CLK 43 -#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 -#define IMX7ULP_CLK_HSRUN_CORE_DIV 45 - -#define IMX7ULP_CLK_CORE 46 -#define IMX7ULP_CLK_HSRUN_CORE 47 - -#define IMX7ULP_CLK_SCG1_END 48 - -/* PCC2 */ -#define IMX7ULP_CLK_DMA1 0 -#define IMX7ULP_CLK_RGPIO2P1 1 -#define IMX7ULP_CLK_FLEXBUS 2 -#define IMX7ULP_CLK_SEMA42_1 3 -#define IMX7ULP_CLK_DMA_MUX1 4 -#define IMX7ULP_CLK_CAAM 6 -#define IMX7ULP_CLK_LPTPM4 7 -#define IMX7ULP_CLK_LPTPM5 8 -#define IMX7ULP_CLK_LPIT1 9 -#define IMX7ULP_CLK_LPSPI2 10 -#define IMX7ULP_CLK_LPSPI3 11 -#define IMX7ULP_CLK_LPI2C4 12 -#define IMX7ULP_CLK_LPI2C5 13 -#define IMX7ULP_CLK_LPUART4 14 -#define IMX7ULP_CLK_LPUART5 15 -#define IMX7ULP_CLK_FLEXIO1 16 -#define IMX7ULP_CLK_USB0 17 -#define IMX7ULP_CLK_USB1 18 -#define IMX7ULP_CLK_USB_PHY 19 -#define IMX7ULP_CLK_USB_PL301 20 -#define IMX7ULP_CLK_USDHC0 21 -#define IMX7ULP_CLK_USDHC1 22 -#define IMX7ULP_CLK_WDG1 23 -#define IMX7ULP_CLK_WDG2 24 - -#define IMX7ULP_CLK_PCC2_END 25 - -/* PCC3 */ -#define IMX7ULP_CLK_LPTPM6 0 -#define IMX7ULP_CLK_LPTPM7 1 -#define IMX7ULP_CLK_LPI2C6 2 -#define IMX7ULP_CLK_LPI2C7 3 -#define IMX7ULP_CLK_LPUART6 4 -#define IMX7ULP_CLK_LPUART7 5 -#define IMX7ULP_CLK_VIU 6 -#define IMX7ULP_CLK_DSI 7 -#define IMX7ULP_CLK_LCDIF 8 -#define IMX7ULP_CLK_MMDC 9 -#define IMX7ULP_CLK_PCTLC 10 -#define IMX7ULP_CLK_PCTLD 11 -#define IMX7ULP_CLK_PCTLE 12 -#define IMX7ULP_CLK_PCTLF 13 -#define IMX7ULP_CLK_GPU3D 14 -#define IMX7ULP_CLK_GPU2D 15 - -#define IMX7ULP_CLK_PCC3_END 16 - -/* SMC1 */ -#define IMX7ULP_CLK_ARM 0 - -#define IMX7ULP_CLK_SMC1_END 1 - -#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h deleted file mode 100644 index 1f768b2eeb1a..000000000000 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ /dev/null @@ -1,286 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2017-2018 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H -#define __DT_BINDINGS_CLOCK_IMX8MM_H - -#define IMX8MM_CLK_DUMMY 0 -#define IMX8MM_CLK_32K 1 -#define IMX8MM_CLK_24M 2 -#define IMX8MM_OSC_HDMI_CLK 3 -#define IMX8MM_CLK_EXT1 4 -#define IMX8MM_CLK_EXT2 5 -#define IMX8MM_CLK_EXT3 6 -#define IMX8MM_CLK_EXT4 7 -#define IMX8MM_AUDIO_PLL1_REF_SEL 8 -#define IMX8MM_AUDIO_PLL2_REF_SEL 9 -#define IMX8MM_VIDEO_PLL1_REF_SEL 10 -#define IMX8MM_DRAM_PLL_REF_SEL 11 -#define IMX8MM_GPU_PLL_REF_SEL 12 -#define IMX8MM_VPU_PLL_REF_SEL 13 -#define IMX8MM_ARM_PLL_REF_SEL 14 -#define IMX8MM_SYS_PLL1_REF_SEL 15 -#define IMX8MM_SYS_PLL2_REF_SEL 16 -#define IMX8MM_SYS_PLL3_REF_SEL 17 -#define IMX8MM_AUDIO_PLL1 18 -#define IMX8MM_AUDIO_PLL2 19 -#define IMX8MM_VIDEO_PLL1 20 -#define IMX8MM_DRAM_PLL 21 -#define IMX8MM_GPU_PLL 22 -#define IMX8MM_VPU_PLL 23 -#define IMX8MM_ARM_PLL 24 -#define IMX8MM_SYS_PLL1 25 -#define IMX8MM_SYS_PLL2 26 -#define IMX8MM_SYS_PLL3 27 -#define IMX8MM_AUDIO_PLL1_BYPASS 28 -#define IMX8MM_AUDIO_PLL2_BYPASS 29 -#define IMX8MM_VIDEO_PLL1_BYPASS 30 -#define IMX8MM_DRAM_PLL_BYPASS 31 -#define IMX8MM_GPU_PLL_BYPASS 32 -#define IMX8MM_VPU_PLL_BYPASS 33 -#define IMX8MM_ARM_PLL_BYPASS 34 -#define IMX8MM_SYS_PLL1_BYPASS 35 -#define IMX8MM_SYS_PLL2_BYPASS 36 -#define IMX8MM_SYS_PLL3_BYPASS 37 -#define IMX8MM_AUDIO_PLL1_OUT 38 -#define IMX8MM_AUDIO_PLL2_OUT 39 -#define IMX8MM_VIDEO_PLL1_OUT 40 -#define IMX8MM_DRAM_PLL_OUT 41 -#define IMX8MM_GPU_PLL_OUT 42 -#define IMX8MM_VPU_PLL_OUT 43 -#define IMX8MM_ARM_PLL_OUT 44 -#define IMX8MM_SYS_PLL1_OUT 45 -#define IMX8MM_SYS_PLL2_OUT 46 -#define IMX8MM_SYS_PLL3_OUT 47 -#define IMX8MM_SYS_PLL1_40M 48 -#define IMX8MM_SYS_PLL1_80M 49 -#define IMX8MM_SYS_PLL1_100M 50 -#define IMX8MM_SYS_PLL1_133M 51 -#define IMX8MM_SYS_PLL1_160M 52 -#define IMX8MM_SYS_PLL1_200M 53 -#define IMX8MM_SYS_PLL1_266M 54 -#define IMX8MM_SYS_PLL1_400M 55 -#define IMX8MM_SYS_PLL1_800M 56 -#define IMX8MM_SYS_PLL2_50M 57 -#define IMX8MM_SYS_PLL2_100M 58 -#define IMX8MM_SYS_PLL2_125M 59 -#define IMX8MM_SYS_PLL2_166M 60 -#define IMX8MM_SYS_PLL2_200M 61 -#define IMX8MM_SYS_PLL2_250M 62 -#define IMX8MM_SYS_PLL2_333M 63 -#define IMX8MM_SYS_PLL2_500M 64 -#define IMX8MM_SYS_PLL2_1000M 65 - -/* core */ -#define IMX8MM_CLK_A53_SRC 66 -#define IMX8MM_CLK_M4_SRC 67 -#define IMX8MM_CLK_VPU_SRC 68 -#define IMX8MM_CLK_GPU3D_SRC 69 -#define IMX8MM_CLK_GPU2D_SRC 70 -#define IMX8MM_CLK_A53_CG 71 -#define IMX8MM_CLK_M4_CG 72 -#define IMX8MM_CLK_VPU_CG 73 -#define IMX8MM_CLK_GPU3D_CG 74 -#define IMX8MM_CLK_GPU2D_CG 75 -#define IMX8MM_CLK_A53_DIV 76 -#define IMX8MM_CLK_M4_DIV 77 -#define IMX8MM_CLK_VPU_DIV 78 -#define IMX8MM_CLK_GPU3D_DIV 79 -#define IMX8MM_CLK_GPU2D_DIV 80 - -/* bus */ -#define IMX8MM_CLK_MAIN_AXI 81 -#define IMX8MM_CLK_ENET_AXI 82 -#define IMX8MM_CLK_NAND_USDHC_BUS 83 -#define IMX8MM_CLK_VPU_BUS 84 -#define IMX8MM_CLK_DISP_AXI 85 -#define IMX8MM_CLK_DISP_APB 86 -#define IMX8MM_CLK_DISP_RTRM 87 -#define IMX8MM_CLK_USB_BUS 88 -#define IMX8MM_CLK_GPU_AXI 89 -#define IMX8MM_CLK_GPU_AHB 90 -#define IMX8MM_CLK_NOC 91 -#define IMX8MM_CLK_NOC_APB 92 - -#define IMX8MM_CLK_AHB 93 -#define IMX8MM_CLK_AUDIO_AHB 94 -#define IMX8MM_CLK_IPG_ROOT 95 -#define IMX8MM_CLK_IPG_AUDIO_ROOT 96 - -#define IMX8MM_CLK_DRAM_ALT 97 -#define IMX8MM_CLK_DRAM_APB 98 -#define IMX8MM_CLK_VPU_G1 99 -#define IMX8MM_CLK_VPU_G2 100 -#define IMX8MM_CLK_DISP_DTRC 101 -#define IMX8MM_CLK_DISP_DC8000 102 -#define IMX8MM_CLK_PCIE1_CTRL 103 -#define IMX8MM_CLK_PCIE1_PHY 104 -#define IMX8MM_CLK_PCIE1_AUX 105 -#define IMX8MM_CLK_DC_PIXEL 106 -#define IMX8MM_CLK_LCDIF_PIXEL 107 -#define IMX8MM_CLK_SAI1 108 -#define IMX8MM_CLK_SAI2 109 -#define IMX8MM_CLK_SAI3 110 -#define IMX8MM_CLK_SAI4 111 -#define IMX8MM_CLK_SAI5 112 -#define IMX8MM_CLK_SAI6 113 -#define IMX8MM_CLK_SPDIF1 114 -#define IMX8MM_CLK_SPDIF2 115 -#define IMX8MM_CLK_ENET_REF 116 -#define IMX8MM_CLK_ENET_TIMER 117 -#define IMX8MM_CLK_ENET_PHY_REF 118 -#define IMX8MM_CLK_NAND 119 -#define IMX8MM_CLK_QSPI 120 -#define IMX8MM_CLK_USDHC1 121 -#define IMX8MM_CLK_USDHC2 122 -#define IMX8MM_CLK_I2C1 123 -#define IMX8MM_CLK_I2C2 124 -#define IMX8MM_CLK_I2C3 125 -#define IMX8MM_CLK_I2C4 126 -#define IMX8MM_CLK_UART1 127 -#define IMX8MM_CLK_UART2 128 -#define IMX8MM_CLK_UART3 129 -#define IMX8MM_CLK_UART4 130 -#define IMX8MM_CLK_USB_CORE_REF 131 -#define IMX8MM_CLK_USB_PHY_REF 132 -#define IMX8MM_CLK_ECSPI1 133 -#define IMX8MM_CLK_ECSPI2 134 -#define IMX8MM_CLK_PWM1 135 -#define IMX8MM_CLK_PWM2 136 -#define IMX8MM_CLK_PWM3 137 -#define IMX8MM_CLK_PWM4 138 -#define IMX8MM_CLK_GPT1 139 -#define IMX8MM_CLK_WDOG 140 -#define IMX8MM_CLK_WRCLK 141 -#define IMX8MM_CLK_DSI_CORE 142 -#define IMX8MM_CLK_DSI_PHY_REF 143 -#define IMX8MM_CLK_DSI_DBI 144 -#define IMX8MM_CLK_USDHC3 145 -#define IMX8MM_CLK_CSI1_CORE 146 -#define IMX8MM_CLK_CSI1_PHY_REF 147 -#define IMX8MM_CLK_CSI1_ESC 148 -#define IMX8MM_CLK_CSI2_CORE 149 -#define IMX8MM_CLK_CSI2_PHY_REF 150 -#define IMX8MM_CLK_CSI2_ESC 151 -#define IMX8MM_CLK_PCIE2_CTRL 152 -#define IMX8MM_CLK_PCIE2_PHY 153 -#define IMX8MM_CLK_PCIE2_AUX 154 -#define IMX8MM_CLK_ECSPI3 155 -#define IMX8MM_CLK_PDM 156 -#define IMX8MM_CLK_VPU_H1 157 -#define IMX8MM_CLK_CLKO1 158 - -#define IMX8MM_CLK_ECSPI1_ROOT 159 -#define IMX8MM_CLK_ECSPI2_ROOT 160 -#define IMX8MM_CLK_ECSPI3_ROOT 161 -#define IMX8MM_CLK_ENET1_ROOT 162 -#define IMX8MM_CLK_GPT1_ROOT 163 -#define IMX8MM_CLK_I2C1_ROOT 164 -#define IMX8MM_CLK_I2C2_ROOT 165 -#define IMX8MM_CLK_I2C3_ROOT 166 -#define IMX8MM_CLK_I2C4_ROOT 167 -#define IMX8MM_CLK_OCOTP_ROOT 168 -#define IMX8MM_CLK_PCIE1_ROOT 169 -#define IMX8MM_CLK_PWM1_ROOT 170 -#define IMX8MM_CLK_PWM2_ROOT 171 -#define IMX8MM_CLK_PWM3_ROOT 172 -#define IMX8MM_CLK_PWM4_ROOT 173 -#define IMX8MM_CLK_QSPI_ROOT 174 -#define IMX8MM_CLK_NAND_ROOT 175 -#define IMX8MM_CLK_SAI1_ROOT 176 -#define IMX8MM_CLK_SAI1_IPG 177 -#define IMX8MM_CLK_SAI2_ROOT 178 -#define IMX8MM_CLK_SAI2_IPG 179 -#define IMX8MM_CLK_SAI3_ROOT 180 -#define IMX8MM_CLK_SAI3_IPG 181 -#define IMX8MM_CLK_SAI4_ROOT 182 -#define IMX8MM_CLK_SAI4_IPG 183 -#define IMX8MM_CLK_SAI5_ROOT 184 -#define IMX8MM_CLK_SAI5_IPG 185 -#define IMX8MM_CLK_SAI6_ROOT 186 -#define IMX8MM_CLK_SAI6_IPG 187 -#define IMX8MM_CLK_UART1_ROOT 188 -#define IMX8MM_CLK_UART2_ROOT 189 -#define IMX8MM_CLK_UART3_ROOT 190 -#define IMX8MM_CLK_UART4_ROOT 191 -#define IMX8MM_CLK_USB1_CTRL_ROOT 192 -#define IMX8MM_CLK_GPU3D_ROOT 193 -#define IMX8MM_CLK_USDHC1_ROOT 194 -#define IMX8MM_CLK_USDHC2_ROOT 195 -#define IMX8MM_CLK_WDOG1_ROOT 196 -#define IMX8MM_CLK_WDOG2_ROOT 197 -#define IMX8MM_CLK_WDOG3_ROOT 198 -#define IMX8MM_CLK_VPU_G1_ROOT 199 -#define IMX8MM_CLK_GPU_BUS_ROOT 200 -#define IMX8MM_CLK_VPU_H1_ROOT 201 -#define IMX8MM_CLK_VPU_G2_ROOT 202 -#define IMX8MM_CLK_PDM_ROOT 203 -#define IMX8MM_CLK_DISP_ROOT 204 -#define IMX8MM_CLK_DISP_AXI_ROOT 205 -#define IMX8MM_CLK_DISP_APB_ROOT 206 -#define IMX8MM_CLK_DISP_RTRM_ROOT 207 -#define IMX8MM_CLK_USDHC3_ROOT 208 -#define IMX8MM_CLK_TMU_ROOT 209 -#define IMX8MM_CLK_VPU_DEC_ROOT 210 -#define IMX8MM_CLK_SDMA1_ROOT 211 -#define IMX8MM_CLK_SDMA2_ROOT 212 -#define IMX8MM_CLK_SDMA3_ROOT 213 -#define IMX8MM_CLK_GPT_3M 214 -#define IMX8MM_CLK_ARM 215 -#define IMX8MM_CLK_PDM_IPG 216 -#define IMX8MM_CLK_GPU2D_ROOT 217 -#define IMX8MM_CLK_MU_ROOT 218 -#define IMX8MM_CLK_CSI1_ROOT 219 - -#define IMX8MM_CLK_DRAM_CORE 220 -#define IMX8MM_CLK_DRAM_ALT_ROOT 221 - -#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 - -#define IMX8MM_CLK_GPIO1_ROOT 223 -#define IMX8MM_CLK_GPIO2_ROOT 224 -#define IMX8MM_CLK_GPIO3_ROOT 225 -#define IMX8MM_CLK_GPIO4_ROOT 226 -#define IMX8MM_CLK_GPIO5_ROOT 227 - -#define IMX8MM_CLK_SNVS_ROOT 228 -#define IMX8MM_CLK_GIC 229 - -#define IMX8MM_SYS_PLL1_40M_CG 230 -#define IMX8MM_SYS_PLL1_80M_CG 231 -#define IMX8MM_SYS_PLL1_100M_CG 232 -#define IMX8MM_SYS_PLL1_133M_CG 233 -#define IMX8MM_SYS_PLL1_160M_CG 234 -#define IMX8MM_SYS_PLL1_200M_CG 235 -#define IMX8MM_SYS_PLL1_266M_CG 236 -#define IMX8MM_SYS_PLL1_400M_CG 237 -#define IMX8MM_SYS_PLL2_50M_CG 238 -#define IMX8MM_SYS_PLL2_100M_CG 239 -#define IMX8MM_SYS_PLL2_125M_CG 240 -#define IMX8MM_SYS_PLL2_166M_CG 241 -#define IMX8MM_SYS_PLL2_200M_CG 242 -#define IMX8MM_SYS_PLL2_250M_CG 243 -#define IMX8MM_SYS_PLL2_333M_CG 244 -#define IMX8MM_SYS_PLL2_500M_CG 245 - -#define IMX8MM_CLK_M4_CORE 246 -#define IMX8MM_CLK_VPU_CORE 247 -#define IMX8MM_CLK_GPU3D_CORE 248 -#define IMX8MM_CLK_GPU2D_CORE 249 - -#define IMX8MM_CLK_CLKO2 250 - -#define IMX8MM_CLK_A53_CORE 251 - -#define IMX8MM_CLK_CLKOUT1_SEL 252 -#define IMX8MM_CLK_CLKOUT1_DIV 253 -#define IMX8MM_CLK_CLKOUT1 254 -#define IMX8MM_CLK_CLKOUT2_SEL 255 -#define IMX8MM_CLK_CLKOUT2_DIV 256 -#define IMX8MM_CLK_CLKOUT2 257 - -#define IMX8MM_CLK_END 258 - -#endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h deleted file mode 100644 index 07b8a282c268..000000000000 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ /dev/null @@ -1,262 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H -#define __DT_BINDINGS_CLOCK_IMX8MN_H - -#define IMX8MN_CLK_DUMMY 0 -#define IMX8MN_CLK_32K 1 -#define IMX8MN_CLK_24M 2 -#define IMX8MN_OSC_HDMI_CLK 3 -#define IMX8MN_CLK_EXT1 4 -#define IMX8MN_CLK_EXT2 5 -#define IMX8MN_CLK_EXT3 6 -#define IMX8MN_CLK_EXT4 7 -#define IMX8MN_AUDIO_PLL1_REF_SEL 8 -#define IMX8MN_AUDIO_PLL2_REF_SEL 9 -#define IMX8MN_VIDEO_PLL1_REF_SEL 10 -#define IMX8MN_DRAM_PLL_REF_SEL 11 -#define IMX8MN_GPU_PLL_REF_SEL 12 -#define IMX8MN_VPU_PLL_REF_SEL 13 -#define IMX8MN_ARM_PLL_REF_SEL 14 -#define IMX8MN_SYS_PLL1_REF_SEL 15 -#define IMX8MN_SYS_PLL2_REF_SEL 16 -#define IMX8MN_SYS_PLL3_REF_SEL 17 -#define IMX8MN_AUDIO_PLL1 18 -#define IMX8MN_AUDIO_PLL2 19 -#define IMX8MN_VIDEO_PLL1 20 -#define IMX8MN_DRAM_PLL 21 -#define IMX8MN_GPU_PLL 22 -#define IMX8MN_VPU_PLL 23 -#define IMX8MN_ARM_PLL 24 -#define IMX8MN_SYS_PLL1 25 -#define IMX8MN_SYS_PLL2 26 -#define IMX8MN_SYS_PLL3 27 -#define IMX8MN_AUDIO_PLL1_BYPASS 28 -#define IMX8MN_AUDIO_PLL2_BYPASS 29 -#define IMX8MN_VIDEO_PLL1_BYPASS 30 -#define IMX8MN_DRAM_PLL_BYPASS 31 -#define IMX8MN_GPU_PLL_BYPASS 32 -#define IMX8MN_VPU_PLL_BYPASS 33 -#define IMX8MN_ARM_PLL_BYPASS 34 -#define IMX8MN_SYS_PLL1_BYPASS 35 -#define IMX8MN_SYS_PLL2_BYPASS 36 -#define IMX8MN_SYS_PLL3_BYPASS 37 -#define IMX8MN_AUDIO_PLL1_OUT 38 -#define IMX8MN_AUDIO_PLL2_OUT 39 -#define IMX8MN_VIDEO_PLL1_OUT 40 -#define IMX8MN_DRAM_PLL_OUT 41 -#define IMX8MN_GPU_PLL_OUT 42 -#define IMX8MN_VPU_PLL_OUT 43 -#define IMX8MN_ARM_PLL_OUT 44 -#define IMX8MN_SYS_PLL1_OUT 45 -#define IMX8MN_SYS_PLL2_OUT 46 -#define IMX8MN_SYS_PLL3_OUT 47 -#define IMX8MN_SYS_PLL1_40M 48 -#define IMX8MN_SYS_PLL1_80M 49 -#define IMX8MN_SYS_PLL1_100M 50 -#define IMX8MN_SYS_PLL1_133M 51 -#define IMX8MN_SYS_PLL1_160M 52 -#define IMX8MN_SYS_PLL1_200M 53 -#define IMX8MN_SYS_PLL1_266M 54 -#define IMX8MN_SYS_PLL1_400M 55 -#define IMX8MN_SYS_PLL1_800M 56 -#define IMX8MN_SYS_PLL2_50M 57 -#define IMX8MN_SYS_PLL2_100M 58 -#define IMX8MN_SYS_PLL2_125M 59 -#define IMX8MN_SYS_PLL2_166M 60 -#define IMX8MN_SYS_PLL2_200M 61 -#define IMX8MN_SYS_PLL2_250M 62 -#define IMX8MN_SYS_PLL2_333M 63 -#define IMX8MN_SYS_PLL2_500M 64 -#define IMX8MN_SYS_PLL2_1000M 65 - -/* CORE CLOCK ROOT */ -#define IMX8MN_CLK_A53_SRC 66 -#define IMX8MN_CLK_GPU_CORE_SRC 67 -#define IMX8MN_CLK_GPU_SHADER_SRC 68 -#define IMX8MN_CLK_A53_CG 69 -#define IMX8MN_CLK_GPU_CORE_CG 70 -#define IMX8MN_CLK_GPU_SHADER_CG 71 -#define IMX8MN_CLK_A53_DIV 72 -#define IMX8MN_CLK_GPU_CORE_DIV 73 -#define IMX8MN_CLK_GPU_SHADER_DIV 74 - -/* BUS CLOCK ROOT */ -#define IMX8MN_CLK_MAIN_AXI 75 -#define IMX8MN_CLK_ENET_AXI 76 -#define IMX8MN_CLK_NAND_USDHC_BUS 77 -#define IMX8MN_CLK_DISP_AXI 78 -#define IMX8MN_CLK_DISP_APB 79 -#define IMX8MN_CLK_USB_BUS 80 -#define IMX8MN_CLK_GPU_AXI 81 -#define IMX8MN_CLK_GPU_AHB 82 -#define IMX8MN_CLK_NOC 83 -#define IMX8MN_CLK_AHB 84 -#define IMX8MN_CLK_AUDIO_AHB 85 - -/* IPG CLOCK ROOT */ -#define IMX8MN_CLK_IPG_ROOT 86 -#define IMX8MN_CLK_IPG_AUDIO_ROOT 87 - -/* IP */ -#define IMX8MN_CLK_DRAM_CORE 88 -#define IMX8MN_CLK_DRAM_ALT 89 -#define IMX8MN_CLK_DRAM_APB 90 -#define IMX8MN_CLK_DRAM_ALT_ROOT 91 -#define IMX8MN_CLK_DISP_PIXEL 92 -#define IMX8MN_CLK_SAI2 93 -#define IMX8MN_CLK_SAI3 94 -#define IMX8MN_CLK_SAI5 95 -#define IMX8MN_CLK_SAI6 96 -#define IMX8MN_CLK_SPDIF1 97 -#define IMX8MN_CLK_ENET_REF 98 -#define IMX8MN_CLK_ENET_TIMER 99 -#define IMX8MN_CLK_ENET_PHY_REF 100 -#define IMX8MN_CLK_NAND 101 -#define IMX8MN_CLK_QSPI 102 -#define IMX8MN_CLK_USDHC1 103 -#define IMX8MN_CLK_USDHC2 104 -#define IMX8MN_CLK_I2C1 105 -#define IMX8MN_CLK_I2C2 106 -#define IMX8MN_CLK_I2C3 107 -#define IMX8MN_CLK_I2C4 108 -#define IMX8MN_CLK_UART1 109 -#define IMX8MN_CLK_UART2 110 -#define IMX8MN_CLK_UART3 111 -#define IMX8MN_CLK_UART4 112 -#define IMX8MN_CLK_USB_CORE_REF 113 -#define IMX8MN_CLK_USB_PHY_REF 114 -#define IMX8MN_CLK_ECSPI1 115 -#define IMX8MN_CLK_ECSPI2 116 -#define IMX8MN_CLK_PWM1 117 -#define IMX8MN_CLK_PWM2 118 -#define IMX8MN_CLK_PWM3 119 -#define IMX8MN_CLK_PWM4 120 -#define IMX8MN_CLK_WDOG 121 -#define IMX8MN_CLK_WRCLK 122 -#define IMX8MN_CLK_CLKO1 123 -#define IMX8MN_CLK_CLKO2 124 -#define IMX8MN_CLK_DSI_CORE 125 -#define IMX8MN_CLK_DSI_PHY_REF 126 -#define IMX8MN_CLK_DSI_DBI 127 -#define IMX8MN_CLK_USDHC3 128 -#define IMX8MN_CLK_CAMERA_PIXEL 129 -#define IMX8MN_CLK_CSI1_PHY_REF 130 -#define IMX8MN_CLK_CSI2_PHY_REF 131 -#define IMX8MN_CLK_CSI2_ESC 132 -#define IMX8MN_CLK_ECSPI3 133 -#define IMX8MN_CLK_PDM 134 -#define IMX8MN_CLK_SAI7 135 - -#define IMX8MN_CLK_ECSPI1_ROOT 136 -#define IMX8MN_CLK_ECSPI2_ROOT 137 -#define IMX8MN_CLK_ECSPI3_ROOT 138 -#define IMX8MN_CLK_ENET1_ROOT 139 -#define IMX8MN_CLK_GPIO1_ROOT 140 -#define IMX8MN_CLK_GPIO2_ROOT 141 -#define IMX8MN_CLK_GPIO3_ROOT 142 -#define IMX8MN_CLK_GPIO4_ROOT 143 -#define IMX8MN_CLK_GPIO5_ROOT 144 -#define IMX8MN_CLK_I2C1_ROOT 145 -#define IMX8MN_CLK_I2C2_ROOT 146 -#define IMX8MN_CLK_I2C3_ROOT 147 -#define IMX8MN_CLK_I2C4_ROOT 148 -#define IMX8MN_CLK_MU_ROOT 149 -#define IMX8MN_CLK_OCOTP_ROOT 150 -#define IMX8MN_CLK_PWM1_ROOT 151 -#define IMX8MN_CLK_PWM2_ROOT 152 -#define IMX8MN_CLK_PWM3_ROOT 153 -#define IMX8MN_CLK_PWM4_ROOT 154 -#define IMX8MN_CLK_QSPI_ROOT 155 -#define IMX8MN_CLK_NAND_ROOT 156 -#define IMX8MN_CLK_SAI2_ROOT 157 -#define IMX8MN_CLK_SAI2_IPG 158 -#define IMX8MN_CLK_SAI3_ROOT 159 -#define IMX8MN_CLK_SAI3_IPG 160 -#define IMX8MN_CLK_SAI5_ROOT 161 -#define IMX8MN_CLK_SAI5_IPG 162 -#define IMX8MN_CLK_SAI6_ROOT 163 -#define IMX8MN_CLK_SAI6_IPG 164 -#define IMX8MN_CLK_SAI7_ROOT 165 -#define IMX8MN_CLK_SAI7_IPG 166 -#define IMX8MN_CLK_SDMA1_ROOT 167 -#define IMX8MN_CLK_SDMA2_ROOT 168 -#define IMX8MN_CLK_UART1_ROOT 169 -#define IMX8MN_CLK_UART2_ROOT 170 -#define IMX8MN_CLK_UART3_ROOT 171 -#define IMX8MN_CLK_UART4_ROOT 172 -#define IMX8MN_CLK_USB1_CTRL_ROOT 173 -#define IMX8MN_CLK_USDHC1_ROOT 174 -#define IMX8MN_CLK_USDHC2_ROOT 175 -#define IMX8MN_CLK_WDOG1_ROOT 176 -#define IMX8MN_CLK_WDOG2_ROOT 177 -#define IMX8MN_CLK_WDOG3_ROOT 178 -#define IMX8MN_CLK_GPU_BUS_ROOT 179 -#define IMX8MN_CLK_ASRC_ROOT 180 -#define IMX8MN_CLK_GPU3D_ROOT 181 -#define IMX8MN_CLK_PDM_ROOT 182 -#define IMX8MN_CLK_PDM_IPG 183 -#define IMX8MN_CLK_DISP_AXI_ROOT 184 -#define IMX8MN_CLK_DISP_APB_ROOT 185 -#define IMX8MN_CLK_DISP_PIXEL_ROOT 186 -#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 -#define IMX8MN_CLK_USDHC3_ROOT 188 -#define IMX8MN_CLK_SDMA3_ROOT 189 -#define IMX8MN_CLK_TMU_ROOT 190 -#define IMX8MN_CLK_ARM 191 -#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 -#define IMX8MN_CLK_GPU_CORE_ROOT 193 -#define IMX8MN_CLK_GIC 194 - -#define IMX8MN_SYS_PLL1_40M_CG 195 -#define IMX8MN_SYS_PLL1_80M_CG 196 -#define IMX8MN_SYS_PLL1_100M_CG 197 -#define IMX8MN_SYS_PLL1_133M_CG 198 -#define IMX8MN_SYS_PLL1_160M_CG 199 -#define IMX8MN_SYS_PLL1_200M_CG 200 -#define IMX8MN_SYS_PLL1_266M_CG 201 -#define IMX8MN_SYS_PLL1_400M_CG 202 -#define IMX8MN_SYS_PLL2_50M_CG 203 -#define IMX8MN_SYS_PLL2_100M_CG 204 -#define IMX8MN_SYS_PLL2_125M_CG 205 -#define IMX8MN_SYS_PLL2_166M_CG 206 -#define IMX8MN_SYS_PLL2_200M_CG 207 -#define IMX8MN_SYS_PLL2_250M_CG 208 -#define IMX8MN_SYS_PLL2_333M_CG 209 -#define IMX8MN_SYS_PLL2_500M_CG 210 - -#define IMX8MN_CLK_SNVS_ROOT 211 -#define IMX8MN_CLK_GPU_CORE 212 -#define IMX8MN_CLK_GPU_SHADER 213 - -#define IMX8MN_CLK_A53_CORE 214 - -#define IMX8MN_CLK_CLKOUT1_SEL 215 -#define IMX8MN_CLK_CLKOUT1_DIV 216 -#define IMX8MN_CLK_CLKOUT1 217 -#define IMX8MN_CLK_CLKOUT2_SEL 218 -#define IMX8MN_CLK_CLKOUT2_DIV 219 -#define IMX8MN_CLK_CLKOUT2 220 - -#define IMX8MN_CLK_M7_CORE 221 - -#define IMX8MN_CLK_GPT_3M 222 -#define IMX8MN_CLK_GPT1 223 -#define IMX8MN_CLK_GPT1_ROOT 224 -#define IMX8MN_CLK_GPT2 225 -#define IMX8MN_CLK_GPT2_ROOT 226 -#define IMX8MN_CLK_GPT3 227 -#define IMX8MN_CLK_GPT3_ROOT 228 -#define IMX8MN_CLK_GPT4 229 -#define IMX8MN_CLK_GPT4_ROOT 230 -#define IMX8MN_CLK_GPT5 231 -#define IMX8MN_CLK_GPT5_ROOT 232 -#define IMX8MN_CLK_GPT6 233 -#define IMX8MN_CLK_GPT6_ROOT 234 - -#define IMX8MN_CLK_END 235 - -#endif diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h deleted file mode 100644 index 7da4243984b2..000000000000 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ /dev/null @@ -1,401 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2019 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H -#define __DT_BINDINGS_CLOCK_IMX8MP_H - -#define IMX8MP_CLK_DUMMY 0 -#define IMX8MP_CLK_32K 1 -#define IMX8MP_CLK_24M 2 -#define IMX8MP_OSC_HDMI_CLK 3 -#define IMX8MP_CLK_EXT1 4 -#define IMX8MP_CLK_EXT2 5 -#define IMX8MP_CLK_EXT3 6 -#define IMX8MP_CLK_EXT4 7 -#define IMX8MP_AUDIO_PLL1_REF_SEL 8 -#define IMX8MP_AUDIO_PLL2_REF_SEL 9 -#define IMX8MP_VIDEO_PLL1_REF_SEL 10 -#define IMX8MP_DRAM_PLL_REF_SEL 11 -#define IMX8MP_GPU_PLL_REF_SEL 12 -#define IMX8MP_VPU_PLL_REF_SEL 13 -#define IMX8MP_ARM_PLL_REF_SEL 14 -#define IMX8MP_SYS_PLL1_REF_SEL 15 -#define IMX8MP_SYS_PLL2_REF_SEL 16 -#define IMX8MP_SYS_PLL3_REF_SEL 17 -#define IMX8MP_AUDIO_PLL1 18 -#define IMX8MP_AUDIO_PLL2 19 -#define IMX8MP_VIDEO_PLL1 20 -#define IMX8MP_DRAM_PLL 21 -#define IMX8MP_GPU_PLL 22 -#define IMX8MP_VPU_PLL 23 -#define IMX8MP_ARM_PLL 24 -#define IMX8MP_SYS_PLL1 25 -#define IMX8MP_SYS_PLL2 26 -#define IMX8MP_SYS_PLL3 27 -#define IMX8MP_AUDIO_PLL1_BYPASS 28 -#define IMX8MP_AUDIO_PLL2_BYPASS 29 -#define IMX8MP_VIDEO_PLL1_BYPASS 30 -#define IMX8MP_DRAM_PLL_BYPASS 31 -#define IMX8MP_GPU_PLL_BYPASS 32 -#define IMX8MP_VPU_PLL_BYPASS 33 -#define IMX8MP_ARM_PLL_BYPASS 34 -#define IMX8MP_SYS_PLL1_BYPASS 35 -#define IMX8MP_SYS_PLL2_BYPASS 36 -#define IMX8MP_SYS_PLL3_BYPASS 37 -#define IMX8MP_AUDIO_PLL1_OUT 38 -#define IMX8MP_AUDIO_PLL2_OUT 39 -#define IMX8MP_VIDEO_PLL1_OUT 40 -#define IMX8MP_DRAM_PLL_OUT 41 -#define IMX8MP_GPU_PLL_OUT 42 -#define IMX8MP_VPU_PLL_OUT 43 -#define IMX8MP_ARM_PLL_OUT 44 -#define IMX8MP_SYS_PLL1_OUT 45 -#define IMX8MP_SYS_PLL2_OUT 46 -#define IMX8MP_SYS_PLL3_OUT 47 -#define IMX8MP_SYS_PLL1_40M 48 -#define IMX8MP_SYS_PLL1_80M 49 -#define IMX8MP_SYS_PLL1_100M 50 -#define IMX8MP_SYS_PLL1_133M 51 -#define IMX8MP_SYS_PLL1_160M 52 -#define IMX8MP_SYS_PLL1_200M 53 -#define IMX8MP_SYS_PLL1_266M 54 -#define IMX8MP_SYS_PLL1_400M 55 -#define IMX8MP_SYS_PLL1_800M 56 -#define IMX8MP_SYS_PLL2_50M 57 -#define IMX8MP_SYS_PLL2_100M 58 -#define IMX8MP_SYS_PLL2_125M 59 -#define IMX8MP_SYS_PLL2_166M 60 -#define IMX8MP_SYS_PLL2_200M 61 -#define IMX8MP_SYS_PLL2_250M 62 -#define IMX8MP_SYS_PLL2_333M 63 -#define IMX8MP_SYS_PLL2_500M 64 -#define IMX8MP_SYS_PLL2_1000M 65 -#define IMX8MP_CLK_A53_SRC 66 -#define IMX8MP_CLK_M7_SRC 67 -#define IMX8MP_CLK_ML_SRC 68 -#define IMX8MP_CLK_GPU3D_CORE_SRC 69 -#define IMX8MP_CLK_GPU3D_SHADER_SRC 70 -#define IMX8MP_CLK_GPU2D_SRC 71 -#define IMX8MP_CLK_AUDIO_AXI_SRC 72 -#define IMX8MP_CLK_HSIO_AXI_SRC 73 -#define IMX8MP_CLK_MEDIA_ISP_SRC 74 -#define IMX8MP_CLK_A53_CG 75 -#define IMX8MP_CLK_M4_CG 76 -#define IMX8MP_CLK_ML_CG 77 -#define IMX8MP_CLK_GPU3D_CORE_CG 78 -#define IMX8MP_CLK_GPU3D_SHADER_CG 79 -#define IMX8MP_CLK_GPU2D_CG 80 -#define IMX8MP_CLK_AUDIO_AXI_CG 81 -#define IMX8MP_CLK_HSIO_AXI_CG 82 -#define IMX8MP_CLK_MEDIA_ISP_CG 83 -#define IMX8MP_CLK_A53_DIV 84 -#define IMX8MP_CLK_M7_DIV 85 -#define IMX8MP_CLK_ML_DIV 86 -#define IMX8MP_CLK_GPU3D_CORE_DIV 87 -#define IMX8MP_CLK_GPU3D_SHADER_DIV 88 -#define IMX8MP_CLK_GPU2D_DIV 89 -#define IMX8MP_CLK_AUDIO_AXI_DIV 90 -#define IMX8MP_CLK_HSIO_AXI_DIV 91 -#define IMX8MP_CLK_MEDIA_ISP_DIV 92 -#define IMX8MP_CLK_MAIN_AXI 93 -#define IMX8MP_CLK_ENET_AXI 94 -#define IMX8MP_CLK_NAND_USDHC_BUS 95 -#define IMX8MP_CLK_VPU_BUS 96 -#define IMX8MP_CLK_MEDIA_AXI 97 -#define IMX8MP_CLK_MEDIA_APB 98 -#define IMX8MP_CLK_HDMI_APB 99 -#define IMX8MP_CLK_HDMI_AXI 100 -#define IMX8MP_CLK_GPU_AXI 101 -#define IMX8MP_CLK_GPU_AHB 102 -#define IMX8MP_CLK_NOC 103 -#define IMX8MP_CLK_NOC_IO 104 -#define IMX8MP_CLK_ML_AXI 105 -#define IMX8MP_CLK_ML_AHB 106 -#define IMX8MP_CLK_AHB 107 -#define IMX8MP_CLK_AUDIO_AHB 108 -#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 -#define IMX8MP_CLK_IPG_ROOT 110 -#define IMX8MP_CLK_DRAM_ALT 112 -#define IMX8MP_CLK_DRAM_APB 113 -#define IMX8MP_CLK_VPU_G1 114 -#define IMX8MP_CLK_VPU_G2 115 -#define IMX8MP_CLK_CAN1 116 -#define IMX8MP_CLK_CAN2 117 -#define IMX8MP_CLK_MEMREPAIR 118 -#define IMX8MP_CLK_PCIE_AUX 120 -#define IMX8MP_CLK_I2C5 121 -#define IMX8MP_CLK_I2C6 122 -#define IMX8MP_CLK_SAI1 123 -#define IMX8MP_CLK_SAI2 124 -#define IMX8MP_CLK_SAI3 125 -/* #define IMX8MP_CLK_SAI4 126 */ -#define IMX8MP_CLK_SAI5 127 -#define IMX8MP_CLK_SAI6 128 -#define IMX8MP_CLK_ENET_QOS 129 -#define IMX8MP_CLK_ENET_QOS_TIMER 130 -#define IMX8MP_CLK_ENET_REF 131 -#define IMX8MP_CLK_ENET_TIMER 132 -#define IMX8MP_CLK_ENET_PHY_REF 133 -#define IMX8MP_CLK_NAND 134 -#define IMX8MP_CLK_QSPI 135 -#define IMX8MP_CLK_USDHC1 136 -#define IMX8MP_CLK_USDHC2 137 -#define IMX8MP_CLK_I2C1 138 -#define IMX8MP_CLK_I2C2 139 -#define IMX8MP_CLK_I2C3 140 -#define IMX8MP_CLK_I2C4 141 -#define IMX8MP_CLK_UART1 142 -#define IMX8MP_CLK_UART2 143 -#define IMX8MP_CLK_UART3 144 -#define IMX8MP_CLK_UART4 145 -#define IMX8MP_CLK_USB_CORE_REF 146 -#define IMX8MP_CLK_USB_PHY_REF 147 -#define IMX8MP_CLK_GIC 148 -#define IMX8MP_CLK_ECSPI1 149 -#define IMX8MP_CLK_ECSPI2 150 -#define IMX8MP_CLK_PWM1 151 -#define IMX8MP_CLK_PWM2 152 -#define IMX8MP_CLK_PWM3 153 -#define IMX8MP_CLK_PWM4 154 -#define IMX8MP_CLK_GPT1 155 -#define IMX8MP_CLK_GPT2 156 -#define IMX8MP_CLK_GPT3 157 -#define IMX8MP_CLK_GPT4 158 -#define IMX8MP_CLK_GPT5 159 -#define IMX8MP_CLK_GPT6 160 -#define IMX8MP_CLK_TRACE 161 -#define IMX8MP_CLK_WDOG 162 -#define IMX8MP_CLK_WRCLK 163 -#define IMX8MP_CLK_IPP_DO_CLKO1 164 -#define IMX8MP_CLK_IPP_DO_CLKO2 165 -#define IMX8MP_CLK_HDMI_FDCC_TST 166 -#define IMX8MP_CLK_HDMI_24M 167 -#define IMX8MP_CLK_HDMI_REF_266M 168 -#define IMX8MP_CLK_USDHC3 169 -#define IMX8MP_CLK_MEDIA_CAM1_PIX 170 -#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171 -#define IMX8MP_CLK_MEDIA_DISP1_PIX 172 -#define IMX8MP_CLK_MEDIA_CAM2_PIX 173 -#define IMX8MP_CLK_MEDIA_LDB 174 -#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 -#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 -#define IMX8MP_CLK_ECSPI3 179 -#define IMX8MP_CLK_PDM 180 -#define IMX8MP_CLK_VPU_VC8000E 181 -#define IMX8MP_CLK_SAI7 182 -#define IMX8MP_CLK_GPC_ROOT 183 -#define IMX8MP_CLK_ANAMIX_ROOT 184 -#define IMX8MP_CLK_CPU_ROOT 185 -#define IMX8MP_CLK_CSU_ROOT 186 -#define IMX8MP_CLK_DEBUG_ROOT 187 -#define IMX8MP_CLK_DRAM1_ROOT 188 -#define IMX8MP_CLK_ECSPI1_ROOT 189 -#define IMX8MP_CLK_ECSPI2_ROOT 190 -#define IMX8MP_CLK_ECSPI3_ROOT 191 -#define IMX8MP_CLK_ENET1_ROOT 192 -#define IMX8MP_CLK_GPIO1_ROOT 193 -#define IMX8MP_CLK_GPIO2_ROOT 194 -#define IMX8MP_CLK_GPIO3_ROOT 195 -#define IMX8MP_CLK_GPIO4_ROOT 196 -#define IMX8MP_CLK_GPIO5_ROOT 197 -#define IMX8MP_CLK_GPT1_ROOT 198 -#define IMX8MP_CLK_GPT2_ROOT 199 -#define IMX8MP_CLK_GPT3_ROOT 200 -#define IMX8MP_CLK_GPT4_ROOT 201 -#define IMX8MP_CLK_GPT5_ROOT 202 -#define IMX8MP_CLK_GPT6_ROOT 203 -#define IMX8MP_CLK_HS_ROOT 204 -#define IMX8MP_CLK_I2C1_ROOT 205 -#define IMX8MP_CLK_I2C2_ROOT 206 -#define IMX8MP_CLK_I2C3_ROOT 207 -#define IMX8MP_CLK_I2C4_ROOT 208 -#define IMX8MP_CLK_IOMUX_ROOT 209 -#define IMX8MP_CLK_IPMUX1_ROOT 210 -#define IMX8MP_CLK_IPMUX2_ROOT 211 -#define IMX8MP_CLK_IPMUX3_ROOT 212 -#define IMX8MP_CLK_MU_ROOT 213 -#define IMX8MP_CLK_OCOTP_ROOT 214 -#define IMX8MP_CLK_OCRAM_ROOT 215 -#define IMX8MP_CLK_OCRAM_S_ROOT 216 -#define IMX8MP_CLK_PCIE_ROOT 217 -#define IMX8MP_CLK_PERFMON1_ROOT 218 -#define IMX8MP_CLK_PERFMON2_ROOT 219 -#define IMX8MP_CLK_PWM1_ROOT 220 -#define IMX8MP_CLK_PWM2_ROOT 221 -#define IMX8MP_CLK_PWM3_ROOT 222 -#define IMX8MP_CLK_PWM4_ROOT 223 -#define IMX8MP_CLK_QOS_ROOT 224 -#define IMX8MP_CLK_QOS_ENET_ROOT 225 -#define IMX8MP_CLK_QSPI_ROOT 226 -#define IMX8MP_CLK_NAND_ROOT 227 -#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228 -#define IMX8MP_CLK_RDC_ROOT 229 -#define IMX8MP_CLK_ROM_ROOT 230 -#define IMX8MP_CLK_I2C5_ROOT 231 -#define IMX8MP_CLK_I2C6_ROOT 232 -#define IMX8MP_CLK_CAN1_ROOT 233 -#define IMX8MP_CLK_CAN2_ROOT 234 -#define IMX8MP_CLK_SCTR_ROOT 235 -#define IMX8MP_CLK_SDMA1_ROOT 236 -#define IMX8MP_CLK_ENET_QOS_ROOT 237 -#define IMX8MP_CLK_SEC_DEBUG_ROOT 238 -#define IMX8MP_CLK_SEMA1_ROOT 239 -#define IMX8MP_CLK_SEMA2_ROOT 240 -#define IMX8MP_CLK_IRQ_STEER_ROOT 241 -#define IMX8MP_CLK_SIM_ENET_ROOT 242 -#define IMX8MP_CLK_SIM_M_ROOT 243 -#define IMX8MP_CLK_SIM_MAIN_ROOT 244 -#define IMX8MP_CLK_SIM_S_ROOT 245 -#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246 -#define IMX8MP_CLK_GPU2D_ROOT 247 -#define IMX8MP_CLK_GPU3D_ROOT 248 -#define IMX8MP_CLK_SNVS_ROOT 249 -#define IMX8MP_CLK_TRACE_ROOT 250 -#define IMX8MP_CLK_UART1_ROOT 251 -#define IMX8MP_CLK_UART2_ROOT 252 -#define IMX8MP_CLK_UART3_ROOT 253 -#define IMX8MP_CLK_UART4_ROOT 254 -#define IMX8MP_CLK_USB_ROOT 255 -#define IMX8MP_CLK_USB_PHY_ROOT 256 -#define IMX8MP_CLK_USDHC1_ROOT 257 -#define IMX8MP_CLK_USDHC2_ROOT 258 -#define IMX8MP_CLK_WDOG1_ROOT 259 -#define IMX8MP_CLK_WDOG2_ROOT 260 -#define IMX8MP_CLK_WDOG3_ROOT 261 -#define IMX8MP_CLK_VPU_G1_ROOT 262 -#define IMX8MP_CLK_GPU_ROOT 263 -#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264 -#define IMX8MP_CLK_VPU_VC8KE_ROOT 265 -#define IMX8MP_CLK_VPU_G2_ROOT 266 -#define IMX8MP_CLK_NPU_ROOT 267 -#define IMX8MP_CLK_HSIO_ROOT 268 -#define IMX8MP_CLK_MEDIA_APB_ROOT 269 -#define IMX8MP_CLK_MEDIA_AXI_ROOT 270 -#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271 -#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272 -#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273 -#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274 -#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275 -#define IMX8MP_CLK_MEDIA_ISP_ROOT 276 -#define IMX8MP_CLK_USDHC3_ROOT 277 -#define IMX8MP_CLK_HDMI_ROOT 278 -#define IMX8MP_CLK_XTAL_ROOT 279 -#define IMX8MP_CLK_PLL_ROOT 280 -#define IMX8MP_CLK_TSENSOR_ROOT 281 -#define IMX8MP_CLK_VPU_ROOT 282 -#define IMX8MP_CLK_MRPR_ROOT 283 -#define IMX8MP_CLK_AUDIO_ROOT 284 -#define IMX8MP_CLK_DRAM_ALT_ROOT 285 -#define IMX8MP_CLK_DRAM_CORE 286 -#define IMX8MP_CLK_ARM 287 -#define IMX8MP_CLK_A53_CORE 288 - -#define IMX8MP_SYS_PLL1_40M_CG 289 -#define IMX8MP_SYS_PLL1_80M_CG 290 -#define IMX8MP_SYS_PLL1_100M_CG 291 -#define IMX8MP_SYS_PLL1_133M_CG 292 -#define IMX8MP_SYS_PLL1_160M_CG 293 -#define IMX8MP_SYS_PLL1_200M_CG 294 -#define IMX8MP_SYS_PLL1_266M_CG 295 -#define IMX8MP_SYS_PLL1_400M_CG 296 -#define IMX8MP_SYS_PLL2_50M_CG 297 -#define IMX8MP_SYS_PLL2_100M_CG 298 -#define IMX8MP_SYS_PLL2_125M_CG 299 -#define IMX8MP_SYS_PLL2_166M_CG 300 -#define IMX8MP_SYS_PLL2_200M_CG 301 -#define IMX8MP_SYS_PLL2_250M_CG 302 -#define IMX8MP_SYS_PLL2_333M_CG 303 -#define IMX8MP_SYS_PLL2_500M_CG 304 - -#define IMX8MP_CLK_M7_CORE 305 -#define IMX8MP_CLK_ML_CORE 306 -#define IMX8MP_CLK_GPU3D_CORE 307 -#define IMX8MP_CLK_GPU3D_SHADER_CORE 308 -#define IMX8MP_CLK_GPU2D_CORE 309 -#define IMX8MP_CLK_AUDIO_AXI 310 -#define IMX8MP_CLK_HSIO_AXI 311 -#define IMX8MP_CLK_MEDIA_ISP 312 -#define IMX8MP_CLK_MEDIA_DISP2_PIX 313 -#define IMX8MP_CLK_CLKOUT1_SEL 314 -#define IMX8MP_CLK_CLKOUT1_DIV 315 -#define IMX8MP_CLK_CLKOUT1 316 -#define IMX8MP_CLK_CLKOUT2_SEL 317 -#define IMX8MP_CLK_CLKOUT2_DIV 318 -#define IMX8MP_CLK_CLKOUT2 319 -#define IMX8MP_CLK_USB_SUSP 320 -#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT -#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 -#define IMX8MP_CLK_SAI1_ROOT 322 -#define IMX8MP_CLK_SAI2_ROOT 323 -#define IMX8MP_CLK_SAI3_ROOT 324 -#define IMX8MP_CLK_SAI5_ROOT 325 -#define IMX8MP_CLK_SAI6_ROOT 326 -#define IMX8MP_CLK_SAI7_ROOT 327 -#define IMX8MP_CLK_PDM_ROOT 328 -#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 -#define IMX8MP_CLK_END 330 - -#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 -#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 -#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 -#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 -#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 -#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 -#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 -#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 -#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 -#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 -#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 -#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 -#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 -#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 -#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 -#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 -#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 -#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 -#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 -#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 -#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 -#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 - -#define IMX8MP_CLK_AUDIOMIX_END 59 - -#endif diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h deleted file mode 100644 index afa74d7ba100..000000000000 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ /dev/null @@ -1,431 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H -#define __DT_BINDINGS_CLOCK_IMX8MQ_H - -#define IMX8MQ_CLK_DUMMY 0 -#define IMX8MQ_CLK_32K 1 -#define IMX8MQ_CLK_25M 2 -#define IMX8MQ_CLK_27M 3 -#define IMX8MQ_CLK_EXT1 4 -#define IMX8MQ_CLK_EXT2 5 -#define IMX8MQ_CLK_EXT3 6 -#define IMX8MQ_CLK_EXT4 7 - -/* ANAMIX PLL clocks */ -/* FRAC PLLs */ -/* ARM PLL */ -#define IMX8MQ_ARM_PLL_REF_SEL 8 -#define IMX8MQ_ARM_PLL_REF_DIV 9 -#define IMX8MQ_ARM_PLL 10 -#define IMX8MQ_ARM_PLL_BYPASS 11 -#define IMX8MQ_ARM_PLL_OUT 12 - -/* GPU PLL */ -#define IMX8MQ_GPU_PLL_REF_SEL 13 -#define IMX8MQ_GPU_PLL_REF_DIV 14 -#define IMX8MQ_GPU_PLL 15 -#define IMX8MQ_GPU_PLL_BYPASS 16 -#define IMX8MQ_GPU_PLL_OUT 17 - -/* VPU PLL */ -#define IMX8MQ_VPU_PLL_REF_SEL 18 -#define IMX8MQ_VPU_PLL_REF_DIV 19 -#define IMX8MQ_VPU_PLL 20 -#define IMX8MQ_VPU_PLL_BYPASS 21 -#define IMX8MQ_VPU_PLL_OUT 22 - -/* AUDIO PLL1 */ -#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 -#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 -#define IMX8MQ_AUDIO_PLL1 25 -#define IMX8MQ_AUDIO_PLL1_BYPASS 26 -#define IMX8MQ_AUDIO_PLL1_OUT 27 - -/* AUDIO PLL2 */ -#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 -#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 -#define IMX8MQ_AUDIO_PLL2 30 -#define IMX8MQ_AUDIO_PLL2_BYPASS 31 -#define IMX8MQ_AUDIO_PLL2_OUT 32 - -/* VIDEO PLL1 */ -#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 -#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 -#define IMX8MQ_VIDEO_PLL1 35 -#define IMX8MQ_VIDEO_PLL1_BYPASS 36 -#define IMX8MQ_VIDEO_PLL1_OUT 37 - -/* SYS1 PLL */ -#define IMX8MQ_SYS1_PLL1_REF_SEL 38 -#define IMX8MQ_SYS1_PLL1_REF_DIV 39 -#define IMX8MQ_SYS1_PLL1 40 -#define IMX8MQ_SYS1_PLL1_OUT 41 -#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 -#define IMX8MQ_SYS1_PLL2 43 -#define IMX8MQ_SYS1_PLL2_DIV 44 -#define IMX8MQ_SYS1_PLL2_OUT 45 - -/* SYS2 PLL */ -#define IMX8MQ_SYS2_PLL1_REF_SEL 46 -#define IMX8MQ_SYS2_PLL1_REF_DIV 47 -#define IMX8MQ_SYS2_PLL1 48 -#define IMX8MQ_SYS2_PLL1_OUT 49 -#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 -#define IMX8MQ_SYS2_PLL2 51 -#define IMX8MQ_SYS2_PLL2_DIV 52 -#define IMX8MQ_SYS2_PLL2_OUT 53 - -/* SYS3 PLL */ -#define IMX8MQ_SYS3_PLL1_REF_SEL 54 -#define IMX8MQ_SYS3_PLL1_REF_DIV 55 -#define IMX8MQ_SYS3_PLL1 56 -#define IMX8MQ_SYS3_PLL1_OUT 57 -#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 -#define IMX8MQ_SYS3_PLL2 59 -#define IMX8MQ_SYS3_PLL2_DIV 60 -#define IMX8MQ_SYS3_PLL2_OUT 61 - -/* DRAM PLL */ -#define IMX8MQ_DRAM_PLL1_REF_SEL 62 -#define IMX8MQ_DRAM_PLL1_REF_DIV 63 -#define IMX8MQ_DRAM_PLL1 64 -#define IMX8MQ_DRAM_PLL1_OUT 65 -#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 -#define IMX8MQ_DRAM_PLL2 67 -#define IMX8MQ_DRAM_PLL2_DIV 68 -#define IMX8MQ_DRAM_PLL2_OUT 69 - -/* SYS PLL DIV */ -#define IMX8MQ_SYS1_PLL_40M 70 -#define IMX8MQ_SYS1_PLL_80M 71 -#define IMX8MQ_SYS1_PLL_100M 72 -#define IMX8MQ_SYS1_PLL_133M 73 -#define IMX8MQ_SYS1_PLL_160M 74 -#define IMX8MQ_SYS1_PLL_200M 75 -#define IMX8MQ_SYS1_PLL_266M 76 -#define IMX8MQ_SYS1_PLL_400M 77 -#define IMX8MQ_SYS1_PLL_800M 78 - -#define IMX8MQ_SYS2_PLL_50M 79 -#define IMX8MQ_SYS2_PLL_100M 80 -#define IMX8MQ_SYS2_PLL_125M 81 -#define IMX8MQ_SYS2_PLL_166M 82 -#define IMX8MQ_SYS2_PLL_200M 83 -#define IMX8MQ_SYS2_PLL_250M 84 -#define IMX8MQ_SYS2_PLL_333M 85 -#define IMX8MQ_SYS2_PLL_500M 86 -#define IMX8MQ_SYS2_PLL_1000M 87 - -/* CCM ROOT clocks */ -/* A53 */ -#define IMX8MQ_CLK_A53_SRC 88 -#define IMX8MQ_CLK_A53_CG 89 -#define IMX8MQ_CLK_A53_DIV 90 -/* M4 */ -#define IMX8MQ_CLK_M4_SRC 91 -#define IMX8MQ_CLK_M4_CG 92 -#define IMX8MQ_CLK_M4_DIV 93 -/* VPU */ -#define IMX8MQ_CLK_VPU_SRC 94 -#define IMX8MQ_CLK_VPU_CG 95 -#define IMX8MQ_CLK_VPU_DIV 96 -/* GPU CORE */ -#define IMX8MQ_CLK_GPU_CORE_SRC 97 -#define IMX8MQ_CLK_GPU_CORE_CG 98 -#define IMX8MQ_CLK_GPU_CORE_DIV 99 -/* GPU SHADER */ -#define IMX8MQ_CLK_GPU_SHADER_SRC 100 -#define IMX8MQ_CLK_GPU_SHADER_CG 101 -#define IMX8MQ_CLK_GPU_SHADER_DIV 102 - -/* BUS TYPE */ -/* MAIN AXI */ -#define IMX8MQ_CLK_MAIN_AXI 103 -/* ENET AXI */ -#define IMX8MQ_CLK_ENET_AXI 104 -/* NAND_USDHC_BUS */ -#define IMX8MQ_CLK_NAND_USDHC_BUS 105 -/* VPU BUS */ -#define IMX8MQ_CLK_VPU_BUS 106 -/* DISP_AXI */ -#define IMX8MQ_CLK_DISP_AXI 107 -/* DISP APB */ -#define IMX8MQ_CLK_DISP_APB 108 -/* DISP RTRM */ -#define IMX8MQ_CLK_DISP_RTRM 109 -/* USB_BUS */ -#define IMX8MQ_CLK_USB_BUS 110 -/* GPU_AXI */ -#define IMX8MQ_CLK_GPU_AXI 111 -/* GPU_AHB */ -#define IMX8MQ_CLK_GPU_AHB 112 -/* NOC */ -#define IMX8MQ_CLK_NOC 113 -/* NOC_APB */ -#define IMX8MQ_CLK_NOC_APB 115 - -/* AHB */ -#define IMX8MQ_CLK_AHB 116 -/* AUDIO AHB */ -#define IMX8MQ_CLK_AUDIO_AHB 117 - -/* DRAM_ALT */ -#define IMX8MQ_CLK_DRAM_ALT 118 -/* DRAM APB */ -#define IMX8MQ_CLK_DRAM_APB 119 -/* VPU_G1 */ -#define IMX8MQ_CLK_VPU_G1 120 -/* VPU_G2 */ -#define IMX8MQ_CLK_VPU_G2 121 -/* DISP_DTRC */ -#define IMX8MQ_CLK_DISP_DTRC 122 -/* DISP_DC8000 */ -#define IMX8MQ_CLK_DISP_DC8000 123 -/* PCIE_CTRL */ -#define IMX8MQ_CLK_PCIE1_CTRL 124 -/* PCIE_PHY */ -#define IMX8MQ_CLK_PCIE1_PHY 125 -/* PCIE_AUX */ -#define IMX8MQ_CLK_PCIE1_AUX 126 -/* DC_PIXEL */ -#define IMX8MQ_CLK_DC_PIXEL 127 -/* LCDIF_PIXEL */ -#define IMX8MQ_CLK_LCDIF_PIXEL 128 -/* SAI1~6 */ -#define IMX8MQ_CLK_SAI1 129 - -#define IMX8MQ_CLK_SAI2 130 - -#define IMX8MQ_CLK_SAI3 131 - -#define IMX8MQ_CLK_SAI4 132 - -#define IMX8MQ_CLK_SAI5 133 - -#define IMX8MQ_CLK_SAI6 134 -/* SPDIF1 */ -#define IMX8MQ_CLK_SPDIF1 135 -/* SPDIF2 */ -#define IMX8MQ_CLK_SPDIF2 136 -/* ENET_REF */ -#define IMX8MQ_CLK_ENET_REF 137 -/* ENET_TIMER */ -#define IMX8MQ_CLK_ENET_TIMER 138 -/* ENET_PHY */ -#define IMX8MQ_CLK_ENET_PHY_REF 139 -/* NAND */ -#define IMX8MQ_CLK_NAND 140 -/* QSPI */ -#define IMX8MQ_CLK_QSPI 141 -/* USDHC1 */ -#define IMX8MQ_CLK_USDHC1 142 -/* USDHC2 */ -#define IMX8MQ_CLK_USDHC2 143 -/* I2C1 */ -#define IMX8MQ_CLK_I2C1 144 -/* I2C2 */ -#define IMX8MQ_CLK_I2C2 145 -/* I2C3 */ -#define IMX8MQ_CLK_I2C3 146 -/* I2C4 */ -#define IMX8MQ_CLK_I2C4 147 -/* UART1 */ -#define IMX8MQ_CLK_UART1 148 -/* UART2 */ -#define IMX8MQ_CLK_UART2 149 -/* UART3 */ -#define IMX8MQ_CLK_UART3 150 -/* UART4 */ -#define IMX8MQ_CLK_UART4 151 -/* USB_CORE_REF */ -#define IMX8MQ_CLK_USB_CORE_REF 152 -/* USB_PHY_REF */ -#define IMX8MQ_CLK_USB_PHY_REF 153 -/* ECSPI1 */ -#define IMX8MQ_CLK_ECSPI1 154 -/* ECSPI2 */ -#define IMX8MQ_CLK_ECSPI2 155 -/* PWM1 */ -#define IMX8MQ_CLK_PWM1 156 -/* PWM2 */ -#define IMX8MQ_CLK_PWM2 157 -/* PWM3 */ -#define IMX8MQ_CLK_PWM3 158 -/* PWM4 */ -#define IMX8MQ_CLK_PWM4 159 -/* GPT1 */ -#define IMX8MQ_CLK_GPT1 160 -/* WDOG */ -#define IMX8MQ_CLK_WDOG 161 -/* WRCLK */ -#define IMX8MQ_CLK_WRCLK 162 -/* DSI_CORE */ -#define IMX8MQ_CLK_DSI_CORE 163 -/* DSI_PHY */ -#define IMX8MQ_CLK_DSI_PHY_REF 164 -/* DSI_DBI */ -#define IMX8MQ_CLK_DSI_DBI 165 -/*DSI_ESC */ -#define IMX8MQ_CLK_DSI_ESC 166 -/* CSI1_CORE */ -#define IMX8MQ_CLK_CSI1_CORE 167 -/* CSI1_PHY */ -#define IMX8MQ_CLK_CSI1_PHY_REF 168 -/* CSI_ESC */ -#define IMX8MQ_CLK_CSI1_ESC 169 -/* CSI2_CORE */ -#define IMX8MQ_CLK_CSI2_CORE 170 -/* CSI2_PHY */ -#define IMX8MQ_CLK_CSI2_PHY_REF 171 -/* CSI2_ESC */ -#define IMX8MQ_CLK_CSI2_ESC 172 -/* PCIE2_CTRL */ -#define IMX8MQ_CLK_PCIE2_CTRL 173 -/* PCIE2_PHY */ -#define IMX8MQ_CLK_PCIE2_PHY 174 -/* PCIE2_AUX */ -#define IMX8MQ_CLK_PCIE2_AUX 175 -/* ECSPI3 */ -#define IMX8MQ_CLK_ECSPI3 176 - -/* CCGR clocks */ -#define IMX8MQ_CLK_A53_ROOT 177 -#define IMX8MQ_CLK_DRAM_ROOT 178 -#define IMX8MQ_CLK_ECSPI1_ROOT 179 -#define IMX8MQ_CLK_ECSPI2_ROOT 180 -#define IMX8MQ_CLK_ECSPI3_ROOT 181 -#define IMX8MQ_CLK_ENET1_ROOT 182 -#define IMX8MQ_CLK_GPT1_ROOT 183 -#define IMX8MQ_CLK_I2C1_ROOT 184 -#define IMX8MQ_CLK_I2C2_ROOT 185 -#define IMX8MQ_CLK_I2C3_ROOT 186 -#define IMX8MQ_CLK_I2C4_ROOT 187 -#define IMX8MQ_CLK_M4_ROOT 188 -#define IMX8MQ_CLK_PCIE1_ROOT 189 -#define IMX8MQ_CLK_PCIE2_ROOT 190 -#define IMX8MQ_CLK_PWM1_ROOT 191 -#define IMX8MQ_CLK_PWM2_ROOT 192 -#define IMX8MQ_CLK_PWM3_ROOT 193 -#define IMX8MQ_CLK_PWM4_ROOT 194 -#define IMX8MQ_CLK_QSPI_ROOT 195 -#define IMX8MQ_CLK_SAI1_ROOT 196 -#define IMX8MQ_CLK_SAI2_ROOT 197 -#define IMX8MQ_CLK_SAI3_ROOT 198 -#define IMX8MQ_CLK_SAI4_ROOT 199 -#define IMX8MQ_CLK_SAI5_ROOT 200 -#define IMX8MQ_CLK_SAI6_ROOT 201 -#define IMX8MQ_CLK_UART1_ROOT 202 -#define IMX8MQ_CLK_UART2_ROOT 203 -#define IMX8MQ_CLK_UART3_ROOT 204 -#define IMX8MQ_CLK_UART4_ROOT 205 -#define IMX8MQ_CLK_USB1_CTRL_ROOT 206 -#define IMX8MQ_CLK_USB2_CTRL_ROOT 207 -#define IMX8MQ_CLK_USB1_PHY_ROOT 208 -#define IMX8MQ_CLK_USB2_PHY_ROOT 209 -#define IMX8MQ_CLK_USDHC1_ROOT 210 -#define IMX8MQ_CLK_USDHC2_ROOT 211 -#define IMX8MQ_CLK_WDOG1_ROOT 212 -#define IMX8MQ_CLK_WDOG2_ROOT 213 -#define IMX8MQ_CLK_WDOG3_ROOT 214 -#define IMX8MQ_CLK_GPU_ROOT 215 -#define IMX8MQ_CLK_HEVC_ROOT 216 -#define IMX8MQ_CLK_AVC_ROOT 217 -#define IMX8MQ_CLK_VP9_ROOT 218 -#define IMX8MQ_CLK_HEVC_INTER_ROOT 219 -#define IMX8MQ_CLK_DISP_ROOT 220 -#define IMX8MQ_CLK_HDMI_ROOT 221 -#define IMX8MQ_CLK_HDMI_PHY_ROOT 222 -#define IMX8MQ_CLK_VPU_DEC_ROOT 223 -#define IMX8MQ_CLK_CSI1_ROOT 224 -#define IMX8MQ_CLK_CSI2_ROOT 225 -#define IMX8MQ_CLK_RAWNAND_ROOT 226 -#define IMX8MQ_CLK_SDMA1_ROOT 227 -#define IMX8MQ_CLK_SDMA2_ROOT 228 -#define IMX8MQ_CLK_VPU_G1_ROOT 229 -#define IMX8MQ_CLK_VPU_G2_ROOT 230 - -/* SCCG PLL GATE */ -#define IMX8MQ_SYS1_PLL_OUT 231 -#define IMX8MQ_SYS2_PLL_OUT 232 -#define IMX8MQ_SYS3_PLL_OUT 233 -#define IMX8MQ_DRAM_PLL_OUT 234 - -#define IMX8MQ_GPT_3M_CLK 235 - -#define IMX8MQ_CLK_IPG_ROOT 236 -#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237 -#define IMX8MQ_CLK_SAI1_IPG 238 -#define IMX8MQ_CLK_SAI2_IPG 239 -#define IMX8MQ_CLK_SAI3_IPG 240 -#define IMX8MQ_CLK_SAI4_IPG 241 -#define IMX8MQ_CLK_SAI5_IPG 242 -#define IMX8MQ_CLK_SAI6_IPG 243 - -/* DSI AHB/IPG clocks */ -/* rxesc clock */ -#define IMX8MQ_CLK_DSI_AHB 244 -/* txesc clock */ -#define IMX8MQ_CLK_DSI_IPG_DIV 245 - -#define IMX8MQ_CLK_TMU_ROOT 246 - -/* Display root clocks */ -#define IMX8MQ_CLK_DISP_AXI_ROOT 247 -#define IMX8MQ_CLK_DISP_APB_ROOT 248 -#define IMX8MQ_CLK_DISP_RTRM_ROOT 249 - -#define IMX8MQ_CLK_OCOTP_ROOT 250 - -#define IMX8MQ_CLK_DRAM_ALT_ROOT 251 -#define IMX8MQ_CLK_DRAM_CORE 252 - -#define IMX8MQ_CLK_MU_ROOT 253 -#define IMX8MQ_VIDEO2_PLL_OUT 254 - -#define IMX8MQ_CLK_CLKO2 255 - -#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 - -#define IMX8MQ_CLK_CLKO1 257 -#define IMX8MQ_CLK_ARM 258 - -#define IMX8MQ_CLK_GPIO1_ROOT 259 -#define IMX8MQ_CLK_GPIO2_ROOT 260 -#define IMX8MQ_CLK_GPIO3_ROOT 261 -#define IMX8MQ_CLK_GPIO4_ROOT 262 -#define IMX8MQ_CLK_GPIO5_ROOT 263 - -#define IMX8MQ_CLK_SNVS_ROOT 264 -#define IMX8MQ_CLK_GIC 265 - -#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 - -#define IMX8MQ_CLK_GPU_CORE 285 -#define IMX8MQ_CLK_GPU_SHADER 286 -#define IMX8MQ_CLK_M4_CORE 287 -#define IMX8MQ_CLK_VPU_CORE 288 - -#define IMX8MQ_CLK_A53_CORE 289 - -#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290 -#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291 -#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292 -#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293 -#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294 -#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295 -#define IMX8MQ_CLK_MON_SYS_PLL1_DIV 296 -#define IMX8MQ_CLK_MON_SYS_PLL2_DIV 297 -#define IMX8MQ_CLK_MON_SYS_PLL3_DIV 298 -#define IMX8MQ_CLK_MON_DRAM_PLL_DIV 299 -#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300 -#define IMX8MQ_CLK_MON_SEL 301 -#define IMX8MQ_CLK_MON_CLK2_OUT 302 - -#define IMX8MQ_CLK_END 303 - -#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h deleted file mode 100644 index 953ecfe8ebcc..000000000000 --- a/include/dt-bindings/clock/imx8ulp-clock.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Copyright 2021 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H -#define __DT_BINDINGS_CLOCK_IMX8ULP_H - -#define IMX8ULP_CLK_DUMMY 0 - -/* CGC1 */ -#define IMX8ULP_CLK_SPLL2 5 -#define IMX8ULP_CLK_SPLL3 6 -#define IMX8ULP_CLK_A35_SEL 7 -#define IMX8ULP_CLK_A35_DIV 8 -#define IMX8ULP_CLK_SPLL2_PRE_SEL 9 -#define IMX8ULP_CLK_SPLL3_PRE_SEL 10 -#define IMX8ULP_CLK_SPLL3_PFD0 11 -#define IMX8ULP_CLK_SPLL3_PFD1 12 -#define IMX8ULP_CLK_SPLL3_PFD2 13 -#define IMX8ULP_CLK_SPLL3_PFD3 14 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22 -#define IMX8ULP_CLK_NIC_SEL 23 -#define IMX8ULP_CLK_NIC_AD_DIVPLAT 24 -#define IMX8ULP_CLK_NIC_PER_DIVPLAT 25 -#define IMX8ULP_CLK_XBAR_SEL 26 -#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27 -#define IMX8ULP_CLK_XBAR_DIVBUS 28 -#define IMX8ULP_CLK_XBAR_AD_SLOW 29 -#define IMX8ULP_CLK_SOSC_DIV1 30 -#define IMX8ULP_CLK_SOSC_DIV2 31 -#define IMX8ULP_CLK_SOSC_DIV3 32 -#define IMX8ULP_CLK_FROSC_DIV1 33 -#define IMX8ULP_CLK_FROSC_DIV2 34 -#define IMX8ULP_CLK_FROSC_DIV3 35 -#define IMX8ULP_CLK_SPLL3_VCODIV 36 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37 -#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39 -#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41 -#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43 -#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44 -#define IMX8ULP_CLK_SOSC_DIV1_GATE 45 -#define IMX8ULP_CLK_SOSC_DIV2_GATE 46 -#define IMX8ULP_CLK_SOSC_DIV3_GATE 47 -#define IMX8ULP_CLK_FROSC_DIV1_GATE 48 -#define IMX8ULP_CLK_FROSC_DIV2_GATE 49 -#define IMX8ULP_CLK_FROSC_DIV3_GATE 50 -#define IMX8ULP_CLK_SAI4_SEL 51 -#define IMX8ULP_CLK_SAI5_SEL 52 -#define IMX8ULP_CLK_AUD_CLK1 53 -#define IMX8ULP_CLK_ARM 54 -#define IMX8ULP_CLK_ENET_TS_SEL 55 - -#define IMX8ULP_CLK_CGC1_END 56 - -/* CGC2 */ -#define IMX8ULP_CLK_PLL4_PRE_SEL 0 -#define IMX8ULP_CLK_PLL4 1 -#define IMX8ULP_CLK_PLL4_VCODIV 2 -#define IMX8ULP_CLK_DDR_SEL 3 -#define IMX8ULP_CLK_DDR_DIV 4 -#define IMX8ULP_CLK_LPAV_AXI_SEL 5 -#define IMX8ULP_CLK_LPAV_AXI_DIV 6 -#define IMX8ULP_CLK_LPAV_AHB_DIV 7 -#define IMX8ULP_CLK_LPAV_BUS_DIV 8 -#define IMX8ULP_CLK_PLL4_PFD0 9 -#define IMX8ULP_CLK_PLL4_PFD1 10 -#define IMX8ULP_CLK_PLL4_PFD2 11 -#define IMX8ULP_CLK_PLL4_PFD3 12 -#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13 -#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14 -#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15 -#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16 -#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17 -#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18 -#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19 -#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20 -#define IMX8ULP_CLK_PLL4_PFD0_DIV1 21 -#define IMX8ULP_CLK_PLL4_PFD0_DIV2 22 -#define IMX8ULP_CLK_PLL4_PFD1_DIV1 23 -#define IMX8ULP_CLK_PLL4_PFD1_DIV2 24 -#define IMX8ULP_CLK_PLL4_PFD2_DIV1 25 -#define IMX8ULP_CLK_PLL4_PFD2_DIV2 26 -#define IMX8ULP_CLK_PLL4_PFD3_DIV1 27 -#define IMX8ULP_CLK_PLL4_PFD3_DIV2 28 -#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29 -#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30 -#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31 -#define IMX8ULP_CLK_CGC2_SOSC_DIV1 32 -#define IMX8ULP_CLK_CGC2_SOSC_DIV2 33 -#define IMX8ULP_CLK_CGC2_SOSC_DIV3 34 -#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35 -#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36 -#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37 -#define IMX8ULP_CLK_CGC2_FROSC_DIV1 38 -#define IMX8ULP_CLK_CGC2_FROSC_DIV2 39 -#define IMX8ULP_CLK_CGC2_FROSC_DIV3 40 -#define IMX8ULP_CLK_AUD_CLK2 41 -#define IMX8ULP_CLK_SAI6_SEL 42 -#define IMX8ULP_CLK_SAI7_SEL 43 -#define IMX8ULP_CLK_SPDIF_SEL 44 -#define IMX8ULP_CLK_HIFI_SEL 45 -#define IMX8ULP_CLK_HIFI_DIVCORE 46 -#define IMX8ULP_CLK_HIFI_DIVPLAT 47 -#define IMX8ULP_CLK_DSI_PHY_REF 48 - -#define IMX8ULP_CLK_CGC2_END 49 - -/* PCC3 */ -#define IMX8ULP_CLK_WDOG3 0 -#define IMX8ULP_CLK_WDOG4 1 -#define IMX8ULP_CLK_LPIT1 2 -#define IMX8ULP_CLK_TPM4 3 -#define IMX8ULP_CLK_TPM5 4 -#define IMX8ULP_CLK_FLEXIO1 5 -#define IMX8ULP_CLK_I3C2 6 -#define IMX8ULP_CLK_LPI2C4 7 -#define IMX8ULP_CLK_LPI2C5 8 -#define IMX8ULP_CLK_LPUART4 9 -#define IMX8ULP_CLK_LPUART5 10 -#define IMX8ULP_CLK_LPSPI4 11 -#define IMX8ULP_CLK_LPSPI5 12 -#define IMX8ULP_CLK_DMA1_MP 13 -#define IMX8ULP_CLK_DMA1_CH0 14 -#define IMX8ULP_CLK_DMA1_CH1 15 -#define IMX8ULP_CLK_DMA1_CH2 16 -#define IMX8ULP_CLK_DMA1_CH3 17 -#define IMX8ULP_CLK_DMA1_CH4 18 -#define IMX8ULP_CLK_DMA1_CH5 19 -#define IMX8ULP_CLK_DMA1_CH6 20 -#define IMX8ULP_CLK_DMA1_CH7 21 -#define IMX8ULP_CLK_DMA1_CH8 22 -#define IMX8ULP_CLK_DMA1_CH9 23 -#define IMX8ULP_CLK_DMA1_CH10 24 -#define IMX8ULP_CLK_DMA1_CH11 25 -#define IMX8ULP_CLK_DMA1_CH12 26 -#define IMX8ULP_CLK_DMA1_CH13 27 -#define IMX8ULP_CLK_DMA1_CH14 28 -#define IMX8ULP_CLK_DMA1_CH15 29 -#define IMX8ULP_CLK_DMA1_CH16 30 -#define IMX8ULP_CLK_DMA1_CH17 31 -#define IMX8ULP_CLK_DMA1_CH18 32 -#define IMX8ULP_CLK_DMA1_CH19 33 -#define IMX8ULP_CLK_DMA1_CH20 34 -#define IMX8ULP_CLK_DMA1_CH21 35 -#define IMX8ULP_CLK_DMA1_CH22 36 -#define IMX8ULP_CLK_DMA1_CH23 37 -#define IMX8ULP_CLK_DMA1_CH24 38 -#define IMX8ULP_CLK_DMA1_CH25 39 -#define IMX8ULP_CLK_DMA1_CH26 40 -#define IMX8ULP_CLK_DMA1_CH27 41 -#define IMX8ULP_CLK_DMA1_CH28 42 -#define IMX8ULP_CLK_DMA1_CH29 43 -#define IMX8ULP_CLK_DMA1_CH30 44 -#define IMX8ULP_CLK_DMA1_CH31 45 -#define IMX8ULP_CLK_MU3_A 46 -#define IMX8ULP_CLK_MU0_B 47 - -#define IMX8ULP_CLK_PCC3_END 48 - -/* PCC4 */ -#define IMX8ULP_CLK_FLEXSPI2 0 -#define IMX8ULP_CLK_TPM6 1 -#define IMX8ULP_CLK_TPM7 2 -#define IMX8ULP_CLK_LPI2C6 3 -#define IMX8ULP_CLK_LPI2C7 4 -#define IMX8ULP_CLK_LPUART6 5 -#define IMX8ULP_CLK_LPUART7 6 -#define IMX8ULP_CLK_SAI4 7 -#define IMX8ULP_CLK_SAI5 8 -#define IMX8ULP_CLK_PCTLE 9 -#define IMX8ULP_CLK_PCTLF 10 -#define IMX8ULP_CLK_USDHC0 11 -#define IMX8ULP_CLK_USDHC1 12 -#define IMX8ULP_CLK_USDHC2 13 -#define IMX8ULP_CLK_USB0 14 -#define IMX8ULP_CLK_USB0_PHY 15 -#define IMX8ULP_CLK_USB1 16 -#define IMX8ULP_CLK_USB1_PHY 17 -#define IMX8ULP_CLK_USB_XBAR 18 -#define IMX8ULP_CLK_ENET 19 -#define IMX8ULP_CLK_SFA1 20 -#define IMX8ULP_CLK_RGPIOE 21 -#define IMX8ULP_CLK_RGPIOF 22 - -#define IMX8ULP_CLK_PCC4_END 23 - -/* PCC5 */ -#define IMX8ULP_CLK_TPM8 0 -#define IMX8ULP_CLK_SAI6 1 -#define IMX8ULP_CLK_SAI7 2 -#define IMX8ULP_CLK_SPDIF 3 -#define IMX8ULP_CLK_ISI 4 -#define IMX8ULP_CLK_CSI_REGS 5 -#define IMX8ULP_CLK_PCTLD 6 -#define IMX8ULP_CLK_CSI 7 -#define IMX8ULP_CLK_DSI 8 -#define IMX8ULP_CLK_WDOG5 9 -#define IMX8ULP_CLK_EPDC 10 -#define IMX8ULP_CLK_PXP 11 -#define IMX8ULP_CLK_SFA2 12 -#define IMX8ULP_CLK_GPU2D 13 -#define IMX8ULP_CLK_GPU3D 14 -#define IMX8ULP_CLK_DC_NANO 15 -#define IMX8ULP_CLK_CSI_CLK_UI 16 -#define IMX8ULP_CLK_CSI_CLK_ESC 17 -#define IMX8ULP_CLK_RGPIOD 18 -#define IMX8ULP_CLK_DMA2_MP 19 -#define IMX8ULP_CLK_DMA2_CH0 20 -#define IMX8ULP_CLK_DMA2_CH1 21 -#define IMX8ULP_CLK_DMA2_CH2 22 -#define IMX8ULP_CLK_DMA2_CH3 23 -#define IMX8ULP_CLK_DMA2_CH4 24 -#define IMX8ULP_CLK_DMA2_CH5 25 -#define IMX8ULP_CLK_DMA2_CH6 26 -#define IMX8ULP_CLK_DMA2_CH7 27 -#define IMX8ULP_CLK_DMA2_CH8 28 -#define IMX8ULP_CLK_DMA2_CH9 29 -#define IMX8ULP_CLK_DMA2_CH10 30 -#define IMX8ULP_CLK_DMA2_CH11 31 -#define IMX8ULP_CLK_DMA2_CH12 32 -#define IMX8ULP_CLK_DMA2_CH13 33 -#define IMX8ULP_CLK_DMA2_CH14 34 -#define IMX8ULP_CLK_DMA2_CH15 35 -#define IMX8ULP_CLK_DMA2_CH16 36 -#define IMX8ULP_CLK_DMA2_CH17 37 -#define IMX8ULP_CLK_DMA2_CH18 38 -#define IMX8ULP_CLK_DMA2_CH19 39 -#define IMX8ULP_CLK_DMA2_CH20 40 -#define IMX8ULP_CLK_DMA2_CH21 41 -#define IMX8ULP_CLK_DMA2_CH22 42 -#define IMX8ULP_CLK_DMA2_CH23 43 -#define IMX8ULP_CLK_DMA2_CH24 44 -#define IMX8ULP_CLK_DMA2_CH25 45 -#define IMX8ULP_CLK_DMA2_CH26 46 -#define IMX8ULP_CLK_DMA2_CH27 47 -#define IMX8ULP_CLK_DMA2_CH28 48 -#define IMX8ULP_CLK_DMA2_CH29 49 -#define IMX8ULP_CLK_DMA2_CH30 50 -#define IMX8ULP_CLK_DMA2_CH31 51 -#define IMX8ULP_CLK_MU2_B 52 -#define IMX8ULP_CLK_MU3_B 53 -#define IMX8ULP_CLK_AVD_SIM 54 -#define IMX8ULP_CLK_DSI_TX_ESC 55 - -#define IMX8ULP_CLK_PCC5_END 56 - -#endif diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h deleted file mode 100644 index 35a1f62053a5..000000000000 --- a/include/dt-bindings/clock/imx93-clock.h +++ /dev/null @@ -1,208 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Copyright 2022 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H -#define __DT_BINDINGS_CLOCK_IMX93_CLK_H - -#define IMX93_CLK_DUMMY 0 -#define IMX93_CLK_24M 1 -#define IMX93_CLK_EXT1 2 -#define IMX93_CLK_SYS_PLL_PFD0 3 -#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4 -#define IMX93_CLK_SYS_PLL_PFD1 5 -#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 -#define IMX93_CLK_SYS_PLL_PFD2 7 -#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8 -#define IMX93_CLK_AUDIO_PLL 9 -#define IMX93_CLK_VIDEO_PLL 10 -#define IMX93_CLK_A55_PERIPH 11 -#define IMX93_CLK_A55_MTR_BUS 12 -#define IMX93_CLK_A55 13 -#define IMX93_CLK_M33 14 -#define IMX93_CLK_BUS_WAKEUP 15 -#define IMX93_CLK_BUS_AON 16 -#define IMX93_CLK_WAKEUP_AXI 17 -#define IMX93_CLK_SWO_TRACE 18 -#define IMX93_CLK_M33_SYSTICK 19 -#define IMX93_CLK_FLEXIO1 20 -#define IMX93_CLK_FLEXIO2 21 -#define IMX93_CLK_LPTMR1 24 -#define IMX93_CLK_LPTMR2 25 -#define IMX93_CLK_TPM2 27 -#define IMX93_CLK_TPM4 29 -#define IMX93_CLK_TPM5 30 -#define IMX93_CLK_TPM6 31 -#define IMX93_CLK_FLEXSPI1 32 -#define IMX93_CLK_CAN1 33 -#define IMX93_CLK_CAN2 34 -#define IMX93_CLK_LPUART1 35 -#define IMX93_CLK_LPUART2 36 -#define IMX93_CLK_LPUART3 37 -#define IMX93_CLK_LPUART4 38 -#define IMX93_CLK_LPUART5 39 -#define IMX93_CLK_LPUART6 40 -#define IMX93_CLK_LPUART7 41 -#define IMX93_CLK_LPUART8 42 -#define IMX93_CLK_LPI2C1 43 -#define IMX93_CLK_LPI2C2 44 -#define IMX93_CLK_LPI2C3 45 -#define IMX93_CLK_LPI2C4 46 -#define IMX93_CLK_LPI2C5 47 -#define IMX93_CLK_LPI2C6 48 -#define IMX93_CLK_LPI2C7 49 -#define IMX93_CLK_LPI2C8 50 -#define IMX93_CLK_LPSPI1 51 -#define IMX93_CLK_LPSPI2 52 -#define IMX93_CLK_LPSPI3 53 -#define IMX93_CLK_LPSPI4 54 -#define IMX93_CLK_LPSPI5 55 -#define IMX93_CLK_LPSPI6 56 -#define IMX93_CLK_LPSPI7 57 -#define IMX93_CLK_LPSPI8 58 -#define IMX93_CLK_I3C1 59 -#define IMX93_CLK_I3C2 60 -#define IMX93_CLK_USDHC1 61 -#define IMX93_CLK_USDHC2 62 -#define IMX93_CLK_USDHC3 63 -#define IMX93_CLK_SAI1 64 -#define IMX93_CLK_SAI2 65 -#define IMX93_CLK_SAI3 66 -#define IMX93_CLK_CCM_CKO1 67 -#define IMX93_CLK_CCM_CKO2 68 -#define IMX93_CLK_CCM_CKO3 69 -#define IMX93_CLK_CCM_CKO4 70 -#define IMX93_CLK_HSIO 71 -#define IMX93_CLK_HSIO_USB_TEST_60M 72 -#define IMX93_CLK_HSIO_ACSCAN_80M 73 -#define IMX93_CLK_HSIO_ACSCAN_480M 74 -#define IMX93_CLK_ML_APB 75 -#define IMX93_CLK_ML 76 -#define IMX93_CLK_MEDIA_AXI 77 -#define IMX93_CLK_MEDIA_APB 78 -#define IMX93_CLK_MEDIA_LDB 79 -#define IMX93_CLK_MEDIA_DISP_PIX 80 -#define IMX93_CLK_CAM_PIX 81 -#define IMX93_CLK_MIPI_TEST_BYTE 82 -#define IMX93_CLK_MIPI_PHY_CFG 83 -#define IMX93_CLK_ADC 84 -#define IMX93_CLK_PDM 85 -#define IMX93_CLK_TSTMR1 86 -#define IMX93_CLK_TSTMR2 87 -#define IMX93_CLK_MQS1 88 -#define IMX93_CLK_MQS2 89 -#define IMX93_CLK_AUDIO_XCVR 90 -#define IMX93_CLK_SPDIF 91 -#define IMX93_CLK_ENET 92 -#define IMX93_CLK_ENET_TIMER1 93 -#define IMX93_CLK_ENET_TIMER2 94 -#define IMX93_CLK_ENET_REF 95 -#define IMX93_CLK_ENET_REF_PHY 96 -#define IMX93_CLK_I3C1_SLOW 97 -#define IMX93_CLK_I3C2_SLOW 98 -#define IMX93_CLK_USB_PHY_BURUNIN 99 -#define IMX93_CLK_PAL_CAME_SCAN 100 -#define IMX93_CLK_A55_GATE 101 -#define IMX93_CLK_CM33_GATE 102 -#define IMX93_CLK_ADC1_GATE 103 -#define IMX93_CLK_WDOG1_GATE 104 -#define IMX93_CLK_WDOG2_GATE 105 -#define IMX93_CLK_WDOG3_GATE 106 -#define IMX93_CLK_WDOG4_GATE 107 -#define IMX93_CLK_WDOG5_GATE 108 -#define IMX93_CLK_SEMA1_GATE 109 -#define IMX93_CLK_SEMA2_GATE 110 -#define IMX93_CLK_MU_A_GATE 111 -#define IMX93_CLK_MU_B_GATE 112 -#define IMX93_CLK_EDMA1_GATE 113 -#define IMX93_CLK_EDMA2_GATE 114 -#define IMX93_CLK_FLEXSPI1_GATE 115 -#define IMX93_CLK_GPIO1_GATE 116 -#define IMX93_CLK_GPIO2_GATE 117 -#define IMX93_CLK_GPIO3_GATE 118 -#define IMX93_CLK_GPIO4_GATE 119 -#define IMX93_CLK_FLEXIO1_GATE 120 -#define IMX93_CLK_FLEXIO2_GATE 121 -#define IMX93_CLK_LPIT1_GATE 122 -#define IMX93_CLK_LPIT2_GATE 123 -#define IMX93_CLK_LPTMR1_GATE 124 -#define IMX93_CLK_LPTMR2_GATE 125 -#define IMX93_CLK_TPM1_GATE 126 -#define IMX93_CLK_TPM2_GATE 127 -#define IMX93_CLK_TPM3_GATE 128 -#define IMX93_CLK_TPM4_GATE 129 -#define IMX93_CLK_TPM5_GATE 130 -#define IMX93_CLK_TPM6_GATE 131 -#define IMX93_CLK_CAN1_GATE 132 -#define IMX93_CLK_CAN2_GATE 133 -#define IMX93_CLK_LPUART1_GATE 134 -#define IMX93_CLK_LPUART2_GATE 135 -#define IMX93_CLK_LPUART3_GATE 136 -#define IMX93_CLK_LPUART4_GATE 137 -#define IMX93_CLK_LPUART5_GATE 138 -#define IMX93_CLK_LPUART6_GATE 139 -#define IMX93_CLK_LPUART7_GATE 140 -#define IMX93_CLK_LPUART8_GATE 141 -#define IMX93_CLK_LPI2C1_GATE 142 -#define IMX93_CLK_LPI2C2_GATE 143 -#define IMX93_CLK_LPI2C3_GATE 144 -#define IMX93_CLK_LPI2C4_GATE 145 -#define IMX93_CLK_LPI2C5_GATE 146 -#define IMX93_CLK_LPI2C6_GATE 147 -#define IMX93_CLK_LPI2C7_GATE 148 -#define IMX93_CLK_LPI2C8_GATE 149 -#define IMX93_CLK_LPSPI1_GATE 150 -#define IMX93_CLK_LPSPI2_GATE 151 -#define IMX93_CLK_LPSPI3_GATE 152 -#define IMX93_CLK_LPSPI4_GATE 153 -#define IMX93_CLK_LPSPI5_GATE 154 -#define IMX93_CLK_LPSPI6_GATE 155 -#define IMX93_CLK_LPSPI7_GATE 156 -#define IMX93_CLK_LPSPI8_GATE 157 -#define IMX93_CLK_I3C1_GATE 158 -#define IMX93_CLK_I3C2_GATE 159 -#define IMX93_CLK_USDHC1_GATE 160 -#define IMX93_CLK_USDHC2_GATE 161 -#define IMX93_CLK_USDHC3_GATE 162 -#define IMX93_CLK_SAI1_GATE 163 -#define IMX93_CLK_SAI2_GATE 164 -#define IMX93_CLK_SAI3_GATE 165 -#define IMX93_CLK_MIPI_CSI_GATE 166 -#define IMX93_CLK_MIPI_DSI_GATE 167 -#define IMX93_CLK_LVDS_GATE 168 -#define IMX93_CLK_LCDIF_GATE 169 -#define IMX93_CLK_PXP_GATE 170 -#define IMX93_CLK_ISI_GATE 171 -#define IMX93_CLK_NIC_MEDIA_GATE 172 -#define IMX93_CLK_USB_CONTROLLER_GATE 173 -#define IMX93_CLK_USB_TEST_60M_GATE 174 -#define IMX93_CLK_HSIO_TROUT_24M_GATE 175 -#define IMX93_CLK_PDM_GATE 176 -#define IMX93_CLK_MQS1_GATE 177 -#define IMX93_CLK_MQS2_GATE 178 -#define IMX93_CLK_AUD_XCVR_GATE 179 -#define IMX93_CLK_SPDIF_GATE 180 -#define IMX93_CLK_HSIO_32K_GATE 181 -#define IMX93_CLK_ENET1_GATE 182 -#define IMX93_CLK_ENET_QOS_GATE 183 -#define IMX93_CLK_SYS_CNT_GATE 184 -#define IMX93_CLK_TSTMR1_GATE 185 -#define IMX93_CLK_TSTMR2_GATE 186 -#define IMX93_CLK_TMC_GATE 187 -#define IMX93_CLK_PMRO_GATE 188 -#define IMX93_CLK_32K 189 -#define IMX93_CLK_SAI1_IPG 190 -#define IMX93_CLK_SAI2_IPG 191 -#define IMX93_CLK_SAI3_IPG 192 -#define IMX93_CLK_MU1_A_GATE 193 -#define IMX93_CLK_MU1_B_GATE 194 -#define IMX93_CLK_MU2_A_GATE 195 -#define IMX93_CLK_MU2_B_GATE 196 -#define IMX93_CLK_NIC_AXI 197 -#define IMX93_CLK_ARM_PLL 198 -#define IMX93_CLK_A55_SEL 199 -#define IMX93_CLK_A55_CORE 200 -#define IMX93_CLK_END 201 - -#endif diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h deleted file mode 100644 index 93bef0832d16..000000000000 --- a/include/dt-bindings/clock/imxrt1050-clock.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright(C) 2019 - * Author(s): Giulio Benetti giulio.benetti@benettiengineering.com - */ - -#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H -#define __DT_BINDINGS_CLOCK_IMXRT1050_H - -#define IMXRT1050_CLK_DUMMY 0 -#define IMXRT1050_CLK_CKIL 1 -#define IMXRT1050_CLK_CKIH 2 -#define IMXRT1050_CLK_OSC 3 -#define IMXRT1050_CLK_PLL2_PFD0_352M 4 -#define IMXRT1050_CLK_PLL2_PFD1_594M 5 -#define IMXRT1050_CLK_PLL2_PFD2_396M 6 -#define IMXRT1050_CLK_PLL3_PFD0_720M 7 -#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 -#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 -#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 -#define IMXRT1050_CLK_PLL2_198M 11 -#define IMXRT1050_CLK_PLL3_120M 12 -#define IMXRT1050_CLK_PLL3_80M 13 -#define IMXRT1050_CLK_PLL3_60M 14 -#define IMXRT1050_CLK_PLL1_BYPASS 15 -#define IMXRT1050_CLK_PLL2_BYPASS 16 -#define IMXRT1050_CLK_PLL3_BYPASS 17 -#define IMXRT1050_CLK_PLL5_BYPASS 19 -#define IMXRT1050_CLK_PLL1_REF_SEL 20 -#define IMXRT1050_CLK_PLL2_REF_SEL 21 -#define IMXRT1050_CLK_PLL3_REF_SEL 22 -#define IMXRT1050_CLK_PLL5_REF_SEL 23 -#define IMXRT1050_CLK_PRE_PERIPH_SEL 24 -#define IMXRT1050_CLK_PERIPH_SEL 25 -#define IMXRT1050_CLK_SEMC_ALT_SEL 26 -#define IMXRT1050_CLK_SEMC_SEL 27 -#define IMXRT1050_CLK_USDHC1_SEL 28 -#define IMXRT1050_CLK_USDHC2_SEL 29 -#define IMXRT1050_CLK_LPUART_SEL 30 -#define IMXRT1050_CLK_LCDIF_SEL 31 -#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32 -#define IMXRT1050_CLK_VIDEO_DIV 33 -#define IMXRT1050_CLK_ARM_PODF 34 -#define IMXRT1050_CLK_LPUART_PODF 35 -#define IMXRT1050_CLK_USDHC1_PODF 36 -#define IMXRT1050_CLK_USDHC2_PODF 37 -#define IMXRT1050_CLK_SEMC_PODF 38 -#define IMXRT1050_CLK_AHB_PODF 39 -#define IMXRT1050_CLK_LCDIF_PRED 40 -#define IMXRT1050_CLK_LCDIF_PODF 41 -#define IMXRT1050_CLK_USDHC1 42 -#define IMXRT1050_CLK_USDHC2 43 -#define IMXRT1050_CLK_LPUART1 44 -#define IMXRT1050_CLK_SEMC 45 -#define IMXRT1050_CLK_LCDIF_APB 46 -#define IMXRT1050_CLK_PLL1_ARM 47 -#define IMXRT1050_CLK_PLL2_SYS 48 -#define IMXRT1050_CLK_PLL3_USB_OTG 49 -#define IMXRT1050_CLK_PLL4_AUDIO 50 -#define IMXRT1050_CLK_PLL5_VIDEO 51 -#define IMXRT1050_CLK_PLL6_ENET 52 -#define IMXRT1050_CLK_PLL7_USB_HOST 53 -#define IMXRT1050_CLK_LCDIF_PIX 54 -#define IMXRT1050_CLK_USBOH3 55 -#define IMXRT1050_CLK_IPG_PDOF 56 -#define IMXRT1050_CLK_PER_CLK_SEL 57 -#define IMXRT1050_CLK_PER_PDOF 58 -#define IMXRT1050_CLK_DMA 59 -#define IMXRT1050_CLK_DMA_MUX 60 -#define IMXRT1050_CLK_END 61 - -#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */

Dropped in favour of dts/upstream

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- .../clock/amlogic,a1-peripherals-clkc.h | 168 --------------------- include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 25 --- include/dt-bindings/clock/axg-aoclkc.h | 31 ---- include/dt-bindings/clock/axg-audio-clkc.h | 94 ------------ include/dt-bindings/clock/axg-clkc.h | 100 ------------ include/dt-bindings/clock/g12a-aoclkc.h | 36 ----- include/dt-bindings/clock/g12a-clkc.h | 153 ------------------- include/dt-bindings/clock/gxbb-aoclkc.h | 74 --------- include/dt-bindings/clock/gxbb-clkc.h | 151 ------------------ include/dt-bindings/gpio/meson-a1-gpio.h | 73 --------- include/dt-bindings/gpio/meson-axg-gpio.h | 116 -------------- include/dt-bindings/gpio/meson-g12a-gpio.h | 114 -------------- include/dt-bindings/gpio/meson-gxbb-gpio.h | 148 ------------------ include/dt-bindings/gpio/meson-gxl-gpio.h | 125 --------------- include/dt-bindings/power/meson-a1-power.h | 32 ---- include/dt-bindings/power/meson-axg-power.h | 14 -- include/dt-bindings/power/meson-g12a-power.h | 13 -- include/dt-bindings/power/meson-gxbb-power.h | 13 -- include/dt-bindings/power/meson-sm1-power.h | 18 --- include/dt-bindings/reset/amlogic,meson-a1-reset.h | 76 ---------- .../reset/amlogic,meson-axg-audio-arb.h | 19 --- .../dt-bindings/reset/amlogic,meson-axg-reset.h | 123 --------------- .../reset/amlogic,meson-g12a-audio-reset.h | 53 ------- .../dt-bindings/reset/amlogic,meson-g12a-reset.h | 137 ----------------- .../dt-bindings/reset/amlogic,meson-gxbb-reset.h | 161 -------------------- include/dt-bindings/reset/axg-aoclkc.h | 20 --- include/dt-bindings/reset/g12a-aoclkc.h | 18 --- include/dt-bindings/reset/gxbb-aoclkc.h | 66 -------- include/dt-bindings/sound/meson-aiu.h | 18 --- include/dt-bindings/sound/meson-g12a-toacodec.h | 10 -- include/dt-bindings/sound/meson-g12a-tohdmitx.h | 13 -- 31 files changed, 2212 deletions(-)

diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h deleted file mode 100644 index 06f198ee7623..000000000000 --- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu jian.hu@amlogic.com - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov ddrokosov@sberdevices.ru - */ - -#ifndef __A1_PERIPHERALS_CLKC_H -#define __A1_PERIPHERALS_CLKC_H - -#define CLKID_XTAL_IN 0 -#define CLKID_FIXPLL_IN 1 -#define CLKID_USB_PHY_IN 2 -#define CLKID_USB_CTRL_IN 3 -#define CLKID_HIFIPLL_IN 4 -#define CLKID_SYSPLL_IN 5 -#define CLKID_DDS_IN 6 -#define CLKID_SYS 7 -#define CLKID_CLKTREE 8 -#define CLKID_RESET_CTRL 9 -#define CLKID_ANALOG_CTRL 10 -#define CLKID_PWR_CTRL 11 -#define CLKID_PAD_CTRL 12 -#define CLKID_SYS_CTRL 13 -#define CLKID_TEMP_SENSOR 14 -#define CLKID_AM2AXI_DIV 15 -#define CLKID_SPICC_B 16 -#define CLKID_SPICC_A 17 -#define CLKID_MSR 18 -#define CLKID_AUDIO 19 -#define CLKID_JTAG_CTRL 20 -#define CLKID_SARADC_EN 21 -#define CLKID_PWM_EF 22 -#define CLKID_PWM_CD 23 -#define CLKID_PWM_AB 24 -#define CLKID_CEC 25 -#define CLKID_I2C_S 26 -#define CLKID_IR_CTRL 27 -#define CLKID_I2C_M_D 28 -#define CLKID_I2C_M_C 29 -#define CLKID_I2C_M_B 30 -#define CLKID_I2C_M_A 31 -#define CLKID_ACODEC 32 -#define CLKID_OTP 33 -#define CLKID_SD_EMMC_A 34 -#define CLKID_USB_PHY 35 -#define CLKID_USB_CTRL 36 -#define CLKID_SYS_DSPB 37 -#define CLKID_SYS_DSPA 38 -#define CLKID_DMA 39 -#define CLKID_IRQ_CTRL 40 -#define CLKID_NIC 41 -#define CLKID_GIC 42 -#define CLKID_UART_C 43 -#define CLKID_UART_B 44 -#define CLKID_UART_A 45 -#define CLKID_SYS_PSRAM 46 -#define CLKID_RSA 47 -#define CLKID_CORESIGHT 48 -#define CLKID_AM2AXI_VAD 49 -#define CLKID_AUDIO_VAD 50 -#define CLKID_AXI_DMC 51 -#define CLKID_AXI_PSRAM 52 -#define CLKID_RAMB 53 -#define CLKID_RAMA 54 -#define CLKID_AXI_SPIFC 55 -#define CLKID_AXI_NIC 56 -#define CLKID_AXI_DMA 57 -#define CLKID_CPU_CTRL 58 -#define CLKID_ROM 59 -#define CLKID_PROC_I2C 60 -#define CLKID_DSPA_SEL 61 -#define CLKID_DSPB_SEL 62 -#define CLKID_DSPA_EN 63 -#define CLKID_DSPA_EN_NIC 64 -#define CLKID_DSPB_EN 65 -#define CLKID_DSPB_EN_NIC 66 -#define CLKID_RTC 67 -#define CLKID_CECA_32K 68 -#define CLKID_CECB_32K 69 -#define CLKID_24M 70 -#define CLKID_12M 71 -#define CLKID_FCLK_DIV2_DIVN 72 -#define CLKID_GEN 73 -#define CLKID_SARADC_SEL 74 -#define CLKID_SARADC 75 -#define CLKID_PWM_A 76 -#define CLKID_PWM_B 77 -#define CLKID_PWM_C 78 -#define CLKID_PWM_D 79 -#define CLKID_PWM_E 80 -#define CLKID_PWM_F 81 -#define CLKID_SPICC 82 -#define CLKID_TS 83 -#define CLKID_SPIFC 84 -#define CLKID_USB_BUS 85 -#define CLKID_SD_EMMC 86 -#define CLKID_PSRAM 87 -#define CLKID_DMC 88 -#define CLKID_SYS_A_SEL 89 -#define CLKID_SYS_A_DIV 90 -#define CLKID_SYS_A 91 -#define CLKID_SYS_B_SEL 92 -#define CLKID_SYS_B_DIV 93 -#define CLKID_SYS_B 94 -#define CLKID_DSPA_A_SEL 95 -#define CLKID_DSPA_A_DIV 96 -#define CLKID_DSPA_A 97 -#define CLKID_DSPA_B_SEL 98 -#define CLKID_DSPA_B_DIV 99 -#define CLKID_DSPA_B 100 -#define CLKID_DSPB_A_SEL 101 -#define CLKID_DSPB_A_DIV 102 -#define CLKID_DSPB_A 103 -#define CLKID_DSPB_B_SEL 104 -#define CLKID_DSPB_B_DIV 105 -#define CLKID_DSPB_B 106 -#define CLKID_RTC_32K_IN 107 -#define CLKID_RTC_32K_DIV 108 -#define CLKID_RTC_32K_XTAL 109 -#define CLKID_RTC_32K_SEL 110 -#define CLKID_CECB_32K_IN 111 -#define CLKID_CECB_32K_DIV 112 -#define CLKID_CECB_32K_SEL_PRE 113 -#define CLKID_CECB_32K_SEL 114 -#define CLKID_CECA_32K_IN 115 -#define CLKID_CECA_32K_DIV 116 -#define CLKID_CECA_32K_SEL_PRE 117 -#define CLKID_CECA_32K_SEL 118 -#define CLKID_DIV2_PRE 119 -#define CLKID_24M_DIV2 120 -#define CLKID_GEN_SEL 121 -#define CLKID_GEN_DIV 122 -#define CLKID_SARADC_DIV 123 -#define CLKID_PWM_A_SEL 124 -#define CLKID_PWM_A_DIV 125 -#define CLKID_PWM_B_SEL 126 -#define CLKID_PWM_B_DIV 127 -#define CLKID_PWM_C_SEL 128 -#define CLKID_PWM_C_DIV 129 -#define CLKID_PWM_D_SEL 130 -#define CLKID_PWM_D_DIV 131 -#define CLKID_PWM_E_SEL 132 -#define CLKID_PWM_E_DIV 133 -#define CLKID_PWM_F_SEL 134 -#define CLKID_PWM_F_DIV 135 -#define CLKID_SPICC_SEL 136 -#define CLKID_SPICC_DIV 137 -#define CLKID_SPICC_SEL2 138 -#define CLKID_TS_DIV 139 -#define CLKID_SPIFC_SEL 140 -#define CLKID_SPIFC_DIV 141 -#define CLKID_SPIFC_SEL2 142 -#define CLKID_USB_BUS_SEL 143 -#define CLKID_USB_BUS_DIV 144 -#define CLKID_SD_EMMC_SEL 145 -#define CLKID_SD_EMMC_DIV 146 -#define CLKID_SD_EMMC_SEL2 147 -#define CLKID_PSRAM_SEL 148 -#define CLKID_PSRAM_DIV 149 -#define CLKID_PSRAM_SEL2 150 -#define CLKID_DMC_SEL 151 -#define CLKID_DMC_DIV 152 -#define CLKID_DMC_SEL2 153 - -#endif /* __A1_PERIPHERALS_CLKC_H */ diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h deleted file mode 100644 index 2b660c0f2c9f..000000000000 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu jian.hu@amlogic.com - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov ddrokosov@sberdevices.ru - */ - -#ifndef __A1_PLL_CLKC_H -#define __A1_PLL_CLKC_H - -#define CLKID_FIXED_PLL_DCO 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2_DIV 2 -#define CLKID_FCLK_DIV3_DIV 3 -#define CLKID_FCLK_DIV5_DIV 4 -#define CLKID_FCLK_DIV7_DIV 5 -#define CLKID_FCLK_DIV2 6 -#define CLKID_FCLK_DIV3 7 -#define CLKID_FCLK_DIV5 8 -#define CLKID_FCLK_DIV7 9 -#define CLKID_HIFI_PLL 10 - -#endif /* __A1_PLL_CLKC_H */ diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h deleted file mode 100644 index 8ec4a269c7a6..000000000000 --- a/include/dt-bindings/clock/axg-aoclkc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai qiufang.dai@amlogic.com - */ - -#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK -#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK - -#define CLKID_AO_REMOTE 0 -#define CLKID_AO_I2C_MASTER 1 -#define CLKID_AO_I2C_SLAVE 2 -#define CLKID_AO_UART1 3 -#define CLKID_AO_UART2 4 -#define CLKID_AO_IR_BLASTER 5 -#define CLKID_AO_SAR_ADC 6 -#define CLKID_AO_CLK81 7 -#define CLKID_AO_SAR_ADC_SEL 8 -#define CLKID_AO_SAR_ADC_DIV 9 -#define CLKID_AO_SAR_ADC_CLK 10 -#define CLKID_AO_CTS_OSCIN 11 -#define CLKID_AO_32K_PRE 12 -#define CLKID_AO_32K_DIV 13 -#define CLKID_AO_32K_SEL 14 -#define CLKID_AO_32K 15 -#define CLKID_AO_CTS_RTC_OSCIN 16 - -#endif diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h deleted file mode 100644 index f561f5c5ef8f..000000000000 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet jbrunet@baylibre.com - */ - -#ifndef __AXG_AUDIO_CLKC_BINDINGS_H -#define __AXG_AUDIO_CLKC_BINDINGS_H - -#define AUD_CLKID_DDR_ARB 29 -#define AUD_CLKID_PDM 30 -#define AUD_CLKID_TDMIN_A 31 -#define AUD_CLKID_TDMIN_B 32 -#define AUD_CLKID_TDMIN_C 33 -#define AUD_CLKID_TDMIN_LB 34 -#define AUD_CLKID_TDMOUT_A 35 -#define AUD_CLKID_TDMOUT_B 36 -#define AUD_CLKID_TDMOUT_C 37 -#define AUD_CLKID_FRDDR_A 38 -#define AUD_CLKID_FRDDR_B 39 -#define AUD_CLKID_FRDDR_C 40 -#define AUD_CLKID_TODDR_A 41 -#define AUD_CLKID_TODDR_B 42 -#define AUD_CLKID_TODDR_C 43 -#define AUD_CLKID_LOOPBACK 44 -#define AUD_CLKID_SPDIFIN 45 -#define AUD_CLKID_SPDIFOUT 46 -#define AUD_CLKID_RESAMPLE 47 -#define AUD_CLKID_POWER_DETECT 48 -#define AUD_CLKID_MST_A_MCLK 49 -#define AUD_CLKID_MST_B_MCLK 50 -#define AUD_CLKID_MST_C_MCLK 51 -#define AUD_CLKID_MST_D_MCLK 52 -#define AUD_CLKID_MST_E_MCLK 53 -#define AUD_CLKID_MST_F_MCLK 54 -#define AUD_CLKID_SPDIFOUT_CLK 55 -#define AUD_CLKID_SPDIFIN_CLK 56 -#define AUD_CLKID_PDM_DCLK 57 -#define AUD_CLKID_PDM_SYSCLK 58 -#define AUD_CLKID_MST_A_SCLK 79 -#define AUD_CLKID_MST_B_SCLK 80 -#define AUD_CLKID_MST_C_SCLK 81 -#define AUD_CLKID_MST_D_SCLK 82 -#define AUD_CLKID_MST_E_SCLK 83 -#define AUD_CLKID_MST_F_SCLK 84 -#define AUD_CLKID_MST_A_LRCLK 86 -#define AUD_CLKID_MST_B_LRCLK 87 -#define AUD_CLKID_MST_C_LRCLK 88 -#define AUD_CLKID_MST_D_LRCLK 89 -#define AUD_CLKID_MST_E_LRCLK 90 -#define AUD_CLKID_MST_F_LRCLK 91 -#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 -#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 -#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 -#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 -#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 -#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 -#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 -#define AUD_CLKID_TDMIN_A_SCLK 123 -#define AUD_CLKID_TDMIN_B_SCLK 124 -#define AUD_CLKID_TDMIN_C_SCLK 125 -#define AUD_CLKID_TDMIN_LB_SCLK 126 -#define AUD_CLKID_TDMOUT_A_SCLK 127 -#define AUD_CLKID_TDMOUT_B_SCLK 128 -#define AUD_CLKID_TDMOUT_C_SCLK 129 -#define AUD_CLKID_TDMIN_A_LRCLK 130 -#define AUD_CLKID_TDMIN_B_LRCLK 131 -#define AUD_CLKID_TDMIN_C_LRCLK 132 -#define AUD_CLKID_TDMIN_LB_LRCLK 133 -#define AUD_CLKID_TDMOUT_A_LRCLK 134 -#define AUD_CLKID_TDMOUT_B_LRCLK 135 -#define AUD_CLKID_TDMOUT_C_LRCLK 136 -#define AUD_CLKID_SPDIFOUT_B 151 -#define AUD_CLKID_SPDIFOUT_B_CLK 152 -#define AUD_CLKID_TDM_MCLK_PAD0 155 -#define AUD_CLKID_TDM_MCLK_PAD1 156 -#define AUD_CLKID_TDM_LRCLK_PAD0 157 -#define AUD_CLKID_TDM_LRCLK_PAD1 158 -#define AUD_CLKID_TDM_LRCLK_PAD2 159 -#define AUD_CLKID_TDM_SCLK_PAD0 160 -#define AUD_CLKID_TDM_SCLK_PAD1 161 -#define AUD_CLKID_TDM_SCLK_PAD2 162 -#define AUD_CLKID_TOP 163 -#define AUD_CLKID_TORAM 164 -#define AUD_CLKID_EQDRC 165 -#define AUD_CLKID_RESAMPLE_B 166 -#define AUD_CLKID_TOVAD 167 -#define AUD_CLKID_LOCKER 168 -#define AUD_CLKID_SPDIFIN_LB 169 -#define AUD_CLKID_FRDDR_D 170 -#define AUD_CLKID_TODDR_D 171 -#define AUD_CLKID_LOOPBACK_B 172 - -#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h deleted file mode 100644 index 93752ea107e3..000000000000 --- a/include/dt-bindings/clock/axg-clkc.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Meson-AXG clock tree IDs - * - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -#ifndef __AXG_CLKC_H -#define __AXG_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2 2 -#define CLKID_FCLK_DIV3 3 -#define CLKID_FCLK_DIV4 4 -#define CLKID_FCLK_DIV5 5 -#define CLKID_FCLK_DIV7 6 -#define CLKID_GP0_PLL 7 -#define CLKID_CLK81 10 -#define CLKID_MPLL0 11 -#define CLKID_MPLL1 12 -#define CLKID_MPLL2 13 -#define CLKID_MPLL3 14 -#define CLKID_DDR 15 -#define CLKID_AUDIO_LOCKER 16 -#define CLKID_MIPI_DSI_HOST 17 -#define CLKID_ISA 18 -#define CLKID_PL301 19 -#define CLKID_PERIPHS 20 -#define CLKID_SPICC0 21 -#define CLKID_I2C 22 -#define CLKID_RNG0 23 -#define CLKID_UART0 24 -#define CLKID_MIPI_DSI_PHY 25 -#define CLKID_SPICC1 26 -#define CLKID_PCIE_A 27 -#define CLKID_PCIE_B 28 -#define CLKID_HIU_IFACE 29 -#define CLKID_ASSIST_MISC 30 -#define CLKID_SD_EMMC_B 31 -#define CLKID_SD_EMMC_C 32 -#define CLKID_DMA 33 -#define CLKID_SPI 34 -#define CLKID_AUDIO 35 -#define CLKID_ETH 36 -#define CLKID_UART1 37 -#define CLKID_G2D 38 -#define CLKID_USB0 39 -#define CLKID_USB1 40 -#define CLKID_RESET 41 -#define CLKID_USB 42 -#define CLKID_AHB_ARB0 43 -#define CLKID_EFUSE 44 -#define CLKID_BOOT_ROM 45 -#define CLKID_AHB_DATA_BUS 46 -#define CLKID_AHB_CTRL_BUS 47 -#define CLKID_USB1_DDR_BRIDGE 48 -#define CLKID_USB0_DDR_BRIDGE 49 -#define CLKID_MMC_PCLK 50 -#define CLKID_VPU_INTR 51 -#define CLKID_SEC_AHB_AHB3_BRIDGE 52 -#define CLKID_GIC 53 -#define CLKID_AO_MEDIA_CPU 54 -#define CLKID_AO_AHB_SRAM 55 -#define CLKID_AO_AHB_BUS 56 -#define CLKID_AO_IFACE 57 -#define CLKID_AO_I2C 58 -#define CLKID_SD_EMMC_B_CLK0 59 -#define CLKID_SD_EMMC_C_CLK0 60 -#define CLKID_HIFI_PLL 69 -#define CLKID_PCIE_CML_EN0 79 -#define CLKID_PCIE_CML_EN1 80 -#define CLKID_GEN_CLK 84 -#define CLKID_VPU_0_SEL 92 -#define CLKID_VPU_0 93 -#define CLKID_VPU_1_SEL 95 -#define CLKID_VPU_1 96 -#define CLKID_VPU 97 -#define CLKID_VAPB_0_SEL 99 -#define CLKID_VAPB_0 100 -#define CLKID_VAPB_1_SEL 102 -#define CLKID_VAPB_1 103 -#define CLKID_VAPB_SEL 104 -#define CLKID_VAPB 105 -#define CLKID_VCLK 106 -#define CLKID_VCLK2 107 -#define CLKID_VCLK_DIV1 122 -#define CLKID_VCLK_DIV2 123 -#define CLKID_VCLK_DIV4 124 -#define CLKID_VCLK_DIV6 125 -#define CLKID_VCLK_DIV12 126 -#define CLKID_VCLK2_DIV1 127 -#define CLKID_VCLK2_DIV2 128 -#define CLKID_VCLK2_DIV4 129 -#define CLKID_VCLK2_DIV6 130 -#define CLKID_VCLK2_DIV12 131 -#define CLKID_CTS_ENCL 133 -#define CLKID_VDIN_MEAS 136 - -#endif /* __AXG_CLKC_H */ diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h deleted file mode 100644 index e916e49ff288..000000000000 --- a/include/dt-bindings/clock/g12a-aoclkc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai qiufang.dai@amlogic.com - */ - -#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK -#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK - -#define CLKID_AO_AHB 0 -#define CLKID_AO_IR_IN 1 -#define CLKID_AO_I2C_M0 2 -#define CLKID_AO_I2C_S0 3 -#define CLKID_AO_UART 4 -#define CLKID_AO_PROD_I2C 5 -#define CLKID_AO_UART2 6 -#define CLKID_AO_IR_OUT 7 -#define CLKID_AO_SAR_ADC 8 -#define CLKID_AO_MAILBOX 9 -#define CLKID_AO_M3 10 -#define CLKID_AO_AHB_SRAM 11 -#define CLKID_AO_RTI 12 -#define CLKID_AO_M4_FCLK 13 -#define CLKID_AO_M4_HCLK 14 -#define CLKID_AO_CLK81 15 -#define CLKID_AO_SAR_ADC_SEL 16 -#define CLKID_AO_SAR_ADC_CLK 18 -#define CLKID_AO_CTS_OSCIN 19 -#define CLKID_AO_32K 23 -#define CLKID_AO_CEC 27 -#define CLKID_AO_CTS_RTC_OSCIN 28 - -#endif diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h deleted file mode 100644 index a93b58c5e18e..000000000000 --- a/include/dt-bindings/clock/g12a-clkc.h +++ /dev/null @@ -1,153 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Meson-G12A clock tree IDs - * - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#ifndef __G12A_CLKC_H -#define __G12A_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2 2 -#define CLKID_FCLK_DIV3 3 -#define CLKID_FCLK_DIV4 4 -#define CLKID_FCLK_DIV5 5 -#define CLKID_FCLK_DIV7 6 -#define CLKID_GP0_PLL 7 -#define CLKID_CLK81 10 -#define CLKID_MPLL0 11 -#define CLKID_MPLL1 12 -#define CLKID_MPLL2 13 -#define CLKID_MPLL3 14 -#define CLKID_DDR 15 -#define CLKID_DOS 16 -#define CLKID_AUDIO_LOCKER 17 -#define CLKID_MIPI_DSI_HOST 18 -#define CLKID_ETH_PHY 19 -#define CLKID_ISA 20 -#define CLKID_PL301 21 -#define CLKID_PERIPHS 22 -#define CLKID_SPICC0 23 -#define CLKID_I2C 24 -#define CLKID_SANA 25 -#define CLKID_SD 26 -#define CLKID_RNG0 27 -#define CLKID_UART0 28 -#define CLKID_SPICC1 29 -#define CLKID_HIU_IFACE 30 -#define CLKID_MIPI_DSI_PHY 31 -#define CLKID_ASSIST_MISC 32 -#define CLKID_SD_EMMC_A 33 -#define CLKID_SD_EMMC_B 34 -#define CLKID_SD_EMMC_C 35 -#define CLKID_AUDIO_CODEC 36 -#define CLKID_AUDIO 37 -#define CLKID_ETH 38 -#define CLKID_DEMUX 39 -#define CLKID_AUDIO_IFIFO 40 -#define CLKID_ADC 41 -#define CLKID_UART1 42 -#define CLKID_G2D 43 -#define CLKID_RESET 44 -#define CLKID_PCIE_COMB 45 -#define CLKID_PARSER 46 -#define CLKID_USB 47 -#define CLKID_PCIE_PHY 48 -#define CLKID_AHB_ARB0 49 -#define CLKID_AHB_DATA_BUS 50 -#define CLKID_AHB_CTRL_BUS 51 -#define CLKID_HTX_HDCP22 52 -#define CLKID_HTX_PCLK 53 -#define CLKID_BT656 54 -#define CLKID_USB1_DDR_BRIDGE 55 -#define CLKID_MMC_PCLK 56 -#define CLKID_UART2 57 -#define CLKID_VPU_INTR 58 -#define CLKID_GIC 59 -#define CLKID_SD_EMMC_A_CLK0 60 -#define CLKID_SD_EMMC_B_CLK0 61 -#define CLKID_SD_EMMC_C_CLK0 62 -#define CLKID_HIFI_PLL 74 -#define CLKID_VCLK2_VENCI0 80 -#define CLKID_VCLK2_VENCI1 81 -#define CLKID_VCLK2_VENCP0 82 -#define CLKID_VCLK2_VENCP1 83 -#define CLKID_VCLK2_VENCT0 84 -#define CLKID_VCLK2_VENCT1 85 -#define CLKID_VCLK2_OTHER 86 -#define CLKID_VCLK2_ENCI 87 -#define CLKID_VCLK2_ENCP 88 -#define CLKID_DAC_CLK 89 -#define CLKID_AOCLK 90 -#define CLKID_IEC958 91 -#define CLKID_ENC480P 92 -#define CLKID_RNG1 93 -#define CLKID_VCLK2_ENCT 94 -#define CLKID_VCLK2_ENCL 95 -#define CLKID_VCLK2_VENCLMMC 96 -#define CLKID_VCLK2_VENCL 97 -#define CLKID_VCLK2_OTHER1 98 -#define CLKID_FCLK_DIV2P5 99 -#define CLKID_DMA 105 -#define CLKID_EFUSE 106 -#define CLKID_ROM_BOOT 107 -#define CLKID_RESET_SEC 108 -#define CLKID_SEC_AHB_APB3 109 -#define CLKID_VPU_0_SEL 110 -#define CLKID_VPU_0 112 -#define CLKID_VPU_1_SEL 113 -#define CLKID_VPU_1 115 -#define CLKID_VPU 116 -#define CLKID_VAPB_0_SEL 117 -#define CLKID_VAPB_0 119 -#define CLKID_VAPB_1_SEL 120 -#define CLKID_VAPB_1 122 -#define CLKID_VAPB_SEL 123 -#define CLKID_VAPB 124 -#define CLKID_HDMI_PLL 128 -#define CLKID_VID_PLL 129 -#define CLKID_VCLK 138 -#define CLKID_VCLK2 139 -#define CLKID_VCLK_DIV1 148 -#define CLKID_VCLK_DIV2 149 -#define CLKID_VCLK_DIV4 150 -#define CLKID_VCLK_DIV6 151 -#define CLKID_VCLK_DIV12 152 -#define CLKID_VCLK2_DIV1 153 -#define CLKID_VCLK2_DIV2 154 -#define CLKID_VCLK2_DIV4 155 -#define CLKID_VCLK2_DIV6 156 -#define CLKID_VCLK2_DIV12 157 -#define CLKID_CTS_ENCI 162 -#define CLKID_CTS_ENCP 163 -#define CLKID_CTS_VDAC 164 -#define CLKID_HDMI_TX 165 -#define CLKID_HDMI 168 -#define CLKID_MALI_0_SEL 169 -#define CLKID_MALI_0 171 -#define CLKID_MALI_1_SEL 172 -#define CLKID_MALI_1 174 -#define CLKID_MALI 175 -#define CLKID_MPLL_50M 177 -#define CLKID_CPU_CLK 187 -#define CLKID_PCIE_PLL 201 -#define CLKID_VDEC_1 204 -#define CLKID_VDEC_HEVC 207 -#define CLKID_VDEC_HEVCF 210 -#define CLKID_TS 212 -#define CLKID_CPUB_CLK 224 -#define CLKID_GP1_PLL 243 -#define CLKID_DSU_CLK 252 -#define CLKID_CPU1_CLK 253 -#define CLKID_CPU2_CLK 254 -#define CLKID_CPU3_CLK 255 -#define CLKID_SPICC0_SCLK 258 -#define CLKID_SPICC1_SCLK 261 -#define CLKID_NNA_AXI_CLK 264 -#define CLKID_NNA_CORE_CLK 267 -#define CLKID_MIPI_DSI_PXCLK_SEL 269 -#define CLKID_MIPI_DSI_PXCLK 270 - -#endif /* __G12A_CLKC_H */ diff --git a/include/dt-bindings/clock/gxbb-aoclkc.h b/include/dt-bindings/clock/gxbb-aoclkc.h deleted file mode 100644 index ec3b26319fc4..000000000000 --- a/include/dt-bindings/clock/gxbb-aoclkc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is provided under a dual BSD/GPLv2 license. When using or - * redistributing this file, you may do so under either license. - * - * GPL LICENSE SUMMARY - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see http://www.gnu.org/licenses/. - * The full GNU General Public License is included in this distribution - * in the file called COPYING. - * - * BSD LICENSE - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK -#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK - -#define CLKID_AO_REMOTE 0 -#define CLKID_AO_I2C_MASTER 1 -#define CLKID_AO_I2C_SLAVE 2 -#define CLKID_AO_UART1 3 -#define CLKID_AO_UART2 4 -#define CLKID_AO_IR_BLASTER 5 -#define CLKID_AO_CEC_32K 6 -#define CLKID_AO_CTS_OSCIN 7 -#define CLKID_AO_32K_PRE 8 -#define CLKID_AO_32K_DIV 9 -#define CLKID_AO_32K_SEL 10 -#define CLKID_AO_32K 11 -#define CLKID_AO_CTS_RTC_OSCIN 12 -#define CLKID_AO_CLK81 13 - -#endif diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h deleted file mode 100644 index 4073eb7a9da1..000000000000 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ /dev/null @@ -1,151 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * GXBB clock tree IDs - */ - -#ifndef __GXBB_CLKC_H -#define __GXBB_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_HDMI_PLL 2 -#define CLKID_FIXED_PLL 3 -#define CLKID_FCLK_DIV2 4 -#define CLKID_FCLK_DIV3 5 -#define CLKID_FCLK_DIV4 6 -#define CLKID_FCLK_DIV5 7 -#define CLKID_FCLK_DIV7 8 -#define CLKID_GP0_PLL 9 -#define CLKID_CLK81 12 -#define CLKID_MPLL0 13 -#define CLKID_MPLL1 14 -#define CLKID_MPLL2 15 -#define CLKID_DDR 16 -#define CLKID_DOS 17 -#define CLKID_ISA 18 -#define CLKID_PL301 19 -#define CLKID_PERIPHS 20 -#define CLKID_SPICC 21 -#define CLKID_I2C 22 -#define CLKID_SAR_ADC 23 -#define CLKID_SMART_CARD 24 -#define CLKID_RNG0 25 -#define CLKID_UART0 26 -#define CLKID_SDHC 27 -#define CLKID_STREAM 28 -#define CLKID_ASYNC_FIFO 29 -#define CLKID_SDIO 30 -#define CLKID_ABUF 31 -#define CLKID_HIU_IFACE 32 -#define CLKID_ASSIST_MISC 33 -#define CLKID_SPI 34 -#define CLKID_ETH 36 -#define CLKID_I2S_SPDIF 35 -#define CLKID_DEMUX 37 -#define CLKID_AIU_GLUE 38 -#define CLKID_IEC958 39 -#define CLKID_I2S_OUT 40 -#define CLKID_AMCLK 41 -#define CLKID_AIFIFO2 42 -#define CLKID_MIXER 43 -#define CLKID_MIXER_IFACE 44 -#define CLKID_ADC 45 -#define CLKID_BLKMV 46 -#define CLKID_AIU 47 -#define CLKID_UART1 48 -#define CLKID_G2D 49 -#define CLKID_USB0 50 -#define CLKID_USB1 51 -#define CLKID_RESET 52 -#define CLKID_NAND 53 -#define CLKID_DOS_PARSER 54 -#define CLKID_USB 55 -#define CLKID_VDIN1 56 -#define CLKID_AHB_ARB0 57 -#define CLKID_EFUSE 58 -#define CLKID_BOOT_ROM 59 -#define CLKID_AHB_DATA_BUS 60 -#define CLKID_AHB_CTRL_BUS 61 -#define CLKID_HDMI_INTR_SYNC 62 -#define CLKID_HDMI_PCLK 63 -#define CLKID_USB1_DDR_BRIDGE 64 -#define CLKID_USB0_DDR_BRIDGE 65 -#define CLKID_MMC_PCLK 66 -#define CLKID_DVIN 67 -#define CLKID_UART2 68 -#define CLKID_SANA 69 -#define CLKID_VPU_INTR 70 -#define CLKID_SEC_AHB_AHB3_BRIDGE 71 -#define CLKID_CLK81_A53 72 -#define CLKID_VCLK2_VENCI0 73 -#define CLKID_VCLK2_VENCI1 74 -#define CLKID_VCLK2_VENCP0 75 -#define CLKID_VCLK2_VENCP1 76 -#define CLKID_GCLK_VENCI_INT0 77 -#define CLKID_GCLK_VENCI_INT 78 -#define CLKID_DAC_CLK 79 -#define CLKID_AOCLK_GATE 80 -#define CLKID_IEC958_GATE 81 -#define CLKID_ENC480P 82 -#define CLKID_RNG1 83 -#define CLKID_GCLK_VENCI_INT1 84 -#define CLKID_VCLK2_VENCLMCC 85 -#define CLKID_VCLK2_VENCL 86 -#define CLKID_VCLK_OTHER 87 -#define CLKID_EDP 88 -#define CLKID_AO_MEDIA_CPU 89 -#define CLKID_AO_AHB_SRAM 90 -#define CLKID_AO_AHB_BUS 91 -#define CLKID_AO_IFACE 92 -#define CLKID_AO_I2C 93 -#define CLKID_SD_EMMC_A 94 -#define CLKID_SD_EMMC_B 95 -#define CLKID_SD_EMMC_C 96 -#define CLKID_SAR_ADC_CLK 97 -#define CLKID_SAR_ADC_SEL 98 -#define CLKID_MALI_0_SEL 100 -#define CLKID_MALI_0 102 -#define CLKID_MALI_1_SEL 103 -#define CLKID_MALI_1 105 -#define CLKID_MALI 106 -#define CLKID_CTS_AMCLK 107 -#define CLKID_CTS_MCLK_I958 110 -#define CLKID_CTS_I958 113 -#define CLKID_32K_CLK 114 -#define CLKID_SD_EMMC_A_CLK0 119 -#define CLKID_SD_EMMC_B_CLK0 122 -#define CLKID_SD_EMMC_C_CLK0 125 -#define CLKID_VPU_0_SEL 126 -#define CLKID_VPU_0 128 -#define CLKID_VPU_1_SEL 129 -#define CLKID_VPU_1 131 -#define CLKID_VPU 132 -#define CLKID_VAPB_0_SEL 133 -#define CLKID_VAPB_0 135 -#define CLKID_VAPB_1_SEL 136 -#define CLKID_VAPB_1 138 -#define CLKID_VAPB_SEL 139 -#define CLKID_VAPB 140 -#define CLKID_VDEC_1 153 -#define CLKID_VDEC_HEVC 156 -#define CLKID_GEN_CLK 159 -#define CLKID_VID_PLL 166 -#define CLKID_VCLK 175 -#define CLKID_VCLK2 176 -#define CLKID_VCLK_DIV1 185 -#define CLKID_VCLK_DIV2 186 -#define CLKID_VCLK_DIV4 187 -#define CLKID_VCLK_DIV6 188 -#define CLKID_VCLK_DIV12 189 -#define CLKID_VCLK2_DIV1 190 -#define CLKID_VCLK2_DIV2 191 -#define CLKID_VCLK2_DIV4 192 -#define CLKID_VCLK2_DIV6 193 -#define CLKID_VCLK2_DIV12 194 -#define CLKID_CTS_ENCI 199 -#define CLKID_CTS_ENCP 200 -#define CLKID_CTS_VDAC 201 -#define CLKID_HDMI_TX 202 -#define CLKID_HDMI 205 -#define CLKID_ACODEC 206 - -#endif /* __GXBB_CLKC_H */ diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h deleted file mode 100644 index 40e57a5ff1db..000000000000 --- a/include/dt-bindings/gpio/meson-a1-gpio.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Qianggui Song qianggui.song@amlogic.com - */ - -#ifndef _DT_BINDINGS_MESON_A1_GPIO_H -#define _DT_BINDINGS_MESON_A1_GPIO_H - -#define GPIOP_0 0 -#define GPIOP_1 1 -#define GPIOP_2 2 -#define GPIOP_3 3 -#define GPIOP_4 4 -#define GPIOP_5 5 -#define GPIOP_6 6 -#define GPIOP_7 7 -#define GPIOP_8 8 -#define GPIOP_9 9 -#define GPIOP_10 10 -#define GPIOP_11 11 -#define GPIOP_12 12 -#define GPIOB_0 13 -#define GPIOB_1 14 -#define GPIOB_2 15 -#define GPIOB_3 16 -#define GPIOB_4 17 -#define GPIOB_5 18 -#define GPIOB_6 19 -#define GPIOX_0 20 -#define GPIOX_1 21 -#define GPIOX_2 22 -#define GPIOX_3 23 -#define GPIOX_4 24 -#define GPIOX_5 25 -#define GPIOX_6 26 -#define GPIOX_7 27 -#define GPIOX_8 28 -#define GPIOX_9 29 -#define GPIOX_10 30 -#define GPIOX_11 31 -#define GPIOX_12 32 -#define GPIOX_13 33 -#define GPIOX_14 34 -#define GPIOX_15 35 -#define GPIOX_16 36 -#define GPIOF_0 37 -#define GPIOF_1 38 -#define GPIOF_2 39 -#define GPIOF_3 40 -#define GPIOF_4 41 -#define GPIOF_5 42 -#define GPIOF_6 43 -#define GPIOF_7 44 -#define GPIOF_8 45 -#define GPIOF_9 46 -#define GPIOF_10 47 -#define GPIOF_11 48 -#define GPIOF_12 49 -#define GPIOA_0 50 -#define GPIOA_1 51 -#define GPIOA_2 52 -#define GPIOA_3 53 -#define GPIOA_4 54 -#define GPIOA_5 55 -#define GPIOA_6 56 -#define GPIOA_7 57 -#define GPIOA_8 58 -#define GPIOA_9 59 -#define GPIOA_10 60 -#define GPIOA_11 61 - -#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h deleted file mode 100644 index 25bb1fffa97a..000000000000 --- a/include/dt-bindings/gpio/meson-axg-gpio.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen xingyu.chen@amlogic.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H -#define _DT_BINDINGS_MESON_AXG_GPIO_H - -/* First GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_TEST_N 14 - -/* Second GPIO chip */ -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define BOOT_0 11 -#define BOOT_1 12 -#define BOOT_2 13 -#define BOOT_3 14 -#define BOOT_4 15 -#define BOOT_5 16 -#define BOOT_6 17 -#define BOOT_7 18 -#define BOOT_8 19 -#define BOOT_9 20 -#define BOOT_10 21 -#define BOOT_11 22 -#define BOOT_12 23 -#define BOOT_13 24 -#define BOOT_14 25 -#define GPIOA_0 26 -#define GPIOA_1 27 -#define GPIOA_2 28 -#define GPIOA_3 29 -#define GPIOA_4 30 -#define GPIOA_5 31 -#define GPIOA_6 32 -#define GPIOA_7 33 -#define GPIOA_8 34 -#define GPIOA_9 35 -#define GPIOA_10 36 -#define GPIOA_11 37 -#define GPIOA_12 38 -#define GPIOA_13 39 -#define GPIOA_14 40 -#define GPIOA_15 41 -#define GPIOA_16 42 -#define GPIOA_17 43 -#define GPIOA_18 44 -#define GPIOA_19 45 -#define GPIOA_20 46 -#define GPIOX_0 47 -#define GPIOX_1 48 -#define GPIOX_2 49 -#define GPIOX_3 50 -#define GPIOX_4 51 -#define GPIOX_5 52 -#define GPIOX_6 53 -#define GPIOX_7 54 -#define GPIOX_8 55 -#define GPIOX_9 56 -#define GPIOX_10 57 -#define GPIOX_11 58 -#define GPIOX_12 59 -#define GPIOX_13 60 -#define GPIOX_14 61 -#define GPIOX_15 62 -#define GPIOX_16 63 -#define GPIOX_17 64 -#define GPIOX_18 65 -#define GPIOX_19 66 -#define GPIOX_20 67 -#define GPIOX_21 68 -#define GPIOX_22 69 -#define GPIOY_0 70 -#define GPIOY_1 71 -#define GPIOY_2 72 -#define GPIOY_3 73 -#define GPIOY_4 74 -#define GPIOY_5 75 -#define GPIOY_6 76 -#define GPIOY_7 77 -#define GPIOY_8 78 -#define GPIOY_9 79 -#define GPIOY_10 80 -#define GPIOY_11 81 -#define GPIOY_12 82 -#define GPIOY_13 83 -#define GPIOY_14 84 -#define GPIOY_15 85 - -#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h deleted file mode 100644 index f7bd69350d18..000000000000 --- a/include/dt-bindings/gpio/meson-g12a-gpio.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen xingyu.chen@amlogic.com - */ - -#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H -#define _DT_BINDINGS_MESON_G12A_GPIO_H - -/* First GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOE_0 12 -#define GPIOE_1 13 -#define GPIOE_2 14 - -/* Second GPIO chip */ -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define GPIOH_4 20 -#define GPIOH_5 21 -#define GPIOH_6 22 -#define GPIOH_7 23 -#define GPIOH_8 24 -#define BOOT_0 25 -#define BOOT_1 26 -#define BOOT_2 27 -#define BOOT_3 28 -#define BOOT_4 29 -#define BOOT_5 30 -#define BOOT_6 31 -#define BOOT_7 32 -#define BOOT_8 33 -#define BOOT_9 34 -#define BOOT_10 35 -#define BOOT_11 36 -#define BOOT_12 37 -#define BOOT_13 38 -#define BOOT_14 39 -#define BOOT_15 40 -#define GPIOC_0 41 -#define GPIOC_1 42 -#define GPIOC_2 43 -#define GPIOC_3 44 -#define GPIOC_4 45 -#define GPIOC_5 46 -#define GPIOC_6 47 -#define GPIOC_7 48 -#define GPIOA_0 49 -#define GPIOA_1 50 -#define GPIOA_2 51 -#define GPIOA_3 52 -#define GPIOA_4 53 -#define GPIOA_5 54 -#define GPIOA_6 55 -#define GPIOA_7 56 -#define GPIOA_8 57 -#define GPIOA_9 58 -#define GPIOA_10 59 -#define GPIOA_11 60 -#define GPIOA_12 61 -#define GPIOA_13 62 -#define GPIOA_14 63 -#define GPIOA_15 64 -#define GPIOX_0 65 -#define GPIOX_1 66 -#define GPIOX_2 67 -#define GPIOX_3 68 -#define GPIOX_4 69 -#define GPIOX_5 70 -#define GPIOX_6 71 -#define GPIOX_7 72 -#define GPIOX_8 73 -#define GPIOX_9 74 -#define GPIOX_10 75 -#define GPIOX_11 76 -#define GPIOX_12 77 -#define GPIOX_13 78 -#define GPIOX_14 79 -#define GPIOX_15 80 -#define GPIOX_16 81 -#define GPIOX_17 82 -#define GPIOX_18 83 -#define GPIOX_19 84 - -#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h deleted file mode 100644 index 489c75b27645..000000000000 --- a/include/dt-bindings/gpio/meson-gxbb-gpio.h +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson GXBB SoCs - * - * Copyright (C) 2016 Endless Mobile, Inc. - * Author: Carlo Caione carlo@endlessm.com - */ - -#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H -#define _DT_BINDINGS_MESON_GXBB_GPIO_H - -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_TEST_N 14 - -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define BOOT_0 20 -#define BOOT_1 21 -#define BOOT_2 22 -#define BOOT_3 23 -#define BOOT_4 24 -#define BOOT_5 25 -#define BOOT_6 26 -#define BOOT_7 27 -#define BOOT_8 28 -#define BOOT_9 29 -#define BOOT_10 30 -#define BOOT_11 31 -#define BOOT_12 32 -#define BOOT_13 33 -#define BOOT_14 34 -#define BOOT_15 35 -#define BOOT_16 36 -#define BOOT_17 37 -#define CARD_0 38 -#define CARD_1 39 -#define CARD_2 40 -#define CARD_3 41 -#define CARD_4 42 -#define CARD_5 43 -#define CARD_6 44 -#define GPIODV_0 45 -#define GPIODV_1 46 -#define GPIODV_2 47 -#define GPIODV_3 48 -#define GPIODV_4 49 -#define GPIODV_5 50 -#define GPIODV_6 51 -#define GPIODV_7 52 -#define GPIODV_8 53 -#define GPIODV_9 54 -#define GPIODV_10 55 -#define GPIODV_11 56 -#define GPIODV_12 57 -#define GPIODV_13 58 -#define GPIODV_14 59 -#define GPIODV_15 60 -#define GPIODV_16 61 -#define GPIODV_17 62 -#define GPIODV_18 63 -#define GPIODV_19 64 -#define GPIODV_20 65 -#define GPIODV_21 66 -#define GPIODV_22 67 -#define GPIODV_23 68 -#define GPIODV_24 69 -#define GPIODV_25 70 -#define GPIODV_26 71 -#define GPIODV_27 72 -#define GPIODV_28 73 -#define GPIODV_29 74 -#define GPIOY_0 75 -#define GPIOY_1 76 -#define GPIOY_2 77 -#define GPIOY_3 78 -#define GPIOY_4 79 -#define GPIOY_5 80 -#define GPIOY_6 81 -#define GPIOY_7 82 -#define GPIOY_8 83 -#define GPIOY_9 84 -#define GPIOY_10 85 -#define GPIOY_11 86 -#define GPIOY_12 87 -#define GPIOY_13 88 -#define GPIOY_14 89 -#define GPIOY_15 90 -#define GPIOY_16 91 -#define GPIOX_0 92 -#define GPIOX_1 93 -#define GPIOX_2 94 -#define GPIOX_3 95 -#define GPIOX_4 96 -#define GPIOX_5 97 -#define GPIOX_6 98 -#define GPIOX_7 99 -#define GPIOX_8 100 -#define GPIOX_9 101 -#define GPIOX_10 102 -#define GPIOX_11 103 -#define GPIOX_12 104 -#define GPIOX_13 105 -#define GPIOX_14 106 -#define GPIOX_15 107 -#define GPIOX_16 108 -#define GPIOX_17 109 -#define GPIOX_18 110 -#define GPIOX_19 111 -#define GPIOX_20 112 -#define GPIOX_21 113 -#define GPIOX_22 114 -#define GPIOCLK_0 115 -#define GPIOCLK_1 116 -#define GPIOCLK_2 117 -#define GPIOCLK_3 118 - -#endif diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h deleted file mode 100644 index 0a001ae48272..000000000000 --- a/include/dt-bindings/gpio/meson-gxl-gpio.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson GXL SoCs - * - * Copyright (C) 2016 Endless Mobile, Inc. - * Author: Carlo Caione carlo@endlessm.com - */ - -#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H -#define _DT_BINDINGS_MESON_GXL_GPIO_H - -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIO_TEST_N 10 - -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define GPIOH_4 20 -#define GPIOH_5 21 -#define GPIOH_6 22 -#define GPIOH_7 23 -#define GPIOH_8 24 -#define GPIOH_9 25 -#define BOOT_0 26 -#define BOOT_1 27 -#define BOOT_2 28 -#define BOOT_3 29 -#define BOOT_4 30 -#define BOOT_5 31 -#define BOOT_6 32 -#define BOOT_7 33 -#define BOOT_8 34 -#define BOOT_9 35 -#define BOOT_10 36 -#define BOOT_11 37 -#define BOOT_12 38 -#define BOOT_13 39 -#define BOOT_14 40 -#define BOOT_15 41 -#define CARD_0 42 -#define CARD_1 43 -#define CARD_2 44 -#define CARD_3 45 -#define CARD_4 46 -#define CARD_5 47 -#define CARD_6 48 -#define GPIODV_0 49 -#define GPIODV_1 50 -#define GPIODV_2 51 -#define GPIODV_3 52 -#define GPIODV_4 53 -#define GPIODV_5 54 -#define GPIODV_6 55 -#define GPIODV_7 56 -#define GPIODV_8 57 -#define GPIODV_9 58 -#define GPIODV_10 59 -#define GPIODV_11 60 -#define GPIODV_12 61 -#define GPIODV_13 62 -#define GPIODV_14 63 -#define GPIODV_15 64 -#define GPIODV_16 65 -#define GPIODV_17 66 -#define GPIODV_18 67 -#define GPIODV_19 68 -#define GPIODV_20 69 -#define GPIODV_21 70 -#define GPIODV_22 71 -#define GPIODV_23 72 -#define GPIODV_24 73 -#define GPIODV_25 74 -#define GPIODV_26 75 -#define GPIODV_27 76 -#define GPIODV_28 77 -#define GPIODV_29 78 -#define GPIOX_0 79 -#define GPIOX_1 80 -#define GPIOX_2 81 -#define GPIOX_3 82 -#define GPIOX_4 83 -#define GPIOX_5 84 -#define GPIOX_6 85 -#define GPIOX_7 86 -#define GPIOX_8 87 -#define GPIOX_9 88 -#define GPIOX_10 89 -#define GPIOX_11 90 -#define GPIOX_12 91 -#define GPIOX_13 92 -#define GPIOX_14 93 -#define GPIOX_15 94 -#define GPIOX_16 95 -#define GPIOX_17 96 -#define GPIOX_18 97 -#define GPIOCLK_0 98 -#define GPIOCLK_1 99 - -#endif diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h deleted file mode 100644 index 8e39dfc0b62a..000000000000 --- a/include/dt-bindings/power/meson-a1-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2023 SberDevices, Inc. - * Author: Alexey Romanov avromanov@sberdevices.ru - */ - -#ifndef _DT_BINDINGS_MESON_A1_POWER_H -#define _DT_BINDINGS_MESON_A1_POWER_H - -#define PWRC_DSPA_ID 8 -#define PWRC_DSPB_ID 9 -#define PWRC_UART_ID 10 -#define PWRC_DMC_ID 11 -#define PWRC_I2C_ID 12 -#define PWRC_PSRAM_ID 13 -#define PWRC_ACODEC_ID 14 -#define PWRC_AUDIO_ID 15 -#define PWRC_OTP_ID 16 -#define PWRC_DMA_ID 17 -#define PWRC_SD_EMMC_ID 18 -#define PWRC_RAMA_ID 19 -#define PWRC_RAMB_ID 20 -#define PWRC_IR_ID 21 -#define PWRC_SPICC_ID 22 -#define PWRC_SPIFC_ID 23 -#define PWRC_USB_ID 24 -#define PWRC_NIC_ID 25 -#define PWRC_PDMIN_ID 26 -#define PWRC_RSA_ID 27 -#define PWRC_MAX_ID 28 - -#endif diff --git a/include/dt-bindings/power/meson-axg-power.h b/include/dt-bindings/power/meson-axg-power.h deleted file mode 100644 index e5243884b249..000000000000 --- a/include/dt-bindings/power/meson-axg-power.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2020 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - */ - -#ifndef _DT_BINDINGS_MESON_AXG_POWER_H -#define _DT_BINDINGS_MESON_AXG_POWER_H - -#define PWRC_AXG_VPU_ID 0 -#define PWRC_AXG_ETHERNET_MEM_ID 1 -#define PWRC_AXG_AUDIO_ID 2 - -#endif diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h deleted file mode 100644 index bb5e67a842de..000000000000 --- a/include/dt-bindings/power/meson-g12a-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - */ - -#ifndef _DT_BINDINGS_MESON_G12A_POWER_H -#define _DT_BINDINGS_MESON_G12A_POWER_H - -#define PWRC_G12A_VPU_ID 0 -#define PWRC_G12A_ETH_ID 1 - -#endif diff --git a/include/dt-bindings/power/meson-gxbb-power.h b/include/dt-bindings/power/meson-gxbb-power.h deleted file mode 100644 index 1262dac696c0..000000000000 --- a/include/dt-bindings/power/meson-gxbb-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - */ - -#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H -#define _DT_BINDINGS_MESON_GXBB_POWER_H - -#define PWRC_GXBB_VPU_ID 0 -#define PWRC_GXBB_ETHERNET_MEM_ID 1 - -#endif diff --git a/include/dt-bindings/power/meson-sm1-power.h b/include/dt-bindings/power/meson-sm1-power.h deleted file mode 100644 index a020ab00c134..000000000000 --- a/include/dt-bindings/power/meson-sm1-power.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - */ - -#ifndef _DT_BINDINGS_MESON_SM1_POWER_H -#define _DT_BINDINGS_MESON_SM1_POWER_H - -#define PWRC_SM1_VPU_ID 0 -#define PWRC_SM1_NNA_ID 1 -#define PWRC_SM1_USB_ID 2 -#define PWRC_SM1_PCIE_ID 3 -#define PWRC_SM1_GE2D_ID 4 -#define PWRC_SM1_AUDIO_ID 5 -#define PWRC_SM1_ETH_ID 6 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h deleted file mode 100644 index 2c749c655e1e..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-a1-reset.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen xingyu.chen@amlogic.com - * - * Copyright (c) 2023, SberDevices, Inc. - * Author: Alexey Romanov avromanov@salutedevices.com - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H - -/* RESET0 */ -/* 0 */ -#define RESET_AM2AXI_VAD 1 -/* 2-3 */ -#define RESET_PSRAM 4 -#define RESET_PAD_CTRL 5 -/* 6 */ -#define RESET_TEMP_SENSOR 7 -#define RESET_AM2AXI_DEV 8 -/* 9 */ -#define RESET_SPICC_A 10 -#define RESET_MSR_CLK 11 -#define RESET_AUDIO 12 -#define RESET_ANALOG_CTRL 13 -#define RESET_SAR_ADC 14 -#define RESET_AUDIO_VAD 15 -#define RESET_CEC 16 -#define RESET_PWM_EF 17 -#define RESET_PWM_CD 18 -#define RESET_PWM_AB 19 -/* 20 */ -#define RESET_IR_CTRL 21 -#define RESET_I2C_S_A 22 -/* 23 */ -#define RESET_I2C_M_D 24 -#define RESET_I2C_M_C 25 -#define RESET_I2C_M_B 26 -#define RESET_I2C_M_A 27 -#define RESET_I2C_PROD_AHB 28 -#define RESET_I2C_PROD 29 -/* 30-31 */ - -/* RESET1 */ -#define RESET_ACODEC 32 -#define RESET_DMA 33 -#define RESET_SD_EMMC_A 34 -/* 35 */ -#define RESET_USBCTRL 36 -/* 37 */ -#define RESET_USBPHY 38 -/* 39-41 */ -#define RESET_RSA 42 -#define RESET_DMC 43 -/* 44 */ -#define RESET_IRQ_CTRL 45 -/* 46 */ -#define RESET_NIC_VAD 47 -#define RESET_NIC_AXI 48 -#define RESET_RAMA 49 -#define RESET_RAMB 50 -/* 51-52 */ -#define RESET_ROM 53 -#define RESET_SPIFC 54 -#define RESET_GIC 55 -#define RESET_UART_C 56 -#define RESET_UART_B 57 -#define RESET_UART_A 58 -#define RESET_OSC_RING 59 -/* 60-63 */ - -/* RESET2 */ -/* 64-95 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h deleted file mode 100644 index 1ef807856cb8..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) - * - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet jbrunet@baylibre.com - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H - -#define AXG_ARB_TODDR_A 0 -#define AXG_ARB_TODDR_B 1 -#define AXG_ARB_TODDR_C 2 -#define AXG_ARB_FRDDR_A 3 -#define AXG_ARB_FRDDR_B 4 -#define AXG_ARB_FRDDR_C 5 -#define AXG_ARB_TODDR_D 6 -#define AXG_ARB_FRDDR_D 7 - -#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h deleted file mode 100644 index 0f2e0fe45ca4..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Copyright (c) 2017 Amlogic, inc. - * Author: Yixun Lan yixun.lan@amlogic.com - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -#define RESET_PCIE_A 1 -#define RESET_PCIE_B 2 -#define RESET_DDR_TOP 3 -/* 4 */ -#define RESET_VIU 5 -#define RESET_PCIE_PHY 6 -#define RESET_PCIE_APB 7 -/* 8 */ -/* 9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -/* 12 */ -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18-21 */ -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -/* 28-31 */ -/* RESET1 */ -/* 32 */ -/* 33 */ -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -/* 37 */ -#define RESET_AHB_SRAM 38 -/* 39 */ -/* 40 */ -#define RESET_DMA 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -/* 44 */ -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -/* 61-63 */ -/* RESET2 */ -/* 64 */ -/* 65 */ -#define RESET_AUDIO 66 -/* 67 */ -#define RESET_MIPI_HOST 68 -#define RESET_AUDIO_LOCKER 69 -#define RESET_GE2D 70 -/* 71-76 */ -#define RESET_AO_CPU_RESET 77 -/* 78-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -/* 97-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -#define RESET_MIPI_PHY 130 -/* 131-140 */ -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -/* 194 */ -/* 195 */ -#define RESET_PERIPHS_I2C_MASTER_0 196 -/* 197-200 */ -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1 202 -/* 203-204 */ -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_I2C_MASTER_3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -#define RESET_DMC_VPU_PIPEL 233 -/* 234-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h deleted file mode 100644 index f805129ca7af..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet jbrunet@baylibre.com - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H - -#define AUD_RESET_PDM 0 -#define AUD_RESET_TDMIN_A 1 -#define AUD_RESET_TDMIN_B 2 -#define AUD_RESET_TDMIN_C 3 -#define AUD_RESET_TDMIN_LB 4 -#define AUD_RESET_LOOPBACK 5 -#define AUD_RESET_TODDR_A 6 -#define AUD_RESET_TODDR_B 7 -#define AUD_RESET_TODDR_C 8 -#define AUD_RESET_FRDDR_A 9 -#define AUD_RESET_FRDDR_B 10 -#define AUD_RESET_FRDDR_C 11 -#define AUD_RESET_TDMOUT_A 12 -#define AUD_RESET_TDMOUT_B 13 -#define AUD_RESET_TDMOUT_C 14 -#define AUD_RESET_SPDIFOUT 15 -#define AUD_RESET_SPDIFOUT_B 16 -#define AUD_RESET_SPDIFIN 17 -#define AUD_RESET_EQDRC 18 -#define AUD_RESET_RESAMPLE 19 -#define AUD_RESET_DDRARB 20 -#define AUD_RESET_POWDET 21 -#define AUD_RESET_TORAM 22 -#define AUD_RESET_TOACODEC 23 -#define AUD_RESET_TOHDMITX 24 -#define AUD_RESET_CLKTREE 25 - -/* SM1 added resets */ -#define AUD_RESET_RESAMPLE_B 26 -#define AUD_RESET_TOVAD 27 -#define AUD_RESET_LOCKER 28 -#define AUD_RESET_SPDIFIN_LB 29 -#define AUD_RESET_FRATV 30 -#define AUD_RESET_FRHDMIRX 31 -#define AUD_RESET_FRDDR_D 32 -#define AUD_RESET_TODDR_D 33 -#define AUD_RESET_LOOPBACK_B 34 -#define AUD_RESET_EARCTX 35 -#define AUD_RESET_EARCRX 36 -#define AUD_RESET_FRDDR_E 37 -#define AUD_RESET_TODDR_E 38 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h deleted file mode 100644 index 6d487c5eba2c..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet jbrunet@baylibre.com - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS 2 -/* 3-4 */ -#define RESET_VIU 5 -#define RESET_AFIFO 6 -#define RESET_VID_PLL_DIV 7 -/* 8-9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_PCIE_CTRL_A 12 -#define RESET_VCBUS 13 -#define RESET_PCIE_PHY 14 -#define RESET_PCIE_APB 15 -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18 */ -#define RESET_HDMITX_CAPB3 19 -#define RESET_DVALIN_CAPB3 20 -#define RESET_DOS_CAPB3 21 -/* 22 */ -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -/* 27-31 */ -/* RESET1 */ -/* 32 */ -#define RESET_DEMUX 33 -#define RESET_USB 34 -#define RESET_DDR 35 -/* 36 */ -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -/* 41 */ -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -/* 47 */ -#define RESET_USB_PHY20 48 -#define RESET_USB_PHY21 49 -/* 50-60 */ -#define RESET_AUDIO_CODEC 61 -/* 62-63 */ -/* RESET2 */ -/* 64 */ -#define RESET_AUDIO 65 -#define RESET_HDMITX_PHY 66 -/* 67 */ -#define RESET_MIPI_DSI_HOST 68 -#define RESET_ALOCKER 69 -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75-77 */ -#define RESET_DVALIN 78 -#define RESET_HDMITX 79 -/* 80-95 */ -/* RESET3 */ -/* 96-95 */ -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES_PL 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_0 109 -#define RESET_DEMUX_1 110 -#define RESET_DEMUX_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128-129 */ -#define RESET_MIPI_DSI_PHY 130 -/* 131-132 */ -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -/* 138-139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_M1 142 -#define RESET_I2C_M2 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_GEN 192 -#define RESET_SPICC0 193 -#define RESET_SC 194 -#define RESET_SANA_3 195 -#define RESET_I2C_M0 196 -#define RESET_TS_PLL 197 -#define RESET_SPICC1 198 -#define RESET_STREAM 199 -#define RESET_TS_CPU 200 -#define RESET_UART0 201 -#define RESET_UART1_2 202 -#define RESET_ASYNC0 203 -#define RESET_ASYNC1 204 -#define RESET_SPIFC0 205 -#define RESET_I2C_M3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -#define RESET_TS_GPU 228 -#define RESET_DEVICE_MMC_ARB 229 -#define RESET_DVALIN_DMC_PIPL 230 -#define RESET_VID_LOCK 231 -#define RESET_NIC_DMC_PIPL 232 -#define RESET_DMC_VPU_PIPL 233 -#define RESET_GE2D_DMC_PIPL 234 -#define RESET_HCODEC_DMC_PIPL 235 -#define RESET_WAVE420_DMC_PIPL 236 -#define RESET_HEVCF_DMC_PIPL 237 -/* 238-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h deleted file mode 100644 index 883bfd3bcbad..000000000000 --- a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - */ -#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS_RESET 2 -#define RESET_DDR_TOP 3 -#define RESET_DCU_RESET 4 -#define RESET_VIU 5 -#define RESET_AIU 6 -#define RESET_VID_PLL_DIV 7 -/* 8 */ -#define RESET_PMUX 9 -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_AFIFO2 12 -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -#define RESET_NAND_CAPB3 18 -#define RESET_HDMITX_CAPB3 19 -#define RESET_MALI_CAPB3 20 -#define RESET_DOS_CAPB3 21 -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -#define RESET_MIPI_0 28 -#define RESET_MIPI_1 29 -#define RESET_MIPI_2 30 -#define RESET_MIPI_3 31 -/* RESET1 */ -#define RESET_CPPM 32 -#define RESET_DEMUX 33 -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -#define RESET_BLKMV 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -#define RESET_ACODEC 61 -/* 62 */ -/* 63 */ -/* RESET2 */ -#define RESET_VD_RMEM 64 -#define RESET_AUDIN 65 -#define RESET_HDMI_TX 66 -/* 67 */ -/* 68 */ -/* 69 */ -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_PARSER_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75 */ -/* 76 */ -#define RESET_AO_CPU_RESET 77 -#define RESET_MALI 78 -#define RESET_HDMI_SYSTEM_RESET 79 -/* 80-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -#define RESET_SYS_CPU 97 -#define RESET_EFUSE 98 -#define RESET_SYS_CPU_BVCI 99 -#define RESET_AIFIFO 100 -#define RESET_TVFE 101 -#define RESET_AHB_BRIDGE_CNTL 102 -/* 103 */ -#define RESET_AUDIO_DAC 104 -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_RESET_0 109 -#define RESET_DEMUX_RESET_1 110 -#define RESET_DEMUX_RESET_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -/* 130 */ -/* 131 */ -#define RESET_DVIN_RESET 132 -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -#define RESET_RTC 138 -/* 139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -#define RESET_PERIPHS_SMART_CARD 194 -#define RESET_PERIPHS_SAR_ADC 195 -#define RESET_PERIPHS_I2C_MASTER_0 196 -#define RESET_SANA 197 -/* 198 */ -#define RESET_PERIPHS_STREAM_INTERFACE 199 -#define RESET_PERIPHS_SDIO 200 -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1_2 202 -#define RESET_PERIPHS_ASYNC_0 203 -#define RESET_PERIPHS_ASYNC_1 204 -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_SDHC 206 -#define RESET_UART_SLIP 207 -/* 208-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -/* 233-255 */ - -#endif diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h deleted file mode 100644 index d342c0b6b2a7..000000000000 --- a/include/dt-bindings/reset/axg-aoclkc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai qiufang.dai@amlogic.com - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK - -#define RESET_AO_REMOTE 0 -#define RESET_AO_I2C_MASTER 1 -#define RESET_AO_I2C_SLAVE 2 -#define RESET_AO_UART1 3 -#define RESET_AO_UART2 4 -#define RESET_AO_IR_BLASTER 5 - -#endif diff --git a/include/dt-bindings/reset/g12a-aoclkc.h b/include/dt-bindings/reset/g12a-aoclkc.h deleted file mode 100644 index bd2e2337135c..000000000000 --- a/include/dt-bindings/reset/g12a-aoclkc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong narmstrong@baylibre.com - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK - -#define RESET_AO_IR_IN 0 -#define RESET_AO_UART 1 -#define RESET_AO_I2C_M 2 -#define RESET_AO_I2C_S 3 -#define RESET_AO_SAR_ADC 4 -#define RESET_AO_UART2 5 -#define RESET_AO_IR_OUT 6 - -#endif diff --git a/include/dt-bindings/reset/gxbb-aoclkc.h b/include/dt-bindings/reset/gxbb-aoclkc.h deleted file mode 100644 index 9e3fd60c309c..000000000000 --- a/include/dt-bindings/reset/gxbb-aoclkc.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is provided under a dual BSD/GPLv2 license. When using or - * redistributing this file, you may do so under either license. - * - * GPL LICENSE SUMMARY - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see http://www.gnu.org/licenses/. - * The full GNU General Public License is included in this distribution - * in the file called COPYING. - * - * BSD LICENSE - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong narmstrong@baylibre.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK - -#define RESET_AO_REMOTE 0 -#define RESET_AO_I2C_MASTER 1 -#define RESET_AO_I2C_SLAVE 2 -#define RESET_AO_UART1 3 -#define RESET_AO_UART2 4 -#define RESET_AO_IR_BLASTER 5 - -#endif diff --git a/include/dt-bindings/sound/meson-aiu.h b/include/dt-bindings/sound/meson-aiu.h deleted file mode 100644 index 1051b8af298b..000000000000 --- a/include/dt-bindings/sound/meson-aiu.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_AIU_H -#define __DT_MESON_AIU_H - -#define AIU_CPU 0 -#define AIU_HDMI 1 -#define AIU_ACODEC 2 - -#define CPU_I2S_FIFO 0 -#define CPU_SPDIF_FIFO 1 -#define CPU_I2S_ENCODER 2 -#define CPU_SPDIF_ENCODER 3 - -#define CTRL_I2S 0 -#define CTRL_PCM 1 -#define CTRL_OUT 2 - -#endif /* __DT_MESON_AIU_H */ diff --git a/include/dt-bindings/sound/meson-g12a-toacodec.h b/include/dt-bindings/sound/meson-g12a-toacodec.h deleted file mode 100644 index 69d7a75592a2..000000000000 --- a/include/dt-bindings/sound/meson-g12a-toacodec.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_G12A_TOACODEC_H -#define __DT_MESON_G12A_TOACODEC_H - -#define TOACODEC_IN_A 0 -#define TOACODEC_IN_B 1 -#define TOACODEC_IN_C 2 -#define TOACODEC_OUT 3 - -#endif /* __DT_MESON_G12A_TOACODEC_H */ diff --git a/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/include/dt-bindings/sound/meson-g12a-tohdmitx.h deleted file mode 100644 index c5e1f48d30d0..000000000000 --- a/include/dt-bindings/sound/meson-g12a-tohdmitx.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_G12A_TOHDMITX_H -#define __DT_MESON_G12A_TOHDMITX_H - -#define TOHDMITX_I2S_IN_A 0 -#define TOHDMITX_I2S_IN_B 1 -#define TOHDMITX_I2S_IN_C 2 -#define TOHDMITX_I2S_OUT 3 -#define TOHDMITX_SPDIF_IN_A 4 -#define TOHDMITX_SPDIF_IN_B 5 -#define TOHDMITX_SPDIF_OUT 6 - -#endif /* __DT_MESON_G12A_TOHDMITX_H */

Dropped in favour of dts/upstream

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/ste-ab8500.h | 12 - include/dt-bindings/clock/stih407-clks.h | 90 ------- include/dt-bindings/clock/stih410-clks.h | 25 -- include/dt-bindings/clock/stm32fx-clock.h | 63 ----- include/dt-bindings/clock/stm32h7-clks.h | 167 ------------- include/dt-bindings/clock/stm32mp1-clks.h | 274 --------------------- include/dt-bindings/clock/stm32mp13-clks.h | 229 ----------------- include/dt-bindings/mfd/st,stpmic1.h | 50 ---- include/dt-bindings/mfd/st-lpc.h | 16 -- include/dt-bindings/mfd/stm32f4-rcc.h | 108 -------- include/dt-bindings/mfd/stm32f7-rcc.h | 116 --------- include/dt-bindings/mfd/stm32h7-rcc.h | 138 ----------- include/dt-bindings/pinctrl/stm32-pinfunc.h | 45 ---- .../dt-bindings/regulator/st,stm32mp13-regulator.h | 42 ---- include/dt-bindings/reset/stih407-resets.h | 65 ----- include/dt-bindings/reset/stm32mp1-resets.h | 123 --------- include/dt-bindings/reset/stm32mp13-resets.h | 100 -------- 17 files changed, 1663 deletions(-)

diff --git a/include/dt-bindings/clock/ste-ab8500.h b/include/dt-bindings/clock/ste-ab8500.h deleted file mode 100644 index fb42dd0cab5f..000000000000 --- a/include/dt-bindings/clock/ste-ab8500.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __STE_CLK_AB8500_H__ -#define __STE_CLK_AB8500_H__ - -#define AB8500_SYSCLK_BUF2 0 -#define AB8500_SYSCLK_BUF3 1 -#define AB8500_SYSCLK_BUF4 2 -#define AB8500_SYSCLK_ULP 3 -#define AB8500_SYSCLK_INT 4 -#define AB8500_SYSCLK_AUDIO 5 - -#endif diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h deleted file mode 100644 index 082edd9badfa..000000000000 --- a/include/dt-bindings/clock/stih407-clks.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This header provides constants clk index STMicroelectronics - * STiH407 SoC. - */ -#ifndef _DT_BINDINGS_CLK_STIH407 -#define _DT_BINDINGS_CLK_STIH407 - -/* CLOCKGEN A0 */ -#define CLK_IC_LMI0 0 -#define CLK_IC_LMI1 1 - -/* CLOCKGEN C0 */ -#define CLK_ICN_GPU 0 -#define CLK_FDMA 1 -#define CLK_NAND 2 -#define CLK_HVA 3 -#define CLK_PROC_STFE 4 -#define CLK_PROC_TP 5 -#define CLK_RX_ICN_DMU 6 -#define CLK_RX_ICN_DISP_0 6 -#define CLK_RX_ICN_DISP_1 6 -#define CLK_RX_ICN_HVA 7 -#define CLK_RX_ICN_TS 7 -#define CLK_ICN_CPU 8 -#define CLK_TX_ICN_DMU 9 -#define CLK_TX_ICN_HVA 9 -#define CLK_TX_ICN_TS 9 -#define CLK_ICN_COMPO 9 -#define CLK_MMC_0 10 -#define CLK_MMC_1 11 -#define CLK_JPEGDEC 12 -#define CLK_ICN_REG 13 -#define CLK_TRACE_A9 13 -#define CLK_PTI_STM 13 -#define CLK_EXT2F_A9 13 -#define CLK_IC_BDISP_0 14 -#define CLK_IC_BDISP_1 15 -#define CLK_PP_DMU 16 -#define CLK_VID_DMU 17 -#define CLK_DSS_LPC 18 -#define CLK_ST231_AUD_0 19 -#define CLK_ST231_GP_0 19 -#define CLK_ST231_GP_1 20 -#define CLK_ST231_DMU 21 -#define CLK_ICN_LMI 22 -#define CLK_TX_ICN_DISP_0 23 -#define CLK_TX_ICN_DISP_1 23 -#define CLK_ICN_SBC 24 -#define CLK_STFE_FRC2 25 -#define CLK_ETH_PHY 26 -#define CLK_ETH_REF_PHYCLK 27 -#define CLK_FLASH_PROMIP 28 -#define CLK_MAIN_DISP 29 -#define CLK_AUX_DISP 30 -#define CLK_COMPO_DVP 31 - -/* CLOCKGEN D0 */ -#define CLK_PCM_0 0 -#define CLK_PCM_1 1 -#define CLK_PCM_2 2 -#define CLK_SPDIFF 3 - -/* CLOCKGEN D2 */ -#define CLK_PIX_MAIN_DISP 0 -#define CLK_PIX_PIP 1 -#define CLK_PIX_GDP1 2 -#define CLK_PIX_GDP2 3 -#define CLK_PIX_GDP3 4 -#define CLK_PIX_GDP4 5 -#define CLK_PIX_AUX_DISP 6 -#define CLK_DENC 7 -#define CLK_PIX_HDDAC 8 -#define CLK_HDDAC 9 -#define CLK_SDDAC 10 -#define CLK_PIX_DVO 11 -#define CLK_DVO 12 -#define CLK_PIX_HDMI 13 -#define CLK_TMDS_HDMI 14 -#define CLK_REF_HDMIPHY 15 - -/* CLOCKGEN D3 */ -#define CLK_STFE_FRC1 0 -#define CLK_TSOUT_0 1 -#define CLK_TSOUT_1 2 -#define CLK_MCHI 3 -#define CLK_VSENS_COMPO 4 -#define CLK_FRC1_REMOTE 5 -#define CLK_LPC_0 6 -#define CLK_LPC_1 7 -#endif diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h deleted file mode 100644 index 2097a4bbe155..000000000000 --- a/include/dt-bindings/clock/stih410-clks.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This header provides constants clk index STMicroelectronics - * STiH410 SoC. - */ -#ifndef _DT_BINDINGS_CLK_STIH410 -#define _DT_BINDINGS_CLK_STIH410 - -#include "stih407-clks.h" - -/* STiH410 introduces new clock outputs compared to STiH407 */ - -/* CLOCKGEN C0 */ -#define CLK_TX_ICN_HADES 32 -#define CLK_RX_ICN_HADES 33 -#define CLK_ICN_REG_16 34 -#define CLK_PP_HADES 35 -#define CLK_CLUST_HADES 36 -#define CLK_HWPE_HADES 37 -#define CLK_FC_HADES 38 - -/* CLOCKGEN D0 */ -#define CLK_PCMR10_MASTER 4 -#define CLK_USB2_PHY 5 - -#endif diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h deleted file mode 100644 index e5dad050d518..000000000000 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * stm32fx-clock.h - * - * Copyright (C) 2016 STMicroelectronics - * Author: Gabriel Fernandez for STMicroelectronics. - */ - -/* - * List of clocks which are not derived from system clock (SYSCLOCK) - * - * The index of these clocks is the secondary index of DT bindings - * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) - * - * e.g: - <assigned-clocks = <&rcc 1 CLK_LSE>; -*/ - -#ifndef _DT_BINDINGS_CLK_STMFX_H -#define _DT_BINDINGS_CLK_STMFX_H - -#define SYSTICK 0 -#define FCLK 1 -#define CLK_LSI 2 -#define CLK_LSE 3 -#define CLK_HSE_RTC 4 -#define CLK_RTC 5 -#define PLL_VCO_I2S 6 -#define PLL_VCO_SAI 7 -#define CLK_LCD 8 -#define CLK_I2S 9 -#define CLK_SAI1 10 -#define CLK_SAI2 11 -#define CLK_I2SQ_PDIV 12 -#define CLK_SAIQ_PDIV 13 -#define CLK_HSI 14 -#define CLK_SYSCLK 15 -#define CLK_F469_DSI 16 - -#define END_PRIMARY_CLK 17 - -#define CLK_HDMI_CEC 16 -#define CLK_SPDIF 17 -#define CLK_USART1 18 -#define CLK_USART2 19 -#define CLK_USART3 20 -#define CLK_UART4 21 -#define CLK_UART5 22 -#define CLK_USART6 23 -#define CLK_UART7 24 -#define CLK_UART8 25 -#define CLK_I2C1 26 -#define CLK_I2C2 27 -#define CLK_I2C3 28 -#define CLK_I2C4 29 -#define CLK_LPTIMER 30 -#define CLK_PLL_SRC 31 -#define CLK_DFSDM1 32 -#define CLK_ADFSDM1 33 -#define CLK_F769_DSI 34 -#define END_PRIMARY_CLK_F7 35 - -#endif diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h deleted file mode 100644 index 4d87e7ebc39b..000000000000 --- a/include/dt-bindings/clock/stm32h7-clks.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SYS, CORE AND BUS CLOCKS */ -#define SYS_D1CPRE 0 -#define HCLK 1 -#define PCLK1 2 -#define PCLK2 3 -#define PCLK3 4 -#define PCLK4 5 -#define HSI_DIV 6 -#define HSE_1M 7 -#define I2S_CKIN 8 -#define CK_DSI_PHY 9 -#define HSE_CK 10 -#define LSE_CK 11 -#define CSI_KER_DIV122 12 -#define RTC_CK 13 -#define CPU_SYSTICK 14 - -/* OSCILLATOR BANK */ -#define OSC_BANK 18 -#define HSI_CK 18 -#define HSI_KER_CK 19 -#define CSI_CK 20 -#define CSI_KER_CK 21 -#define RC48_CK 22 -#define LSI_CK 23 - -/* MCLOCK BANK */ -#define MCLK_BANK 28 -#define PER_CK 28 -#define PLLSRC 29 -#define SYS_CK 30 -#define TRACEIN_CK 31 - -/* ODF BANK */ -#define ODF_BANK 32 -#define PLL1_P 32 -#define PLL1_Q 33 -#define PLL1_R 34 -#define PLL2_P 35 -#define PLL2_Q 36 -#define PLL2_R 37 -#define PLL3_P 38 -#define PLL3_Q 39 -#define PLL3_R 40 - -/* MCO BANK */ -#define MCO_BANK 41 -#define MCO1 41 -#define MCO2 42 - -/* PERIF BANK */ -#define PERIF_BANK 50 -#define D1SRAM1_CK 50 -#define ITCM_CK 51 -#define DTCM2_CK 52 -#define DTCM1_CK 53 -#define FLITF_CK 54 -#define JPGDEC_CK 55 -#define DMA2D_CK 56 -#define MDMA_CK 57 -#define USB2ULPI_CK 58 -#define USB1ULPI_CK 59 -#define ETH1RX_CK 60 -#define ETH1TX_CK 61 -#define ETH1MAC_CK 62 -#define ART_CK 63 -#define DMA2_CK 64 -#define DMA1_CK 65 -#define D2SRAM3_CK 66 -#define D2SRAM2_CK 67 -#define D2SRAM1_CK 68 -#define HASH_CK 69 -#define CRYPT_CK 70 -#define CAMITF_CK 71 -#define BKPRAM_CK 72 -#define HSEM_CK 73 -#define BDMA_CK 74 -#define CRC_CK 75 -#define GPIOK_CK 76 -#define GPIOJ_CK 77 -#define GPIOI_CK 78 -#define GPIOH_CK 79 -#define GPIOG_CK 80 -#define GPIOF_CK 81 -#define GPIOE_CK 82 -#define GPIOD_CK 83 -#define GPIOC_CK 84 -#define GPIOB_CK 85 -#define GPIOA_CK 86 -#define WWDG1_CK 87 -#define DAC12_CK 88 -#define WWDG2_CK 89 -#define TIM14_CK 90 -#define TIM13_CK 91 -#define TIM12_CK 92 -#define TIM7_CK 93 -#define TIM6_CK 94 -#define TIM5_CK 95 -#define TIM4_CK 96 -#define TIM3_CK 97 -#define TIM2_CK 98 -#define MDIOS_CK 99 -#define OPAMP_CK 100 -#define CRS_CK 101 -#define TIM17_CK 102 -#define TIM16_CK 103 -#define TIM15_CK 104 -#define TIM8_CK 105 -#define TIM1_CK 106 -#define TMPSENS_CK 107 -#define RTCAPB_CK 108 -#define VREF_CK 109 -#define COMP12_CK 110 -#define SYSCFG_CK 111 -/* must be equal to last peripheral clock index */ -#define LAST_PERIF_BANK SYSCFG_CK - -/* KERNEL BANK */ -#define KERN_BANK 120 -#define SDMMC1_CK 120 -#define QUADSPI_CK 121 -#define FMC_CK 122 -#define USB2OTG_CK 123 -#define USB1OTG_CK 124 -#define ADC12_CK 125 -#define SDMMC2_CK 126 -#define RNG_CK 127 -#define ADC3_CK 128 -#define DSI_CK 129 -#define LTDC_CK 130 -#define USART8_CK 131 -#define USART7_CK 132 -#define HDMICEC_CK 133 -#define I2C3_CK 134 -#define I2C2_CK 135 -#define I2C1_CK 136 -#define UART5_CK 137 -#define UART4_CK 138 -#define USART3_CK 139 -#define USART2_CK 140 -#define SPDIFRX_CK 141 -#define SPI3_CK 142 -#define SPI2_CK 143 -#define LPTIM1_CK 144 -#define FDCAN_CK 145 -#define SWP_CK 146 -#define HRTIM_CK 147 -#define DFSDM1_CK 148 -#define SAI3_CK 149 -#define SAI2_CK 150 -#define SAI1_CK 151 -#define SPI5_CK 152 -#define SPI4_CK 153 -#define SPI1_CK 154 -#define USART6_CK 155 -#define USART1_CK 156 -#define SAI4B_CK 157 -#define SAI4A_CK 158 -#define LPTIM5_CK 159 -#define LPTIM4_CK 160 -#define LPTIM3_CK 161 -#define LPTIM2_CK 162 -#define I2C4_CK 163 -#define SPI6_CK 164 -#define LPUART1_CK 165 - -#define STM32H7_MAX_CLKS 166 diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h deleted file mode 100644 index 0a5324bcdbda..000000000000 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ /dev/null @@ -1,274 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez gabriel.fernandez@st.com for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ -#define _DT_BINDINGS_STM32MP1_CLKS_H_ - -/* OSCILLATOR clocks */ -#define CK_HSE 0 -#define CK_CSI 1 -#define CK_LSI 2 -#define CK_LSE 3 -#define CK_HSI 4 -#define CK_HSE_DIV2 5 - -/* Bus clocks */ -#define TIM2 6 -#define TIM3 7 -#define TIM4 8 -#define TIM5 9 -#define TIM6 10 -#define TIM7 11 -#define TIM12 12 -#define TIM13 13 -#define TIM14 14 -#define LPTIM1 15 -#define SPI2 16 -#define SPI3 17 -#define USART2 18 -#define USART3 19 -#define UART4 20 -#define UART5 21 -#define UART7 22 -#define UART8 23 -#define I2C1 24 -#define I2C2 25 -#define I2C3 26 -#define I2C5 27 -#define SPDIF 28 -#define CEC 29 -#define DAC12 30 -#define MDIO 31 -#define TIM1 32 -#define TIM8 33 -#define TIM15 34 -#define TIM16 35 -#define TIM17 36 -#define SPI1 37 -#define SPI4 38 -#define SPI5 39 -#define USART6 40 -#define SAI1 41 -#define SAI2 42 -#define SAI3 43 -#define DFSDM 44 -#define FDCAN 45 -#define LPTIM2 46 -#define LPTIM3 47 -#define LPTIM4 48 -#define LPTIM5 49 -#define SAI4 50 -#define SYSCFG 51 -#define VREF 52 -#define TMPSENS 53 -#define PMBCTRL 54 -#define HDP 55 -#define LTDC 56 -#define DSI 57 -#define IWDG2 58 -#define USBPHY 59 -#define STGENRO 60 -#define SPI6 61 -#define I2C4 62 -#define I2C6 63 -#define USART1 64 -#define RTCAPB 65 -#define TZC1 66 -#define TZPC 67 -#define IWDG1 68 -#define BSEC 69 -#define STGEN 70 -#define DMA1 71 -#define DMA2 72 -#define DMAMUX 73 -#define ADC12 74 -#define USBO 75 -#define SDMMC3 76 -#define DCMI 77 -#define CRYP2 78 -#define HASH2 79 -#define RNG2 80 -#define CRC2 81 -#define HSEM 82 -#define IPCC 83 -#define GPIOA 84 -#define GPIOB 85 -#define GPIOC 86 -#define GPIOD 87 -#define GPIOE 88 -#define GPIOF 89 -#define GPIOG 90 -#define GPIOH 91 -#define GPIOI 92 -#define GPIOJ 93 -#define GPIOK 94 -#define GPIOZ 95 -#define CRYP1 96 -#define HASH1 97 -#define RNG1 98 -#define BKPSRAM 99 -#define MDMA 100 -#define GPU 101 -#define ETHCK 102 -#define ETHTX 103 -#define ETHRX 104 -#define ETHMAC 105 -#define FMC 106 -#define QSPI 107 -#define SDMMC1 108 -#define SDMMC2 109 -#define CRC1 110 -#define USBH 111 -#define ETHSTP 112 -#define TZC2 113 - -/* Kernel clocks */ -#define SDMMC1_K 118 -#define SDMMC2_K 119 -#define SDMMC3_K 120 -#define FMC_K 121 -#define QSPI_K 122 -#define ETHCK_K 123 -#define RNG1_K 124 -#define RNG2_K 125 -#define GPU_K 126 -#define USBPHY_K 127 -#define STGEN_K 128 -#define SPDIF_K 129 -#define SPI1_K 130 -#define SPI2_K 131 -#define SPI3_K 132 -#define SPI4_K 133 -#define SPI5_K 134 -#define SPI6_K 135 -#define CEC_K 136 -#define I2C1_K 137 -#define I2C2_K 138 -#define I2C3_K 139 -#define I2C4_K 140 -#define I2C5_K 141 -#define I2C6_K 142 -#define LPTIM1_K 143 -#define LPTIM2_K 144 -#define LPTIM3_K 145 -#define LPTIM4_K 146 -#define LPTIM5_K 147 -#define USART1_K 148 -#define USART2_K 149 -#define USART3_K 150 -#define UART4_K 151 -#define UART5_K 152 -#define USART6_K 153 -#define UART7_K 154 -#define UART8_K 155 -#define DFSDM_K 156 -#define FDCAN_K 157 -#define SAI1_K 158 -#define SAI2_K 159 -#define SAI3_K 160 -#define SAI4_K 161 -#define ADC12_K 162 -#define DSI_K 163 -#define DSI_PX 164 -#define ADFSDM_K 165 -#define USBO_K 166 -#define LTDC_PX 167 -#define DAC12_K 168 -#define ETHPTP_K 169 - -/* PLL */ -#define PLL1 176 -#define PLL2 177 -#define PLL3 178 -#define PLL4 179 - -/* ODF */ -#define PLL1_P 180 -#define PLL1_Q 181 -#define PLL1_R 182 -#define PLL2_P 183 -#define PLL2_Q 184 -#define PLL2_R 185 -#define PLL3_P 186 -#define PLL3_Q 187 -#define PLL3_R 188 -#define PLL4_P 189 -#define PLL4_Q 190 -#define PLL4_R 191 - -/* AUX */ -#define RTC 192 - -/* MCLK */ -#define CK_PER 193 -#define CK_MPU 194 -#define CK_AXI 195 -#define CK_MCU 196 - -/* Time base */ -#define TIM2_K 197 -#define TIM3_K 198 -#define TIM4_K 199 -#define TIM5_K 200 -#define TIM6_K 201 -#define TIM7_K 202 -#define TIM12_K 203 -#define TIM13_K 204 -#define TIM14_K 205 -#define TIM1_K 206 -#define TIM8_K 207 -#define TIM15_K 208 -#define TIM16_K 209 -#define TIM17_K 210 - -/* MCO clocks */ -#define CK_MCO1 211 -#define CK_MCO2 212 - -/* TRACE & DEBUG clocks */ -#define CK_DBG 214 -#define CK_TRACE 215 - -/* DDR */ -#define DDRC1 220 -#define DDRC1LP 221 -#define DDRC2 222 -#define DDRC2LP 223 -#define DDRPHYC 224 -#define DDRPHYCLP 225 -#define DDRCAPB 226 -#define DDRCAPBLP 227 -#define AXIDCG 228 -#define DDRPHYCAPB 229 -#define DDRPHYCAPBLP 230 -#define DDRPERFM 231 - -#define STM32MP1_LAST_CLK 232 - -/* SCMI clock identifiers */ -#define CK_SCMI_HSE 0 -#define CK_SCMI_HSI 1 -#define CK_SCMI_CSI 2 -#define CK_SCMI_LSE 3 -#define CK_SCMI_LSI 4 -#define CK_SCMI_PLL2_Q 5 -#define CK_SCMI_PLL2_R 6 -#define CK_SCMI_MPU 7 -#define CK_SCMI_AXI 8 -#define CK_SCMI_BSEC 9 -#define CK_SCMI_CRYP1 10 -#define CK_SCMI_GPIOZ 11 -#define CK_SCMI_HASH1 12 -#define CK_SCMI_I2C4 13 -#define CK_SCMI_I2C6 14 -#define CK_SCMI_IWDG1 15 -#define CK_SCMI_RNG1 16 -#define CK_SCMI_RTC 17 -#define CK_SCMI_RTCAPB 18 -#define CK_SCMI_SPI6 19 -#define CK_SCMI_USART1 20 - -#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h deleted file mode 100644 index 0bd7b54c65ff..000000000000 --- a/include/dt-bindings/clock/stm32mp13-clks.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2020 - All Rights Reserved - * Author: Gabriel Fernandez gabriel.fernandez@foss.st.com for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_ -#define _DT_BINDINGS_STM32MP13_CLKS_H_ - -/* OSCILLATOR clocks */ -#define CK_HSE 0 -#define CK_CSI 1 -#define CK_LSI 2 -#define CK_LSE 3 -#define CK_HSI 4 -#define CK_HSE_DIV2 5 - -/* PLL */ -#define PLL1 6 -#define PLL2 7 -#define PLL3 8 -#define PLL4 9 - -/* ODF */ -#define PLL1_P 10 -#define PLL1_Q 11 -#define PLL1_R 12 -#define PLL2_P 13 -#define PLL2_Q 14 -#define PLL2_R 15 -#define PLL3_P 16 -#define PLL3_Q 17 -#define PLL3_R 18 -#define PLL4_P 19 -#define PLL4_Q 20 -#define PLL4_R 21 - -#define PCLK1 22 -#define PCLK2 23 -#define PCLK3 24 -#define PCLK4 25 -#define PCLK5 26 -#define PCLK6 27 - -/* SYSTEM CLOCK */ -#define CK_PER 28 -#define CK_MPU 29 -#define CK_AXI 30 -#define CK_MLAHB 31 - -/* BASE TIMER */ -#define CK_TIMG1 32 -#define CK_TIMG2 33 -#define CK_TIMG3 34 - -/* AUX */ -#define RTC 35 - -/* TRACE & DEBUG clocks */ -#define CK_DBG 36 -#define CK_TRACE 37 - -/* MCO clocks */ -#define CK_MCO1 38 -#define CK_MCO2 39 - -/* IP clocks */ -#define SYSCFG 40 -#define VREF 41 -#define DTS 42 -#define PMBCTRL 43 -#define HDP 44 -#define IWDG2 45 -#define STGENRO 46 -#define USART1 47 -#define RTCAPB 48 -#define TZC 49 -#define TZPC 50 -#define IWDG1 51 -#define BSEC 52 -#define DMA1 53 -#define DMA2 54 -#define DMAMUX1 55 -#define DMAMUX2 56 -#define GPIOA 57 -#define GPIOB 58 -#define GPIOC 59 -#define GPIOD 60 -#define GPIOE 61 -#define GPIOF 62 -#define GPIOG 63 -#define GPIOH 64 -#define GPIOI 65 -#define CRYP1 66 -#define HASH1 67 -#define BKPSRAM 68 -#define MDMA 69 -#define CRC1 70 -#define USBH 71 -#define DMA3 72 -#define TSC 73 -#define PKA 74 -#define AXIMC 75 -#define MCE 76 -#define ETH1TX 77 -#define ETH2TX 78 -#define ETH1RX 79 -#define ETH2RX 80 -#define ETH1MAC 81 -#define ETH2MAC 82 -#define ETH1STP 83 -#define ETH2STP 84 - -/* IP clocks with parents */ -#define SDMMC1_K 85 -#define SDMMC2_K 86 -#define ADC1_K 87 -#define ADC2_K 88 -#define FMC_K 89 -#define QSPI_K 90 -#define RNG1_K 91 -#define USBPHY_K 92 -#define STGEN_K 93 -#define SPDIF_K 94 -#define SPI1_K 95 -#define SPI2_K 96 -#define SPI3_K 97 -#define SPI4_K 98 -#define SPI5_K 99 -#define I2C1_K 100 -#define I2C2_K 101 -#define I2C3_K 102 -#define I2C4_K 103 -#define I2C5_K 104 -#define TIM2_K 105 -#define TIM3_K 106 -#define TIM4_K 107 -#define TIM5_K 108 -#define TIM6_K 109 -#define TIM7_K 110 -#define TIM12_K 111 -#define TIM13_K 112 -#define TIM14_K 113 -#define TIM1_K 114 -#define TIM8_K 115 -#define TIM15_K 116 -#define TIM16_K 117 -#define TIM17_K 118 -#define LPTIM1_K 119 -#define LPTIM2_K 120 -#define LPTIM3_K 121 -#define LPTIM4_K 122 -#define LPTIM5_K 123 -#define USART1_K 124 -#define USART2_K 125 -#define USART3_K 126 -#define UART4_K 127 -#define UART5_K 128 -#define USART6_K 129 -#define UART7_K 130 -#define UART8_K 131 -#define DFSDM_K 132 -#define FDCAN_K 133 -#define SAI1_K 134 -#define SAI2_K 135 -#define ADFSDM_K 136 -#define USBO_K 137 -#define LTDC_PX 138 -#define ETH1CK_K 139 -#define ETH1PTP_K 140 -#define ETH2CK_K 141 -#define ETH2PTP_K 142 -#define DCMIPP_K 143 -#define SAES_K 144 -#define DTS_K 145 - -/* DDR */ -#define DDRC1 146 -#define DDRC1LP 147 -#define DDRC2 148 -#define DDRC2LP 149 -#define DDRPHYC 150 -#define DDRPHYCLP 151 -#define DDRCAPB 152 -#define DDRCAPBLP 153 -#define AXIDCG 154 -#define DDRPHYCAPB 155 -#define DDRPHYCAPBLP 156 -#define DDRPERFM 157 - -#define ADC1 158 -#define ADC2 159 -#define SAI1 160 -#define SAI2 161 - -#define STM32MP1_LAST_CLK 162 - -/* SCMI clock identifiers */ -#define CK_SCMI_HSE 0 -#define CK_SCMI_HSI 1 -#define CK_SCMI_CSI 2 -#define CK_SCMI_LSE 3 -#define CK_SCMI_LSI 4 -#define CK_SCMI_HSE_DIV2 5 -#define CK_SCMI_PLL2_Q 6 -#define CK_SCMI_PLL2_R 7 -#define CK_SCMI_PLL3_P 8 -#define CK_SCMI_PLL3_Q 9 -#define CK_SCMI_PLL3_R 10 -#define CK_SCMI_PLL4_P 11 -#define CK_SCMI_PLL4_Q 12 -#define CK_SCMI_PLL4_R 13 -#define CK_SCMI_MPU 14 -#define CK_SCMI_AXI 15 -#define CK_SCMI_MLAHB 16 -#define CK_SCMI_CKPER 17 -#define CK_SCMI_PCLK1 18 -#define CK_SCMI_PCLK2 19 -#define CK_SCMI_PCLK3 20 -#define CK_SCMI_PCLK4 21 -#define CK_SCMI_PCLK5 22 -#define CK_SCMI_PCLK6 23 -#define CK_SCMI_CKTIMG1 24 -#define CK_SCMI_CKTIMG2 25 -#define CK_SCMI_CKTIMG3 26 -#define CK_SCMI_RTC 27 -#define CK_SCMI_RTCAPB 28 - -#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */ diff --git a/include/dt-bindings/mfd/st,stpmic1.h b/include/dt-bindings/mfd/st,stpmic1.h deleted file mode 100644 index 321cd08797d9..000000000000 --- a/include/dt-bindings/mfd/st,stpmic1.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Philippe Peurichard philippe.peurichard@st.com, - * Pascal Paillet p.paillet@st.com for STMicroelectronics. - */ - -#ifndef __DT_BINDINGS_STPMIC1_H__ -#define __DT_BINDINGS_STPMIC1_H__ - -/* IRQ definitions */ -#define IT_PONKEY_F 0 -#define IT_PONKEY_R 1 -#define IT_WAKEUP_F 2 -#define IT_WAKEUP_R 3 -#define IT_VBUS_OTG_F 4 -#define IT_VBUS_OTG_R 5 -#define IT_SWOUT_F 6 -#define IT_SWOUT_R 7 - -#define IT_CURLIM_BUCK1 8 -#define IT_CURLIM_BUCK2 9 -#define IT_CURLIM_BUCK3 10 -#define IT_CURLIM_BUCK4 11 -#define IT_OCP_OTG 12 -#define IT_OCP_SWOUT 13 -#define IT_OCP_BOOST 14 -#define IT_OVP_BOOST 15 - -#define IT_CURLIM_LDO1 16 -#define IT_CURLIM_LDO2 17 -#define IT_CURLIM_LDO3 18 -#define IT_CURLIM_LDO4 19 -#define IT_CURLIM_LDO5 20 -#define IT_CURLIM_LDO6 21 -#define IT_SHORT_SWOTG 22 -#define IT_SHORT_SWOUT 23 - -#define IT_TWARN_F 24 -#define IT_TWARN_R 25 -#define IT_VINLOW_F 26 -#define IT_VINLOW_R 27 -#define IT_SWIN_F 30 -#define IT_SWIN_R 31 - -/* BUCK MODES definitions */ -#define STPMIC1_BUCK_MODE_NORMAL 0 -#define STPMIC1_BUCK_MODE_LP 2 - -#endif /* __DT_BINDINGS_STPMIC1_H__ */ diff --git a/include/dt-bindings/mfd/st-lpc.h b/include/dt-bindings/mfd/st-lpc.h deleted file mode 100644 index d05894afa7e7..000000000000 --- a/include/dt-bindings/mfd/st-lpc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This header provides shared DT/Driver defines for ST's LPC device - * - * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved - * - * Author: Lee Jones lee.jones@linaro.org for STMicroelectronics - */ - -#ifndef __DT_BINDINGS_ST_LPC_H__ -#define __DT_BINDINGS_ST_LPC_H__ - -#define ST_LPC_MODE_RTC 0 -#define ST_LPC_MODE_WDT 1 -#define ST_LPC_MODE_CLKSRC 2 - -#endif /* __DT_BINDINGS_ST_LPC_H__ */ diff --git a/include/dt-bindings/mfd/stm32f4-rcc.h b/include/dt-bindings/mfd/stm32f4-rcc.h deleted file mode 100644 index 36448a5619a1..000000000000 --- a/include/dt-bindings/mfd/stm32f4-rcc.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the STM32F4 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H -#define _DT_BINDINGS_MFD_STM32F4_RCC_H - -/* AHB1 */ -#define STM32F4_RCC_AHB1_GPIOA 0 -#define STM32F4_RCC_AHB1_GPIOB 1 -#define STM32F4_RCC_AHB1_GPIOC 2 -#define STM32F4_RCC_AHB1_GPIOD 3 -#define STM32F4_RCC_AHB1_GPIOE 4 -#define STM32F4_RCC_AHB1_GPIOF 5 -#define STM32F4_RCC_AHB1_GPIOG 6 -#define STM32F4_RCC_AHB1_GPIOH 7 -#define STM32F4_RCC_AHB1_GPIOI 8 -#define STM32F4_RCC_AHB1_GPIOJ 9 -#define STM32F4_RCC_AHB1_GPIOK 10 -#define STM32F4_RCC_AHB1_CRC 12 -#define STM32F4_RCC_AHB1_BKPSRAM 18 -#define STM32F4_RCC_AHB1_CCMDATARAM 20 -#define STM32F4_RCC_AHB1_DMA1 21 -#define STM32F4_RCC_AHB1_DMA2 22 -#define STM32F4_RCC_AHB1_DMA2D 23 -#define STM32F4_RCC_AHB1_ETHMAC 25 -#define STM32F4_RCC_AHB1_ETHMACTX 26 -#define STM32F4_RCC_AHB1_ETHMACRX 27 -#define STM32F4_RCC_AHB1_ETHMACPTP 28 -#define STM32F4_RCC_AHB1_OTGHS 29 -#define STM32F4_RCC_AHB1_OTGHSULPI 30 - -#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) -#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) - -/* AHB2 */ -#define STM32F4_RCC_AHB2_DCMI 0 -#define STM32F4_RCC_AHB2_CRYP 4 -#define STM32F4_RCC_AHB2_HASH 5 -#define STM32F4_RCC_AHB2_RNG 6 -#define STM32F4_RCC_AHB2_OTGFS 7 - -#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) -#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) - -/* AHB3 */ -#define STM32F4_RCC_AHB3_FMC 0 -#define STM32F4_RCC_AHB3_QSPI 1 - -#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) -#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) - -/* APB1 */ -#define STM32F4_RCC_APB1_TIM2 0 -#define STM32F4_RCC_APB1_TIM3 1 -#define STM32F4_RCC_APB1_TIM4 2 -#define STM32F4_RCC_APB1_TIM5 3 -#define STM32F4_RCC_APB1_TIM6 4 -#define STM32F4_RCC_APB1_TIM7 5 -#define STM32F4_RCC_APB1_TIM12 6 -#define STM32F4_RCC_APB1_TIM13 7 -#define STM32F4_RCC_APB1_TIM14 8 -#define STM32F4_RCC_APB1_WWDG 11 -#define STM32F4_RCC_APB1_SPI2 14 -#define STM32F4_RCC_APB1_SPI3 15 -#define STM32F4_RCC_APB1_UART2 17 -#define STM32F4_RCC_APB1_UART3 18 -#define STM32F4_RCC_APB1_UART4 19 -#define STM32F4_RCC_APB1_UART5 20 -#define STM32F4_RCC_APB1_I2C1 21 -#define STM32F4_RCC_APB1_I2C2 22 -#define STM32F4_RCC_APB1_I2C3 23 -#define STM32F4_RCC_APB1_CAN1 25 -#define STM32F4_RCC_APB1_CAN2 26 -#define STM32F4_RCC_APB1_PWR 28 -#define STM32F4_RCC_APB1_DAC 29 -#define STM32F4_RCC_APB1_UART7 30 -#define STM32F4_RCC_APB1_UART8 31 - -#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) -#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) - -/* APB2 */ -#define STM32F4_RCC_APB2_TIM1 0 -#define STM32F4_RCC_APB2_TIM8 1 -#define STM32F4_RCC_APB2_USART1 4 -#define STM32F4_RCC_APB2_USART6 5 -#define STM32F4_RCC_APB2_ADC1 8 -#define STM32F4_RCC_APB2_ADC2 9 -#define STM32F4_RCC_APB2_ADC3 10 -#define STM32F4_RCC_APB2_SDIO 11 -#define STM32F4_RCC_APB2_SPI1 12 -#define STM32F4_RCC_APB2_SPI4 13 -#define STM32F4_RCC_APB2_SYSCFG 14 -#define STM32F4_RCC_APB2_TIM9 16 -#define STM32F4_RCC_APB2_TIM10 17 -#define STM32F4_RCC_APB2_TIM11 18 -#define STM32F4_RCC_APB2_SPI5 20 -#define STM32F4_RCC_APB2_SPI6 21 -#define STM32F4_RCC_APB2_SAI1 22 -#define STM32F4_RCC_APB2_LTDC 26 -#define STM32F4_RCC_APB2_DSI 27 - -#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) -#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) - -#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h deleted file mode 100644 index a4e4f9271395..000000000000 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the STM32F7 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H -#define _DT_BINDINGS_MFD_STM32F7_RCC_H - -/* AHB1 */ -#define STM32F7_RCC_AHB1_GPIOA 0 -#define STM32F7_RCC_AHB1_GPIOB 1 -#define STM32F7_RCC_AHB1_GPIOC 2 -#define STM32F7_RCC_AHB1_GPIOD 3 -#define STM32F7_RCC_AHB1_GPIOE 4 -#define STM32F7_RCC_AHB1_GPIOF 5 -#define STM32F7_RCC_AHB1_GPIOG 6 -#define STM32F7_RCC_AHB1_GPIOH 7 -#define STM32F7_RCC_AHB1_GPIOI 8 -#define STM32F7_RCC_AHB1_GPIOJ 9 -#define STM32F7_RCC_AHB1_GPIOK 10 -#define STM32F7_RCC_AHB1_CRC 12 -#define STM32F7_RCC_AHB1_BKPSRAM 18 -#define STM32F7_RCC_AHB1_DTCMRAM 20 -#define STM32F7_RCC_AHB1_DMA1 21 -#define STM32F7_RCC_AHB1_DMA2 22 -#define STM32F7_RCC_AHB1_DMA2D 23 -#define STM32F7_RCC_AHB1_ETHMAC 25 -#define STM32F7_RCC_AHB1_ETHMACTX 26 -#define STM32F7_RCC_AHB1_ETHMACRX 27 -#define STM32FF_RCC_AHB1_ETHMACPTP 28 -#define STM32F7_RCC_AHB1_OTGHS 29 -#define STM32F7_RCC_AHB1_OTGHSULPI 30 - -#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) -#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) - - -/* AHB2 */ -#define STM32F7_RCC_AHB2_DCMI 0 -#define STM32F7_RCC_AHB2_CRYP 4 -#define STM32F7_RCC_AHB2_HASH 5 -#define STM32F7_RCC_AHB2_RNG 6 -#define STM32F7_RCC_AHB2_OTGFS 7 - -#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) -#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) - -/* AHB3 */ -#define STM32F7_RCC_AHB3_FMC 0 -#define STM32F7_RCC_AHB3_QSPI 1 - -#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) -#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) - -/* APB1 */ -#define STM32F7_RCC_APB1_TIM2 0 -#define STM32F7_RCC_APB1_TIM3 1 -#define STM32F7_RCC_APB1_TIM4 2 -#define STM32F7_RCC_APB1_TIM5 3 -#define STM32F7_RCC_APB1_TIM6 4 -#define STM32F7_RCC_APB1_TIM7 5 -#define STM32F7_RCC_APB1_TIM12 6 -#define STM32F7_RCC_APB1_TIM13 7 -#define STM32F7_RCC_APB1_TIM14 8 -#define STM32F7_RCC_APB1_LPTIM1 9 -#define STM32F7_RCC_APB1_WWDG 11 -#define STM32F7_RCC_APB1_CAN3 13 -#define STM32F7_RCC_APB1_SPI2 14 -#define STM32F7_RCC_APB1_SPI3 15 -#define STM32F7_RCC_APB1_SPDIFRX 16 -#define STM32F7_RCC_APB1_UART2 17 -#define STM32F7_RCC_APB1_UART3 18 -#define STM32F7_RCC_APB1_UART4 19 -#define STM32F7_RCC_APB1_UART5 20 -#define STM32F7_RCC_APB1_I2C1 21 -#define STM32F7_RCC_APB1_I2C2 22 -#define STM32F7_RCC_APB1_I2C3 23 -#define STM32F7_RCC_APB1_I2C4 24 -#define STM32F7_RCC_APB1_CAN1 25 -#define STM32F7_RCC_APB1_CAN2 26 -#define STM32F7_RCC_APB1_CEC 27 -#define STM32F7_RCC_APB1_PWR 28 -#define STM32F7_RCC_APB1_DAC 29 -#define STM32F7_RCC_APB1_UART7 30 -#define STM32F7_RCC_APB1_UART8 31 - -#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) -#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) - -/* APB2 */ -#define STM32F7_RCC_APB2_TIM1 0 -#define STM32F7_RCC_APB2_TIM8 1 -#define STM32F7_RCC_APB2_USART1 4 -#define STM32F7_RCC_APB2_USART6 5 -#define STM32F7_RCC_APB2_SDMMC2 7 -#define STM32F7_RCC_APB2_ADC1 8 -#define STM32F7_RCC_APB2_ADC2 9 -#define STM32F7_RCC_APB2_ADC3 10 -#define STM32F7_RCC_APB2_SDMMC1 11 -#define STM32F7_RCC_APB2_SPI1 12 -#define STM32F7_RCC_APB2_SPI4 13 -#define STM32F7_RCC_APB2_SYSCFG 14 -#define STM32F7_RCC_APB2_TIM9 16 -#define STM32F7_RCC_APB2_TIM10 17 -#define STM32F7_RCC_APB2_TIM11 18 -#define STM32F7_RCC_APB2_SPI5 20 -#define STM32F7_RCC_APB2_SPI6 21 -#define STM32F7_RCC_APB2_SAI1 22 -#define STM32F7_RCC_APB2_SAI2 23 -#define STM32F7_RCC_APB2_LTDC 26 -#define STM32F7_RCC_APB2_DSI 27 - -#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) -#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) - -#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */ diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h deleted file mode 100644 index 06e8476bf08f..000000000000 --- a/include/dt-bindings/mfd/stm32h7-rcc.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This header provides constants for the STM32H7 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H -#define _DT_BINDINGS_MFD_STM32H7_RCC_H - -/* AHB3 */ -#define STM32H7_RCC_AHB3_MDMA 0 -#define STM32H7_RCC_AHB3_DMA2D 4 -#define STM32H7_RCC_AHB3_JPGDEC 5 -#define STM32H7_RCC_AHB3_FMC 12 -#define STM32H7_RCC_AHB3_QUADSPI 14 -#define STM32H7_RCC_AHB3_SDMMC1 16 -#define STM32H7_RCC_AHB3_CPU 31 -#define STM32H7_RCC_AHB3_CPU1 31 - -#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) - -/* AHB1 */ -#define STM32H7_RCC_AHB1_DMA1 0 -#define STM32H7_RCC_AHB1_DMA2 1 -#define STM32H7_RCC_AHB1_ADC12 5 -#define STM32H7_RCC_AHB1_ART 14 -#define STM32H7_RCC_AHB1_ETH1MAC 15 -#define STM32H7_RCC_AHB1_USB1OTG 25 -#define STM32H7_RCC_AHB1_USB2OTG 27 -#define STM32H7_RCC_AHB1_CPU2 31 - -#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) - -/* AHB2 */ -#define STM32H7_RCC_AHB2_CAMITF 0 -#define STM32H7_RCC_AHB2_CRYPT 4 -#define STM32H7_RCC_AHB2_HASH 5 -#define STM32H7_RCC_AHB2_RNG 6 -#define STM32H7_RCC_AHB2_SDMMC2 9 - -#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) - -/* AHB4 */ -#define STM32H7_RCC_AHB4_GPIOA 0 -#define STM32H7_RCC_AHB4_GPIOB 1 -#define STM32H7_RCC_AHB4_GPIOC 2 -#define STM32H7_RCC_AHB4_GPIOD 3 -#define STM32H7_RCC_AHB4_GPIOE 4 -#define STM32H7_RCC_AHB4_GPIOF 5 -#define STM32H7_RCC_AHB4_GPIOG 6 -#define STM32H7_RCC_AHB4_GPIOH 7 -#define STM32H7_RCC_AHB4_GPIOI 8 -#define STM32H7_RCC_AHB4_GPIOJ 9 -#define STM32H7_RCC_AHB4_GPIOK 10 -#define STM32H7_RCC_AHB4_CRC 19 -#define STM32H7_RCC_AHB4_BDMA 21 -#define STM32H7_RCC_AHB4_ADC3 24 -#define STM32H7_RCC_AHB4_HSEM 25 - -#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) - -/* APB3 */ -#define STM32H7_RCC_APB3_LTDC 3 -#define STM32H7_RCC_APB3_DSI 4 - -#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) - -/* APB1L */ -#define STM32H7_RCC_APB1L_TIM2 0 -#define STM32H7_RCC_APB1L_TIM3 1 -#define STM32H7_RCC_APB1L_TIM4 2 -#define STM32H7_RCC_APB1L_TIM5 3 -#define STM32H7_RCC_APB1L_TIM6 4 -#define STM32H7_RCC_APB1L_TIM7 5 -#define STM32H7_RCC_APB1L_TIM12 6 -#define STM32H7_RCC_APB1L_TIM13 7 -#define STM32H7_RCC_APB1L_TIM14 8 -#define STM32H7_RCC_APB1L_LPTIM1 9 -#define STM32H7_RCC_APB1L_SPI2 14 -#define STM32H7_RCC_APB1L_SPI3 15 -#define STM32H7_RCC_APB1L_SPDIF_RX 16 -#define STM32H7_RCC_APB1L_USART2 17 -#define STM32H7_RCC_APB1L_USART3 18 -#define STM32H7_RCC_APB1L_UART4 19 -#define STM32H7_RCC_APB1L_UART5 20 -#define STM32H7_RCC_APB1L_I2C1 21 -#define STM32H7_RCC_APB1L_I2C2 22 -#define STM32H7_RCC_APB1L_I2C3 23 -#define STM32H7_RCC_APB1L_HDMICEC 27 -#define STM32H7_RCC_APB1L_DAC12 29 -#define STM32H7_RCC_APB1L_USART7 30 -#define STM32H7_RCC_APB1L_USART8 31 - -#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) - -/* APB1H */ -#define STM32H7_RCC_APB1H_CRS 1 -#define STM32H7_RCC_APB1H_SWP 2 -#define STM32H7_RCC_APB1H_OPAMP 4 -#define STM32H7_RCC_APB1H_MDIOS 5 -#define STM32H7_RCC_APB1H_FDCAN 8 - -#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) - -/* APB2 */ -#define STM32H7_RCC_APB2_TIM1 0 -#define STM32H7_RCC_APB2_TIM8 1 -#define STM32H7_RCC_APB2_USART1 4 -#define STM32H7_RCC_APB2_USART6 5 -#define STM32H7_RCC_APB2_SPI1 12 -#define STM32H7_RCC_APB2_SPI4 13 -#define STM32H7_RCC_APB2_TIM15 16 -#define STM32H7_RCC_APB2_TIM16 17 -#define STM32H7_RCC_APB2_TIM17 18 -#define STM32H7_RCC_APB2_SPI5 20 -#define STM32H7_RCC_APB2_SAI1 22 -#define STM32H7_RCC_APB2_SAI2 23 -#define STM32H7_RCC_APB2_SAI3 24 -#define STM32H7_RCC_APB2_DFSDM1 28 -#define STM32H7_RCC_APB2_HRTIM 29 - -#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) - -/* APB4 */ -#define STM32H7_RCC_APB4_SYSCFG 1 -#define STM32H7_RCC_APB4_LPUART1 3 -#define STM32H7_RCC_APB4_SPI6 5 -#define STM32H7_RCC_APB4_I2C4 7 -#define STM32H7_RCC_APB4_LPTIM2 9 -#define STM32H7_RCC_APB4_LPTIM3 10 -#define STM32H7_RCC_APB4_LPTIM4 11 -#define STM32H7_RCC_APB4_LPTIM5 12 -#define STM32H7_RCC_APB4_COMP12 14 -#define STM32H7_RCC_APB4_VREF 15 -#define STM32H7_RCC_APB4_SAI4 21 -#define STM32H7_RCC_APB4_TMPSENS 26 - -#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) - -#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */ diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h deleted file mode 100644 index 28ad0235086a..000000000000 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Torgue Alexandre alexandre.torgue@st.com for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32_PINFUNC_H -#define _DT_BINDINGS_STM32_PINFUNC_H - -/* define PIN modes */ -#define GPIO 0x0 -#define AF0 0x1 -#define AF1 0x2 -#define AF2 0x3 -#define AF3 0x4 -#define AF4 0x5 -#define AF5 0x6 -#define AF6 0x7 -#define AF7 0x8 -#define AF8 0x9 -#define AF9 0xa -#define AF10 0xb -#define AF11 0xc -#define AF12 0xd -#define AF13 0xe -#define AF14 0xf -#define AF15 0x10 -#define ANALOG 0x11 - -/* define Pins number*/ -#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) - -#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) - -/* package information */ -#define STM32MP_PKG_AA 0x1 -#define STM32MP_PKG_AB 0x2 -#define STM32MP_PKG_AC 0x4 -#define STM32MP_PKG_AD 0x8 -#define STM32MP_PKG_AI 0x100 -#define STM32MP_PKG_AK 0x400 -#define STM32MP_PKG_AL 0x800 - -#endif /* _DT_BINDINGS_STM32_PINFUNC_H */ - diff --git a/include/dt-bindings/regulator/st,stm32mp13-regulator.h b/include/dt-bindings/regulator/st,stm32mp13-regulator.h deleted file mode 100644 index b3a974dfc585..000000000000 --- a/include/dt-bindings/regulator/st,stm32mp13-regulator.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ -/* - * Copyright (C) 2022, STMicroelectronics - All Rights Reserved - */ - -#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H -#define __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H - -/* SCMI voltage domains identifiers */ - -/* SOC Internal regulators */ -#define VOLTD_SCMI_REG11 0 -#define VOLTD_SCMI_REG18 1 -#define VOLTD_SCMI_USB33 2 -#define VOLTD_SCMI_SDMMC1_IO 3 -#define VOLTD_SCMI_SDMMC2_IO 4 -#define VOLTD_SCMI_VREFBUF 5 - -/* STPMIC1 regulators */ -#define VOLTD_SCMI_STPMIC1_BUCK1 6 -#define VOLTD_SCMI_STPMIC1_BUCK2 7 -#define VOLTD_SCMI_STPMIC1_BUCK3 8 -#define VOLTD_SCMI_STPMIC1_BUCK4 9 -#define VOLTD_SCMI_STPMIC1_LDO1 10 -#define VOLTD_SCMI_STPMIC1_LDO2 11 -#define VOLTD_SCMI_STPMIC1_LDO3 12 -#define VOLTD_SCMI_STPMIC1_LDO4 13 -#define VOLTD_SCMI_STPMIC1_LDO5 14 -#define VOLTD_SCMI_STPMIC1_LDO6 15 -#define VOLTD_SCMI_STPMIC1_VREFDDR 16 -#define VOLTD_SCMI_STPMIC1_BOOST 17 -#define VOLTD_SCMI_STPMIC1_PWR_SW1 18 -#define VOLTD_SCMI_STPMIC1_PWR_SW2 19 - -/* External regulators */ -#define VOLTD_SCMI_REGU0 20 -#define VOLTD_SCMI_REGU1 21 -#define VOLTD_SCMI_REGU2 22 -#define VOLTD_SCMI_REGU3 23 -#define VOLTD_SCMI_REGU4 24 - -#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H */ diff --git a/include/dt-bindings/reset/stih407-resets.h b/include/dt-bindings/reset/stih407-resets.h deleted file mode 100644 index 4ab3a1c94958..000000000000 --- a/include/dt-bindings/reset/stih407-resets.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH407 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH407 - -/* Powerdown requests control 0 */ -#define STIH407_EMISS_POWERDOWN 0 -#define STIH407_NAND_POWERDOWN 1 - -/* Synp GMAC PowerDown */ -#define STIH407_ETH1_POWERDOWN 2 - -/* Powerdown requests control 1 */ -#define STIH407_USB3_POWERDOWN 3 -#define STIH407_USB2_PORT1_POWERDOWN 4 -#define STIH407_USB2_PORT0_POWERDOWN 5 -#define STIH407_PCIE1_POWERDOWN 6 -#define STIH407_PCIE0_POWERDOWN 7 -#define STIH407_SATA1_POWERDOWN 8 -#define STIH407_SATA0_POWERDOWN 9 - -/* Reset defines */ -#define STIH407_ETH1_SOFTRESET 0 -#define STIH407_MMC1_SOFTRESET 1 -#define STIH407_PICOPHY_SOFTRESET 2 -#define STIH407_IRB_SOFTRESET 3 -#define STIH407_PCIE0_SOFTRESET 4 -#define STIH407_PCIE1_SOFTRESET 5 -#define STIH407_SATA0_SOFTRESET 6 -#define STIH407_SATA1_SOFTRESET 7 -#define STIH407_MIPHY0_SOFTRESET 8 -#define STIH407_MIPHY1_SOFTRESET 9 -#define STIH407_MIPHY2_SOFTRESET 10 -#define STIH407_SATA0_PWR_SOFTRESET 11 -#define STIH407_SATA1_PWR_SOFTRESET 12 -#define STIH407_DELTA_SOFTRESET 13 -#define STIH407_BLITTER_SOFTRESET 14 -#define STIH407_HDTVOUT_SOFTRESET 15 -#define STIH407_HDQVDP_SOFTRESET 16 -#define STIH407_VDP_AUX_SOFTRESET 17 -#define STIH407_COMPO_SOFTRESET 18 -#define STIH407_HDMI_TX_PHY_SOFTRESET 19 -#define STIH407_JPEG_DEC_SOFTRESET 20 -#define STIH407_VP8_DEC_SOFTRESET 21 -#define STIH407_GPU_SOFTRESET 22 -#define STIH407_HVA_SOFTRESET 23 -#define STIH407_ERAM_HVA_SOFTRESET 24 -#define STIH407_LPM_SOFTRESET 25 -#define STIH407_KEYSCAN_SOFTRESET 26 -#define STIH407_USB2_PORT0_SOFTRESET 27 -#define STIH407_USB2_PORT1_SOFTRESET 28 -#define STIH407_ST231_AUD_SOFTRESET 29 -#define STIH407_ST231_DMU_SOFTRESET 30 -#define STIH407_ST231_GP0_SOFTRESET 31 -#define STIH407_ST231_GP1_SOFTRESET 32 - -/* Picophy reset defines */ -#define STIH407_PICOPHY0_RESET 0 -#define STIH407_PICOPHY1_RESET 1 -#define STIH407_PICOPHY2_RESET 2 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h deleted file mode 100644 index 9071f139649f..000000000000 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez gabriel.fernandez@st.com for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ -#define _DT_BINDINGS_STM32MP1_RESET_H_ - -#define MCU_HOLD_BOOT_R 2144 -#define LTDC_R 3072 -#define DSI_R 3076 -#define DDRPERFM_R 3080 -#define USBPHY_R 3088 -#define SPI6_R 3136 -#define I2C4_R 3138 -#define I2C6_R 3139 -#define USART1_R 3140 -#define STGEN_R 3156 -#define GPIOZ_R 3200 -#define CRYP1_R 3204 -#define HASH1_R 3205 -#define RNG1_R 3206 -#define AXIM_R 3216 -#define GPU_R 3269 -#define ETHMAC_R 3274 -#define FMC_R 3276 -#define QSPI_R 3278 -#define SDMMC1_R 3280 -#define SDMMC2_R 3281 -#define CRC1_R 3284 -#define USBH_R 3288 -#define MDMA_R 3328 -#define MCU_R 8225 -#define TIM2_R 19456 -#define TIM3_R 19457 -#define TIM4_R 19458 -#define TIM5_R 19459 -#define TIM6_R 19460 -#define TIM7_R 19461 -#define TIM12_R 16462 -#define TIM13_R 16463 -#define TIM14_R 16464 -#define LPTIM1_R 19465 -#define SPI2_R 19467 -#define SPI3_R 19468 -#define USART2_R 19470 -#define USART3_R 19471 -#define UART4_R 19472 -#define UART5_R 19473 -#define UART7_R 19474 -#define UART8_R 19475 -#define I2C1_R 19477 -#define I2C2_R 19478 -#define I2C3_R 19479 -#define I2C5_R 19480 -#define SPDIF_R 19482 -#define CEC_R 19483 -#define DAC12_R 19485 -#define MDIO_R 19847 -#define TIM1_R 19520 -#define TIM8_R 19521 -#define TIM15_R 19522 -#define TIM16_R 19523 -#define TIM17_R 19524 -#define SPI1_R 19528 -#define SPI4_R 19529 -#define SPI5_R 19530 -#define USART6_R 19533 -#define SAI1_R 19536 -#define SAI2_R 19537 -#define SAI3_R 19538 -#define DFSDM_R 19540 -#define FDCAN_R 19544 -#define LPTIM2_R 19584 -#define LPTIM3_R 19585 -#define LPTIM4_R 19586 -#define LPTIM5_R 19587 -#define SAI4_R 19592 -#define SYSCFG_R 19595 -#define VREF_R 19597 -#define TMPSENS_R 19600 -#define PMBCTRL_R 19601 -#define DMA1_R 19648 -#define DMA2_R 19649 -#define DMAMUX_R 19650 -#define ADC12_R 19653 -#define USBO_R 19656 -#define SDMMC3_R 19664 -#define CAMITF_R 19712 -#define CRYP2_R 19716 -#define HASH2_R 19717 -#define RNG2_R 19718 -#define CRC2_R 19719 -#define HSEM_R 19723 -#define MBOX_R 19724 -#define GPIOA_R 19776 -#define GPIOB_R 19777 -#define GPIOC_R 19778 -#define GPIOD_R 19779 -#define GPIOE_R 19780 -#define GPIOF_R 19781 -#define GPIOG_R 19782 -#define GPIOH_R 19783 -#define GPIOI_R 19784 -#define GPIOJ_R 19785 -#define GPIOK_R 19786 - -/* SCMI reset domain identifiers */ -#define RST_SCMI_SPI6 0 -#define RST_SCMI_I2C4 1 -#define RST_SCMI_I2C6 2 -#define RST_SCMI_USART1 3 -#define RST_SCMI_STGEN 4 -#define RST_SCMI_GPIOZ 5 -#define RST_SCMI_CRYP1 6 -#define RST_SCMI_HASH1 7 -#define RST_SCMI_RNG1 8 -#define RST_SCMI_MDMA 9 -#define RST_SCMI_MCU 10 -#define RST_SCMI_MCU_HOLD_BOOT 11 - -#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h deleted file mode 100644 index ecb37c7ddde1..000000000000 --- a/include/dt-bindings/reset/stm32mp13-resets.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez gabriel.fernandez@foss.st.com for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ -#define _DT_BINDINGS_STM32MP13_RESET_H_ - -#define TIM2_R 13568 -#define TIM3_R 13569 -#define TIM4_R 13570 -#define TIM5_R 13571 -#define TIM6_R 13572 -#define TIM7_R 13573 -#define LPTIM1_R 13577 -#define SPI2_R 13579 -#define SPI3_R 13580 -#define USART3_R 13583 -#define UART4_R 13584 -#define UART5_R 13585 -#define UART7_R 13586 -#define UART8_R 13587 -#define I2C1_R 13589 -#define I2C2_R 13590 -#define SPDIF_R 13594 -#define TIM1_R 13632 -#define TIM8_R 13633 -#define SPI1_R 13640 -#define USART6_R 13645 -#define SAI1_R 13648 -#define SAI2_R 13649 -#define DFSDM_R 13652 -#define FDCAN_R 13656 -#define LPTIM2_R 13696 -#define LPTIM3_R 13697 -#define LPTIM4_R 13698 -#define LPTIM5_R 13699 -#define SYSCFG_R 13707 -#define VREF_R 13709 -#define DTS_R 13712 -#define PMBCTRL_R 13713 -#define LTDC_R 13760 -#define DCMIPP_R 13761 -#define DDRPERFM_R 13768 -#define USBPHY_R 13776 -#define STGEN_R 13844 -#define USART1_R 13888 -#define USART2_R 13889 -#define SPI4_R 13890 -#define SPI5_R 13891 -#define I2C3_R 13892 -#define I2C4_R 13893 -#define I2C5_R 13894 -#define TIM12_R 13895 -#define TIM13_R 13896 -#define TIM14_R 13897 -#define TIM15_R 13898 -#define TIM16_R 13899 -#define TIM17_R 13900 -#define DMA1_R 13952 -#define DMA2_R 13953 -#define DMAMUX1_R 13954 -#define DMA3_R 13955 -#define DMAMUX2_R 13956 -#define ADC1_R 13957 -#define ADC2_R 13958 -#define USBO_R 13960 -#define GPIOA_R 14080 -#define GPIOB_R 14081 -#define GPIOC_R 14082 -#define GPIOD_R 14083 -#define GPIOE_R 14084 -#define GPIOF_R 14085 -#define GPIOG_R 14086 -#define GPIOH_R 14087 -#define GPIOI_R 14088 -#define TSC_R 14095 -#define PKA_R 14146 -#define SAES_R 14147 -#define CRYP1_R 14148 -#define HASH1_R 14149 -#define RNG1_R 14150 -#define AXIMC_R 14160 -#define MDMA_R 14208 -#define MCE_R 14209 -#define ETH1MAC_R 14218 -#define FMC_R 14220 -#define QSPI_R 14222 -#define SDMMC1_R 14224 -#define SDMMC2_R 14225 -#define CRC1_R 14228 -#define USBH_R 14232 -#define ETH2MAC_R 14238 - -/* SCMI reset domain identifiers */ -#define RST_SCMI_LTDC 0 -#define RST_SCMI_MDMA 1 - -#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */

Drop in favour of dts/upstream.

Small driver adjustment to fix compatibility.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/pinctrl/rockchip/pinctrl-rk3568.c | 15 + include/dt-bindings/pinctrl/rockchip.h | 60 -- include/dt-bindings/power/px30-power.h | 27 - include/dt-bindings/power/rk3066-power.h | 22 - include/dt-bindings/power/rk3188-power.h | 24 - include/dt-bindings/power/rk3228-power.h | 21 - include/dt-bindings/power/rk3288-power.h | 32 - include/dt-bindings/power/rk3328-power.h | 19 - include/dt-bindings/power/rk3399-power.h | 53 -- include/dt-bindings/power/rk3568-power.h | 32 - include/dt-bindings/power/rk3588-power.h | 69 -- include/dt-bindings/power/rockchip,rv1126-power.h | 35 - include/dt-bindings/reset/rockchip,rk3588-cru.h | 754 ---------------------- include/dt-bindings/soc/rockchip,boot-mode.h | 16 - include/dt-bindings/soc/rockchip,vop2.h | 18 - 15 files changed, 15 insertions(+), 1182 deletions(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c index 1d4391982605..35a69c2a1a28 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -11,8 +11,23 @@ #include <dt-bindings/pinctrl/rockchip.h>

#include "pinctrl-rockchip.h"

+#define RK_GPIO0 0 +#define RK_GPIO1 1 +#define RK_GPIO2 2 +#define RK_GPIO3 3 +#define RK_GPIO4 4 +#define RK_GPIO6 6 + +#define RK_FUNC_GPIO 0 +#define RK_FUNC_1 1 +#define RK_FUNC_2 2 +#define RK_FUNC_3 3 +#define RK_FUNC_4 4 +#define RK_FUNC_5 5 +#define RK_FUNC_6 6 + static struct rockchip_mux_route_data rk3568_mux_route_data[] = { MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */ MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */ MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */ diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h deleted file mode 100644 index 1c28d6cb1fad..000000000000 --- a/include/dt-bindings/pinctrl/rockchip.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Header providing constants for Rockchip pinctrl bindings. - * - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner heiko@sntech.de - */ - -#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ -#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ - -#define RK_GPIO0 0 -#define RK_GPIO1 1 -#define RK_GPIO2 2 -#define RK_GPIO3 3 -#define RK_GPIO4 4 -#define RK_GPIO6 6 - -#define RK_PA0 0 -#define RK_PA1 1 -#define RK_PA2 2 -#define RK_PA3 3 -#define RK_PA4 4 -#define RK_PA5 5 -#define RK_PA6 6 -#define RK_PA7 7 -#define RK_PB0 8 -#define RK_PB1 9 -#define RK_PB2 10 -#define RK_PB3 11 -#define RK_PB4 12 -#define RK_PB5 13 -#define RK_PB6 14 -#define RK_PB7 15 -#define RK_PC0 16 -#define RK_PC1 17 -#define RK_PC2 18 -#define RK_PC3 19 -#define RK_PC4 20 -#define RK_PC5 21 -#define RK_PC6 22 -#define RK_PC7 23 -#define RK_PD0 24 -#define RK_PD1 25 -#define RK_PD2 26 -#define RK_PD3 27 -#define RK_PD4 28 -#define RK_PD5 29 -#define RK_PD6 30 -#define RK_PD7 31 - -#define RK_FUNC_GPIO 0 -#define RK_FUNC_1 1 -#define RK_FUNC_2 2 -#define RK_FUNC_3 3 -#define RK_FUNC_4 4 -#define RK_FUNC_5 5 -#define RK_FUNC_6 6 - -#endif diff --git a/include/dt-bindings/power/px30-power.h b/include/dt-bindings/power/px30-power.h deleted file mode 100644 index 30917a99ad20..000000000000 --- a/include/dt-bindings/power/px30-power.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ -#define __DT_BINDINGS_POWER_PX30_POWER_H__ - -/* VD_CORE */ -#define PX30_PD_A35_0 0 -#define PX30_PD_A35_1 1 -#define PX30_PD_A35_2 2 -#define PX30_PD_A35_3 3 -#define PX30_PD_SCU 4 - -/* VD_LOGIC */ -#define PX30_PD_USB 5 -#define PX30_PD_DDR 6 -#define PX30_PD_SDCARD 7 -#define PX30_PD_CRYPTO 8 -#define PX30_PD_GMAC 9 -#define PX30_PD_MMC_NAND 10 -#define PX30_PD_VPU 11 -#define PX30_PD_VO 12 -#define PX30_PD_VI 13 -#define PX30_PD_GPU 14 - -/* VD_PMU */ -#define PX30_PD_PMU 15 - -#endif diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h deleted file mode 100644 index acf9f310ac53..000000000000 --- a/include/dt-bindings/power/rk3066-power.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ -#define __DT_BINDINGS_POWER_RK3066_POWER_H__ - -/* VD_CORE */ -#define RK3066_PD_A9_0 0 -#define RK3066_PD_A9_1 1 -#define RK3066_PD_DBG 4 -#define RK3066_PD_SCU 5 - -/* VD_LOGIC */ -#define RK3066_PD_VIDEO 6 -#define RK3066_PD_VIO 7 -#define RK3066_PD_GPU 8 -#define RK3066_PD_PERI 9 -#define RK3066_PD_CPU 10 -#define RK3066_PD_ALIVE 11 - -/* VD_PMU */ -#define RK3066_PD_RTC 12 - -#endif diff --git a/include/dt-bindings/power/rk3188-power.h b/include/dt-bindings/power/rk3188-power.h deleted file mode 100644 index 93d23dfba33f..000000000000 --- a/include/dt-bindings/power/rk3188-power.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ -#define __DT_BINDINGS_POWER_RK3188_POWER_H__ - -/* VD_CORE */ -#define RK3188_PD_A9_0 0 -#define RK3188_PD_A9_1 1 -#define RK3188_PD_A9_2 2 -#define RK3188_PD_A9_3 3 -#define RK3188_PD_DBG 4 -#define RK3188_PD_SCU 5 - -/* VD_LOGIC */ -#define RK3188_PD_VIDEO 6 -#define RK3188_PD_VIO 7 -#define RK3188_PD_GPU 8 -#define RK3188_PD_PERI 9 -#define RK3188_PD_CPU 10 -#define RK3188_PD_ALIVE 11 - -/* VD_PMU */ -#define RK3188_PD_RTC 12 - -#endif diff --git a/include/dt-bindings/power/rk3228-power.h b/include/dt-bindings/power/rk3228-power.h deleted file mode 100644 index 6a8dc1bf76ce..000000000000 --- a/include/dt-bindings/power/rk3228-power.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__ -#define __DT_BINDINGS_POWER_RK3228_POWER_H__ - -/** - * RK3228 idle id Summary. - */ - -#define RK3228_PD_CORE 0 -#define RK3228_PD_MSCH 1 -#define RK3228_PD_BUS 2 -#define RK3228_PD_SYS 3 -#define RK3228_PD_VIO 4 -#define RK3228_PD_VOP 5 -#define RK3228_PD_VPU 6 -#define RK3228_PD_RKVDEC 7 -#define RK3228_PD_GPU 8 -#define RK3228_PD_PERI 9 -#define RK3228_PD_GMAC 10 - -#endif diff --git a/include/dt-bindings/power/rk3288-power.h b/include/dt-bindings/power/rk3288-power.h deleted file mode 100644 index f710b56ccd81..000000000000 --- a/include/dt-bindings/power/rk3288-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__ -#define __DT_BINDINGS_POWER_RK3288_POWER_H__ - -/** - * RK3288 Power Domain and Voltage Domain Summary. - */ - -/* VD_CORE */ -#define RK3288_PD_A17_0 0 -#define RK3288_PD_A17_1 1 -#define RK3288_PD_A17_2 2 -#define RK3288_PD_A17_3 3 -#define RK3288_PD_SCU 4 -#define RK3288_PD_DEBUG 5 -#define RK3288_PD_MEM 6 - -/* VD_LOGIC */ -#define RK3288_PD_BUS 7 -#define RK3288_PD_PERI 8 -#define RK3288_PD_VIO 9 -#define RK3288_PD_ALIVE 10 -#define RK3288_PD_HEVC 11 -#define RK3288_PD_VIDEO 12 - -/* VD_GPU */ -#define RK3288_PD_GPU 13 - -/* VD_PMU */ -#define RK3288_PD_PMU 14 - -#endif diff --git a/include/dt-bindings/power/rk3328-power.h b/include/dt-bindings/power/rk3328-power.h deleted file mode 100644 index 02e3d7fc1cce..000000000000 --- a/include/dt-bindings/power/rk3328-power.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__ -#define __DT_BINDINGS_POWER_RK3328_POWER_H__ - -/** - * RK3328 idle id Summary. - */ -#define RK3328_PD_CORE 0 -#define RK3328_PD_GPU 1 -#define RK3328_PD_BUS 2 -#define RK3328_PD_MSCH 3 -#define RK3328_PD_PERI 4 -#define RK3328_PD_VIDEO 5 -#define RK3328_PD_HEVC 6 -#define RK3328_PD_SYS 7 -#define RK3328_PD_VPU 8 -#define RK3328_PD_VIO 9 - -#endif diff --git a/include/dt-bindings/power/rk3399-power.h b/include/dt-bindings/power/rk3399-power.h deleted file mode 100644 index 168b3bfbd6f5..000000000000 --- a/include/dt-bindings/power/rk3399-power.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ -#define __DT_BINDINGS_POWER_RK3399_POWER_H__ - -/* VD_CORE_L */ -#define RK3399_PD_A53_L0 0 -#define RK3399_PD_A53_L1 1 -#define RK3399_PD_A53_L2 2 -#define RK3399_PD_A53_L3 3 -#define RK3399_PD_SCU_L 4 - -/* VD_CORE_B */ -#define RK3399_PD_A72_B0 5 -#define RK3399_PD_A72_B1 6 -#define RK3399_PD_SCU_B 7 - -/* VD_LOGIC */ -#define RK3399_PD_TCPD0 8 -#define RK3399_PD_TCPD1 9 -#define RK3399_PD_CCI 10 -#define RK3399_PD_CCI0 11 -#define RK3399_PD_CCI1 12 -#define RK3399_PD_PERILP 13 -#define RK3399_PD_PERIHP 14 -#define RK3399_PD_VIO 15 -#define RK3399_PD_VO 16 -#define RK3399_PD_VOPB 17 -#define RK3399_PD_VOPL 18 -#define RK3399_PD_ISP0 19 -#define RK3399_PD_ISP1 20 -#define RK3399_PD_HDCP 21 -#define RK3399_PD_GMAC 22 -#define RK3399_PD_EMMC 23 -#define RK3399_PD_USB3 24 -#define RK3399_PD_EDP 25 -#define RK3399_PD_GIC 26 -#define RK3399_PD_SD 27 -#define RK3399_PD_SDIOAUDIO 28 -#define RK3399_PD_ALIVE 29 - -/* VD_CENTER */ -#define RK3399_PD_CENTER 30 -#define RK3399_PD_VCODEC 31 -#define RK3399_PD_VDU 32 -#define RK3399_PD_RGA 33 -#define RK3399_PD_IEP 34 - -/* VD_GPU */ -#define RK3399_PD_GPU 35 - -/* VD_PMU */ -#define RK3399_PD_PMU 36 - -#endif diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h deleted file mode 100644 index 6cc1af1a9d26..000000000000 --- a/include/dt-bindings/power/rk3568-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ -#define __DT_BINDINGS_POWER_RK3568_POWER_H__ - -/* VD_CORE */ -#define RK3568_PD_CPU_0 0 -#define RK3568_PD_CPU_1 1 -#define RK3568_PD_CPU_2 2 -#define RK3568_PD_CPU_3 3 -#define RK3568_PD_CORE_ALIVE 4 - -/* VD_PMU */ -#define RK3568_PD_PMU 5 - -/* VD_NPU */ -#define RK3568_PD_NPU 6 - -/* VD_GPU */ -#define RK3568_PD_GPU 7 - -/* VD_LOGIC */ -#define RK3568_PD_VI 8 -#define RK3568_PD_VO 9 -#define RK3568_PD_RGA 10 -#define RK3568_PD_VPU 11 -#define RK3568_PD_CENTER 12 -#define RK3568_PD_RKVDEC 13 -#define RK3568_PD_RKVENC 14 -#define RK3568_PD_PIPE 15 -#define RK3568_PD_LOGIC_ALIVE 16 - -#endif diff --git a/include/dt-bindings/power/rk3588-power.h b/include/dt-bindings/power/rk3588-power.h deleted file mode 100644 index 1b92fec013cb..000000000000 --- a/include/dt-bindings/power/rk3588-power.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ -#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ -#define __DT_BINDINGS_POWER_RK3588_POWER_H__ - -/* VD_LITDSU */ -#define RK3588_PD_CPU_0 0 -#define RK3588_PD_CPU_1 1 -#define RK3588_PD_CPU_2 2 -#define RK3588_PD_CPU_3 3 - -/* VD_BIGCORE0 */ -#define RK3588_PD_CPU_4 4 -#define RK3588_PD_CPU_5 5 - -/* VD_BIGCORE1 */ -#define RK3588_PD_CPU_6 6 -#define RK3588_PD_CPU_7 7 - -/* VD_NPU */ -#define RK3588_PD_NPU 8 -#define RK3588_PD_NPUTOP 9 -#define RK3588_PD_NPU1 10 -#define RK3588_PD_NPU2 11 - -/* VD_GPU */ -#define RK3588_PD_GPU 12 - -/* VD_VCODEC */ -#define RK3588_PD_VCODEC 13 -#define RK3588_PD_RKVDEC0 14 -#define RK3588_PD_RKVDEC1 15 -#define RK3588_PD_VENC0 16 -#define RK3588_PD_VENC1 17 - -/* VD_DD01 */ -#define RK3588_PD_DDR01 18 - -/* VD_DD23 */ -#define RK3588_PD_DDR23 19 - -/* VD_LOGIC */ -#define RK3588_PD_CENTER 20 -#define RK3588_PD_VDPU 21 -#define RK3588_PD_RGA30 22 -#define RK3588_PD_AV1 23 -#define RK3588_PD_VOP 24 -#define RK3588_PD_VO0 25 -#define RK3588_PD_VO1 26 -#define RK3588_PD_VI 27 -#define RK3588_PD_ISP1 28 -#define RK3588_PD_FEC 29 -#define RK3588_PD_RGA31 30 -#define RK3588_PD_USB 31 -#define RK3588_PD_PHP 32 -#define RK3588_PD_GMAC 33 -#define RK3588_PD_PCIE 34 -#define RK3588_PD_NVM 35 -#define RK3588_PD_NVM0 36 -#define RK3588_PD_SDIO 37 -#define RK3588_PD_AUDIO 38 -#define RK3588_PD_SECURE 39 -#define RK3588_PD_SDMMC 40 -#define RK3588_PD_CRYPTO 41 -#define RK3588_PD_BUS 42 - -/* VD_PMU */ -#define RK3588_PD_PMU1 43 - -#endif diff --git a/include/dt-bindings/power/rockchip,rv1126-power.h b/include/dt-bindings/power/rockchip,rv1126-power.h deleted file mode 100644 index 38a68e000d38..000000000000 --- a/include/dt-bindings/power/rockchip,rv1126-power.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__ -#define __DT_BINDINGS_POWER_RV1126_POWER_H__ - -/* VD_CORE */ -#define RV1126_PD_CPU_0 0 -#define RV1126_PD_CPU_1 1 -#define RV1126_PD_CPU_2 2 -#define RV1126_PD_CPU_3 3 -#define RV1126_PD_CORE_ALIVE 4 - -/* VD_PMU */ -#define RV1126_PD_PMU 5 -#define RV1126_PD_PMU_ALIVE 6 - -/* VD_NPU */ -#define RV1126_PD_NPU 7 - -/* VD_VEPU */ -#define RV1126_PD_VEPU 8 - -/* VD_LOGIC */ -#define RV1126_PD_VI 9 -#define RV1126_PD_VO 10 -#define RV1126_PD_ISPP 11 -#define RV1126_PD_VDPU 12 -#define RV1126_PD_CRYPTO 13 -#define RV1126_PD_DDR 14 -#define RV1126_PD_NVM 15 -#define RV1126_PD_SDIO 16 -#define RV1126_PD_USB 17 -#define RV1126_PD_LOGIC_ALIVE 18 - -#endif diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h deleted file mode 100644 index 738e56aead93..000000000000 --- a/include/dt-bindings/reset/rockchip,rk3588-cru.h +++ /dev/null @@ -1,754 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ -/* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. - * Copyright (c) 2022 Collabora Ltd. - * - * Author: Elaine Zhang zhangqing@rock-chips.com - * Author: Sebastian Reichel sebastian.reichel@collabora.com - */ - -#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H -#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H - -#define SRST_A_TOP_BIU 0 -#define SRST_P_TOP_BIU 1 -#define SRST_P_CSIPHY0 2 -#define SRST_CSIPHY0 3 -#define SRST_P_CSIPHY1 4 -#define SRST_CSIPHY1 5 -#define SRST_A_TOP_M500_BIU 6 - -#define SRST_A_TOP_M400_BIU 7 -#define SRST_A_TOP_S200_BIU 8 -#define SRST_A_TOP_S400_BIU 9 -#define SRST_A_TOP_M300_BIU 10 -#define SRST_USBDP_COMBO_PHY0_INIT 11 -#define SRST_USBDP_COMBO_PHY0_CMN 12 -#define SRST_USBDP_COMBO_PHY0_LANE 13 -#define SRST_USBDP_COMBO_PHY0_PCS 14 -#define SRST_USBDP_COMBO_PHY1_INIT 15 - -#define SRST_USBDP_COMBO_PHY1_CMN 16 -#define SRST_USBDP_COMBO_PHY1_LANE 17 -#define SRST_USBDP_COMBO_PHY1_PCS 18 -#define SRST_DCPHY0 19 -#define SRST_P_MIPI_DCPHY0 20 -#define SRST_P_MIPI_DCPHY0_GRF 21 - -#define SRST_DCPHY1 22 -#define SRST_P_MIPI_DCPHY1 23 -#define SRST_P_MIPI_DCPHY1_GRF 24 -#define SRST_P_APB2ASB_SLV_CDPHY 25 -#define SRST_P_APB2ASB_SLV_CSIPHY 26 -#define SRST_P_APB2ASB_SLV_VCCIO3_5 27 -#define SRST_P_APB2ASB_SLV_VCCIO6 28 -#define SRST_P_APB2ASB_SLV_EMMCIO 29 -#define SRST_P_APB2ASB_SLV_IOC_TOP 30 -#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31 - -#define SRST_P_CRU 32 -#define SRST_A_CHANNEL_SECURE2VO1USB 33 -#define SRST_A_CHANNEL_SECURE2CENTER 34 -#define SRST_H_CHANNEL_SECURE2VO1USB 35 -#define SRST_H_CHANNEL_SECURE2CENTER 36 - -#define SRST_P_CHANNEL_SECURE2VO1USB 37 -#define SRST_P_CHANNEL_SECURE2CENTER 38 - -#define SRST_H_AUDIO_BIU 39 -#define SRST_P_AUDIO_BIU 40 -#define SRST_H_I2S0_8CH 41 -#define SRST_M_I2S0_8CH_TX 42 -#define SRST_M_I2S0_8CH_RX 43 -#define SRST_P_ACDCDIG 44 -#define SRST_H_I2S2_2CH 45 -#define SRST_H_I2S3_2CH 46 - -#define SRST_M_I2S2_2CH 47 -#define SRST_M_I2S3_2CH 48 -#define SRST_DAC_ACDCDIG 49 -#define SRST_H_SPDIF0 50 - -#define SRST_M_SPDIF0 51 -#define SRST_H_SPDIF1 52 -#define SRST_M_SPDIF1 53 -#define SRST_H_PDM1 54 -#define SRST_PDM1 55 - -#define SRST_A_BUS_BIU 56 -#define SRST_P_BUS_BIU 57 -#define SRST_A_GIC 58 -#define SRST_A_GIC_DBG 59 -#define SRST_A_DMAC0 60 -#define SRST_A_DMAC1 61 -#define SRST_A_DMAC2 62 -#define SRST_P_I2C1 63 -#define SRST_P_I2C2 64 -#define SRST_P_I2C3 65 -#define SRST_P_I2C4 66 -#define SRST_P_I2C5 67 -#define SRST_P_I2C6 68 -#define SRST_P_I2C7 69 -#define SRST_P_I2C8 70 - -#define SRST_I2C1 71 -#define SRST_I2C2 72 -#define SRST_I2C3 73 -#define SRST_I2C4 74 -#define SRST_I2C5 75 -#define SRST_I2C6 76 -#define SRST_I2C7 77 -#define SRST_I2C8 78 -#define SRST_P_CAN0 79 -#define SRST_CAN0 80 -#define SRST_P_CAN1 81 -#define SRST_CAN1 82 -#define SRST_P_CAN2 83 -#define SRST_CAN2 84 -#define SRST_P_SARADC 85 - -#define SRST_P_TSADC 86 -#define SRST_TSADC 87 -#define SRST_P_UART1 88 -#define SRST_P_UART2 89 -#define SRST_P_UART3 90 -#define SRST_P_UART4 91 -#define SRST_P_UART5 92 -#define SRST_P_UART6 93 -#define SRST_P_UART7 94 -#define SRST_P_UART8 95 -#define SRST_P_UART9 96 -#define SRST_S_UART1 97 - -#define SRST_S_UART2 98 -#define SRST_S_UART3 99 -#define SRST_S_UART4 100 -#define SRST_S_UART5 101 -#define SRST_S_UART6 102 -#define SRST_S_UART7 103 - -#define SRST_S_UART8 104 -#define SRST_S_UART9 105 -#define SRST_P_SPI0 106 -#define SRST_P_SPI1 107 -#define SRST_P_SPI2 108 -#define SRST_P_SPI3 109 -#define SRST_P_SPI4 110 -#define SRST_SPI0 111 -#define SRST_SPI1 112 -#define SRST_SPI2 113 -#define SRST_SPI3 114 -#define SRST_SPI4 115 - -#define SRST_P_WDT0 116 -#define SRST_T_WDT0 117 -#define SRST_P_SYS_GRF 118 -#define SRST_P_PWM1 119 -#define SRST_PWM1 120 -#define SRST_P_PWM2 121 -#define SRST_PWM2 122 -#define SRST_P_PWM3 123 -#define SRST_PWM3 124 -#define SRST_P_BUSTIMER0 125 -#define SRST_P_BUSTIMER1 126 -#define SRST_BUSTIMER0 127 - -#define SRST_BUSTIMER1 128 -#define SRST_BUSTIMER2 129 -#define SRST_BUSTIMER3 130 -#define SRST_BUSTIMER4 131 -#define SRST_BUSTIMER5 132 -#define SRST_BUSTIMER6 133 -#define SRST_BUSTIMER7 134 -#define SRST_BUSTIMER8 135 -#define SRST_BUSTIMER9 136 -#define SRST_BUSTIMER10 137 -#define SRST_BUSTIMER11 138 -#define SRST_P_MAILBOX0 139 -#define SRST_P_MAILBOX1 140 -#define SRST_P_MAILBOX2 141 -#define SRST_P_GPIO1 142 -#define SRST_GPIO1 143 - -#define SRST_P_GPIO2 144 -#define SRST_GPIO2 145 -#define SRST_P_GPIO3 146 -#define SRST_GPIO3 147 -#define SRST_P_GPIO4 148 -#define SRST_GPIO4 149 -#define SRST_A_DECOM 150 -#define SRST_P_DECOM 151 -#define SRST_D_DECOM 152 -#define SRST_P_TOP 153 -#define SRST_A_GICADB_GIC2CORE_BUS 154 -#define SRST_P_DFT2APB 155 -#define SRST_P_APB2ASB_MST_TOP 156 -#define SRST_P_APB2ASB_MST_CDPHY 157 -#define SRST_P_APB2ASB_MST_BOT_RIGHT 158 - -#define SRST_P_APB2ASB_MST_IOC_TOP 159 -#define SRST_P_APB2ASB_MST_IOC_RIGHT 160 -#define SRST_P_APB2ASB_MST_CSIPHY 161 -#define SRST_P_APB2ASB_MST_VCCIO3_5 162 -#define SRST_P_APB2ASB_MST_VCCIO6 163 -#define SRST_P_APB2ASB_MST_EMMCIO 164 -#define SRST_A_SPINLOCK 165 -#define SRST_P_OTPC_NS 166 -#define SRST_OTPC_NS 167 -#define SRST_OTPC_ARB 168 - -#define SRST_P_BUSIOC 169 -#define SRST_P_PMUCM0_INTMUX 170 -#define SRST_P_DDRCM0_INTMUX 171 - -#define SRST_P_DDR_DFICTL_CH0 172 -#define SRST_P_DDR_MON_CH0 173 -#define SRST_P_DDR_STANDBY_CH0 174 -#define SRST_P_DDR_UPCTL_CH0 175 -#define SRST_TM_DDR_MON_CH0 176 -#define SRST_P_DDR_GRF_CH01 177 -#define SRST_DFI_CH0 178 -#define SRST_SBR_CH0 179 -#define SRST_DDR_UPCTL_CH0 180 -#define SRST_DDR_DFICTL_CH0 181 -#define SRST_DDR_MON_CH0 182 -#define SRST_DDR_STANDBY_CH0 183 -#define SRST_A_DDR_UPCTL_CH0 184 -#define SRST_P_DDR_DFICTL_CH1 185 -#define SRST_P_DDR_MON_CH1 186 -#define SRST_P_DDR_STANDBY_CH1 187 - -#define SRST_P_DDR_UPCTL_CH1 188 -#define SRST_TM_DDR_MON_CH1 189 -#define SRST_DFI_CH1 190 -#define SRST_SBR_CH1 191 -#define SRST_DDR_UPCTL_CH1 192 -#define SRST_DDR_DFICTL_CH1 193 -#define SRST_DDR_MON_CH1 194 -#define SRST_DDR_STANDBY_CH1 195 -#define SRST_A_DDR_UPCTL_CH1 196 -#define SRST_A_DDR01_MSCH0 197 -#define SRST_A_DDR01_RS_MSCH0 198 -#define SRST_A_DDR01_FRS_MSCH0 199 - -#define SRST_A_DDR01_SCRAMBLE0 200 -#define SRST_A_DDR01_FRS_SCRAMBLE0 201 -#define SRST_A_DDR01_MSCH1 202 -#define SRST_A_DDR01_RS_MSCH1 203 -#define SRST_A_DDR01_FRS_MSCH1 204 -#define SRST_A_DDR01_SCRAMBLE1 205 -#define SRST_A_DDR01_FRS_SCRAMBLE1 206 -#define SRST_P_DDR01_MSCH0 207 -#define SRST_P_DDR01_MSCH1 208 - -#define SRST_P_DDR_DFICTL_CH2 209 -#define SRST_P_DDR_MON_CH2 210 -#define SRST_P_DDR_STANDBY_CH2 211 -#define SRST_P_DDR_UPCTL_CH2 212 -#define SRST_TM_DDR_MON_CH2 213 -#define SRST_P_DDR_GRF_CH23 214 -#define SRST_DFI_CH2 215 -#define SRST_SBR_CH2 216 -#define SRST_DDR_UPCTL_CH2 217 -#define SRST_DDR_DFICTL_CH2 218 -#define SRST_DDR_MON_CH2 219 -#define SRST_DDR_STANDBY_CH2 220 -#define SRST_A_DDR_UPCTL_CH2 221 -#define SRST_P_DDR_DFICTL_CH3 222 -#define SRST_P_DDR_MON_CH3 223 -#define SRST_P_DDR_STANDBY_CH3 224 - -#define SRST_P_DDR_UPCTL_CH3 225 -#define SRST_TM_DDR_MON_CH3 226 -#define SRST_DFI_CH3 227 -#define SRST_SBR_CH3 228 -#define SRST_DDR_UPCTL_CH3 229 -#define SRST_DDR_DFICTL_CH3 230 -#define SRST_DDR_MON_CH3 231 -#define SRST_DDR_STANDBY_CH3 232 -#define SRST_A_DDR_UPCTL_CH3 233 -#define SRST_A_DDR23_MSCH2 234 -#define SRST_A_DDR23_RS_MSCH2 235 -#define SRST_A_DDR23_FRS_MSCH2 236 - -#define SRST_A_DDR23_SCRAMBLE2 237 -#define SRST_A_DDR23_FRS_SCRAMBLE2 238 -#define SRST_A_DDR23_MSCH3 239 -#define SRST_A_DDR23_RS_MSCH3 240 -#define SRST_A_DDR23_FRS_MSCH3 241 -#define SRST_A_DDR23_SCRAMBLE3 242 -#define SRST_A_DDR23_FRS_SCRAMBLE3 243 -#define SRST_P_DDR23_MSCH2 244 -#define SRST_P_DDR23_MSCH3 245 - -#define SRST_ISP1 246 -#define SRST_ISP1_VICAP 247 -#define SRST_A_ISP1_BIU 248 -#define SRST_H_ISP1_BIU 249 - -#define SRST_A_RKNN1 250 -#define SRST_A_RKNN1_BIU 251 -#define SRST_H_RKNN1 252 -#define SRST_H_RKNN1_BIU 253 - -#define SRST_A_RKNN2 254 -#define SRST_A_RKNN2_BIU 255 -#define SRST_H_RKNN2 256 -#define SRST_H_RKNN2_BIU 257 - -#define SRST_A_RKNN_DSU0 258 -#define SRST_P_NPUTOP_BIU 259 -#define SRST_P_NPU_TIMER 260 -#define SRST_NPUTIMER0 261 -#define SRST_NPUTIMER1 262 -#define SRST_P_NPU_WDT 263 -#define SRST_T_NPU_WDT 264 -#define SRST_P_NPU_PVTM 265 -#define SRST_P_NPU_GRF 266 -#define SRST_NPU_PVTM 267 - -#define SRST_NPU_PVTPLL 268 -#define SRST_H_NPU_CM0_BIU 269 -#define SRST_F_NPU_CM0_CORE 270 -#define SRST_T_NPU_CM0_JTAG 271 -#define SRST_A_RKNN0 272 -#define SRST_A_RKNN0_BIU 273 -#define SRST_H_RKNN0 274 -#define SRST_H_RKNN0_BIU 275 - -#define SRST_H_NVM_BIU 276 -#define SRST_A_NVM_BIU 277 -#define SRST_H_EMMC 278 -#define SRST_A_EMMC 279 -#define SRST_C_EMMC 280 -#define SRST_B_EMMC 281 -#define SRST_T_EMMC 282 -#define SRST_S_SFC 283 -#define SRST_H_SFC 284 -#define SRST_H_SFC_XIP 285 - -#define SRST_P_GRF 286 -#define SRST_P_DEC_BIU 287 -#define SRST_P_PHP_BIU 288 -#define SRST_A_PCIE_GRIDGE 289 -#define SRST_A_PHP_BIU 290 -#define SRST_A_GMAC0 291 -#define SRST_A_GMAC1 292 -#define SRST_A_PCIE_BIU 293 -#define SRST_PCIE0_POWER_UP 294 -#define SRST_PCIE1_POWER_UP 295 -#define SRST_PCIE2_POWER_UP 296 - -#define SRST_PCIE3_POWER_UP 297 -#define SRST_PCIE4_POWER_UP 298 -#define SRST_P_PCIE0 299 -#define SRST_P_PCIE1 300 -#define SRST_P_PCIE2 301 -#define SRST_P_PCIE3 302 - -#define SRST_P_PCIE4 303 -#define SRST_A_PHP_GIC_ITS 304 -#define SRST_A_MMU_PCIE 305 -#define SRST_A_MMU_PHP 306 -#define SRST_A_MMU_BIU 307 - -#define SRST_A_USB3OTG2 308 - -#define SRST_PMALIVE0 309 -#define SRST_PMALIVE1 310 -#define SRST_PMALIVE2 311 -#define SRST_A_SATA0 312 -#define SRST_A_SATA1 313 -#define SRST_A_SATA2 314 -#define SRST_RXOOB0 315 -#define SRST_RXOOB1 316 -#define SRST_RXOOB2 317 -#define SRST_ASIC0 318 -#define SRST_ASIC1 319 -#define SRST_ASIC2 320 - -#define SRST_A_RKVDEC_CCU 321 -#define SRST_H_RKVDEC0 322 -#define SRST_A_RKVDEC0 323 -#define SRST_H_RKVDEC0_BIU 324 -#define SRST_A_RKVDEC0_BIU 325 -#define SRST_RKVDEC0_CA 326 -#define SRST_RKVDEC0_HEVC_CA 327 -#define SRST_RKVDEC0_CORE 328 - -#define SRST_H_RKVDEC1 329 -#define SRST_A_RKVDEC1 330 -#define SRST_H_RKVDEC1_BIU 331 -#define SRST_A_RKVDEC1_BIU 332 -#define SRST_RKVDEC1_CA 333 -#define SRST_RKVDEC1_HEVC_CA 334 -#define SRST_RKVDEC1_CORE 335 - -#define SRST_A_USB_BIU 336 -#define SRST_H_USB_BIU 337 -#define SRST_A_USB3OTG0 338 -#define SRST_A_USB3OTG1 339 -#define SRST_H_HOST0 340 -#define SRST_H_HOST_ARB0 341 -#define SRST_H_HOST1 342 -#define SRST_H_HOST_ARB1 343 -#define SRST_A_USB_GRF 344 -#define SRST_C_USB2P0_HOST0 345 - -#define SRST_C_USB2P0_HOST1 346 -#define SRST_HOST_UTMI0 347 -#define SRST_HOST_UTMI1 348 - -#define SRST_A_VDPU_BIU 349 -#define SRST_A_VDPU_LOW_BIU 350 -#define SRST_H_VDPU_BIU 351 -#define SRST_A_JPEG_DECODER_BIU 352 -#define SRST_A_VPU 353 -#define SRST_H_VPU 354 -#define SRST_A_JPEG_ENCODER0 355 -#define SRST_H_JPEG_ENCODER0 356 -#define SRST_A_JPEG_ENCODER1 357 -#define SRST_H_JPEG_ENCODER1 358 -#define SRST_A_JPEG_ENCODER2 359 -#define SRST_H_JPEG_ENCODER2 360 - -#define SRST_A_JPEG_ENCODER3 361 -#define SRST_H_JPEG_ENCODER3 362 -#define SRST_A_JPEG_DECODER 363 -#define SRST_H_JPEG_DECODER 364 -#define SRST_H_IEP2P0 365 -#define SRST_A_IEP2P0 366 -#define SRST_IEP2P0_CORE 367 -#define SRST_H_RGA2 368 -#define SRST_A_RGA2 369 -#define SRST_RGA2_CORE 370 -#define SRST_H_RGA3_0 371 -#define SRST_A_RGA3_0 372 -#define SRST_RGA3_0_CORE 373 - -#define SRST_H_RKVENC0_BIU 374 -#define SRST_A_RKVENC0_BIU 375 -#define SRST_H_RKVENC0 376 -#define SRST_A_RKVENC0 377 -#define SRST_RKVENC0_CORE 378 - -#define SRST_H_RKVENC1_BIU 379 -#define SRST_A_RKVENC1_BIU 380 -#define SRST_H_RKVENC1 381 -#define SRST_A_RKVENC1 382 -#define SRST_RKVENC1_CORE 383 - -#define SRST_A_VI_BIU 384 -#define SRST_H_VI_BIU 385 -#define SRST_P_VI_BIU 386 -#define SRST_D_VICAP 387 -#define SRST_A_VICAP 388 -#define SRST_H_VICAP 389 -#define SRST_ISP0 390 -#define SRST_ISP0_VICAP 391 - -#define SRST_FISHEYE0 392 -#define SRST_FISHEYE1 393 -#define SRST_P_CSI_HOST_0 394 -#define SRST_P_CSI_HOST_1 395 -#define SRST_P_CSI_HOST_2 396 -#define SRST_P_CSI_HOST_3 397 -#define SRST_P_CSI_HOST_4 398 -#define SRST_P_CSI_HOST_5 399 - -#define SRST_CSIHOST0_VICAP 400 -#define SRST_CSIHOST1_VICAP 401 -#define SRST_CSIHOST2_VICAP 402 -#define SRST_CSIHOST3_VICAP 403 -#define SRST_CSIHOST4_VICAP 404 -#define SRST_CSIHOST5_VICAP 405 -#define SRST_CIFIN 406 - -#define SRST_A_VOP_BIU 407 -#define SRST_A_VOP_LOW_BIU 408 -#define SRST_H_VOP_BIU 409 -#define SRST_P_VOP_BIU 410 -#define SRST_H_VOP 411 -#define SRST_A_VOP 412 -#define SRST_D_VOP0 413 -#define SRST_D_VOP2HDMI_BRIDGE0 414 -#define SRST_D_VOP2HDMI_BRIDGE1 415 - -#define SRST_D_VOP1 416 -#define SRST_D_VOP2 417 -#define SRST_D_VOP3 418 -#define SRST_P_VOPGRF 419 -#define SRST_P_DSIHOST0 420 -#define SRST_P_DSIHOST1 421 -#define SRST_DSIHOST0 422 -#define SRST_DSIHOST1 423 -#define SRST_VOP_PMU 424 -#define SRST_P_VOP_CHANNEL_BIU 425 - -#define SRST_H_VO0_BIU 426 -#define SRST_H_VO0_S_BIU 427 -#define SRST_P_VO0_BIU 428 -#define SRST_P_VO0_S_BIU 429 -#define SRST_A_HDCP0_BIU 430 -#define SRST_P_VO0GRF 431 -#define SRST_H_HDCP_KEY0 432 -#define SRST_A_HDCP0 433 -#define SRST_H_HDCP0 434 -#define SRST_HDCP0 435 - -#define SRST_P_TRNG0 436 -#define SRST_DP0 437 -#define SRST_DP1 438 -#define SRST_H_I2S4_8CH 439 -#define SRST_M_I2S4_8CH_TX 440 -#define SRST_H_I2S8_8CH 441 - -#define SRST_M_I2S8_8CH_TX 442 -#define SRST_H_SPDIF2_DP0 443 -#define SRST_M_SPDIF2_DP0 444 -#define SRST_H_SPDIF5_DP1 445 -#define SRST_M_SPDIF5_DP1 446 - -#define SRST_A_HDCP1_BIU 447 -#define SRST_A_VO1_BIU 448 -#define SRST_H_VOP1_BIU 449 -#define SRST_H_VOP1_S_BIU 450 -#define SRST_P_VOP1_BIU 451 -#define SRST_P_VO1GRF 452 -#define SRST_P_VO1_S_BIU 453 - -#define SRST_H_I2S7_8CH 454 -#define SRST_M_I2S7_8CH_RX 455 -#define SRST_H_HDCP_KEY1 456 -#define SRST_A_HDCP1 457 -#define SRST_H_HDCP1 458 -#define SRST_HDCP1 459 -#define SRST_P_TRNG1 460 -#define SRST_P_HDMITX0 461 - -#define SRST_HDMITX0_REF 462 -#define SRST_P_HDMITX1 463 -#define SRST_HDMITX1_REF 464 -#define SRST_A_HDMIRX 465 -#define SRST_P_HDMIRX 466 -#define SRST_HDMIRX_REF 467 - -#define SRST_P_EDP0 468 -#define SRST_EDP0_24M 469 -#define SRST_P_EDP1 470 -#define SRST_EDP1_24M 471 -#define SRST_M_I2S5_8CH_TX 472 -#define SRST_H_I2S5_8CH 473 -#define SRST_M_I2S6_8CH_TX 474 - -#define SRST_M_I2S6_8CH_RX 475 -#define SRST_H_I2S6_8CH 476 -#define SRST_H_SPDIF3 477 -#define SRST_M_SPDIF3 478 -#define SRST_H_SPDIF4 479 -#define SRST_M_SPDIF4 480 -#define SRST_H_SPDIFRX0 481 -#define SRST_M_SPDIFRX0 482 -#define SRST_H_SPDIFRX1 483 -#define SRST_M_SPDIFRX1 484 - -#define SRST_H_SPDIFRX2 485 -#define SRST_M_SPDIFRX2 486 -#define SRST_LINKSYM_HDMITXPHY0 487 -#define SRST_LINKSYM_HDMITXPHY1 488 -#define SRST_VO1_BRIDGE0 489 -#define SRST_VO1_BRIDGE1 490 - -#define SRST_H_I2S9_8CH 491 -#define SRST_M_I2S9_8CH_RX 492 -#define SRST_H_I2S10_8CH 493 -#define SRST_M_I2S10_8CH_RX 494 -#define SRST_P_S_HDMIRX 495 - -#define SRST_GPU 496 -#define SRST_SYS_GPU 497 -#define SRST_A_S_GPU_BIU 498 -#define SRST_A_M0_GPU_BIU 499 -#define SRST_A_M1_GPU_BIU 500 -#define SRST_A_M2_GPU_BIU 501 -#define SRST_A_M3_GPU_BIU 502 -#define SRST_P_GPU_BIU 503 -#define SRST_P_GPU_PVTM 504 - -#define SRST_GPU_PVTM 505 -#define SRST_P_GPU_GRF 506 -#define SRST_GPU_PVTPLL 507 -#define SRST_GPU_JTAG 508 - -#define SRST_A_AV1_BIU 509 -#define SRST_A_AV1 510 -#define SRST_P_AV1_BIU 511 -#define SRST_P_AV1 512 - -#define SRST_A_DDR_BIU 513 -#define SRST_A_DMA2DDR 514 -#define SRST_A_DDR_SHAREMEM 515 -#define SRST_A_DDR_SHAREMEM_BIU 516 -#define SRST_A_CENTER_S200_BIU 517 -#define SRST_A_CENTER_S400_BIU 518 -#define SRST_H_AHB2APB 519 -#define SRST_H_CENTER_BIU 520 -#define SRST_F_DDR_CM0_CORE 521 - -#define SRST_DDR_TIMER0 522 -#define SRST_DDR_TIMER1 523 -#define SRST_T_WDT_DDR 524 -#define SRST_T_DDR_CM0_JTAG 525 -#define SRST_P_CENTER_GRF 526 -#define SRST_P_AHB2APB 527 -#define SRST_P_WDT 528 -#define SRST_P_TIMER 529 -#define SRST_P_DMA2DDR 530 -#define SRST_P_SHAREMEM 531 -#define SRST_P_CENTER_BIU 532 -#define SRST_P_CENTER_CHANNEL_BIU 533 - -#define SRST_P_USBDPGRF0 534 -#define SRST_P_USBDPPHY0 535 -#define SRST_P_USBDPGRF1 536 -#define SRST_P_USBDPPHY1 537 -#define SRST_P_HDPTX0 538 -#define SRST_P_HDPTX1 539 -#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540 -#define SRST_P_USB2PHY_U3_0_GRF0 541 -#define SRST_P_USB2PHY_U3_1_GRF0 542 -#define SRST_P_USB2PHY_U2_0_GRF0 543 -#define SRST_P_USB2PHY_U2_1_GRF0 544 -#define SRST_HDPTX0_ROPLL 545 -#define SRST_HDPTX0_LCPLL 546 -#define SRST_HDPTX0 547 -#define SRST_HDPTX1_ROPLL 548 - -#define SRST_HDPTX1_LCPLL 549 -#define SRST_HDPTX1 550 -#define SRST_HDPTX0_HDMIRXPHY_SET 551 -#define SRST_USBDP_COMBO_PHY0 552 -#define SRST_USBDP_COMBO_PHY0_LCPLL 553 -#define SRST_USBDP_COMBO_PHY0_ROPLL 554 -#define SRST_USBDP_COMBO_PHY0_PCS_HS 555 -#define SRST_USBDP_COMBO_PHY1 556 -#define SRST_USBDP_COMBO_PHY1_LCPLL 557 -#define SRST_USBDP_COMBO_PHY1_ROPLL 558 -#define SRST_USBDP_COMBO_PHY1_PCS_HS 559 -#define SRST_HDMIHDP0 560 -#define SRST_HDMIHDP1 561 - -#define SRST_A_VO1USB_TOP_BIU 562 -#define SRST_H_VO1USB_TOP_BIU 563 - -#define SRST_H_SDIO_BIU 564 -#define SRST_H_SDIO 565 -#define SRST_SDIO 566 - -#define SRST_H_RGA3_BIU 567 -#define SRST_A_RGA3_BIU 568 -#define SRST_H_RGA3_1 569 -#define SRST_A_RGA3_1 570 -#define SRST_RGA3_1_CORE 571 - -#define SRST_REF_PIPE_PHY0 572 -#define SRST_REF_PIPE_PHY1 573 -#define SRST_REF_PIPE_PHY2 574 - -#define SRST_P_PHPTOP_CRU 575 -#define SRST_P_PCIE2_GRF0 576 -#define SRST_P_PCIE2_GRF1 577 -#define SRST_P_PCIE2_GRF2 578 -#define SRST_P_PCIE2_PHY0 579 -#define SRST_P_PCIE2_PHY1 580 -#define SRST_P_PCIE2_PHY2 581 -#define SRST_P_PCIE3_PHY 582 -#define SRST_P_APB2ASB_SLV_CHIP_TOP 583 -#define SRST_PCIE30_PHY 584 - -#define SRST_H_PMU1_BIU 585 -#define SRST_P_PMU1_BIU 586 -#define SRST_H_PMU_CM0_BIU 587 -#define SRST_F_PMU_CM0_CORE 588 -#define SRST_T_PMU1_CM0_JTAG 589 - -#define SRST_DDR_FAIL_SAFE 590 -#define SRST_P_CRU_PMU1 591 -#define SRST_P_PMU1_GRF 592 -#define SRST_P_PMU1_IOC 593 -#define SRST_P_PMU1WDT 594 -#define SRST_T_PMU1WDT 595 -#define SRST_P_PMU1TIMER 596 -#define SRST_PMU1TIMER0 597 -#define SRST_PMU1TIMER1 598 -#define SRST_P_PMU1PWM 599 -#define SRST_PMU1PWM 600 - -#define SRST_P_I2C0 601 -#define SRST_I2C0 602 -#define SRST_S_UART0 603 -#define SRST_P_UART0 604 -#define SRST_H_I2S1_8CH 605 -#define SRST_M_I2S1_8CH_TX 606 -#define SRST_M_I2S1_8CH_RX 607 -#define SRST_H_PDM0 608 -#define SRST_PDM0 609 - -#define SRST_H_VAD 610 -#define SRST_HDPTX0_INIT 611 -#define SRST_HDPTX0_CMN 612 -#define SRST_HDPTX0_LANE 613 -#define SRST_HDPTX1_INIT 614 - -#define SRST_HDPTX1_CMN 615 -#define SRST_HDPTX1_LANE 616 -#define SRST_M_MIPI_DCPHY0 617 -#define SRST_S_MIPI_DCPHY0 618 -#define SRST_M_MIPI_DCPHY1 619 -#define SRST_S_MIPI_DCPHY1 620 -#define SRST_OTGPHY_U3_0 621 -#define SRST_OTGPHY_U3_1 622 -#define SRST_OTGPHY_U2_0 623 -#define SRST_OTGPHY_U2_1 624 - -#define SRST_P_PMU0GRF 625 -#define SRST_P_PMU0IOC 626 -#define SRST_P_GPIO0 627 -#define SRST_GPIO0 628 - -#define SRST_A_SECURE_NS_BIU 629 -#define SRST_H_SECURE_NS_BIU 630 -#define SRST_A_SECURE_S_BIU 631 -#define SRST_H_SECURE_S_BIU 632 -#define SRST_P_SECURE_S_BIU 633 -#define SRST_CRYPTO_CORE 634 - -#define SRST_CRYPTO_PKA 635 -#define SRST_CRYPTO_RNG 636 -#define SRST_A_CRYPTO 637 -#define SRST_H_CRYPTO 638 -#define SRST_KEYLADDER_CORE 639 -#define SRST_KEYLADDER_RNG 640 -#define SRST_A_KEYLADDER 641 -#define SRST_H_KEYLADDER 642 -#define SRST_P_OTPC_S 643 -#define SRST_OTPC_S 644 -#define SRST_WDT_S 645 - -#define SRST_T_WDT_S 646 -#define SRST_H_BOOTROM 647 -#define SRST_A_DCF 648 -#define SRST_P_DCF 649 -#define SRST_H_BOOTROM_NS 650 -#define SRST_P_KEYLADDER 651 -#define SRST_H_TRNG_S 652 - -#define SRST_H_TRNG_NS 653 -#define SRST_D_SDMMC_BUFFER 654 -#define SRST_H_SDMMC 655 -#define SRST_H_SDMMC_BUFFER 656 -#define SRST_SDMMC 657 -#define SRST_P_TRNG_CHK 658 -#define SRST_TRNG_S 659 - -#endif diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h deleted file mode 100644 index 4b0914c0989d..000000000000 --- a/include/dt-bindings/soc/rockchip,boot-mode.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ROCKCHIP_BOOT_MODE_H -#define __ROCKCHIP_BOOT_MODE_H - -/*high 24 bits is tag, low 8 bits is type*/ -#define REBOOT_FLAG 0x5242C300 -/* normal boot */ -#define BOOT_NORMAL (REBOOT_FLAG + 0) -/* enter bootloader rockusb mode */ -#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) -/* enter recovery */ -#define BOOT_RECOVERY (REBOOT_FLAG + 3) - /* enter fastboot mode */ -#define BOOT_FASTBOOT (REBOOT_FLAG + 9) - -#endif diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h deleted file mode 100644 index 668f199df9f0..000000000000 --- a/include/dt-bindings/soc/rockchip,vop2.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ - -#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H -#define __DT_BINDINGS_ROCKCHIP_VOP2_H - -#define ROCKCHIP_VOP2_EP_RGB0 1 -#define ROCKCHIP_VOP2_EP_HDMI0 2 -#define ROCKCHIP_VOP2_EP_EDP0 3 -#define ROCKCHIP_VOP2_EP_MIPI0 4 -#define ROCKCHIP_VOP2_EP_LVDS0 5 -#define ROCKCHIP_VOP2_EP_MIPI1 6 -#define ROCKCHIP_VOP2_EP_LVDS1 7 -#define ROCKCHIP_VOP2_EP_HDMI1 8 -#define ROCKCHIP_VOP2_EP_EDP1 9 -#define ROCKCHIP_VOP2_EP_DP0 10 -#define ROCKCHIP_VOP2_EP_DP1 11 - -#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */

Drop in favour of dts/upstream.

Small driver and DTS adjustments to use upstream headers.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/dts/exynos7420.dtsi | 2 +- drivers/clk/exynos/clk-exynos7420.c | 2 +- include/dt-bindings/clock/exynos7420-clk.h | 207 ---------------- include/dt-bindings/clock/exynos850.h | 337 --------------------------- include/dt-bindings/soc/samsung,exynos-usi.h | 17 -- 5 files changed, 2 insertions(+), 563 deletions(-)

diff --git a/arch/arm/dts/exynos7420.dtsi b/arch/arm/dts/exynos7420.dtsi index 373f48cf2eca..ba9666f3de01 100644 --- a/arch/arm/dts/exynos7420.dtsi +++ b/arch/arm/dts/exynos7420.dtsi @@ -7,9 +7,9 @@ */

/dts-v1/; #include "skeleton.dtsi" -#include <dt-bindings/clock/exynos7420-clk.h> +#include <dt-bindings/clock/exynos7-clk.h> / { compatible = "samsung,exynos7420";

fin_pll: xxti { diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 9caa932e12fb..cd6d67a0752b 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -10,9 +10,9 @@ #include <errno.h> #include <clk-uclass.h> #include <asm/io.h> #include <div64.h> -#include <dt-bindings/clock/exynos7420-clk.h> +#include <dt-bindings/clock/exynos7-clk.h>

#define PLL145X_MDIV_SHIFT 16 #define PLL145X_MDIV_MASK 0x3ff #define PLL145X_PDIV_SHIFT 8 diff --git a/include/dt-bindings/clock/exynos7420-clk.h b/include/dt-bindings/clock/exynos7420-clk.h deleted file mode 100644 index 10c558611085..000000000000 --- a/include/dt-bindings/clock/exynos7420-clk.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * Author: Naveen Krishna Ch naveenkrishna.ch@gmail.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H -#define _DT_BINDINGS_CLOCK_EXYNOS7_H - -/* TOPC */ -#define DOUT_ACLK_PERIS 1 -#define DOUT_SCLK_BUS0_PLL 2 -#define DOUT_SCLK_BUS1_PLL 3 -#define DOUT_SCLK_CC_PLL 4 -#define DOUT_SCLK_MFC_PLL 5 -#define DOUT_ACLK_CCORE_133 6 -#define DOUT_ACLK_MSCL_532 7 -#define ACLK_MSCL_532 8 -#define DOUT_SCLK_AUD_PLL 9 -#define FOUT_AUD_PLL 10 -#define SCLK_AUD_PLL 11 -#define SCLK_MFC_PLL_B 12 -#define SCLK_MFC_PLL_A 13 -#define SCLK_BUS1_PLL_B 14 -#define SCLK_BUS1_PLL_A 15 -#define SCLK_BUS0_PLL_B 16 -#define SCLK_BUS0_PLL_A 17 -#define SCLK_CC_PLL_B 18 -#define SCLK_CC_PLL_A 19 -#define ACLK_CCORE_133 20 -#define ACLK_PERIS_66 21 -#define TOPC_NR_CLK 22 - -/* TOP0 */ -#define DOUT_ACLK_PERIC1 1 -#define DOUT_ACLK_PERIC0 2 -#define CLK_SCLK_UART0 3 -#define CLK_SCLK_UART1 4 -#define CLK_SCLK_UART2 5 -#define CLK_SCLK_UART3 6 -#define CLK_SCLK_SPI0 7 -#define CLK_SCLK_SPI1 8 -#define CLK_SCLK_SPI2 9 -#define CLK_SCLK_SPI3 10 -#define CLK_SCLK_SPI4 11 -#define CLK_SCLK_SPDIF 12 -#define CLK_SCLK_PCM1 13 -#define CLK_SCLK_I2S1 14 -#define CLK_ACLK_PERIC0_66 15 -#define CLK_ACLK_PERIC1_66 16 -#define TOP0_NR_CLK 17 - -/* TOP1 */ -#define DOUT_ACLK_FSYS1_200 1 -#define DOUT_ACLK_FSYS0_200 2 -#define DOUT_SCLK_MMC2 3 -#define DOUT_SCLK_MMC1 4 -#define DOUT_SCLK_MMC0 5 -#define CLK_SCLK_MMC2 6 -#define CLK_SCLK_MMC1 7 -#define CLK_SCLK_MMC0 8 -#define CLK_ACLK_FSYS0_200 9 -#define CLK_ACLK_FSYS1_200 10 -#define CLK_SCLK_PHY_FSYS1 11 -#define CLK_SCLK_PHY_FSYS1_26M 12 -#define MOUT_SCLK_UFSUNIPRO20 13 -#define DOUT_SCLK_UFSUNIPRO20 14 -#define CLK_SCLK_UFSUNIPRO20 15 -#define DOUT_SCLK_PHY_FSYS1 16 -#define DOUT_SCLK_PHY_FSYS1_26M 17 -#define TOP1_NR_CLK 18 - -/* CCORE */ -#define PCLK_RTC 1 -#define CCORE_NR_CLK 2 - -/* PERIC0 */ -#define PCLK_UART0 1 -#define SCLK_UART0 2 -#define PCLK_HSI2C0 3 -#define PCLK_HSI2C1 4 -#define PCLK_HSI2C4 5 -#define PCLK_HSI2C5 6 -#define PCLK_HSI2C9 7 -#define PCLK_HSI2C10 8 -#define PCLK_HSI2C11 9 -#define PCLK_PWM 10 -#define SCLK_PWM 11 -#define PCLK_ADCIF 12 -#define PERIC0_NR_CLK 13 - -/* PERIC1 */ -#define PCLK_UART1 1 -#define PCLK_UART2 2 -#define PCLK_UART3 3 -#define SCLK_UART1 4 -#define SCLK_UART2 5 -#define SCLK_UART3 6 -#define PCLK_HSI2C2 7 -#define PCLK_HSI2C3 8 -#define PCLK_HSI2C6 9 -#define PCLK_HSI2C7 10 -#define PCLK_HSI2C8 11 -#define PCLK_SPI0 12 -#define PCLK_SPI1 13 -#define PCLK_SPI2 14 -#define PCLK_SPI3 15 -#define PCLK_SPI4 16 -#define SCLK_SPI0 17 -#define SCLK_SPI1 18 -#define SCLK_SPI2 19 -#define SCLK_SPI3 20 -#define SCLK_SPI4 21 -#define PCLK_I2S1 22 -#define PCLK_PCM1 23 -#define PCLK_SPDIF 24 -#define SCLK_I2S1 25 -#define SCLK_PCM1 26 -#define SCLK_SPDIF 27 -#define PERIC1_NR_CLK 28 - -/* PERIS */ -#define PCLK_CHIPID 1 -#define SCLK_CHIPID 2 -#define PCLK_WDT 3 -#define PCLK_TMU 4 -#define SCLK_TMU 5 -#define PERIS_NR_CLK 6 - -/* FSYS0 */ -#define ACLK_MMC2 1 -#define ACLK_AXIUS_USBDRD30X_FSYS0X 2 -#define ACLK_USBDRD300 3 -#define SCLK_USBDRD300_SUSPENDCLK 4 -#define SCLK_USBDRD300_REFCLK 5 -#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 -#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 -#define OSCCLK_PHY_CLKOUT_USB30_PHY 8 -#define ACLK_PDMA0 9 -#define ACLK_PDMA1 10 -#define FSYS0_NR_CLK 11 - -/* FSYS1 */ -#define ACLK_MMC1 1 -#define ACLK_MMC0 2 -#define PHYCLK_UFS20_TX0_SYMBOL 3 -#define PHYCLK_UFS20_RX0_SYMBOL 4 -#define PHYCLK_UFS20_RX1_SYMBOL 5 -#define ACLK_UFS20_LINK 6 -#define SCLK_UFSUNIPRO20_USER 7 -#define PHYCLK_UFS20_RX1_SYMBOL_USER 8 -#define PHYCLK_UFS20_RX0_SYMBOL_USER 9 -#define PHYCLK_UFS20_TX0_SYMBOL_USER 10 -#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11 -#define SCLK_COMBO_PHY_EMBEDDED_26M 12 -#define DOUT_PCLK_FSYS1 13 -#define PCLK_GPIO_FSYS1 14 -#define MOUT_FSYS1_PHYCLK_SEL1 15 -#define FSYS1_NR_CLK 16 - -/* MSCL */ -#define USERMUX_ACLK_MSCL_532 1 -#define DOUT_PCLK_MSCL 2 -#define ACLK_MSCL_0 3 -#define ACLK_MSCL_1 4 -#define ACLK_JPEG 5 -#define ACLK_G2D 6 -#define ACLK_LH_ASYNC_SI_MSCL_0 7 -#define ACLK_LH_ASYNC_SI_MSCL_1 8 -#define ACLK_AXI2ACEL_BRIDGE 9 -#define ACLK_XIU_MSCLX_0 10 -#define ACLK_XIU_MSCLX_1 11 -#define ACLK_QE_MSCL_0 12 -#define ACLK_QE_MSCL_1 13 -#define ACLK_QE_JPEG 14 -#define ACLK_QE_G2D 15 -#define ACLK_PPMU_MSCL_0 16 -#define ACLK_PPMU_MSCL_1 17 -#define ACLK_MSCLNP_133 18 -#define ACLK_AHB2APB_MSCL0P 19 -#define ACLK_AHB2APB_MSCL1P 20 - -#define PCLK_MSCL_0 21 -#define PCLK_MSCL_1 22 -#define PCLK_JPEG 23 -#define PCLK_G2D 24 -#define PCLK_QE_MSCL_0 25 -#define PCLK_QE_MSCL_1 26 -#define PCLK_QE_JPEG 27 -#define PCLK_QE_G2D 28 -#define PCLK_PPMU_MSCL_0 29 -#define PCLK_PPMU_MSCL_1 30 -#define PCLK_AXI2ACEL_BRIDGE 31 -#define PCLK_PMU_MSCL 32 -#define MSCL_NR_CLK 33 - -/* AUD */ -#define SCLK_I2S 1 -#define SCLK_PCM 2 -#define PCLK_I2S 3 -#define PCLK_PCM 4 -#define ACLK_ADMA 5 -#define AUD_NR_CLK 6 -#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h deleted file mode 100644 index 3090e09c9a55..000000000000 --- a/include/dt-bindings/clock/exynos850.h +++ /dev/null @@ -1,337 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (C) 2021 Linaro Ltd. - * Author: Sam Protsenko semen.protsenko@linaro.org - * - * Device Tree binding constants for Exynos850 clock controller. - */ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H -#define _DT_BINDINGS_CLOCK_EXYNOS_850_H - -/* CMU_TOP */ -#define CLK_FOUT_SHARED0_PLL 1 -#define CLK_FOUT_SHARED1_PLL 2 -#define CLK_FOUT_MMC_PLL 3 -#define CLK_MOUT_SHARED0_PLL 4 -#define CLK_MOUT_SHARED1_PLL 5 -#define CLK_MOUT_MMC_PLL 6 -#define CLK_MOUT_CORE_BUS 7 -#define CLK_MOUT_CORE_CCI 8 -#define CLK_MOUT_CORE_MMC_EMBD 9 -#define CLK_MOUT_CORE_SSS 10 -#define CLK_MOUT_DPU 11 -#define CLK_MOUT_HSI_BUS 12 -#define CLK_MOUT_HSI_MMC_CARD 13 -#define CLK_MOUT_HSI_USB20DRD 14 -#define CLK_MOUT_PERI_BUS 15 -#define CLK_MOUT_PERI_UART 16 -#define CLK_MOUT_PERI_IP 17 -#define CLK_DOUT_SHARED0_DIV3 18 -#define CLK_DOUT_SHARED0_DIV2 19 -#define CLK_DOUT_SHARED1_DIV3 20 -#define CLK_DOUT_SHARED1_DIV2 21 -#define CLK_DOUT_SHARED0_DIV4 22 -#define CLK_DOUT_SHARED1_DIV4 23 -#define CLK_DOUT_CORE_BUS 24 -#define CLK_DOUT_CORE_CCI 25 -#define CLK_DOUT_CORE_MMC_EMBD 26 -#define CLK_DOUT_CORE_SSS 27 -#define CLK_DOUT_DPU 28 -#define CLK_DOUT_HSI_BUS 29 -#define CLK_DOUT_HSI_MMC_CARD 30 -#define CLK_DOUT_HSI_USB20DRD 31 -#define CLK_DOUT_PERI_BUS 32 -#define CLK_DOUT_PERI_UART 33 -#define CLK_DOUT_PERI_IP 34 -#define CLK_GOUT_CORE_BUS 35 -#define CLK_GOUT_CORE_CCI 36 -#define CLK_GOUT_CORE_MMC_EMBD 37 -#define CLK_GOUT_CORE_SSS 38 -#define CLK_GOUT_DPU 39 -#define CLK_GOUT_HSI_BUS 40 -#define CLK_GOUT_HSI_MMC_CARD 41 -#define CLK_GOUT_HSI_USB20DRD 42 -#define CLK_GOUT_PERI_BUS 43 -#define CLK_GOUT_PERI_UART 44 -#define CLK_GOUT_PERI_IP 45 -#define CLK_MOUT_CLKCMU_APM_BUS 46 -#define CLK_DOUT_CLKCMU_APM_BUS 47 -#define CLK_GOUT_CLKCMU_APM_BUS 48 -#define CLK_MOUT_AUD 49 -#define CLK_GOUT_AUD 50 -#define CLK_DOUT_AUD 51 -#define CLK_MOUT_IS_BUS 52 -#define CLK_MOUT_IS_ITP 53 -#define CLK_MOUT_IS_VRA 54 -#define CLK_MOUT_IS_GDC 55 -#define CLK_GOUT_IS_BUS 56 -#define CLK_GOUT_IS_ITP 57 -#define CLK_GOUT_IS_VRA 58 -#define CLK_GOUT_IS_GDC 59 -#define CLK_DOUT_IS_BUS 60 -#define CLK_DOUT_IS_ITP 61 -#define CLK_DOUT_IS_VRA 62 -#define CLK_DOUT_IS_GDC 63 -#define CLK_MOUT_MFCMSCL_MFC 64 -#define CLK_MOUT_MFCMSCL_M2M 65 -#define CLK_MOUT_MFCMSCL_MCSC 66 -#define CLK_MOUT_MFCMSCL_JPEG 67 -#define CLK_GOUT_MFCMSCL_MFC 68 -#define CLK_GOUT_MFCMSCL_M2M 69 -#define CLK_GOUT_MFCMSCL_MCSC 70 -#define CLK_GOUT_MFCMSCL_JPEG 71 -#define CLK_DOUT_MFCMSCL_MFC 72 -#define CLK_DOUT_MFCMSCL_M2M 73 -#define CLK_DOUT_MFCMSCL_MCSC 74 -#define CLK_DOUT_MFCMSCL_JPEG 75 -#define CLK_MOUT_G3D_SWITCH 76 -#define CLK_GOUT_G3D_SWITCH 77 -#define CLK_DOUT_G3D_SWITCH 78 - -/* CMU_APM */ -#define CLK_RCO_I3C_PMIC 1 -#define OSCCLK_RCO_APM 2 -#define CLK_RCO_APM__ALV 3 -#define CLK_DLL_DCO 4 -#define CLK_MOUT_APM_BUS_USER 5 -#define CLK_MOUT_RCO_APM_I3C_USER 6 -#define CLK_MOUT_RCO_APM_USER 7 -#define CLK_MOUT_DLL_USER 8 -#define CLK_MOUT_CLKCMU_CHUB_BUS 9 -#define CLK_MOUT_APM_BUS 10 -#define CLK_MOUT_APM_I3C 11 -#define CLK_DOUT_CLKCMU_CHUB_BUS 12 -#define CLK_DOUT_APM_BUS 13 -#define CLK_DOUT_APM_I3C 14 -#define CLK_GOUT_CLKCMU_CMGP_BUS 15 -#define CLK_GOUT_CLKCMU_CHUB_BUS 16 -#define CLK_GOUT_RTC_PCLK 17 -#define CLK_GOUT_TOP_RTC_PCLK 18 -#define CLK_GOUT_I3C_PCLK 19 -#define CLK_GOUT_I3C_SCLK 20 -#define CLK_GOUT_SPEEDY_PCLK 21 -#define CLK_GOUT_GPIO_ALIVE_PCLK 22 -#define CLK_GOUT_PMU_ALIVE_PCLK 23 -#define CLK_GOUT_SYSREG_APM_PCLK 24 - -/* CMU_AUD */ -#define CLK_DOUT_AUD_AUDIF 1 -#define CLK_DOUT_AUD_BUSD 2 -#define CLK_DOUT_AUD_BUSP 3 -#define CLK_DOUT_AUD_CNT 4 -#define CLK_DOUT_AUD_CPU 5 -#define CLK_DOUT_AUD_CPU_ACLK 6 -#define CLK_DOUT_AUD_CPU_PCLKDBG 7 -#define CLK_DOUT_AUD_FM 8 -#define CLK_DOUT_AUD_FM_SPDY 9 -#define CLK_DOUT_AUD_MCLK 10 -#define CLK_DOUT_AUD_UAIF0 11 -#define CLK_DOUT_AUD_UAIF1 12 -#define CLK_DOUT_AUD_UAIF2 13 -#define CLK_DOUT_AUD_UAIF3 14 -#define CLK_DOUT_AUD_UAIF4 15 -#define CLK_DOUT_AUD_UAIF5 16 -#define CLK_DOUT_AUD_UAIF6 17 -#define CLK_FOUT_AUD_PLL 18 -#define CLK_GOUT_AUD_ABOX_ACLK 19 -#define CLK_GOUT_AUD_ASB_CCLK 20 -#define CLK_GOUT_AUD_CA32_CCLK 21 -#define CLK_GOUT_AUD_CNT_BCLK 22 -#define CLK_GOUT_AUD_CODEC_MCLK 23 -#define CLK_GOUT_AUD_DAP_CCLK 24 -#define CLK_GOUT_AUD_GPIO_PCLK 25 -#define CLK_GOUT_AUD_PPMU_ACLK 26 -#define CLK_GOUT_AUD_PPMU_PCLK 27 -#define CLK_GOUT_AUD_SPDY_BCLK 28 -#define CLK_GOUT_AUD_SYSMMU_CLK 29 -#define CLK_GOUT_AUD_SYSREG_PCLK 30 -#define CLK_GOUT_AUD_TZPC_PCLK 31 -#define CLK_GOUT_AUD_UAIF0_BCLK 32 -#define CLK_GOUT_AUD_UAIF1_BCLK 33 -#define CLK_GOUT_AUD_UAIF2_BCLK 34 -#define CLK_GOUT_AUD_UAIF3_BCLK 35 -#define CLK_GOUT_AUD_UAIF4_BCLK 36 -#define CLK_GOUT_AUD_UAIF5_BCLK 37 -#define CLK_GOUT_AUD_UAIF6_BCLK 38 -#define CLK_GOUT_AUD_WDT_PCLK 39 -#define CLK_MOUT_AUD_CPU 40 -#define CLK_MOUT_AUD_CPU_HCH 41 -#define CLK_MOUT_AUD_CPU_USER 42 -#define CLK_MOUT_AUD_FM 43 -#define CLK_MOUT_AUD_PLL 44 -#define CLK_MOUT_AUD_TICK_USB_USER 45 -#define CLK_MOUT_AUD_UAIF0 46 -#define CLK_MOUT_AUD_UAIF1 47 -#define CLK_MOUT_AUD_UAIF2 48 -#define CLK_MOUT_AUD_UAIF3 49 -#define CLK_MOUT_AUD_UAIF4 50 -#define CLK_MOUT_AUD_UAIF5 51 -#define CLK_MOUT_AUD_UAIF6 52 -#define IOCLK_AUDIOCDCLK0 53 -#define IOCLK_AUDIOCDCLK1 54 -#define IOCLK_AUDIOCDCLK2 55 -#define IOCLK_AUDIOCDCLK3 56 -#define IOCLK_AUDIOCDCLK4 57 -#define IOCLK_AUDIOCDCLK5 58 -#define IOCLK_AUDIOCDCLK6 59 -#define TICK_USB 60 -#define CLK_GOUT_AUD_CMU_AUD_PCLK 61 - -/* CMU_CMGP */ -#define CLK_RCO_CMGP 1 -#define CLK_MOUT_CMGP_ADC 2 -#define CLK_MOUT_CMGP_USI0 3 -#define CLK_MOUT_CMGP_USI1 4 -#define CLK_DOUT_CMGP_ADC 5 -#define CLK_DOUT_CMGP_USI0 6 -#define CLK_DOUT_CMGP_USI1 7 -#define CLK_GOUT_CMGP_ADC_S0_PCLK 8 -#define CLK_GOUT_CMGP_ADC_S1_PCLK 9 -#define CLK_GOUT_CMGP_GPIO_PCLK 10 -#define CLK_GOUT_CMGP_USI0_IPCLK 11 -#define CLK_GOUT_CMGP_USI0_PCLK 12 -#define CLK_GOUT_CMGP_USI1_IPCLK 13 -#define CLK_GOUT_CMGP_USI1_PCLK 14 -#define CLK_GOUT_SYSREG_CMGP_PCLK 15 - -/* CMU_G3D */ -#define CLK_FOUT_G3D_PLL 1 -#define CLK_MOUT_G3D_PLL 2 -#define CLK_MOUT_G3D_SWITCH_USER 3 -#define CLK_MOUT_G3D_BUSD 4 -#define CLK_DOUT_G3D_BUSP 5 -#define CLK_GOUT_G3D_CMU_G3D_PCLK 6 -#define CLK_GOUT_G3D_GPU_CLK 7 -#define CLK_GOUT_G3D_TZPC_PCLK 8 -#define CLK_GOUT_G3D_GRAY2BIN_CLK 9 -#define CLK_GOUT_G3D_BUSD_CLK 10 -#define CLK_GOUT_G3D_BUSP_CLK 11 -#define CLK_GOUT_G3D_SYSREG_PCLK 12 - -/* CMU_HSI */ -#define CLK_MOUT_HSI_BUS_USER 1 -#define CLK_MOUT_HSI_MMC_CARD_USER 2 -#define CLK_MOUT_HSI_USB20DRD_USER 3 -#define CLK_MOUT_HSI_RTC 4 -#define CLK_GOUT_USB_RTC_CLK 5 -#define CLK_GOUT_USB_REF_CLK 6 -#define CLK_GOUT_USB_PHY_REF_CLK 7 -#define CLK_GOUT_USB_PHY_ACLK 8 -#define CLK_GOUT_USB_BUS_EARLY_CLK 9 -#define CLK_GOUT_GPIO_HSI_PCLK 10 -#define CLK_GOUT_MMC_CARD_ACLK 11 -#define CLK_GOUT_MMC_CARD_SDCLKIN 12 -#define CLK_GOUT_SYSREG_HSI_PCLK 13 -#define CLK_GOUT_HSI_PPMU_ACLK 14 -#define CLK_GOUT_HSI_PPMU_PCLK 15 -#define CLK_GOUT_HSI_CMU_HSI_PCLK 16 - -/* CMU_IS */ -#define CLK_MOUT_IS_BUS_USER 1 -#define CLK_MOUT_IS_ITP_USER 2 -#define CLK_MOUT_IS_VRA_USER 3 -#define CLK_MOUT_IS_GDC_USER 4 -#define CLK_DOUT_IS_BUSP 5 -#define CLK_GOUT_IS_CMU_IS_PCLK 6 -#define CLK_GOUT_IS_CSIS0_ACLK 7 -#define CLK_GOUT_IS_CSIS1_ACLK 8 -#define CLK_GOUT_IS_CSIS2_ACLK 9 -#define CLK_GOUT_IS_TZPC_PCLK 10 -#define CLK_GOUT_IS_CSIS_DMA_CLK 11 -#define CLK_GOUT_IS_GDC_CLK 12 -#define CLK_GOUT_IS_IPP_CLK 13 -#define CLK_GOUT_IS_ITP_CLK 14 -#define CLK_GOUT_IS_MCSC_CLK 15 -#define CLK_GOUT_IS_VRA_CLK 16 -#define CLK_GOUT_IS_PPMU_IS0_ACLK 17 -#define CLK_GOUT_IS_PPMU_IS0_PCLK 18 -#define CLK_GOUT_IS_PPMU_IS1_ACLK 19 -#define CLK_GOUT_IS_PPMU_IS1_PCLK 20 -#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 -#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 -#define CLK_GOUT_IS_SYSREG_PCLK 23 - -/* CMU_MFCMSCL */ -#define CLK_MOUT_MFCMSCL_MFC_USER 1 -#define CLK_MOUT_MFCMSCL_M2M_USER 2 -#define CLK_MOUT_MFCMSCL_MCSC_USER 3 -#define CLK_MOUT_MFCMSCL_JPEG_USER 4 -#define CLK_DOUT_MFCMSCL_BUSP 5 -#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6 -#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7 -#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8 -#define CLK_GOUT_MFCMSCL_M2M_ACLK 9 -#define CLK_GOUT_MFCMSCL_MCSC_CLK 10 -#define CLK_GOUT_MFCMSCL_MFC_ACLK 11 -#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12 -#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13 -#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14 -#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15 - -/* CMU_PERI */ -#define CLK_MOUT_PERI_BUS_USER 1 -#define CLK_MOUT_PERI_UART_USER 2 -#define CLK_MOUT_PERI_HSI2C_USER 3 -#define CLK_MOUT_PERI_SPI_USER 4 -#define CLK_DOUT_PERI_HSI2C0 5 -#define CLK_DOUT_PERI_HSI2C1 6 -#define CLK_DOUT_PERI_HSI2C2 7 -#define CLK_DOUT_PERI_SPI0 8 -#define CLK_GOUT_PERI_HSI2C0 9 -#define CLK_GOUT_PERI_HSI2C1 10 -#define CLK_GOUT_PERI_HSI2C2 11 -#define CLK_GOUT_GPIO_PERI_PCLK 12 -#define CLK_GOUT_HSI2C0_IPCLK 13 -#define CLK_GOUT_HSI2C0_PCLK 14 -#define CLK_GOUT_HSI2C1_IPCLK 15 -#define CLK_GOUT_HSI2C1_PCLK 16 -#define CLK_GOUT_HSI2C2_IPCLK 17 -#define CLK_GOUT_HSI2C2_PCLK 18 -#define CLK_GOUT_I2C0_PCLK 19 -#define CLK_GOUT_I2C1_PCLK 20 -#define CLK_GOUT_I2C2_PCLK 21 -#define CLK_GOUT_I2C3_PCLK 22 -#define CLK_GOUT_I2C4_PCLK 23 -#define CLK_GOUT_I2C5_PCLK 24 -#define CLK_GOUT_I2C6_PCLK 25 -#define CLK_GOUT_MCT_PCLK 26 -#define CLK_GOUT_PWM_MOTOR_PCLK 27 -#define CLK_GOUT_SPI0_IPCLK 28 -#define CLK_GOUT_SPI0_PCLK 29 -#define CLK_GOUT_SYSREG_PERI_PCLK 30 -#define CLK_GOUT_UART_IPCLK 31 -#define CLK_GOUT_UART_PCLK 32 -#define CLK_GOUT_WDT0_PCLK 33 -#define CLK_GOUT_WDT1_PCLK 34 - -/* CMU_CORE */ -#define CLK_MOUT_CORE_BUS_USER 1 -#define CLK_MOUT_CORE_CCI_USER 2 -#define CLK_MOUT_CORE_MMC_EMBD_USER 3 -#define CLK_MOUT_CORE_SSS_USER 4 -#define CLK_MOUT_CORE_GIC 5 -#define CLK_DOUT_CORE_BUSP 6 -#define CLK_GOUT_CCI_ACLK 7 -#define CLK_GOUT_GIC_CLK 8 -#define CLK_GOUT_MMC_EMBD_ACLK 9 -#define CLK_GOUT_MMC_EMBD_SDCLKIN 10 -#define CLK_GOUT_SSS_ACLK 11 -#define CLK_GOUT_SSS_PCLK 12 -#define CLK_GOUT_GPIO_CORE_PCLK 13 -#define CLK_GOUT_SYSREG_CORE_PCLK 14 - -/* CMU_DPU */ -#define CLK_MOUT_DPU_USER 1 -#define CLK_DOUT_DPU_BUSP 2 -#define CLK_GOUT_DPU_CMU_DPU_PCLK 3 -#define CLK_GOUT_DPU_DECON0_ACLK 4 -#define CLK_GOUT_DPU_DMA_ACLK 5 -#define CLK_GOUT_DPU_DPP_ACLK 6 -#define CLK_GOUT_DPU_PPMU_ACLK 7 -#define CLK_GOUT_DPU_PPMU_PCLK 8 -#define CLK_GOUT_DPU_SMMU_CLK 9 -#define CLK_GOUT_DPU_SYSREG_PCLK 10 -#define DPU_NR_CLK 11 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h deleted file mode 100644 index a01af169d249..000000000000 --- a/include/dt-bindings/soc/samsung,exynos-usi.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2021 Linaro Ltd. - * Author: Sam Protsenko semen.protsenko@linaro.org - * - * Device Tree bindings for Samsung Exynos USI (Universal Serial Interface). - */ - -#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H -#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H - -#define USI_V2_NONE 0 -#define USI_V2_UART 1 -#define USI_V2_SPI 2 -#define USI_V2_I2C 3 - -#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */

Drop in favour of dts/upstream

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/net/phy/dp83869.c | 2 + include/dt-bindings/bus/ti-sysc.h | 28 ---- include/dt-bindings/clk/ti-dra7-atl.h | 40 ----- include/dt-bindings/clock/am3.h | 227 ----------------------------- include/dt-bindings/clock/omap4.h | 149 ------------------- include/dt-bindings/clock/omap5.h | 129 ---------------- include/dt-bindings/media/omap3-isp.h | 22 --- include/dt-bindings/mux/ti-serdes.h | 190 ------------------------ include/dt-bindings/net/ti-dp83867.h | 53 ------- include/dt-bindings/net/ti-dp83869.h | 60 -------- include/dt-bindings/phy/phy-ti.h | 21 --- include/dt-bindings/pinctrl/am33xx.h | 172 ---------------------- include/dt-bindings/pinctrl/am43xx.h | 39 ----- include/dt-bindings/pinctrl/omap.h | 91 ------------ include/dt-bindings/reset/ti-syscon.h | 38 ----- include/dt-bindings/soc/ti,sci_pm_domain.h | 9 -- 16 files changed, 2 insertions(+), 1268 deletions(-)

diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index f9d4782580e9..fa6be1f3ecde 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -105,8 +105,10 @@ #define DP83869_IO_MUX_CFG_CLK_O_DISABLE BIT(6) #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK \ GENMASK(0x1f, DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT) +/* Special flag to indicate clock should be off */ +#define DP83869_CLK_O_SEL_OFF 0xFFFFFFFF

/* CFG3 bits */ #define DP83869_CFG3_PORT_MIRROR_EN BIT(0)

diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h deleted file mode 100644 index eae427454374..000000000000 --- a/include/dt-bindings/bus/ti-sysc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* TI sysc interconnect target module defines */ - -/* Generic sysc found on omap2 and later, also known as type1 */ -#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8) -#define SYSC_OMAP2_EMUFREE (1 << 5) -#define SYSC_OMAP2_ENAWAKEUP (1 << 2) -#define SYSC_OMAP2_SOFTRESET (1 << 1) -#define SYSC_OMAP2_AUTOIDLE (1 << 0) - -/* Generic sysc found on omap4 and later, also known as type2 */ -#define SYSC_OMAP4_DMADISABLE (1 << 16) -#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */ -#define SYSC_OMAP4_SOFTRESET (1 << 0) - -/* SmartReflex sysc found on 36xx and later */ -#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) - -#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) - -/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */ -#define SYSC_PRUSS_SUB_MWAIT (1 << 5) -#define SYSC_PRUSS_STANDBY_INIT (1 << 4) - -/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ -#define SYSC_IDLE_FORCE 0 -#define SYSC_IDLE_NO 1 -#define SYSC_IDLE_SMART 2 -#define SYSC_IDLE_SMART_WKUP 3 diff --git a/include/dt-bindings/clk/ti-dra7-atl.h b/include/dt-bindings/clk/ti-dra7-atl.h deleted file mode 100644 index 42dd4164f6f4..000000000000 --- a/include/dt-bindings/clk/ti-dra7-atl.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This header provides constants for DRA7 ATL (Audio Tracking Logic) - * - * The constants defined in this header are used in dts files - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * Peter Ujfalusi peter.ujfalusi@ti.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H -#define _DT_BINDINGS_CLK_DRA7_ATL_H - -#define DRA7_ATL_WS_MCASP1_FSR 0 -#define DRA7_ATL_WS_MCASP1_FSX 1 -#define DRA7_ATL_WS_MCASP2_FSR 2 -#define DRA7_ATL_WS_MCASP2_FSX 3 -#define DRA7_ATL_WS_MCASP3_FSX 4 -#define DRA7_ATL_WS_MCASP4_FSX 5 -#define DRA7_ATL_WS_MCASP5_FSX 6 -#define DRA7_ATL_WS_MCASP6_FSX 7 -#define DRA7_ATL_WS_MCASP7_FSX 8 -#define DRA7_ATL_WS_MCASP8_FSX 9 -#define DRA7_ATL_WS_MCASP8_AHCLKX 10 -#define DRA7_ATL_WS_XREF_CLK3 11 -#define DRA7_ATL_WS_XREF_CLK0 12 -#define DRA7_ATL_WS_XREF_CLK1 13 -#define DRA7_ATL_WS_XREF_CLK2 14 -#define DRA7_ATL_WS_OSC1_X1 15 - -#endif diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h deleted file mode 100644 index 86a8806e2140..000000000000 --- a/include/dt-bindings/clock/am3.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright 2017 Texas Instruments, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __DT_BINDINGS_CLK_AM3_H -#define __DT_BINDINGS_CLK_AM3_H - -#define AM3_CLKCTRL_OFFSET 0x0 -#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) - -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* l4_per clocks */ -#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 -#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) -#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) -#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) -#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) -#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) -#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) -#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) -#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) -#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) -#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) -#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) -#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) -#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) -#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) -#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) -#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) -#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) -#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) -#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) -#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) -#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) -#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) -#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) -#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) -#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) -#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) -#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) -#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) -#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) -#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) -#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) -#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) -#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) -#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) -#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) -#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) -#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) -#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) -#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) -#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) -#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) -#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) -#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) -#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) -#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) -#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) -#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) -#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) -#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) -#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) -#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) -#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 -#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) -#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) -#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) -#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) -#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) -#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) -#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) -#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) -#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) -#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) -#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) -#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) - -/* mpu clocks */ -#define AM3_MPU_CLKCTRL_OFFSET 0x4 -#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) -#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 -#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) -#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 -#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) -#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) - -/* XXX: Compatibility part end */ - -/* l4ls clocks */ -#define AM3_L4LS_CLKCTRL_OFFSET 0x38 -#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) -#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) -#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) -#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) -#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) -#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) -#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) -#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) -#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) -#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) -#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) -#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) -#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) -#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) -#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) -#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) -#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) -#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) -#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) -#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) -#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) -#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) -#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) -#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) -#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) -#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) -#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) -#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) -#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) -#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) -#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) -#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) - -/* l3s clocks */ -#define AM3_L3S_CLKCTRL_OFFSET 0x1c -#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) -#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) -#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) -#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) -#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) -#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) - -/* l3 clocks */ -#define AM3_L3_CLKCTRL_OFFSET 0x24 -#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) -#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) -#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) -#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) -#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) -#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) -#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) -#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) -#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) -#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) -#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) - -/* l4hs clocks */ -#define AM3_L4HS_CLKCTRL_OFFSET 0x120 -#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) -#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) - -/* pruss_ocp clocks */ -#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 -#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) -#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) - -/* cpsw_125mhz clocks */ -#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) - -/* lcdc clocks */ -#define AM3_LCDC_CLKCTRL_OFFSET 0x18 -#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) -#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) - -/* clk_24mhz clocks */ -#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c -#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) -#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) -#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) -#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) -#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) -#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) -#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) -#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) -#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) -#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) - -/* l3_aon clocks */ -#define AM3_L3_AON_CLKCTRL_OFFSET 0x14 -#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) -#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) - -/* l4_wkup_aon clocks */ -#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 -#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) -#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) - -/* mpu clocks */ -#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) - -#endif diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h deleted file mode 100644 index 88d73be84b94..000000000000 --- a/include/dt-bindings/clock/omap4.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_OMAP4_H -#define __DT_BINDINGS_CLK_OMAP4_H - -#define OMAP4_CLKCTRL_OFFSET 0x20 -#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) - -/* mpuss clocks */ -#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* tesla clocks */ -#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* abe clocks */ -#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) -#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) -#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) -#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) -#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) - -/* l4_ao clocks */ -#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) - -/* l3_1 clocks */ -#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_2 clocks */ -#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) - -/* ducati clocks */ -#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_dma clocks */ -#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_emif clocks */ -#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) - -/* d2d clocks */ -#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l4_cfg clocks */ -#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) - -/* l3_instr clocks */ -#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) - -/* ivahd clocks */ -#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) - -/* iss clocks */ -#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) - -/* l3_dss clocks */ -#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_gfx clocks */ -#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_init clocks */ -#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) -#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) - -/* l4_per clocks */ -#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) -#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) -#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) -#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) -#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) -#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) -#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) -#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) -#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) -#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) -#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) -#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) -#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) -#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) -#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) -#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) -#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) -#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) -#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) -#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) -#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) -#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) -#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) - -/* l4_secure clocks */ -#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 -#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) -#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) -#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) -#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) -#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) -#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) -#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) -#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) - -/* l4_wkup clocks */ -#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) - -/* emu_sys clocks */ -#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -#endif diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h deleted file mode 100644 index 41775272fd27..000000000000 --- a/include/dt-bindings/clock/omap5.h +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_OMAP5_H -#define __DT_BINDINGS_CLK_OMAP5_H - -#define OMAP5_CLKCTRL_OFFSET 0x20 -#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) - -/* mpu clocks */ -#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* dsp clocks */ -#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* abe clocks */ -#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) -#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) -#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) -#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) -#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) - -/* l3main1 clocks */ -#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* l3main2 clocks */ -#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* ipu clocks */ -#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* dma clocks */ -#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* emif clocks */ -#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) - -/* l4cfg clocks */ -#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) - -/* l3instr clocks */ -#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) - -/* l4per clocks */ -#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) -#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) -#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) -#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) -#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) -#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) -#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) -#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) -#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) -#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) -#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) -#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) -#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) -#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) -#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) -#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) -#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) -#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) -#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) -#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) -#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) -#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) -#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) -#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) -#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) -#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) -#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) - -/* l4_secure clocks */ -#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 -#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) -#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) -#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) -#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) -#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) -#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) -#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) -#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) - -/* iva clocks */ -#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) - -/* dss clocks */ -#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* gpu clocks */ -#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* l3init clocks */ -#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) -#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) -#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) -#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) -#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) - -/* wkupaon clocks */ -#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) -#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) - -#endif diff --git a/include/dt-bindings/media/omap3-isp.h b/include/dt-bindings/media/omap3-isp.h deleted file mode 100644 index 4e4208462142..000000000000 --- a/include/dt-bindings/media/omap3-isp.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * include/dt-bindings/media/omap3-isp.h - * - * Copyright (C) 2015 Sakari Ailus - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ - -#ifndef __DT_BINDINGS_OMAP3_ISP_H__ -#define __DT_BINDINGS_OMAP3_ISP_H__ - -#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0 -#define OMAP3ISP_PHY_TYPE_CSIPHY 1 - -#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */ diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h deleted file mode 100644 index b0b1091aad6d..000000000000 --- a/include/dt-bindings/mux/ti-serdes.h +++ /dev/null @@ -1,190 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for SERDES MUX for TI SoCs - */ - -#ifndef _DT_BINDINGS_MUX_TI_SERDES -#define _DT_BINDINGS_MUX_TI_SERDES - -/* - * These bindings are deprecated, because they do not match the actual - * concept of bindings but rather contain pure constants values used only - * in DTS board files. - * Instead include the header in the DTS source directory. - */ -#warning "These bindings are deprecated. Instead, use the header in the DTS source directory." - -/* J721E */ - -#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 -#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 -#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 -#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 -#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 -#define J721E_SERDES0_LANE1_USB3_0 0x2 -#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 -#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 -#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 -#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 - -#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 -#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 -#define J721E_SERDES1_LANE1_USB3_1 0x2 -#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 - -#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 -#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 -#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 -#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 - -#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 -#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 -#define J721E_SERDES2_LANE1_USB3_1 0x2 -#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 - -#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 -#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 -#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 -#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 -#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 -#define J721E_SERDES3_LANE1_USB3_0 0x2 -#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 -#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 -#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 -#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 -#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 -#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 -#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 -#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 -#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 - -/* J7200 */ - -#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 -#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 -#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 -#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 -#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J7200_SERDES0_LANE3_USB 0x2 -#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 - -/* AM64 */ - -#define AM64_SERDES0_LANE0_PCIE0 0x0 -#define AM64_SERDES0_LANE0_USB 0x1 - -/* J721S2 */ - -#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 -#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 -#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J721S2_SERDES0_LANE1_USB 0x2 -#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 -#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 -#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J721S2_SERDES0_LANE3_USB 0x2 -#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 - -/* J784S4 */ - -#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 -#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 -#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 -#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 -#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J784S4_SERDES0_LANE3_USB 0x2 -#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 -#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 -#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 -#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 -#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 -#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 -#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 -#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 -#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 -#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 -#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 -#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 -#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 -#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 -#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 -#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 -#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 -#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 -#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 - -#endif /* _DT_BINDINGS_MUX_TI_SERDES */ diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h deleted file mode 100644 index 6fc4b445d3a1..000000000000 --- a/include/dt-bindings/net/ti-dp83867.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree constants for the Texas Instruments DP83867 PHY - * - * Author: Dan Murphy dmurphy@ti.com - * - * Copyright: (C) 2015 Texas Instruments, Inc. - */ - -#ifndef _DT_BINDINGS_TI_DP83867_H -#define _DT_BINDINGS_TI_DP83867_H - -/* PHY CTRL bits */ -#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 -#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 -#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 -#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 - -/* RGMIIDCTL internal delay for rx and tx */ -#define DP83867_RGMIIDCTL_250_PS 0x0 -#define DP83867_RGMIIDCTL_500_PS 0x1 -#define DP83867_RGMIIDCTL_750_PS 0x2 -#define DP83867_RGMIIDCTL_1_NS 0x3 -#define DP83867_RGMIIDCTL_1_25_NS 0x4 -#define DP83867_RGMIIDCTL_1_50_NS 0x5 -#define DP83867_RGMIIDCTL_1_75_NS 0x6 -#define DP83867_RGMIIDCTL_2_00_NS 0x7 -#define DP83867_RGMIIDCTL_2_25_NS 0x8 -#define DP83867_RGMIIDCTL_2_50_NS 0x9 -#define DP83867_RGMIIDCTL_2_75_NS 0xa -#define DP83867_RGMIIDCTL_3_00_NS 0xb -#define DP83867_RGMIIDCTL_3_25_NS 0xc -#define DP83867_RGMIIDCTL_3_50_NS 0xd -#define DP83867_RGMIIDCTL_3_75_NS 0xe -#define DP83867_RGMIIDCTL_4_00_NS 0xf - -/* IO_MUX_CFG - Clock output selection */ -#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 -#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 -#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 -#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 -#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 -#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 -#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 -#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 -#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 -#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 -#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA -#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB -#define DP83867_CLK_O_SEL_REF_CLK 0xC -/* Special flag to indicate clock should be off */ -#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF -#endif diff --git a/include/dt-bindings/net/ti-dp83869.h b/include/dt-bindings/net/ti-dp83869.h deleted file mode 100644 index b3a5ac4a17b3..000000000000 --- a/include/dt-bindings/net/ti-dp83869.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * TI DP83869 PHY drivers - * - */ - -#ifndef _DT_BINDINGS_TI_DP83869_H -#define _DT_BINDINGS_TI_DP83869_H - -/* PHY CTRL bits */ -#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 -#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 -#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 -#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 - -/* RGMIIDCTL internal delay for rx and tx */ -#define DP83869_RGMIIDCTL_250_PS 0x0 -#define DP83869_RGMIIDCTL_500_PS 0x1 -#define DP83869_RGMIIDCTL_750_PS 0x2 -#define DP83869_RGMIIDCTL_1_NS 0x3 -#define DP83869_RGMIIDCTL_1_25_NS 0x4 -#define DP83869_RGMIIDCTL_1_50_NS 0x5 -#define DP83869_RGMIIDCTL_1_75_NS 0x6 -#define DP83869_RGMIIDCTL_2_00_NS 0x7 -#define DP83869_RGMIIDCTL_2_25_NS 0x8 -#define DP83869_RGMIIDCTL_2_50_NS 0x9 -#define DP83869_RGMIIDCTL_2_75_NS 0xa -#define DP83869_RGMIIDCTL_3_00_NS 0xb -#define DP83869_RGMIIDCTL_3_25_NS 0xc -#define DP83869_RGMIIDCTL_3_50_NS 0xd -#define DP83869_RGMIIDCTL_3_75_NS 0xe -#define DP83869_RGMIIDCTL_4_00_NS 0xf - -/* IO_MUX_CFG - Clock output selection */ -#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 -#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 -#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 -#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 -#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 -#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 -#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 -#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 -#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 -#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 -#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xA -#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xB -#define DP83869_CLK_O_SEL_REF_CLK 0xC -/* Special flag to indicate clock should be off */ -#define DP83869_CLK_O_SEL_OFF 0xFFFFFFFF - -/* OPMODE - Operation mode */ -#define DP83869_RGMII_COPPER_ETHERNET 0x00 -#define DP83869_RGMII_1000_BASE 0x01 -#define DP83869_RGMII_100_BASE 0x02 -#define DP83869_RGMII_SGMII_BRIDGE 0x03 -#define DP83869_1000M_MEDIA_CONVERT 0x04 -#define DP83869_100M_MEDIA_CONVERT 0x05 -#define DP83869_SGMII_COPPER_ETHERNET 0x06 - -#endif diff --git a/include/dt-bindings/phy/phy-ti.h b/include/dt-bindings/phy/phy-ti.h deleted file mode 100644 index ad955d3a56b4..000000000000 --- a/include/dt-bindings/phy/phy-ti.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for TI SERDES. - */ - -#ifndef _DT_BINDINGS_TI_SERDES -#define _DT_BINDINGS_TI_SERDES - -/* Clock index for output clocks from WIZ */ - -/* MUX Clocks */ -#define TI_WIZ_PLL0_REFCLK 0 -#define TI_WIZ_PLL1_REFCLK 1 -#define TI_WIZ_REFCLK_DIG 2 - -/* Reserve index here for future additions */ - -/* MISC Clocks */ -#define TI_WIZ_PHY_EN_REFCLK 16 - -#endif /* _DT_BINDINGS_TI_SERDES */ diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h deleted file mode 100644 index 17877e85980b..000000000000 --- a/include/dt-bindings/pinctrl/am33xx.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants specific to AM33XX pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H -#define _DT_BINDINGS_PINCTRL_AM33XX_H - -#include <dt-bindings/pinctrl/omap.h> - -/* am33xx specific mux bit defines */ -#undef PULL_ENA -#undef INPUT_EN - -#define PULL_DISABLE (1 << 3) -#define INPUT_EN (1 << 5) -#define SLEWCTRL_SLOW (1 << 6) -#define SLEWCTRL_FAST 0 - -/* update macro depending on INPUT_EN and PULL_ENA */ -#undef PIN_OUTPUT -#undef PIN_OUTPUT_PULLUP -#undef PIN_OUTPUT_PULLDOWN -#undef PIN_INPUT -#undef PIN_INPUT_PULLUP -#undef PIN_INPUT_PULLDOWN - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) - -/* undef non-existing modes */ -#undef PIN_OFF_NONE -#undef PIN_OFF_OUTPUT_HIGH -#undef PIN_OFF_OUTPUT_LOW -#undef PIN_OFF_INPUT_PULLUP -#undef PIN_OFF_INPUT_PULLDOWN -#undef PIN_OFF_WAKEUPENABLE - -#define AM335X_PIN_OFFSET_MIN 0x0800U - -#define AM335X_PIN_GPMC_AD0 0x800 -#define AM335X_PIN_GPMC_AD1 0x804 -#define AM335X_PIN_GPMC_AD2 0x808 -#define AM335X_PIN_GPMC_AD3 0x80c -#define AM335X_PIN_GPMC_AD4 0x810 -#define AM335X_PIN_GPMC_AD5 0x814 -#define AM335X_PIN_GPMC_AD6 0x818 -#define AM335X_PIN_GPMC_AD7 0x81c -#define AM335X_PIN_GPMC_AD8 0x820 -#define AM335X_PIN_GPMC_AD9 0x824 -#define AM335X_PIN_GPMC_AD10 0x828 -#define AM335X_PIN_GPMC_AD11 0x82c -#define AM335X_PIN_GPMC_AD12 0x830 -#define AM335X_PIN_GPMC_AD13 0x834 -#define AM335X_PIN_GPMC_AD14 0x838 -#define AM335X_PIN_GPMC_AD15 0x83c -#define AM335X_PIN_GPMC_A0 0x840 -#define AM335X_PIN_GPMC_A1 0x844 -#define AM335X_PIN_GPMC_A2 0x848 -#define AM335X_PIN_GPMC_A3 0x84c -#define AM335X_PIN_GPMC_A4 0x850 -#define AM335X_PIN_GPMC_A5 0x854 -#define AM335X_PIN_GPMC_A6 0x858 -#define AM335X_PIN_GPMC_A7 0x85c -#define AM335X_PIN_GPMC_A8 0x860 -#define AM335X_PIN_GPMC_A9 0x864 -#define AM335X_PIN_GPMC_A10 0x868 -#define AM335X_PIN_GPMC_A11 0x86c -#define AM335X_PIN_GPMC_WAIT0 0x870 -#define AM335X_PIN_GPMC_WPN 0x874 -#define AM335X_PIN_GPMC_BEN1 0x878 -#define AM335X_PIN_GPMC_CSN0 0x87c -#define AM335X_PIN_GPMC_CSN1 0x880 -#define AM335X_PIN_GPMC_CSN2 0x884 -#define AM335X_PIN_GPMC_CSN3 0x888 -#define AM335X_PIN_GPMC_CLK 0x88c -#define AM335X_PIN_GPMC_ADVN_ALE 0x890 -#define AM335X_PIN_GPMC_OEN_REN 0x894 -#define AM335X_PIN_GPMC_WEN 0x898 -#define AM335X_PIN_GPMC_BEN0_CLE 0x89c -#define AM335X_PIN_LCD_DATA0 0x8a0 -#define AM335X_PIN_LCD_DATA1 0x8a4 -#define AM335X_PIN_LCD_DATA2 0x8a8 -#define AM335X_PIN_LCD_DATA3 0x8ac -#define AM335X_PIN_LCD_DATA4 0x8b0 -#define AM335X_PIN_LCD_DATA5 0x8b4 -#define AM335X_PIN_LCD_DATA6 0x8b8 -#define AM335X_PIN_LCD_DATA7 0x8bc -#define AM335X_PIN_LCD_DATA8 0x8c0 -#define AM335X_PIN_LCD_DATA9 0x8c4 -#define AM335X_PIN_LCD_DATA10 0x8c8 -#define AM335X_PIN_LCD_DATA11 0x8cc -#define AM335X_PIN_LCD_DATA12 0x8d0 -#define AM335X_PIN_LCD_DATA13 0x8d4 -#define AM335X_PIN_LCD_DATA14 0x8d8 -#define AM335X_PIN_LCD_DATA15 0x8dc -#define AM335X_PIN_LCD_VSYNC 0x8e0 -#define AM335X_PIN_LCD_HSYNC 0x8e4 -#define AM335X_PIN_LCD_PCLK 0x8e8 -#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec -#define AM335X_PIN_MMC0_DAT3 0x8f0 -#define AM335X_PIN_MMC0_DAT2 0x8f4 -#define AM335X_PIN_MMC0_DAT1 0x8f8 -#define AM335X_PIN_MMC0_DAT0 0x8fc -#define AM335X_PIN_MMC0_CLK 0x900 -#define AM335X_PIN_MMC0_CMD 0x904 -#define AM335X_PIN_MII1_COL 0x908 -#define AM335X_PIN_MII1_CRS 0x90c -#define AM335X_PIN_MII1_RX_ER 0x910 -#define AM335X_PIN_MII1_TX_EN 0x914 -#define AM335X_PIN_MII1_RX_DV 0x918 -#define AM335X_PIN_MII1_TXD3 0x91c -#define AM335X_PIN_MII1_TXD2 0x920 -#define AM335X_PIN_MII1_TXD1 0x924 -#define AM335X_PIN_MII1_TXD0 0x928 -#define AM335X_PIN_MII1_TX_CLK 0x92c -#define AM335X_PIN_MII1_RX_CLK 0x930 -#define AM335X_PIN_MII1_RXD3 0x934 -#define AM335X_PIN_MII1_RXD2 0x938 -#define AM335X_PIN_MII1_RXD1 0x93c -#define AM335X_PIN_MII1_RXD0 0x940 -#define AM335X_PIN_RMII1_REF_CLK 0x944 -#define AM335X_PIN_MDIO 0x948 -#define AM335X_PIN_MDC 0x94c -#define AM335X_PIN_SPI0_SCLK 0x950 -#define AM335X_PIN_SPI0_D0 0x954 -#define AM335X_PIN_SPI0_D1 0x958 -#define AM335X_PIN_SPI0_CS0 0x95c -#define AM335X_PIN_SPI0_CS1 0x960 -#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964 -#define AM335X_PIN_UART0_CTSN 0x968 -#define AM335X_PIN_UART0_RTSN 0x96c -#define AM335X_PIN_UART0_RXD 0x970 -#define AM335X_PIN_UART0_TXD 0x974 -#define AM335X_PIN_UART1_CTSN 0x978 -#define AM335X_PIN_UART1_RTSN 0x97c -#define AM335X_PIN_UART1_RXD 0x980 -#define AM335X_PIN_UART1_TXD 0x984 -#define AM335X_PIN_I2C0_SDA 0x988 -#define AM335X_PIN_I2C0_SCL 0x98c -#define AM335X_PIN_MCASP0_ACLKX 0x990 -#define AM335X_PIN_MCASP0_FSX 0x994 -#define AM335X_PIN_MCASP0_AXR0 0x998 -#define AM335X_PIN_MCASP0_AHCLKR 0x99c -#define AM335X_PIN_MCASP0_ACLKR 0x9a0 -#define AM335X_PIN_MCASP0_FSR 0x9a4 -#define AM335X_PIN_MCASP0_AXR1 0x9a8 -#define AM335X_PIN_MCASP0_AHCLKX 0x9ac -#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0 -#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4 -#define AM335X_PIN_WARMRSTN 0x9b8 -#define AM335X_PIN_NNMI 0x9c0 -#define AM335X_PIN_TMS 0x9d0 -#define AM335X_PIN_TDI 0x9d4 -#define AM335X_PIN_TDO 0x9d8 -#define AM335X_PIN_TCK 0x9dc -#define AM335X_PIN_TRSTN 0x9e0 -#define AM335X_PIN_EMU0 0x9e4 -#define AM335X_PIN_EMU1 0x9e8 -#define AM335X_PIN_RTC_PWRONRSTN 0x9f8 -#define AM335X_PIN_PMIC_POWER_EN 0x9fc -#define AM335X_PIN_EXT_WAKEUP 0xa00 -#define AM335X_PIN_USB0_DRVVBUS 0xa1c -#define AM335X_PIN_USB1_DRVVBUS 0xa34 - -#define AM335X_PIN_OFFSET_MAX 0x0a34U - -#endif diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h deleted file mode 100644 index 292c2ebf58dd..000000000000 --- a/include/dt-bindings/pinctrl/am43xx.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This header provides constants specific to AM43XX pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H -#define _DT_BINDINGS_PINCTRL_AM43XX_H - -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 -#define MUX_MODE8 8 - -#define PULL_DISABLE (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCTRL_SLOW (1 << 19) -#define SLEWCTRL_FAST 0 -#define DS0_PULL_UP_DOWN_EN (1 << 27) -#define WAKEUP_ENABLE (1 << 29) - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) - -/* - * Macro to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) - -#endif diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h deleted file mode 100644 index 4c060ee0e0ad..000000000000 --- a/include/dt-bindings/pinctrl/omap.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for OMAP pinctrl bindings. - * - * Copyright (C) 2009 Nokia - * Copyright (C) 2009-2010 Texas Instruments - */ - -#ifndef _DT_BINDINGS_PINCTRL_OMAP_H -#define _DT_BINDINGS_PINCTRL_OMAP_H - -/* 34xx mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 - -/* 24xx/34xx mux bit defines */ -#define PULL_ENA (1 << 3) -#define PULL_UP (1 << 4) -#define ALTELECTRICALSEL (1 << 5) - -/* omap3/4/5 specific mux bit defines */ -#define INPUT_EN (1 << 8) -#define OFF_EN (1 << 9) -#define OFFOUT_EN (1 << 10) -#define OFFOUT_VAL (1 << 11) -#define OFF_PULL_EN (1 << 12) -#define OFF_PULL_UP (1 << 13) -#define WAKEUP_EN (1 << 14) -#define WAKEUP_EVENT (1 << 15) - -/* Active pin states */ -#define PIN_OUTPUT 0 -#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) -#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) -#define PIN_INPUT INPUT_EN -#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) - -/* Off mode states */ -#define PIN_OFF_NONE 0 -#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) -#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) -#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFFOUT_EN | OFF_PULL_EN | OFF_PULL_UP) -#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFFOUT_EN | OFF_PULL_EN) -#define PIN_OFF_WAKEUPENABLE WAKEUP_EN - -/* - * Macros to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) - -#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) -#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) -#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) -#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) -#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) -#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) -#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0) -#define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux) - -/* - * Macros to allow using the offset from the padconf physical address - * instead of the offset from padconf base. - */ -#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) - -#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) -#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) - -/* - * Define some commonly used pins configured by the boards. - * Note that some boards use alternative pins, so check - * the schematics before using these. - */ -#define OMAP3_UART1_RX 0x152 -#define OMAP3_UART2_RX 0x14a -#define OMAP3_UART3_RX 0x16e -#define OMAP4_UART2_RX 0xdc -#define OMAP4_UART3_RX 0x104 -#define OMAP4_UART4_RX 0x11c - -#endif diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h deleted file mode 100644 index 1427ff140f11..000000000000 --- a/include/dt-bindings/reset/ti-syscon.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * TI Syscon Reset definitions - * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ -#define __DT_BINDINGS_RESET_TI_SYSCON_H__ - -/* - * The reset does not support the feature and corresponding - * values are not valid - */ -#define ASSERT_NONE (1 << 0) -#define DEASSERT_NONE (1 << 1) -#define STATUS_NONE (1 << 2) - -/* When set this function is activated by setting(vs clearing) this bit */ -#define ASSERT_SET (1 << 3) -#define DEASSERT_SET (1 << 4) -#define STATUS_SET (1 << 5) - -/* The following are the inverse of the above and are added for consistency */ -#define ASSERT_CLEAR (0 << 3) -#define DEASSERT_CLEAR (0 << 4) -#define STATUS_CLEAR (0 << 5) - -#endif diff --git a/include/dt-bindings/soc/ti,sci_pm_domain.h b/include/dt-bindings/soc/ti,sci_pm_domain.h deleted file mode 100644 index 8f2a7360b65e..000000000000 --- a/include/dt-bindings/soc/ti,sci_pm_domain.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H -#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H - -#define TI_SCI_PD_EXCLUSIVE 1 -#define TI_SCI_PD_SHARED 0 - -#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */

Drop in favour of dts/upstream.

Small driver adjustment to fix compatibility.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/dts/tegra186.dtsi | 2 +- drivers/mailbox/tegra-hsp.c | 2 +- include/dt-bindings/gpio/tegra-gpio.h | 51 ------ include/dt-bindings/mailbox/tegra186-hsp.h | 19 --- include/dt-bindings/memory/tegra114-mc.h | 25 --- include/dt-bindings/memory/tegra124-mc.h | 31 ---- include/dt-bindings/memory/tegra210-mc.h | 36 ---- include/dt-bindings/memory/tegra30-mc.h | 24 --- include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 - include/dt-bindings/pinctrl/pinctrl-tegra.h | 37 ---- include/dt-bindings/power/tegra186-powergate.h | 28 ---- include/dt-bindings/reset/tegra124-car.h | 12 -- include/dt-bindings/reset/tegra186-reset.h | 205 ----------------------- include/dt-bindings/thermal/tegra124-soctherm.h | 14 -- 14 files changed, 2 insertions(+), 491 deletions(-)

diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index edcb7aacb8ee..58dadc944888 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -313,9 +313,9 @@ };

bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; - mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; + mboxes = <&hsp TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; /* * In theory, these references, and the configuration in the * node these reference point at, are board-specific, since * they depend on the BCT's memory carve-out setup, the diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 08c51c40f141..e5a3d8243780 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -62,9 +62,9 @@ static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,

static int tegra_hsp_db_id(ulong chan_id) { switch (chan_id) { - case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP: + case (TEGRA_HSP_MBOX_TYPE_DB << 16) | TEGRA_HSP_DB_MASTER_BPMP: return TEGRA_HSP_DB_ID_BPMP; default: debug("Invalid channel ID\n"); return -EINVAL; diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h deleted file mode 100644 index a1c09e88e80b..000000000000 --- a/include/dt-bindings/gpio/tegra-gpio.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra*-gpio. - * - * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below - * provide names for this. - * - * The second cell contains standard flag values specified in gpio.h. - */ - -#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H -#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H - -#include <dt-bindings/gpio/gpio.h> - -#define TEGRA_GPIO_PORT_A 0 -#define TEGRA_GPIO_PORT_B 1 -#define TEGRA_GPIO_PORT_C 2 -#define TEGRA_GPIO_PORT_D 3 -#define TEGRA_GPIO_PORT_E 4 -#define TEGRA_GPIO_PORT_F 5 -#define TEGRA_GPIO_PORT_G 6 -#define TEGRA_GPIO_PORT_H 7 -#define TEGRA_GPIO_PORT_I 8 -#define TEGRA_GPIO_PORT_J 9 -#define TEGRA_GPIO_PORT_K 10 -#define TEGRA_GPIO_PORT_L 11 -#define TEGRA_GPIO_PORT_M 12 -#define TEGRA_GPIO_PORT_N 13 -#define TEGRA_GPIO_PORT_O 14 -#define TEGRA_GPIO_PORT_P 15 -#define TEGRA_GPIO_PORT_Q 16 -#define TEGRA_GPIO_PORT_R 17 -#define TEGRA_GPIO_PORT_S 18 -#define TEGRA_GPIO_PORT_T 19 -#define TEGRA_GPIO_PORT_U 20 -#define TEGRA_GPIO_PORT_V 21 -#define TEGRA_GPIO_PORT_W 22 -#define TEGRA_GPIO_PORT_X 23 -#define TEGRA_GPIO_PORT_Y 24 -#define TEGRA_GPIO_PORT_Z 25 -#define TEGRA_GPIO_PORT_AA 26 -#define TEGRA_GPIO_PORT_BB 27 -#define TEGRA_GPIO_PORT_CC 28 -#define TEGRA_GPIO_PORT_DD 29 -#define TEGRA_GPIO_PORT_EE 30 -#define TEGRA_GPIO_PORT_FF 31 - -#define TEGRA_GPIO(port, offset) \ - ((TEGRA_GPIO_PORT_##port * 8) + offset) - -#endif diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h deleted file mode 100644 index b4864325d74b..000000000000 --- a/include/dt-bindings/mailbox/tegra186-hsp.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra186-hsp. - * - * The number with HSP_DB_MASTER prefix indicates the bit that is - * associated with a master ID in the doorbell registers. - */ - -#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H -#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H - -#define HSP_MBOX_TYPE_DB 0x0 -#define HSP_MBOX_TYPE_SM 0x1 -#define HSP_MBOX_TYPE_SS 0x2 -#define HSP_MBOX_TYPE_AS 0x3 - -#define HSP_DB_MASTER_CCPLEX 17 -#define HSP_DB_MASTER_BPMP 19 - -#endif diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h deleted file mode 100644 index 8f48985a3139..000000000000 --- a/include/dt-bindings/memory/tegra114-mc.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H -#define DT_BINDINGS_MEMORY_TEGRA114_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_EPP 3 -#define TEGRA_SWGROUP_G2 4 -#define TEGRA_SWGROUP_AVPC 5 -#define TEGRA_SWGROUP_NV 6 -#define TEGRA_SWGROUP_HDA 7 -#define TEGRA_SWGROUP_HC 8 -#define TEGRA_SWGROUP_MSENC 9 -#define TEGRA_SWGROUP_PPCS 10 -#define TEGRA_SWGROUP_VDE 11 -#define TEGRA_SWGROUP_MPCORELP 12 -#define TEGRA_SWGROUP_MPCORE 13 -#define TEGRA_SWGROUP_VI 14 -#define TEGRA_SWGROUP_ISP 15 -#define TEGRA_SWGROUP_XUSB_HOST 16 -#define TEGRA_SWGROUP_XUSB_DEV 17 -#define TEGRA_SWGROUP_EMUCIF 18 -#define TEGRA_SWGROUP_TSEC 19 - -#endif diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h deleted file mode 100644 index 7d8ee798f34e..000000000000 --- a/include/dt-bindings/memory/tegra124-mc.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H -#define DT_BINDINGS_MEMORY_TEGRA124_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_AFI 3 -#define TEGRA_SWGROUP_AVPC 4 -#define TEGRA_SWGROUP_HDA 5 -#define TEGRA_SWGROUP_HC 6 -#define TEGRA_SWGROUP_MSENC 7 -#define TEGRA_SWGROUP_PPCS 8 -#define TEGRA_SWGROUP_SATA 9 -#define TEGRA_SWGROUP_VDE 10 -#define TEGRA_SWGROUP_MPCORELP 11 -#define TEGRA_SWGROUP_MPCORE 12 -#define TEGRA_SWGROUP_ISP2 13 -#define TEGRA_SWGROUP_XUSB_HOST 14 -#define TEGRA_SWGROUP_XUSB_DEV 15 -#define TEGRA_SWGROUP_ISP2B 16 -#define TEGRA_SWGROUP_TSEC 17 -#define TEGRA_SWGROUP_A9AVP 18 -#define TEGRA_SWGROUP_GPU 19 -#define TEGRA_SWGROUP_SDMMC1A 20 -#define TEGRA_SWGROUP_SDMMC2A 21 -#define TEGRA_SWGROUP_SDMMC3A 22 -#define TEGRA_SWGROUP_SDMMC4A 23 -#define TEGRA_SWGROUP_VIC 24 -#define TEGRA_SWGROUP_VI 25 - -#endif diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h deleted file mode 100644 index d1731bc14dbc..000000000000 --- a/include/dt-bindings/memory/tegra210-mc.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H -#define DT_BINDINGS_MEMORY_TEGRA210_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_AFI 3 -#define TEGRA_SWGROUP_AVPC 4 -#define TEGRA_SWGROUP_HDA 5 -#define TEGRA_SWGROUP_HC 6 -#define TEGRA_SWGROUP_NVENC 7 -#define TEGRA_SWGROUP_PPCS 8 -#define TEGRA_SWGROUP_SATA 9 -#define TEGRA_SWGROUP_MPCORE 10 -#define TEGRA_SWGROUP_ISP2 11 -#define TEGRA_SWGROUP_XUSB_HOST 12 -#define TEGRA_SWGROUP_XUSB_DEV 13 -#define TEGRA_SWGROUP_ISP2B 14 -#define TEGRA_SWGROUP_TSEC 15 -#define TEGRA_SWGROUP_A9AVP 16 -#define TEGRA_SWGROUP_GPU 17 -#define TEGRA_SWGROUP_SDMMC1A 18 -#define TEGRA_SWGROUP_SDMMC2A 19 -#define TEGRA_SWGROUP_SDMMC3A 20 -#define TEGRA_SWGROUP_SDMMC4A 21 -#define TEGRA_SWGROUP_VIC 22 -#define TEGRA_SWGROUP_VI 23 -#define TEGRA_SWGROUP_NVDEC 24 -#define TEGRA_SWGROUP_APE 25 -#define TEGRA_SWGROUP_NVJPG 26 -#define TEGRA_SWGROUP_SE 27 -#define TEGRA_SWGROUP_AXIAP 28 -#define TEGRA_SWGROUP_ETR 29 -#define TEGRA_SWGROUP_TSECB 30 - -#endif diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h deleted file mode 100644 index 502beb03d777..000000000000 --- a/include/dt-bindings/memory/tegra30-mc.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H -#define DT_BINDINGS_MEMORY_TEGRA30_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_EPP 3 -#define TEGRA_SWGROUP_G2 4 -#define TEGRA_SWGROUP_MPE 5 -#define TEGRA_SWGROUP_VI 6 -#define TEGRA_SWGROUP_AFI 7 -#define TEGRA_SWGROUP_AVPC 8 -#define TEGRA_SWGROUP_NV 9 -#define TEGRA_SWGROUP_NV2 10 -#define TEGRA_SWGROUP_HDA 11 -#define TEGRA_SWGROUP_HC 12 -#define TEGRA_SWGROUP_PPCS 13 -#define TEGRA_SWGROUP_SATA 14 -#define TEGRA_SWGROUP_VDE 15 -#define TEGRA_SWGROUP_MPCORELP 16 -#define TEGRA_SWGROUP_MPCORE 17 -#define TEGRA_SWGROUP_ISP 18 - -#endif diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h deleted file mode 100644 index 914d56da9324..000000000000 --- a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H -#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 - -#define TEGRA_XUSB_PADCTL_PCIE 0 -#define TEGRA_XUSB_PADCTL_SATA 1 - -#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h deleted file mode 100644 index c9b57408de68..000000000000 --- a/include/dt-bindings/pinctrl/pinctrl-tegra.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for Tegra pinctrl bindings. - * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * Author: Laxman Dewangan ldewangan@nvidia.com - */ - -#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H -#define _DT_BINDINGS_PINCTRL_TEGRA_H - -/* - * Enable/disable for diffeent dt properties. This is applicable for - * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, - * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. - */ -#define TEGRA_PIN_DISABLE 0 -#define TEGRA_PIN_ENABLE 1 - -#define TEGRA_PIN_PULL_NONE 0 -#define TEGRA_PIN_PULL_DOWN 1 -#define TEGRA_PIN_PULL_UP 2 - -/* Low power mode driver */ -#define TEGRA_PIN_LP_DRIVE_DIV_8 0 -#define TEGRA_PIN_LP_DRIVE_DIV_4 1 -#define TEGRA_PIN_LP_DRIVE_DIV_2 2 -#define TEGRA_PIN_LP_DRIVE_DIV_1 3 - -/* Rising/Falling slew rate */ -#define TEGRA_PIN_SLEW_RATE_FASTEST 0 -#define TEGRA_PIN_SLEW_RATE_FAST 1 -#define TEGRA_PIN_SLEW_RATE_SLOW 2 -#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 - -#endif diff --git a/include/dt-bindings/power/tegra186-powergate.h b/include/dt-bindings/power/tegra186-powergate.h deleted file mode 100644 index 17e75498563c..000000000000 --- a/include/dt-bindings/power/tegra186-powergate.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2015-2016, NVIDIA CORPORATION. - */ - -#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H -#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H - -#define TEGRA186_POWER_DOMAIN_AUD 0 -#define TEGRA186_POWER_DOMAIN_DFD 1 -#define TEGRA186_POWER_DOMAIN_DISP 2 -#define TEGRA186_POWER_DOMAIN_DISPB 3 -#define TEGRA186_POWER_DOMAIN_DISPC 4 -#define TEGRA186_POWER_DOMAIN_ISPA 5 -#define TEGRA186_POWER_DOMAIN_NVDEC 6 -#define TEGRA186_POWER_DOMAIN_NVJPG 7 -#define TEGRA186_POWER_DOMAIN_MPE 8 -#define TEGRA186_POWER_DOMAIN_PCX 9 -#define TEGRA186_POWER_DOMAIN_SAX 10 -#define TEGRA186_POWER_DOMAIN_VE 11 -#define TEGRA186_POWER_DOMAIN_VIC 12 -#define TEGRA186_POWER_DOMAIN_XUSBA 13 -#define TEGRA186_POWER_DOMAIN_XUSBB 14 -#define TEGRA186_POWER_DOMAIN_XUSBC 15 -#define TEGRA186_POWER_DOMAIN_GPU 43 -#define TEGRA186_POWER_DOMAIN_MAX 44 - -#endif diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h deleted file mode 100644 index 070e4f6e7486..000000000000 --- a/include/dt-bindings/reset/tegra124-car.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * This header provides Tegra124-specific constants for binding - * nvidia,tegra124-car. - */ - -#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H -#define _DT_BINDINGS_RESET_TEGRA124_CAR_H - -#define TEGRA124_RESET(x) (6 * 32 + (x)) -#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0) - -#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */ diff --git a/include/dt-bindings/reset/tegra186-reset.h b/include/dt-bindings/reset/tegra186-reset.h deleted file mode 100644 index 7efec9200532..000000000000 --- a/include/dt-bindings/reset/tegra186-reset.h +++ /dev/null @@ -1,205 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. - */ - -#ifndef _ABI_MACH_T186_RESET_T186_H_ -#define _ABI_MACH_T186_RESET_T186_H_ - -#define TEGRA186_RESET_ACTMON 0 -#define TEGRA186_RESET_AFI 1 -#define TEGRA186_RESET_CEC 2 -#define TEGRA186_RESET_CSITE 3 -#define TEGRA186_RESET_DP2 4 -#define TEGRA186_RESET_DPAUX 5 -#define TEGRA186_RESET_DSI 6 -#define TEGRA186_RESET_DSIB 7 -#define TEGRA186_RESET_DTV 8 -#define TEGRA186_RESET_DVFS 9 -#define TEGRA186_RESET_ENTROPY 10 -#define TEGRA186_RESET_EXTPERIPH1 11 -#define TEGRA186_RESET_EXTPERIPH2 12 -#define TEGRA186_RESET_EXTPERIPH3 13 -#define TEGRA186_RESET_GPU 14 -#define TEGRA186_RESET_HDA 15 -#define TEGRA186_RESET_HDA2CODEC_2X 16 -#define TEGRA186_RESET_HDA2HDMICODEC 17 -#define TEGRA186_RESET_HOST1X 18 -#define TEGRA186_RESET_I2C1 19 -#define TEGRA186_RESET_I2C2 20 -#define TEGRA186_RESET_I2C3 21 -#define TEGRA186_RESET_I2C4 22 -#define TEGRA186_RESET_I2C5 23 -#define TEGRA186_RESET_I2C6 24 -#define TEGRA186_RESET_ISP 25 -#define TEGRA186_RESET_KFUSE 26 -#define TEGRA186_RESET_LA 27 -#define TEGRA186_RESET_MIPI_CAL 28 -#define TEGRA186_RESET_PCIE 29 -#define TEGRA186_RESET_PCIEXCLK 30 -#define TEGRA186_RESET_SATA 31 -#define TEGRA186_RESET_SATACOLD 32 -#define TEGRA186_RESET_SDMMC1 33 -#define TEGRA186_RESET_SDMMC2 34 -#define TEGRA186_RESET_SDMMC3 35 -#define TEGRA186_RESET_SDMMC4 36 -#define TEGRA186_RESET_SE 37 -#define TEGRA186_RESET_SOC_THERM 38 -#define TEGRA186_RESET_SOR0 39 -#define TEGRA186_RESET_SPI1 40 -#define TEGRA186_RESET_SPI2 41 -#define TEGRA186_RESET_SPI3 42 -#define TEGRA186_RESET_SPI4 43 -#define TEGRA186_RESET_TMR 44 -#define TEGRA186_RESET_TRIG_SYS 45 -#define TEGRA186_RESET_TSEC 46 -#define TEGRA186_RESET_UARTA 47 -#define TEGRA186_RESET_UARTB 48 -#define TEGRA186_RESET_UARTC 49 -#define TEGRA186_RESET_UARTD 50 -#define TEGRA186_RESET_VI 51 -#define TEGRA186_RESET_VIC 52 -#define TEGRA186_RESET_XUSB_DEV 53 -#define TEGRA186_RESET_XUSB_HOST 54 -#define TEGRA186_RESET_XUSB_PADCTL 55 -#define TEGRA186_RESET_XUSB_SS 56 -#define TEGRA186_RESET_AON_APB 57 -#define TEGRA186_RESET_AXI_CBB 58 -#define TEGRA186_RESET_BPMP_APB 59 -#define TEGRA186_RESET_CAN1 60 -#define TEGRA186_RESET_CAN2 61 -#define TEGRA186_RESET_DMIC5 62 -#define TEGRA186_RESET_DSIC 63 -#define TEGRA186_RESET_DSID 64 -#define TEGRA186_RESET_EMC_EMC 65 -#define TEGRA186_RESET_EMC_MEM 66 -#define TEGRA186_RESET_EMCSB_EMC 67 -#define TEGRA186_RESET_EMCSB_MEM 68 -#define TEGRA186_RESET_EQOS 69 -#define TEGRA186_RESET_GPCDMA 70 -#define TEGRA186_RESET_GPIO_CTL0 71 -#define TEGRA186_RESET_GPIO_CTL1 72 -#define TEGRA186_RESET_GPIO_CTL2 73 -#define TEGRA186_RESET_GPIO_CTL3 74 -#define TEGRA186_RESET_GPIO_CTL4 75 -#define TEGRA186_RESET_GPIO_CTL5 76 -#define TEGRA186_RESET_I2C10 77 -#define TEGRA186_RESET_I2C12 78 -#define TEGRA186_RESET_I2C13 79 -#define TEGRA186_RESET_I2C14 80 -#define TEGRA186_RESET_I2C7 81 -#define TEGRA186_RESET_I2C8 82 -#define TEGRA186_RESET_I2C9 83 -#define TEGRA186_RESET_JTAG2AXI 84 -#define TEGRA186_RESET_MPHY_IOBIST 85 -#define TEGRA186_RESET_MPHY_L0_RX 86 -#define TEGRA186_RESET_MPHY_L0_TX 87 -#define TEGRA186_RESET_NVCSI 88 -#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 -#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 -#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 -#define TEGRA186_RESET_NVDISPLAY0_MISC 92 -#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 -#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 -#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 -#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 -#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 -#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 -#define TEGRA186_RESET_PWM1 99 -#define TEGRA186_RESET_PWM2 100 -#define TEGRA186_RESET_PWM3 101 -#define TEGRA186_RESET_PWM4 102 -#define TEGRA186_RESET_PWM5 103 -#define TEGRA186_RESET_PWM6 104 -#define TEGRA186_RESET_PWM7 105 -#define TEGRA186_RESET_PWM8 106 -#define TEGRA186_RESET_SCE_APB 107 -#define TEGRA186_RESET_SOR1 108 -#define TEGRA186_RESET_TACH 109 -#define TEGRA186_RESET_TSC 110 -#define TEGRA186_RESET_UARTF 111 -#define TEGRA186_RESET_UARTG 112 -#define TEGRA186_RESET_UFSHC 113 -#define TEGRA186_RESET_UFSHC_AXI_M 114 -#define TEGRA186_RESET_UPHY 115 -#define TEGRA186_RESET_ADSP 116 -#define TEGRA186_RESET_ADSPDBG 117 -#define TEGRA186_RESET_ADSPINTF 118 -#define TEGRA186_RESET_ADSPNEON 119 -#define TEGRA186_RESET_ADSPPERIPH 120 -#define TEGRA186_RESET_ADSPSCU 121 -#define TEGRA186_RESET_ADSPWDT 122 -#define TEGRA186_RESET_APE 123 -#define TEGRA186_RESET_DPAUX1 124 -#define TEGRA186_RESET_NVDEC 125 -#define TEGRA186_RESET_NVENC 126 -#define TEGRA186_RESET_NVJPG 127 -#define TEGRA186_RESET_PEX_USB_UPHY 128 -#define TEGRA186_RESET_QSPI 129 -#define TEGRA186_RESET_TSECB 130 -#define TEGRA186_RESET_VI_I2C 131 -#define TEGRA186_RESET_UARTE 132 -#define TEGRA186_RESET_TOP_GTE 133 -#define TEGRA186_RESET_SHSP 134 -#define TEGRA186_RESET_PEX_USB_UPHY_L5 135 -#define TEGRA186_RESET_PEX_USB_UPHY_L4 136 -#define TEGRA186_RESET_PEX_USB_UPHY_L3 137 -#define TEGRA186_RESET_PEX_USB_UPHY_L2 138 -#define TEGRA186_RESET_PEX_USB_UPHY_L1 139 -#define TEGRA186_RESET_PEX_USB_UPHY_L0 140 -#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 -#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 -#define TEGRA186_RESET_TSCTNVI 143 -#define TEGRA186_RESET_EXTPERIPH4 144 -#define TEGRA186_RESET_DSIPADCTL 145 -#define TEGRA186_RESET_AUD_MCLK 146 -#define TEGRA186_RESET_MPHY_CLK_CTL 147 -#define TEGRA186_RESET_MPHY_L1_RX 148 -#define TEGRA186_RESET_MPHY_L1_TX 149 -#define TEGRA186_RESET_UFSHC_LP 150 -#define TEGRA186_RESET_BPMP_NIC 151 -#define TEGRA186_RESET_BPMP_NSYSPORESET 152 -#define TEGRA186_RESET_BPMP_NRESET 153 -#define TEGRA186_RESET_BPMP_DBGRESETN 154 -#define TEGRA186_RESET_BPMP_PRESETDBGN 155 -#define TEGRA186_RESET_BPMP_PM 156 -#define TEGRA186_RESET_BPMP_CVC 157 -#define TEGRA186_RESET_BPMP_DMA 158 -#define TEGRA186_RESET_BPMP_HSP 159 -#define TEGRA186_RESET_TSCTNBPMP 160 -#define TEGRA186_RESET_BPMP_TKE 161 -#define TEGRA186_RESET_BPMP_GTE 162 -#define TEGRA186_RESET_BPMP_PM_ACTMON 163 -#define TEGRA186_RESET_AON_NIC 164 -#define TEGRA186_RESET_AON_NSYSPORESET 165 -#define TEGRA186_RESET_AON_NRESET 166 -#define TEGRA186_RESET_AON_DBGRESETN 167 -#define TEGRA186_RESET_AON_PRESETDBGN 168 -#define TEGRA186_RESET_AON_ACTMON 169 -#define TEGRA186_RESET_AOPM 170 -#define TEGRA186_RESET_AOVC 171 -#define TEGRA186_RESET_AON_DMA 172 -#define TEGRA186_RESET_AON_GPIO 173 -#define TEGRA186_RESET_AON_HSP 174 -#define TEGRA186_RESET_TSCTNAON 175 -#define TEGRA186_RESET_AON_TKE 176 -#define TEGRA186_RESET_AON_GTE 177 -#define TEGRA186_RESET_SCE_NIC 178 -#define TEGRA186_RESET_SCE_NSYSPORESET 179 -#define TEGRA186_RESET_SCE_NRESET 180 -#define TEGRA186_RESET_SCE_DBGRESETN 181 -#define TEGRA186_RESET_SCE_PRESETDBGN 182 -#define TEGRA186_RESET_SCE_ACTMON 183 -#define TEGRA186_RESET_SCE_PM 184 -#define TEGRA186_RESET_SCE_DMA 185 -#define TEGRA186_RESET_SCE_HSP 186 -#define TEGRA186_RESET_TSCTNSCE 187 -#define TEGRA186_RESET_SCE_TKE 188 -#define TEGRA186_RESET_SCE_GTE 189 -#define TEGRA186_RESET_SCE_CFG 190 -#define TEGRA186_RESET_ADSP_ALL 191 -/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ -#define TEGRA186_RESET_UFSHC_LP_SEQ 192 -#define TEGRA186_RESET_SIZE 193 - -#endif diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h deleted file mode 100644 index 729ab9fc325e..000000000000 --- a/include/dt-bindings/thermal/tegra124-soctherm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra124-soctherm. - */ - -#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H -#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H - -#define TEGRA124_SOCTHERM_SENSOR_CPU 0 -#define TEGRA124_SOCTHERM_SENSOR_MEM 1 -#define TEGRA124_SOCTHERM_SENSOR_GPU 2 -#define TEGRA124_SOCTHERM_SENSOR_PLLX 3 -#define TEGRA124_SOCTHERM_SENSOR_NUM 4 - -#endif

Drop in favour of dts/upstream.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/r7s72100-clock.h | 112 ------------- include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 59 ------- include/dt-bindings/clock/r8a774b1-cpg-mssr.h | 57 ------- include/dt-bindings/clock/r8a774c0-cpg-mssr.h | 61 ------- include/dt-bindings/clock/r8a774e1-cpg-mssr.h | 59 ------- include/dt-bindings/clock/r8a7790-clock.h | 158 ------------------ include/dt-bindings/clock/r8a7790-cpg-mssr.h | 48 ------ include/dt-bindings/clock/r8a7791-clock.h | 161 ------------------- include/dt-bindings/clock/r8a7791-cpg-mssr.h | 44 ------ include/dt-bindings/clock/r8a7792-clock.h | 98 ------------ include/dt-bindings/clock/r8a7792-cpg-mssr.h | 39 ----- include/dt-bindings/clock/r8a7793-clock.h | 159 ------------------- include/dt-bindings/clock/r8a7793-cpg-mssr.h | 44 ------ include/dt-bindings/clock/r8a7794-clock.h | 137 ---------------- include/dt-bindings/clock/r8a7794-cpg-mssr.h | 43 ----- include/dt-bindings/clock/r8a7795-cpg-mssr.h | 66 -------- include/dt-bindings/clock/r8a7796-cpg-mssr.h | 65 -------- include/dt-bindings/clock/r8a77961-cpg-mssr.h | 65 -------- include/dt-bindings/clock/r8a77965-cpg-mssr.h | 62 -------- include/dt-bindings/clock/r8a77970-cpg-mssr.h | 44 ------ include/dt-bindings/clock/r8a77980-cpg-mssr.h | 51 ------ include/dt-bindings/clock/r8a77990-cpg-mssr.h | 62 -------- include/dt-bindings/clock/r8a77995-cpg-mssr.h | 54 ------- include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 55 ------- include/dt-bindings/clock/r8a779f0-cpg-mssr.h | 64 -------- include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 90 ----------- include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 ----------------- include/dt-bindings/clock/r9a07g044-cpg.h | 220 -------------------------- include/dt-bindings/clock/renesas-cpg-mssr.h | 15 -- 29 files changed, 2341 deletions(-)

diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h deleted file mode 100644 index a267ac250143..000000000000 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2014 Renesas Solutions Corp. - * Copyright (C) 2014 Wolfram Sang, Sang Engineering wsa@sang-engineering.com - */ - -#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ -#define __DT_BINDINGS_CLOCK_R7S72100_H__ - -#define R7S72100_CLK_PLL 0 -#define R7S72100_CLK_I 1 -#define R7S72100_CLK_G 2 - -/* MSTP2 */ -#define R7S72100_CLK_CORESIGHT 0 - -/* MSTP3 */ -#define R7S72100_CLK_IEBUS 7 -#define R7S72100_CLK_IRDA 6 -#define R7S72100_CLK_LIN0 5 -#define R7S72100_CLK_LIN1 4 -#define R7S72100_CLK_MTU2 3 -#define R7S72100_CLK_CAN 2 -#define R7S72100_CLK_ADCPWR 1 -#define R7S72100_CLK_PWM 0 - -/* MSTP4 */ -#define R7S72100_CLK_SCIF0 7 -#define R7S72100_CLK_SCIF1 6 -#define R7S72100_CLK_SCIF2 5 -#define R7S72100_CLK_SCIF3 4 -#define R7S72100_CLK_SCIF4 3 -#define R7S72100_CLK_SCIF5 2 -#define R7S72100_CLK_SCIF6 1 -#define R7S72100_CLK_SCIF7 0 - -/* MSTP5 */ -#define R7S72100_CLK_SCI0 7 -#define R7S72100_CLK_SCI1 6 -#define R7S72100_CLK_SG0 5 -#define R7S72100_CLK_SG1 4 -#define R7S72100_CLK_SG2 3 -#define R7S72100_CLK_SG3 2 -#define R7S72100_CLK_OSTM0 1 -#define R7S72100_CLK_OSTM1 0 - -/* MSTP6 */ -#define R7S72100_CLK_ADC 7 -#define R7S72100_CLK_CEU 6 -#define R7S72100_CLK_DOC0 5 -#define R7S72100_CLK_DOC1 4 -#define R7S72100_CLK_DRC0 3 -#define R7S72100_CLK_DRC1 2 -#define R7S72100_CLK_JCU 1 -#define R7S72100_CLK_RTC 0 - -/* MSTP7 */ -#define R7S72100_CLK_VDEC0 7 -#define R7S72100_CLK_VDEC1 6 -#define R7S72100_CLK_ETHER 4 -#define R7S72100_CLK_NAND 3 -#define R7S72100_CLK_USB0 1 -#define R7S72100_CLK_USB1 0 - -/* MSTP8 */ -#define R7S72100_CLK_IMR0 7 -#define R7S72100_CLK_IMR1 6 -#define R7S72100_CLK_IMRDISP 5 -#define R7S72100_CLK_MMCIF 4 -#define R7S72100_CLK_MLB 3 -#define R7S72100_CLK_ETHAVB 2 -#define R7S72100_CLK_SCUX 1 - -/* MSTP9 */ -#define R7S72100_CLK_I2C0 7 -#define R7S72100_CLK_I2C1 6 -#define R7S72100_CLK_I2C2 5 -#define R7S72100_CLK_I2C3 4 -#define R7S72100_CLK_SPIBSC0 3 -#define R7S72100_CLK_SPIBSC1 2 -#define R7S72100_CLK_VDC50 1 /* and LVDS */ -#define R7S72100_CLK_VDC51 0 - -/* MSTP10 */ -#define R7S72100_CLK_SPI0 7 -#define R7S72100_CLK_SPI1 6 -#define R7S72100_CLK_SPI2 5 -#define R7S72100_CLK_SPI3 4 -#define R7S72100_CLK_SPI4 3 -#define R7S72100_CLK_CDROM 2 -#define R7S72100_CLK_SPDIF 1 -#define R7S72100_CLK_RGPVG2 0 - -/* MSTP11 */ -#define R7S72100_CLK_SSI0 5 -#define R7S72100_CLK_SSI1 4 -#define R7S72100_CLK_SSI2 3 -#define R7S72100_CLK_SSI3 2 -#define R7S72100_CLK_SSI4 1 -#define R7S72100_CLK_SSI5 0 - -/* MSTP12 */ -#define R7S72100_CLK_SDHI00 3 -#define R7S72100_CLK_SDHI01 2 -#define R7S72100_CLK_SDHI10 1 -#define R7S72100_CLK_SDHI11 0 - -/* MSTP13 */ -#define R7S72100_CLK_PIX1 2 -#define R7S72100_CLK_PIX0 1 - -#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h deleted file mode 100644 index e355363f40c2..000000000000 --- a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a774a1 CPG Core Clocks */ -#define R8A774A1_CLK_Z 0 -#define R8A774A1_CLK_Z2 1 -#define R8A774A1_CLK_ZG 2 -#define R8A774A1_CLK_ZTR 3 -#define R8A774A1_CLK_ZTRD2 4 -#define R8A774A1_CLK_ZT 5 -#define R8A774A1_CLK_ZX 6 -#define R8A774A1_CLK_S0D1 7 -#define R8A774A1_CLK_S0D2 8 -#define R8A774A1_CLK_S0D3 9 -#define R8A774A1_CLK_S0D4 10 -#define R8A774A1_CLK_S0D6 11 -#define R8A774A1_CLK_S0D8 12 -#define R8A774A1_CLK_S0D12 13 -#define R8A774A1_CLK_S1D2 14 -#define R8A774A1_CLK_S1D4 15 -#define R8A774A1_CLK_S2D1 16 -#define R8A774A1_CLK_S2D2 17 -#define R8A774A1_CLK_S2D4 18 -#define R8A774A1_CLK_S3D1 19 -#define R8A774A1_CLK_S3D2 20 -#define R8A774A1_CLK_S3D4 21 -#define R8A774A1_CLK_LB 22 -#define R8A774A1_CLK_CL 23 -#define R8A774A1_CLK_ZB3 24 -#define R8A774A1_CLK_ZB3D2 25 -#define R8A774A1_CLK_ZB3D4 26 -#define R8A774A1_CLK_CR 27 -#define R8A774A1_CLK_CRD2 28 -#define R8A774A1_CLK_SD0H 29 -#define R8A774A1_CLK_SD0 30 -#define R8A774A1_CLK_SD1H 31 -#define R8A774A1_CLK_SD1 32 -#define R8A774A1_CLK_SD2H 33 -#define R8A774A1_CLK_SD2 34 -#define R8A774A1_CLK_SD3H 35 -#define R8A774A1_CLK_SD3 36 -#define R8A774A1_CLK_RPC 37 -#define R8A774A1_CLK_RPCD2 38 -#define R8A774A1_CLK_MSO 39 -#define R8A774A1_CLK_HDMI 40 -#define R8A774A1_CLK_CSI0 41 -#define R8A774A1_CLK_CP 42 -#define R8A774A1_CLK_CPEX 43 -#define R8A774A1_CLK_R 44 -#define R8A774A1_CLK_OSC 45 -#define R8A774A1_CLK_CANFD 46 - -#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h deleted file mode 100644 index 1355451b74b0..000000000000 --- a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a774b1 CPG Core Clocks */ -#define R8A774B1_CLK_Z 0 -#define R8A774B1_CLK_ZG 1 -#define R8A774B1_CLK_ZTR 2 -#define R8A774B1_CLK_ZTRD2 3 -#define R8A774B1_CLK_ZT 4 -#define R8A774B1_CLK_ZX 5 -#define R8A774B1_CLK_S0D1 6 -#define R8A774B1_CLK_S0D2 7 -#define R8A774B1_CLK_S0D3 8 -#define R8A774B1_CLK_S0D4 9 -#define R8A774B1_CLK_S0D6 10 -#define R8A774B1_CLK_S0D8 11 -#define R8A774B1_CLK_S0D12 12 -#define R8A774B1_CLK_S1D2 13 -#define R8A774B1_CLK_S1D4 14 -#define R8A774B1_CLK_S2D1 15 -#define R8A774B1_CLK_S2D2 16 -#define R8A774B1_CLK_S2D4 17 -#define R8A774B1_CLK_S3D1 18 -#define R8A774B1_CLK_S3D2 19 -#define R8A774B1_CLK_S3D4 20 -#define R8A774B1_CLK_LB 21 -#define R8A774B1_CLK_CL 22 -#define R8A774B1_CLK_ZB3 23 -#define R8A774B1_CLK_ZB3D2 24 -#define R8A774B1_CLK_CR 25 -#define R8A774B1_CLK_DDR 26 -#define R8A774B1_CLK_SD0H 27 -#define R8A774B1_CLK_SD0 28 -#define R8A774B1_CLK_SD1H 29 -#define R8A774B1_CLK_SD1 30 -#define R8A774B1_CLK_SD2H 31 -#define R8A774B1_CLK_SD2 32 -#define R8A774B1_CLK_SD3H 33 -#define R8A774B1_CLK_SD3 34 -#define R8A774B1_CLK_RPC 35 -#define R8A774B1_CLK_RPCD2 36 -#define R8A774B1_CLK_MSO 37 -#define R8A774B1_CLK_HDMI 38 -#define R8A774B1_CLK_CSI0 39 -#define R8A774B1_CLK_CP 40 -#define R8A774B1_CLK_CPEX 41 -#define R8A774B1_CLK_R 42 -#define R8A774B1_CLK_OSC 43 -#define R8A774B1_CLK_CANFD 44 - -#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h deleted file mode 100644 index 8ad9cd6be8e9..000000000000 --- a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a774c0 CPG Core Clocks */ -#define R8A774C0_CLK_Z2 0 -#define R8A774C0_CLK_ZG 1 -#define R8A774C0_CLK_ZTR 2 -#define R8A774C0_CLK_ZT 3 -#define R8A774C0_CLK_ZX 4 -#define R8A774C0_CLK_S0D1 5 -#define R8A774C0_CLK_S0D3 6 -#define R8A774C0_CLK_S0D6 7 -#define R8A774C0_CLK_S0D12 8 -#define R8A774C0_CLK_S0D24 9 -#define R8A774C0_CLK_S1D1 10 -#define R8A774C0_CLK_S1D2 11 -#define R8A774C0_CLK_S1D4 12 -#define R8A774C0_CLK_S2D1 13 -#define R8A774C0_CLK_S2D2 14 -#define R8A774C0_CLK_S2D4 15 -#define R8A774C0_CLK_S3D1 16 -#define R8A774C0_CLK_S3D2 17 -#define R8A774C0_CLK_S3D4 18 -#define R8A774C0_CLK_S0D6C 19 -#define R8A774C0_CLK_S3D1C 20 -#define R8A774C0_CLK_S3D2C 21 -#define R8A774C0_CLK_S3D4C 22 -#define R8A774C0_CLK_LB 23 -#define R8A774C0_CLK_CL 24 -#define R8A774C0_CLK_ZB3 25 -#define R8A774C0_CLK_ZB3D2 26 -#define R8A774C0_CLK_CR 27 -#define R8A774C0_CLK_CRD2 28 -#define R8A774C0_CLK_SD0H 29 -#define R8A774C0_CLK_SD0 30 -#define R8A774C0_CLK_SD1H 31 -#define R8A774C0_CLK_SD1 32 -#define R8A774C0_CLK_SD3H 33 -#define R8A774C0_CLK_SD3 34 -#define R8A774C0_CLK_RPC 35 -#define R8A774C0_CLK_RPCD2 36 -#define R8A774C0_CLK_ZA2 37 -#define R8A774C0_CLK_ZA8 38 -#define R8A774C0_CLK_Z2D 39 -#define R8A774C0_CLK_MSO 40 -#define R8A774C0_CLK_R 41 -#define R8A774C0_CLK_OSC 42 -#define R8A774C0_CLK_LV0 43 -#define R8A774C0_CLK_LV1 44 -#define R8A774C0_CLK_CSI0 45 -#define R8A774C0_CLK_CP 46 -#define R8A774C0_CLK_CPEX 47 -#define R8A774C0_CLK_CANFD 48 - -#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h deleted file mode 100644 index b2fc1d1c3c47..000000000000 --- a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* R8A774E1 CPG Core Clocks */ -#define R8A774E1_CLK_Z 0 -#define R8A774E1_CLK_Z2 1 -#define R8A774E1_CLK_ZG 2 -#define R8A774E1_CLK_ZTR 3 -#define R8A774E1_CLK_ZTRD2 4 -#define R8A774E1_CLK_ZT 5 -#define R8A774E1_CLK_ZX 6 -#define R8A774E1_CLK_S0D1 7 -#define R8A774E1_CLK_S0D2 8 -#define R8A774E1_CLK_S0D3 9 -#define R8A774E1_CLK_S0D4 10 -#define R8A774E1_CLK_S0D6 11 -#define R8A774E1_CLK_S0D8 12 -#define R8A774E1_CLK_S0D12 13 -#define R8A774E1_CLK_S1D2 14 -#define R8A774E1_CLK_S1D4 15 -#define R8A774E1_CLK_S2D1 16 -#define R8A774E1_CLK_S2D2 17 -#define R8A774E1_CLK_S2D4 18 -#define R8A774E1_CLK_S3D1 19 -#define R8A774E1_CLK_S3D2 20 -#define R8A774E1_CLK_S3D4 21 -#define R8A774E1_CLK_LB 22 -#define R8A774E1_CLK_CL 23 -#define R8A774E1_CLK_ZB3 24 -#define R8A774E1_CLK_ZB3D2 25 -#define R8A774E1_CLK_ZB3D4 26 -#define R8A774E1_CLK_CR 27 -#define R8A774E1_CLK_CRD2 28 -#define R8A774E1_CLK_SD0H 29 -#define R8A774E1_CLK_SD0 30 -#define R8A774E1_CLK_SD1H 31 -#define R8A774E1_CLK_SD1 32 -#define R8A774E1_CLK_SD2H 33 -#define R8A774E1_CLK_SD2 34 -#define R8A774E1_CLK_SD3H 35 -#define R8A774E1_CLK_SD3 36 -#define R8A774E1_CLK_RPC 37 -#define R8A774E1_CLK_RPCD2 38 -#define R8A774E1_CLK_MSO 39 -#define R8A774E1_CLK_HDMI 40 -#define R8A774E1_CLK_CSI0 41 -#define R8A774E1_CLK_CP 42 -#define R8A774E1_CLK_CPEX 43 -#define R8A774E1_CLK_R 44 -#define R8A774E1_CLK_OSC 45 -#define R8A774E1_CLK_CANFD 46 - -#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h deleted file mode 100644 index c92ff1e60223..000000000000 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ -#define __DT_BINDINGS_CLOCK_R8A7790_H__ - -/* CPG */ -#define R8A7790_CLK_MAIN 0 -#define R8A7790_CLK_PLL0 1 -#define R8A7790_CLK_PLL1 2 -#define R8A7790_CLK_PLL3 3 -#define R8A7790_CLK_LB 4 -#define R8A7790_CLK_QSPI 5 -#define R8A7790_CLK_SDH 6 -#define R8A7790_CLK_SD0 7 -#define R8A7790_CLK_SD1 8 -#define R8A7790_CLK_Z 9 -#define R8A7790_CLK_RCAN 10 -#define R8A7790_CLK_ADSP 11 - -/* MSTP0 */ -#define R8A7790_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7790_CLK_VCP1 0 -#define R8A7790_CLK_VCP0 1 -#define R8A7790_CLK_VPC1 2 -#define R8A7790_CLK_VPC0 3 -#define R8A7790_CLK_JPU 6 -#define R8A7790_CLK_SSP1 9 -#define R8A7790_CLK_TMU1 11 -#define R8A7790_CLK_3DG 12 -#define R8A7790_CLK_2DDMAC 15 -#define R8A7790_CLK_FDP1_2 17 -#define R8A7790_CLK_FDP1_1 18 -#define R8A7790_CLK_FDP1_0 19 -#define R8A7790_CLK_TMU3 21 -#define R8A7790_CLK_TMU2 22 -#define R8A7790_CLK_CMT0 24 -#define R8A7790_CLK_TMU0 25 -#define R8A7790_CLK_VSP1_DU1 27 -#define R8A7790_CLK_VSP1_DU0 28 -#define R8A7790_CLK_VSP1_R 30 -#define R8A7790_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7790_CLK_SCIFA2 2 -#define R8A7790_CLK_SCIFA1 3 -#define R8A7790_CLK_SCIFA0 4 -#define R8A7790_CLK_MSIOF2 5 -#define R8A7790_CLK_SCIFB0 6 -#define R8A7790_CLK_SCIFB1 7 -#define R8A7790_CLK_MSIOF1 8 -#define R8A7790_CLK_MSIOF3 15 -#define R8A7790_CLK_SCIFB2 16 -#define R8A7790_CLK_SYS_DMAC1 18 -#define R8A7790_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7790_CLK_IIC2 0 -#define R8A7790_CLK_TPU0 4 -#define R8A7790_CLK_MMCIF1 5 -#define R8A7790_CLK_SCIF2 10 -#define R8A7790_CLK_SDHI3 11 -#define R8A7790_CLK_SDHI2 12 -#define R8A7790_CLK_SDHI1 13 -#define R8A7790_CLK_SDHI0 14 -#define R8A7790_CLK_MMCIF0 15 -#define R8A7790_CLK_IIC0 18 -#define R8A7790_CLK_PCIEC 19 -#define R8A7790_CLK_IIC1 23 -#define R8A7790_CLK_SSUSB 28 -#define R8A7790_CLK_CMT1 29 -#define R8A7790_CLK_USBDMAC0 30 -#define R8A7790_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7790_CLK_IRQC 7 -#define R8A7790_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7790_CLK_AUDIO_DMAC1 1 -#define R8A7790_CLK_AUDIO_DMAC0 2 -#define R8A7790_CLK_ADSP_MOD 6 -#define R8A7790_CLK_THERMAL 22 -#define R8A7790_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7790_CLK_EHCI 3 -#define R8A7790_CLK_HSUSB 4 -#define R8A7790_CLK_HSCIF1 16 -#define R8A7790_CLK_HSCIF0 17 -#define R8A7790_CLK_SCIF1 20 -#define R8A7790_CLK_SCIF0 21 -#define R8A7790_CLK_DU2 22 -#define R8A7790_CLK_DU1 23 -#define R8A7790_CLK_DU0 24 -#define R8A7790_CLK_LVDS1 25 -#define R8A7790_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7790_CLK_MLB 2 -#define R8A7790_CLK_VIN3 8 -#define R8A7790_CLK_VIN2 9 -#define R8A7790_CLK_VIN1 10 -#define R8A7790_CLK_VIN0 11 -#define R8A7790_CLK_ETHERAVB 12 -#define R8A7790_CLK_ETHER 13 -#define R8A7790_CLK_SATA1 14 -#define R8A7790_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7790_CLK_GPIO5 7 -#define R8A7790_CLK_GPIO4 8 -#define R8A7790_CLK_GPIO3 9 -#define R8A7790_CLK_GPIO2 10 -#define R8A7790_CLK_GPIO1 11 -#define R8A7790_CLK_GPIO0 12 -#define R8A7790_CLK_RCAN1 15 -#define R8A7790_CLK_RCAN0 16 -#define R8A7790_CLK_QSPI_MOD 17 -#define R8A7790_CLK_IICDVFS 26 -#define R8A7790_CLK_I2C3 28 -#define R8A7790_CLK_I2C2 29 -#define R8A7790_CLK_I2C1 30 -#define R8A7790_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7790_CLK_SSI_ALL 5 -#define R8A7790_CLK_SSI9 6 -#define R8A7790_CLK_SSI8 7 -#define R8A7790_CLK_SSI7 8 -#define R8A7790_CLK_SSI6 9 -#define R8A7790_CLK_SSI5 10 -#define R8A7790_CLK_SSI4 11 -#define R8A7790_CLK_SSI3 12 -#define R8A7790_CLK_SSI2 13 -#define R8A7790_CLK_SSI1 14 -#define R8A7790_CLK_SSI0 15 -#define R8A7790_CLK_SCU_ALL 17 -#define R8A7790_CLK_SCU_DVC1 18 -#define R8A7790_CLK_SCU_DVC0 19 -#define R8A7790_CLK_SCU_CTU1_MIX1 20 -#define R8A7790_CLK_SCU_CTU0_MIX0 21 -#define R8A7790_CLK_SCU_SRC9 22 -#define R8A7790_CLK_SCU_SRC8 23 -#define R8A7790_CLK_SCU_SRC7 24 -#define R8A7790_CLK_SCU_SRC6 25 -#define R8A7790_CLK_SCU_SRC5 26 -#define R8A7790_CLK_SCU_SRC4 27 -#define R8A7790_CLK_SCU_SRC3 28 -#define R8A7790_CLK_SCU_SRC2 29 -#define R8A7790_CLK_SCU_SRC1 30 -#define R8A7790_CLK_SCU_SRC0 31 - -#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h deleted file mode 100644 index c5955b56b36d..000000000000 --- a/include/dt-bindings/clock/r8a7790-cpg-mssr.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a7790 CPG Core Clocks */ -#define R8A7790_CLK_Z 0 -#define R8A7790_CLK_Z2 1 -#define R8A7790_CLK_ZG 2 -#define R8A7790_CLK_ZTR 3 -#define R8A7790_CLK_ZTRD2 4 -#define R8A7790_CLK_ZT 5 -#define R8A7790_CLK_ZX 6 -#define R8A7790_CLK_ZS 7 -#define R8A7790_CLK_HP 8 -#define R8A7790_CLK_I 9 -#define R8A7790_CLK_B 10 -#define R8A7790_CLK_LB 11 -#define R8A7790_CLK_P 12 -#define R8A7790_CLK_CL 13 -#define R8A7790_CLK_M2 14 -#define R8A7790_CLK_ADSP 15 -#define R8A7790_CLK_IMP 16 -#define R8A7790_CLK_ZB3 17 -#define R8A7790_CLK_ZB3D2 18 -#define R8A7790_CLK_DDR 19 -#define R8A7790_CLK_SDH 20 -#define R8A7790_CLK_SD0 21 -#define R8A7790_CLK_SD1 22 -#define R8A7790_CLK_SD2 23 -#define R8A7790_CLK_SD3 24 -#define R8A7790_CLK_MMC0 25 -#define R8A7790_CLK_MMC1 26 -#define R8A7790_CLK_MP 27 -#define R8A7790_CLK_SSP 28 -#define R8A7790_CLK_SSPRS 29 -#define R8A7790_CLK_QSPI 30 -#define R8A7790_CLK_CP 31 -#define R8A7790_CLK_RCAN 32 -#define R8A7790_CLK_R 33 -#define R8A7790_CLK_OSC 34 - -#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h deleted file mode 100644 index bb4f18b1b3d5..000000000000 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__ -#define __DT_BINDINGS_CLOCK_R8A7791_H__ - -/* CPG */ -#define R8A7791_CLK_MAIN 0 -#define R8A7791_CLK_PLL0 1 -#define R8A7791_CLK_PLL1 2 -#define R8A7791_CLK_PLL3 3 -#define R8A7791_CLK_LB 4 -#define R8A7791_CLK_QSPI 5 -#define R8A7791_CLK_SDH 6 -#define R8A7791_CLK_SD0 7 -#define R8A7791_CLK_Z 8 -#define R8A7791_CLK_RCAN 9 -#define R8A7791_CLK_ADSP 10 - -/* MSTP0 */ -#define R8A7791_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7791_CLK_VCP0 1 -#define R8A7791_CLK_VPC0 3 -#define R8A7791_CLK_JPU 6 -#define R8A7791_CLK_SSP1 9 -#define R8A7791_CLK_TMU1 11 -#define R8A7791_CLK_3DG 12 -#define R8A7791_CLK_2DDMAC 15 -#define R8A7791_CLK_FDP1_1 18 -#define R8A7791_CLK_FDP1_0 19 -#define R8A7791_CLK_TMU3 21 -#define R8A7791_CLK_TMU2 22 -#define R8A7791_CLK_CMT0 24 -#define R8A7791_CLK_TMU0 25 -#define R8A7791_CLK_VSP1_DU1 27 -#define R8A7791_CLK_VSP1_DU0 28 -#define R8A7791_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7791_CLK_SCIFA2 2 -#define R8A7791_CLK_SCIFA1 3 -#define R8A7791_CLK_SCIFA0 4 -#define R8A7791_CLK_MSIOF2 5 -#define R8A7791_CLK_SCIFB0 6 -#define R8A7791_CLK_SCIFB1 7 -#define R8A7791_CLK_MSIOF1 8 -#define R8A7791_CLK_SCIFB2 16 -#define R8A7791_CLK_SYS_DMAC1 18 -#define R8A7791_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7791_CLK_TPU0 4 -#define R8A7791_CLK_SDHI2 11 -#define R8A7791_CLK_SDHI1 12 -#define R8A7791_CLK_SDHI0 14 -#define R8A7791_CLK_MMCIF0 15 -#define R8A7791_CLK_IIC0 18 -#define R8A7791_CLK_PCIEC 19 -#define R8A7791_CLK_IIC1 23 -#define R8A7791_CLK_SSUSB 28 -#define R8A7791_CLK_CMT1 29 -#define R8A7791_CLK_USBDMAC0 30 -#define R8A7791_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7791_CLK_IRQC 7 -#define R8A7791_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7791_CLK_AUDIO_DMAC1 1 -#define R8A7791_CLK_AUDIO_DMAC0 2 -#define R8A7791_CLK_ADSP_MOD 6 -#define R8A7791_CLK_THERMAL 22 -#define R8A7791_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7791_CLK_EHCI 3 -#define R8A7791_CLK_HSUSB 4 -#define R8A7791_CLK_HSCIF2 13 -#define R8A7791_CLK_SCIF5 14 -#define R8A7791_CLK_SCIF4 15 -#define R8A7791_CLK_HSCIF1 16 -#define R8A7791_CLK_HSCIF0 17 -#define R8A7791_CLK_SCIF3 18 -#define R8A7791_CLK_SCIF2 19 -#define R8A7791_CLK_SCIF1 20 -#define R8A7791_CLK_SCIF0 21 -#define R8A7791_CLK_DU1 23 -#define R8A7791_CLK_DU0 24 -#define R8A7791_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7791_CLK_IPMMU_SGX 0 -#define R8A7791_CLK_MLB 2 -#define R8A7791_CLK_VIN2 9 -#define R8A7791_CLK_VIN1 10 -#define R8A7791_CLK_VIN0 11 -#define R8A7791_CLK_ETHERAVB 12 -#define R8A7791_CLK_ETHER 13 -#define R8A7791_CLK_SATA1 14 -#define R8A7791_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7791_CLK_GYROADC 1 -#define R8A7791_CLK_GPIO7 4 -#define R8A7791_CLK_GPIO6 5 -#define R8A7791_CLK_GPIO5 7 -#define R8A7791_CLK_GPIO4 8 -#define R8A7791_CLK_GPIO3 9 -#define R8A7791_CLK_GPIO2 10 -#define R8A7791_CLK_GPIO1 11 -#define R8A7791_CLK_GPIO0 12 -#define R8A7791_CLK_RCAN1 15 -#define R8A7791_CLK_RCAN0 16 -#define R8A7791_CLK_QSPI_MOD 17 -#define R8A7791_CLK_I2C5 25 -#define R8A7791_CLK_IICDVFS 26 -#define R8A7791_CLK_I2C4 27 -#define R8A7791_CLK_I2C3 28 -#define R8A7791_CLK_I2C2 29 -#define R8A7791_CLK_I2C1 30 -#define R8A7791_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7791_CLK_SSI_ALL 5 -#define R8A7791_CLK_SSI9 6 -#define R8A7791_CLK_SSI8 7 -#define R8A7791_CLK_SSI7 8 -#define R8A7791_CLK_SSI6 9 -#define R8A7791_CLK_SSI5 10 -#define R8A7791_CLK_SSI4 11 -#define R8A7791_CLK_SSI3 12 -#define R8A7791_CLK_SSI2 13 -#define R8A7791_CLK_SSI1 14 -#define R8A7791_CLK_SSI0 15 -#define R8A7791_CLK_SCU_ALL 17 -#define R8A7791_CLK_SCU_DVC1 18 -#define R8A7791_CLK_SCU_DVC0 19 -#define R8A7791_CLK_SCU_CTU1_MIX1 20 -#define R8A7791_CLK_SCU_CTU0_MIX0 21 -#define R8A7791_CLK_SCU_SRC9 22 -#define R8A7791_CLK_SCU_SRC8 23 -#define R8A7791_CLK_SCU_SRC7 24 -#define R8A7791_CLK_SCU_SRC6 25 -#define R8A7791_CLK_SCU_SRC5 26 -#define R8A7791_CLK_SCU_SRC4 27 -#define R8A7791_CLK_SCU_SRC3 28 -#define R8A7791_CLK_SCU_SRC2 29 -#define R8A7791_CLK_SCU_SRC1 30 -#define R8A7791_CLK_SCU_SRC0 31 - -/* MSTP11 */ -#define R8A7791_CLK_SCIFA3 6 -#define R8A7791_CLK_SCIFA4 7 -#define R8A7791_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */ diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h deleted file mode 100644 index aadd06c566c0..000000000000 --- a/include/dt-bindings/clock/r8a7791-cpg-mssr.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a7791 CPG Core Clocks */ -#define R8A7791_CLK_Z 0 -#define R8A7791_CLK_ZG 1 -#define R8A7791_CLK_ZTR 2 -#define R8A7791_CLK_ZTRD2 3 -#define R8A7791_CLK_ZT 4 -#define R8A7791_CLK_ZX 5 -#define R8A7791_CLK_ZS 6 -#define R8A7791_CLK_HP 7 -#define R8A7791_CLK_I 8 -#define R8A7791_CLK_B 9 -#define R8A7791_CLK_LB 10 -#define R8A7791_CLK_P 11 -#define R8A7791_CLK_CL 12 -#define R8A7791_CLK_M2 13 -#define R8A7791_CLK_ADSP 14 -#define R8A7791_CLK_ZB3 15 -#define R8A7791_CLK_ZB3D2 16 -#define R8A7791_CLK_DDR 17 -#define R8A7791_CLK_SDH 18 -#define R8A7791_CLK_SD0 19 -#define R8A7791_CLK_SD2 20 -#define R8A7791_CLK_SD3 21 -#define R8A7791_CLK_MMC0 22 -#define R8A7791_CLK_MP 23 -#define R8A7791_CLK_SSP 24 -#define R8A7791_CLK_SSPRS 25 -#define R8A7791_CLK_QSPI 26 -#define R8A7791_CLK_CP 27 -#define R8A7791_CLK_RCAN 28 -#define R8A7791_CLK_R 29 -#define R8A7791_CLK_OSC 30 - -#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h deleted file mode 100644 index 2948d9ce3a14..000000000000 --- a/include/dt-bindings/clock/r8a7792-clock.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ -#define __DT_BINDINGS_CLOCK_R8A7792_H__ - -/* CPG */ -#define R8A7792_CLK_MAIN 0 -#define R8A7792_CLK_PLL0 1 -#define R8A7792_CLK_PLL1 2 -#define R8A7792_CLK_PLL3 3 -#define R8A7792_CLK_LB 4 -#define R8A7792_CLK_QSPI 5 - -/* MSTP0 */ -#define R8A7792_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7792_CLK_JPU 6 -#define R8A7792_CLK_TMU1 11 -#define R8A7792_CLK_TMU3 21 -#define R8A7792_CLK_TMU2 22 -#define R8A7792_CLK_CMT0 24 -#define R8A7792_CLK_TMU0 25 -#define R8A7792_CLK_VSP1DU1 27 -#define R8A7792_CLK_VSP1DU0 28 -#define R8A7792_CLK_VSP1_SY 31 - -/* MSTP2 */ -#define R8A7792_CLK_MSIOF1 8 -#define R8A7792_CLK_SYS_DMAC1 18 -#define R8A7792_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7792_CLK_TPU0 4 -#define R8A7792_CLK_SDHI0 14 -#define R8A7792_CLK_CMT1 29 - -/* MSTP4 */ -#define R8A7792_CLK_IRQC 7 -#define R8A7792_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7792_CLK_AUDIO_DMAC0 2 -#define R8A7792_CLK_THERMAL 22 -#define R8A7792_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7792_CLK_HSCIF1 16 -#define R8A7792_CLK_HSCIF0 17 -#define R8A7792_CLK_SCIF3 18 -#define R8A7792_CLK_SCIF2 19 -#define R8A7792_CLK_SCIF1 20 -#define R8A7792_CLK_SCIF0 21 -#define R8A7792_CLK_DU1 23 -#define R8A7792_CLK_DU0 24 - -/* MSTP8 */ -#define R8A7792_CLK_VIN5 4 -#define R8A7792_CLK_VIN4 5 -#define R8A7792_CLK_VIN3 8 -#define R8A7792_CLK_VIN2 9 -#define R8A7792_CLK_VIN1 10 -#define R8A7792_CLK_VIN0 11 -#define R8A7792_CLK_ETHERAVB 12 - -/* MSTP9 */ -#define R8A7792_CLK_GPIO7 4 -#define R8A7792_CLK_GPIO6 5 -#define R8A7792_CLK_GPIO5 7 -#define R8A7792_CLK_GPIO4 8 -#define R8A7792_CLK_GPIO3 9 -#define R8A7792_CLK_GPIO2 10 -#define R8A7792_CLK_GPIO1 11 -#define R8A7792_CLK_GPIO0 12 -#define R8A7792_CLK_GPIO11 13 -#define R8A7792_CLK_GPIO10 14 -#define R8A7792_CLK_CAN1 15 -#define R8A7792_CLK_CAN0 16 -#define R8A7792_CLK_QSPI_MOD 17 -#define R8A7792_CLK_GPIO9 19 -#define R8A7792_CLK_GPIO8 21 -#define R8A7792_CLK_I2C5 25 -#define R8A7792_CLK_IICDVFS 26 -#define R8A7792_CLK_I2C4 27 -#define R8A7792_CLK_I2C3 28 -#define R8A7792_CLK_I2C2 29 -#define R8A7792_CLK_I2C1 30 -#define R8A7792_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7792_CLK_SSI_ALL 5 -#define R8A7792_CLK_SSI4 11 -#define R8A7792_CLK_SSI3 12 - -#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h deleted file mode 100644 index 829c44db0271..000000000000 --- a/include/dt-bindings/clock/r8a7792-cpg-mssr.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a7792 CPG Core Clocks */ -#define R8A7792_CLK_Z 0 -#define R8A7792_CLK_ZG 1 -#define R8A7792_CLK_ZTR 2 -#define R8A7792_CLK_ZTRD2 3 -#define R8A7792_CLK_ZT 4 -#define R8A7792_CLK_ZX 5 -#define R8A7792_CLK_ZS 6 -#define R8A7792_CLK_HP 7 -#define R8A7792_CLK_I 8 -#define R8A7792_CLK_B 9 -#define R8A7792_CLK_LB 10 -#define R8A7792_CLK_P 11 -#define R8A7792_CLK_CL 12 -#define R8A7792_CLK_M2 13 -#define R8A7792_CLK_IMP 14 -#define R8A7792_CLK_ZB3 15 -#define R8A7792_CLK_ZB3D2 16 -#define R8A7792_CLK_DDR 17 -#define R8A7792_CLK_SD 18 -#define R8A7792_CLK_MP 19 -#define R8A7792_CLK_QSPI 20 -#define R8A7792_CLK_CP 21 -#define R8A7792_CLK_CPEX 22 -#define R8A7792_CLK_RCAN 23 -#define R8A7792_CLK_R 24 -#define R8A7792_CLK_OSC 25 - -#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h deleted file mode 100644 index 49c66d8ed178..000000000000 --- a/include/dt-bindings/clock/r8a7793-clock.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * r8a7793 clock definition - * - * Copyright (C) 2014 Renesas Electronics Corporation - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ -#define __DT_BINDINGS_CLOCK_R8A7793_H__ - -/* CPG */ -#define R8A7793_CLK_MAIN 0 -#define R8A7793_CLK_PLL0 1 -#define R8A7793_CLK_PLL1 2 -#define R8A7793_CLK_PLL3 3 -#define R8A7793_CLK_LB 4 -#define R8A7793_CLK_QSPI 5 -#define R8A7793_CLK_SDH 6 -#define R8A7793_CLK_SD0 7 -#define R8A7793_CLK_Z 8 -#define R8A7793_CLK_RCAN 9 -#define R8A7793_CLK_ADSP 10 - -/* MSTP0 */ -#define R8A7793_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7793_CLK_VCP0 1 -#define R8A7793_CLK_VPC0 3 -#define R8A7793_CLK_SSP1 9 -#define R8A7793_CLK_TMU1 11 -#define R8A7793_CLK_3DG 12 -#define R8A7793_CLK_2DDMAC 15 -#define R8A7793_CLK_FDP1_1 18 -#define R8A7793_CLK_FDP1_0 19 -#define R8A7793_CLK_TMU3 21 -#define R8A7793_CLK_TMU2 22 -#define R8A7793_CLK_CMT0 24 -#define R8A7793_CLK_TMU0 25 -#define R8A7793_CLK_VSP1_DU1 27 -#define R8A7793_CLK_VSP1_DU0 28 -#define R8A7793_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7793_CLK_SCIFA2 2 -#define R8A7793_CLK_SCIFA1 3 -#define R8A7793_CLK_SCIFA0 4 -#define R8A7793_CLK_MSIOF2 5 -#define R8A7793_CLK_SCIFB0 6 -#define R8A7793_CLK_SCIFB1 7 -#define R8A7793_CLK_MSIOF1 8 -#define R8A7793_CLK_SCIFB2 16 -#define R8A7793_CLK_SYS_DMAC1 18 -#define R8A7793_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7793_CLK_TPU0 4 -#define R8A7793_CLK_SDHI2 11 -#define R8A7793_CLK_SDHI1 12 -#define R8A7793_CLK_SDHI0 14 -#define R8A7793_CLK_MMCIF0 15 -#define R8A7793_CLK_IIC0 18 -#define R8A7793_CLK_PCIEC 19 -#define R8A7793_CLK_IIC1 23 -#define R8A7793_CLK_SSUSB 28 -#define R8A7793_CLK_CMT1 29 -#define R8A7793_CLK_USBDMAC0 30 -#define R8A7793_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7793_CLK_IRQC 7 -#define R8A7793_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7793_CLK_AUDIO_DMAC1 1 -#define R8A7793_CLK_AUDIO_DMAC0 2 -#define R8A7793_CLK_ADSP_MOD 6 -#define R8A7793_CLK_THERMAL 22 -#define R8A7793_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7793_CLK_EHCI 3 -#define R8A7793_CLK_HSUSB 4 -#define R8A7793_CLK_HSCIF2 13 -#define R8A7793_CLK_SCIF5 14 -#define R8A7793_CLK_SCIF4 15 -#define R8A7793_CLK_HSCIF1 16 -#define R8A7793_CLK_HSCIF0 17 -#define R8A7793_CLK_SCIF3 18 -#define R8A7793_CLK_SCIF2 19 -#define R8A7793_CLK_SCIF1 20 -#define R8A7793_CLK_SCIF0 21 -#define R8A7793_CLK_DU1 23 -#define R8A7793_CLK_DU0 24 -#define R8A7793_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7793_CLK_IPMMU_SGX 0 -#define R8A7793_CLK_VIN2 9 -#define R8A7793_CLK_VIN1 10 -#define R8A7793_CLK_VIN0 11 -#define R8A7793_CLK_ETHER 13 -#define R8A7793_CLK_SATA1 14 -#define R8A7793_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7793_CLK_GPIO7 4 -#define R8A7793_CLK_GPIO6 5 -#define R8A7793_CLK_GPIO5 7 -#define R8A7793_CLK_GPIO4 8 -#define R8A7793_CLK_GPIO3 9 -#define R8A7793_CLK_GPIO2 10 -#define R8A7793_CLK_GPIO1 11 -#define R8A7793_CLK_GPIO0 12 -#define R8A7793_CLK_RCAN1 15 -#define R8A7793_CLK_RCAN0 16 -#define R8A7793_CLK_QSPI_MOD 17 -#define R8A7793_CLK_I2C5 25 -#define R8A7793_CLK_IICDVFS 26 -#define R8A7793_CLK_I2C4 27 -#define R8A7793_CLK_I2C3 28 -#define R8A7793_CLK_I2C2 29 -#define R8A7793_CLK_I2C1 30 -#define R8A7793_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7793_CLK_SSI_ALL 5 -#define R8A7793_CLK_SSI9 6 -#define R8A7793_CLK_SSI8 7 -#define R8A7793_CLK_SSI7 8 -#define R8A7793_CLK_SSI6 9 -#define R8A7793_CLK_SSI5 10 -#define R8A7793_CLK_SSI4 11 -#define R8A7793_CLK_SSI3 12 -#define R8A7793_CLK_SSI2 13 -#define R8A7793_CLK_SSI1 14 -#define R8A7793_CLK_SSI0 15 -#define R8A7793_CLK_SCU_ALL 17 -#define R8A7793_CLK_SCU_DVC1 18 -#define R8A7793_CLK_SCU_DVC0 19 -#define R8A7793_CLK_SCU_CTU1_MIX1 20 -#define R8A7793_CLK_SCU_CTU0_MIX0 21 -#define R8A7793_CLK_SCU_SRC9 22 -#define R8A7793_CLK_SCU_SRC8 23 -#define R8A7793_CLK_SCU_SRC7 24 -#define R8A7793_CLK_SCU_SRC6 25 -#define R8A7793_CLK_SCU_SRC5 26 -#define R8A7793_CLK_SCU_SRC4 27 -#define R8A7793_CLK_SCU_SRC3 28 -#define R8A7793_CLK_SCU_SRC2 29 -#define R8A7793_CLK_SCU_SRC1 30 -#define R8A7793_CLK_SCU_SRC0 31 - -/* MSTP11 */ -#define R8A7793_CLK_SCIFA3 6 -#define R8A7793_CLK_SCIFA4 7 -#define R8A7793_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */ diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h deleted file mode 100644 index d1ff646c31f2..000000000000 --- a/include/dt-bindings/clock/r8a7793-cpg-mssr.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a7793 CPG Core Clocks */ -#define R8A7793_CLK_Z 0 -#define R8A7793_CLK_ZG 1 -#define R8A7793_CLK_ZTR 2 -#define R8A7793_CLK_ZTRD2 3 -#define R8A7793_CLK_ZT 4 -#define R8A7793_CLK_ZX 5 -#define R8A7793_CLK_ZS 6 -#define R8A7793_CLK_HP 7 -#define R8A7793_CLK_I 8 -#define R8A7793_CLK_B 9 -#define R8A7793_CLK_LB 10 -#define R8A7793_CLK_P 11 -#define R8A7793_CLK_CL 12 -#define R8A7793_CLK_M2 13 -#define R8A7793_CLK_ADSP 14 -#define R8A7793_CLK_ZB3 15 -#define R8A7793_CLK_ZB3D2 16 -#define R8A7793_CLK_DDR 17 -#define R8A7793_CLK_SDH 18 -#define R8A7793_CLK_SD0 19 -#define R8A7793_CLK_SD2 20 -#define R8A7793_CLK_SD3 21 -#define R8A7793_CLK_MMC0 22 -#define R8A7793_CLK_MP 23 -#define R8A7793_CLK_SSP 24 -#define R8A7793_CLK_SSPRS 25 -#define R8A7793_CLK_QSPI 26 -#define R8A7793_CLK_CP 27 -#define R8A7793_CLK_RCAN 28 -#define R8A7793_CLK_R 29 -#define R8A7793_CLK_OSC 30 - -#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h deleted file mode 100644 index 649f005782d0..000000000000 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ -#define __DT_BINDINGS_CLOCK_R8A7794_H__ - -/* CPG */ -#define R8A7794_CLK_MAIN 0 -#define R8A7794_CLK_PLL0 1 -#define R8A7794_CLK_PLL1 2 -#define R8A7794_CLK_PLL3 3 -#define R8A7794_CLK_LB 4 -#define R8A7794_CLK_QSPI 5 -#define R8A7794_CLK_SDH 6 -#define R8A7794_CLK_SD0 7 -#define R8A7794_CLK_RCAN 8 - -/* MSTP0 */ -#define R8A7794_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7794_CLK_VCP0 1 -#define R8A7794_CLK_VPC0 3 -#define R8A7794_CLK_TMU1 11 -#define R8A7794_CLK_3DG 12 -#define R8A7794_CLK_2DDMAC 15 -#define R8A7794_CLK_FDP1_0 19 -#define R8A7794_CLK_TMU3 21 -#define R8A7794_CLK_TMU2 22 -#define R8A7794_CLK_CMT0 24 -#define R8A7794_CLK_TMU0 25 -#define R8A7794_CLK_VSP1_DU0 28 -#define R8A7794_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7794_CLK_SCIFA2 2 -#define R8A7794_CLK_SCIFA1 3 -#define R8A7794_CLK_SCIFA0 4 -#define R8A7794_CLK_MSIOF2 5 -#define R8A7794_CLK_SCIFB0 6 -#define R8A7794_CLK_SCIFB1 7 -#define R8A7794_CLK_MSIOF1 8 -#define R8A7794_CLK_SCIFB2 16 -#define R8A7794_CLK_SYS_DMAC1 18 -#define R8A7794_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7794_CLK_SDHI2 11 -#define R8A7794_CLK_SDHI1 12 -#define R8A7794_CLK_SDHI0 14 -#define R8A7794_CLK_MMCIF0 15 -#define R8A7794_CLK_IIC0 18 -#define R8A7794_CLK_IIC1 23 -#define R8A7794_CLK_CMT1 29 -#define R8A7794_CLK_USBDMAC0 30 -#define R8A7794_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7794_CLK_IRQC 7 -#define R8A7794_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7794_CLK_AUDIO_DMAC0 2 -#define R8A7794_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7794_CLK_EHCI 3 -#define R8A7794_CLK_HSUSB 4 -#define R8A7794_CLK_HSCIF2 13 -#define R8A7794_CLK_SCIF5 14 -#define R8A7794_CLK_SCIF4 15 -#define R8A7794_CLK_HSCIF1 16 -#define R8A7794_CLK_HSCIF0 17 -#define R8A7794_CLK_SCIF3 18 -#define R8A7794_CLK_SCIF2 19 -#define R8A7794_CLK_SCIF1 20 -#define R8A7794_CLK_SCIF0 21 -#define R8A7794_CLK_DU1 23 -#define R8A7794_CLK_DU0 24 - -/* MSTP8 */ -#define R8A7794_CLK_VIN1 10 -#define R8A7794_CLK_VIN0 11 -#define R8A7794_CLK_ETHERAVB 12 -#define R8A7794_CLK_ETHER 13 - -/* MSTP9 */ -#define R8A7794_CLK_GPIO6 5 -#define R8A7794_CLK_GPIO5 7 -#define R8A7794_CLK_GPIO4 8 -#define R8A7794_CLK_GPIO3 9 -#define R8A7794_CLK_GPIO2 10 -#define R8A7794_CLK_GPIO1 11 -#define R8A7794_CLK_GPIO0 12 -#define R8A7794_CLK_RCAN1 15 -#define R8A7794_CLK_RCAN0 16 -#define R8A7794_CLK_QSPI_MOD 17 -#define R8A7794_CLK_I2C5 25 -#define R8A7794_CLK_I2C4 27 -#define R8A7794_CLK_I2C3 28 -#define R8A7794_CLK_I2C2 29 -#define R8A7794_CLK_I2C1 30 -#define R8A7794_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7794_CLK_SSI_ALL 5 -#define R8A7794_CLK_SSI9 6 -#define R8A7794_CLK_SSI8 7 -#define R8A7794_CLK_SSI7 8 -#define R8A7794_CLK_SSI6 9 -#define R8A7794_CLK_SSI5 10 -#define R8A7794_CLK_SSI4 11 -#define R8A7794_CLK_SSI3 12 -#define R8A7794_CLK_SSI2 13 -#define R8A7794_CLK_SSI1 14 -#define R8A7794_CLK_SSI0 15 -#define R8A7794_CLK_SCU_ALL 17 -#define R8A7794_CLK_SCU_DVC1 18 -#define R8A7794_CLK_SCU_DVC0 19 -#define R8A7794_CLK_SCU_CTU1_MIX1 20 -#define R8A7794_CLK_SCU_CTU0_MIX0 21 -#define R8A7794_CLK_SCU_SRC6 25 -#define R8A7794_CLK_SCU_SRC5 26 -#define R8A7794_CLK_SCU_SRC4 27 -#define R8A7794_CLK_SCU_SRC3 28 -#define R8A7794_CLK_SCU_SRC2 29 -#define R8A7794_CLK_SCU_SRC1 30 - -/* MSTP11 */ -#define R8A7794_CLK_SCIFA3 6 -#define R8A7794_CLK_SCIFA4 7 -#define R8A7794_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h deleted file mode 100644 index 6314e23b51af..000000000000 --- a/include/dt-bindings/clock/r8a7794-cpg-mssr.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a7794 CPG Core Clocks */ -#define R8A7794_CLK_Z2 0 -#define R8A7794_CLK_ZG 1 -#define R8A7794_CLK_ZTR 2 -#define R8A7794_CLK_ZTRD2 3 -#define R8A7794_CLK_ZT 4 -#define R8A7794_CLK_ZX 5 -#define R8A7794_CLK_ZS 6 -#define R8A7794_CLK_HP 7 -#define R8A7794_CLK_I 8 -#define R8A7794_CLK_B 9 -#define R8A7794_CLK_LB 10 -#define R8A7794_CLK_P 11 -#define R8A7794_CLK_CL 12 -#define R8A7794_CLK_CP 13 -#define R8A7794_CLK_M2 14 -#define R8A7794_CLK_ADSP 15 -#define R8A7794_CLK_ZB3 16 -#define R8A7794_CLK_ZB3D2 17 -#define R8A7794_CLK_DDR 18 -#define R8A7794_CLK_SDH 19 -#define R8A7794_CLK_SD0 20 -#define R8A7794_CLK_SD2 21 -#define R8A7794_CLK_SD3 22 -#define R8A7794_CLK_MMC0 23 -#define R8A7794_CLK_MP 24 -#define R8A7794_CLK_QSPI 25 -#define R8A7794_CLK_CPEX 26 -#define R8A7794_CLK_RCAN 27 -#define R8A7794_CLK_R 28 -#define R8A7794_CLK_OSC 29 - -#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h deleted file mode 100644 index 92b3e2a95179..000000000000 --- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a7795 CPG Core Clocks */ -#define R8A7795_CLK_Z 0 -#define R8A7795_CLK_Z2 1 -#define R8A7795_CLK_ZR 2 -#define R8A7795_CLK_ZG 3 -#define R8A7795_CLK_ZTR 4 -#define R8A7795_CLK_ZTRD2 5 -#define R8A7795_CLK_ZT 6 -#define R8A7795_CLK_ZX 7 -#define R8A7795_CLK_S0D1 8 -#define R8A7795_CLK_S0D4 9 -#define R8A7795_CLK_S1D1 10 -#define R8A7795_CLK_S1D2 11 -#define R8A7795_CLK_S1D4 12 -#define R8A7795_CLK_S2D1 13 -#define R8A7795_CLK_S2D2 14 -#define R8A7795_CLK_S2D4 15 -#define R8A7795_CLK_S3D1 16 -#define R8A7795_CLK_S3D2 17 -#define R8A7795_CLK_S3D4 18 -#define R8A7795_CLK_LB 19 -#define R8A7795_CLK_CL 20 -#define R8A7795_CLK_ZB3 21 -#define R8A7795_CLK_ZB3D2 22 -#define R8A7795_CLK_CR 23 -#define R8A7795_CLK_CRD2 24 -#define R8A7795_CLK_SD0H 25 -#define R8A7795_CLK_SD0 26 -#define R8A7795_CLK_SD1H 27 -#define R8A7795_CLK_SD1 28 -#define R8A7795_CLK_SD2H 29 -#define R8A7795_CLK_SD2 30 -#define R8A7795_CLK_SD3H 31 -#define R8A7795_CLK_SD3 32 -#define R8A7795_CLK_SSP2 33 -#define R8A7795_CLK_SSP1 34 -#define R8A7795_CLK_SSPRS 35 -#define R8A7795_CLK_RPC 36 -#define R8A7795_CLK_RPCD2 37 -#define R8A7795_CLK_MSO 38 -#define R8A7795_CLK_CANFD 39 -#define R8A7795_CLK_HDMI 40 -#define R8A7795_CLK_CSI0 41 -/* CLK_CSIREF was removed */ -#define R8A7795_CLK_CP 43 -#define R8A7795_CLK_CPEX 44 -#define R8A7795_CLK_R 45 -#define R8A7795_CLK_OSC 46 - -/* r8a7795 ES2.0 CPG Core Clocks */ -#define R8A7795_CLK_S0D2 47 -#define R8A7795_CLK_S0D3 48 -#define R8A7795_CLK_S0D6 49 -#define R8A7795_CLK_S0D8 50 -#define R8A7795_CLK_S0D12 51 - -#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h deleted file mode 100644 index c0957cf45840..000000000000 --- a/include/dt-bindings/clock/r8a7796-cpg-mssr.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2016 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a7796 CPG Core Clocks */ -#define R8A7796_CLK_Z 0 -#define R8A7796_CLK_Z2 1 -#define R8A7796_CLK_ZR 2 -#define R8A7796_CLK_ZG 3 -#define R8A7796_CLK_ZTR 4 -#define R8A7796_CLK_ZTRD2 5 -#define R8A7796_CLK_ZT 6 -#define R8A7796_CLK_ZX 7 -#define R8A7796_CLK_S0D1 8 -#define R8A7796_CLK_S0D2 9 -#define R8A7796_CLK_S0D3 10 -#define R8A7796_CLK_S0D4 11 -#define R8A7796_CLK_S0D6 12 -#define R8A7796_CLK_S0D8 13 -#define R8A7796_CLK_S0D12 14 -#define R8A7796_CLK_S1D1 15 -#define R8A7796_CLK_S1D2 16 -#define R8A7796_CLK_S1D4 17 -#define R8A7796_CLK_S2D1 18 -#define R8A7796_CLK_S2D2 19 -#define R8A7796_CLK_S2D4 20 -#define R8A7796_CLK_S3D1 21 -#define R8A7796_CLK_S3D2 22 -#define R8A7796_CLK_S3D4 23 -#define R8A7796_CLK_LB 24 -#define R8A7796_CLK_CL 25 -#define R8A7796_CLK_ZB3 26 -#define R8A7796_CLK_ZB3D2 27 -#define R8A7796_CLK_ZB3D4 28 -#define R8A7796_CLK_CR 29 -#define R8A7796_CLK_CRD2 30 -#define R8A7796_CLK_SD0H 31 -#define R8A7796_CLK_SD0 32 -#define R8A7796_CLK_SD1H 33 -#define R8A7796_CLK_SD1 34 -#define R8A7796_CLK_SD2H 35 -#define R8A7796_CLK_SD2 36 -#define R8A7796_CLK_SD3H 37 -#define R8A7796_CLK_SD3 38 -#define R8A7796_CLK_SSP2 39 -#define R8A7796_CLK_SSP1 40 -#define R8A7796_CLK_SSPRS 41 -#define R8A7796_CLK_RPC 42 -#define R8A7796_CLK_RPCD2 43 -#define R8A7796_CLK_MSO 44 -#define R8A7796_CLK_CANFD 45 -#define R8A7796_CLK_HDMI 46 -#define R8A7796_CLK_CSI0 47 -/* CLK_CSIREF was removed */ -#define R8A7796_CLK_CP 49 -#define R8A7796_CLK_CPEX 50 -#define R8A7796_CLK_R 51 -#define R8A7796_CLK_OSC 52 - -#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a77961-cpg-mssr.h b/include/dt-bindings/clock/r8a77961-cpg-mssr.h deleted file mode 100644 index 7921d785546d..000000000000 --- a/include/dt-bindings/clock/r8a77961-cpg-mssr.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a77961 CPG Core Clocks */ -#define R8A77961_CLK_Z 0 -#define R8A77961_CLK_Z2 1 -#define R8A77961_CLK_ZR 2 -#define R8A77961_CLK_ZG 3 -#define R8A77961_CLK_ZTR 4 -#define R8A77961_CLK_ZTRD2 5 -#define R8A77961_CLK_ZT 6 -#define R8A77961_CLK_ZX 7 -#define R8A77961_CLK_S0D1 8 -#define R8A77961_CLK_S0D2 9 -#define R8A77961_CLK_S0D3 10 -#define R8A77961_CLK_S0D4 11 -#define R8A77961_CLK_S0D6 12 -#define R8A77961_CLK_S0D8 13 -#define R8A77961_CLK_S0D12 14 -#define R8A77961_CLK_S1D1 15 -#define R8A77961_CLK_S1D2 16 -#define R8A77961_CLK_S1D4 17 -#define R8A77961_CLK_S2D1 18 -#define R8A77961_CLK_S2D2 19 -#define R8A77961_CLK_S2D4 20 -#define R8A77961_CLK_S3D1 21 -#define R8A77961_CLK_S3D2 22 -#define R8A77961_CLK_S3D4 23 -#define R8A77961_CLK_LB 24 -#define R8A77961_CLK_CL 25 -#define R8A77961_CLK_ZB3 26 -#define R8A77961_CLK_ZB3D2 27 -#define R8A77961_CLK_ZB3D4 28 -#define R8A77961_CLK_CR 29 -#define R8A77961_CLK_CRD2 30 -#define R8A77961_CLK_SD0H 31 -#define R8A77961_CLK_SD0 32 -#define R8A77961_CLK_SD1H 33 -#define R8A77961_CLK_SD1 34 -#define R8A77961_CLK_SD2H 35 -#define R8A77961_CLK_SD2 36 -#define R8A77961_CLK_SD3H 37 -#define R8A77961_CLK_SD3 38 -#define R8A77961_CLK_SSP2 39 -#define R8A77961_CLK_SSP1 40 -#define R8A77961_CLK_SSPRS 41 -#define R8A77961_CLK_RPC 42 -#define R8A77961_CLK_RPCD2 43 -#define R8A77961_CLK_MSO 44 -#define R8A77961_CLK_CANFD 45 -#define R8A77961_CLK_HDMI 46 -#define R8A77961_CLK_CSI0 47 -/* CLK_CSIREF was removed */ -#define R8A77961_CLK_CP 49 -#define R8A77961_CLK_CPEX 50 -#define R8A77961_CLK_R 51 -#define R8A77961_CLK_OSC 52 - -#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/include/dt-bindings/clock/r8a77965-cpg-mssr.h deleted file mode 100644 index 6d3b5a9a6084..000000000000 --- a/include/dt-bindings/clock/r8a77965-cpg-mssr.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Jacopo Mondi jacopo+renesas@jmondi.org - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a77965 CPG Core Clocks */ -#define R8A77965_CLK_Z 0 -#define R8A77965_CLK_ZR 1 -#define R8A77965_CLK_ZG 2 -#define R8A77965_CLK_ZTR 3 -#define R8A77965_CLK_ZTRD2 4 -#define R8A77965_CLK_ZT 5 -#define R8A77965_CLK_ZX 6 -#define R8A77965_CLK_S0D1 7 -#define R8A77965_CLK_S0D2 8 -#define R8A77965_CLK_S0D3 9 -#define R8A77965_CLK_S0D4 10 -#define R8A77965_CLK_S0D6 11 -#define R8A77965_CLK_S0D8 12 -#define R8A77965_CLK_S0D12 13 -#define R8A77965_CLK_S1D1 14 -#define R8A77965_CLK_S1D2 15 -#define R8A77965_CLK_S1D4 16 -#define R8A77965_CLK_S2D1 17 -#define R8A77965_CLK_S2D2 18 -#define R8A77965_CLK_S2D4 19 -#define R8A77965_CLK_S3D1 20 -#define R8A77965_CLK_S3D2 21 -#define R8A77965_CLK_S3D4 22 -#define R8A77965_CLK_LB 23 -#define R8A77965_CLK_CL 24 -#define R8A77965_CLK_ZB3 25 -#define R8A77965_CLK_ZB3D2 26 -#define R8A77965_CLK_CR 27 -#define R8A77965_CLK_CRD2 28 -#define R8A77965_CLK_SD0H 29 -#define R8A77965_CLK_SD0 30 -#define R8A77965_CLK_SD1H 31 -#define R8A77965_CLK_SD1 32 -#define R8A77965_CLK_SD2H 33 -#define R8A77965_CLK_SD2 34 -#define R8A77965_CLK_SD3H 35 -#define R8A77965_CLK_SD3 36 -#define R8A77965_CLK_SSP2 37 -#define R8A77965_CLK_SSP1 38 -#define R8A77965_CLK_SSPRS 39 -#define R8A77965_CLK_RPC 40 -#define R8A77965_CLK_RPCD2 41 -#define R8A77965_CLK_MSO 42 -#define R8A77965_CLK_CANFD 43 -#define R8A77965_CLK_HDMI 44 -#define R8A77965_CLK_CSI0 45 -#define R8A77965_CLK_CP 46 -#define R8A77965_CLK_CPEX 47 -#define R8A77965_CLK_R 48 -#define R8A77965_CLK_OSC 49 - -#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h deleted file mode 100644 index 6145ebe66361..000000000000 --- a/include/dt-bindings/clock/r8a77970-cpg-mssr.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a77970 CPG Core Clocks */ -#define R8A77970_CLK_Z2 0 -#define R8A77970_CLK_ZR 1 -#define R8A77970_CLK_ZTR 2 -#define R8A77970_CLK_ZTRD2 3 -#define R8A77970_CLK_ZT 4 -#define R8A77970_CLK_ZX 5 -#define R8A77970_CLK_S1D1 6 -#define R8A77970_CLK_S1D2 7 -#define R8A77970_CLK_S1D4 8 -#define R8A77970_CLK_S2D1 9 -#define R8A77970_CLK_S2D2 10 -#define R8A77970_CLK_S2D4 11 -#define R8A77970_CLK_LB 12 -#define R8A77970_CLK_CL 13 -#define R8A77970_CLK_ZB3 14 -#define R8A77970_CLK_ZB3D2 15 -#define R8A77970_CLK_DDR 16 -#define R8A77970_CLK_CR 17 -#define R8A77970_CLK_CRD2 18 -#define R8A77970_CLK_SD0H 19 -#define R8A77970_CLK_SD0 20 -#define R8A77970_CLK_RPC 21 -#define R8A77970_CLK_RPCD2 22 -#define R8A77970_CLK_MSO 23 -#define R8A77970_CLK_CANFD 24 -#define R8A77970_CLK_CSI0 25 -#define R8A77970_CLK_FRAY 26 -#define R8A77970_CLK_CP 27 -#define R8A77970_CLK_CPEX 28 -#define R8A77970_CLK_R 29 -#define R8A77970_CLK_OSC 30 - -#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/include/dt-bindings/clock/r8a77980-cpg-mssr.h deleted file mode 100644 index a4c0d76c392e..000000000000 --- a/include/dt-bindings/clock/r8a77980-cpg-mssr.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a77980 CPG Core Clocks */ -#define R8A77980_CLK_Z2 0 -#define R8A77980_CLK_ZR 1 -#define R8A77980_CLK_ZTR 2 -#define R8A77980_CLK_ZTRD2 3 -#define R8A77980_CLK_ZT 4 -#define R8A77980_CLK_ZX 5 -#define R8A77980_CLK_S0D1 6 -#define R8A77980_CLK_S0D2 7 -#define R8A77980_CLK_S0D3 8 -#define R8A77980_CLK_S0D4 9 -#define R8A77980_CLK_S0D6 10 -#define R8A77980_CLK_S0D12 11 -#define R8A77980_CLK_S0D24 12 -#define R8A77980_CLK_S1D1 13 -#define R8A77980_CLK_S1D2 14 -#define R8A77980_CLK_S1D4 15 -#define R8A77980_CLK_S2D1 16 -#define R8A77980_CLK_S2D2 17 -#define R8A77980_CLK_S2D4 18 -#define R8A77980_CLK_S3D1 19 -#define R8A77980_CLK_S3D2 20 -#define R8A77980_CLK_S3D4 21 -#define R8A77980_CLK_LB 22 -#define R8A77980_CLK_CL 23 -#define R8A77980_CLK_ZB3 24 -#define R8A77980_CLK_ZB3D2 25 -#define R8A77980_CLK_ZB3D4 26 -#define R8A77980_CLK_SD0H 27 -#define R8A77980_CLK_SD0 28 -#define R8A77980_CLK_RPC 29 -#define R8A77980_CLK_RPCD2 30 -#define R8A77980_CLK_MSO 31 -#define R8A77980_CLK_CANFD 32 -#define R8A77980_CLK_CSI0 33 -#define R8A77980_CLK_CP 34 -#define R8A77980_CLK_CPEX 35 -#define R8A77980_CLK_R 36 -#define R8A77980_CLK_OSC 37 - -#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h deleted file mode 100644 index a596a482f3a9..000000000000 --- a/include/dt-bindings/clock/r8a77990-cpg-mssr.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a77990 CPG Core Clocks */ -#define R8A77990_CLK_Z2 0 -#define R8A77990_CLK_ZR 1 -#define R8A77990_CLK_ZG 2 -#define R8A77990_CLK_ZTR 3 -#define R8A77990_CLK_ZT 4 -#define R8A77990_CLK_ZX 5 -#define R8A77990_CLK_S0D1 6 -#define R8A77990_CLK_S0D3 7 -#define R8A77990_CLK_S0D6 8 -#define R8A77990_CLK_S0D12 9 -#define R8A77990_CLK_S0D24 10 -#define R8A77990_CLK_S1D1 11 -#define R8A77990_CLK_S1D2 12 -#define R8A77990_CLK_S1D4 13 -#define R8A77990_CLK_S2D1 14 -#define R8A77990_CLK_S2D2 15 -#define R8A77990_CLK_S2D4 16 -#define R8A77990_CLK_S3D1 17 -#define R8A77990_CLK_S3D2 18 -#define R8A77990_CLK_S3D4 19 -#define R8A77990_CLK_S0D6C 20 -#define R8A77990_CLK_S3D1C 21 -#define R8A77990_CLK_S3D2C 22 -#define R8A77990_CLK_S3D4C 23 -#define R8A77990_CLK_LB 24 -#define R8A77990_CLK_CL 25 -#define R8A77990_CLK_ZB3 26 -#define R8A77990_CLK_ZB3D2 27 -#define R8A77990_CLK_CR 28 -#define R8A77990_CLK_CRD2 29 -#define R8A77990_CLK_SD0H 30 -#define R8A77990_CLK_SD0 31 -#define R8A77990_CLK_SD1H 32 -#define R8A77990_CLK_SD1 33 -#define R8A77990_CLK_SD3H 34 -#define R8A77990_CLK_SD3 35 -#define R8A77990_CLK_RPC 36 -#define R8A77990_CLK_RPCD2 37 -#define R8A77990_CLK_ZA2 38 -#define R8A77990_CLK_ZA8 39 -#define R8A77990_CLK_Z2D 40 -#define R8A77990_CLK_CANFD 41 -#define R8A77990_CLK_MSO 42 -#define R8A77990_CLK_R 43 -#define R8A77990_CLK_OSC 44 -#define R8A77990_CLK_LV0 45 -#define R8A77990_CLK_LV1 46 -#define R8A77990_CLK_CSI0 47 -#define R8A77990_CLK_CP 48 -#define R8A77990_CLK_CPEX 49 - -#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h deleted file mode 100644 index fd701c4e87cf..000000000000 --- a/include/dt-bindings/clock/r8a77995-cpg-mssr.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2017 Glider bvba - */ -#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a77995 CPG Core Clocks */ -#define R8A77995_CLK_Z2 0 -#define R8A77995_CLK_ZG 1 -#define R8A77995_CLK_ZTR 2 -#define R8A77995_CLK_ZT 3 -#define R8A77995_CLK_ZX 4 -#define R8A77995_CLK_S0D1 5 -#define R8A77995_CLK_S1D1 6 -#define R8A77995_CLK_S1D2 7 -#define R8A77995_CLK_S1D4 8 -#define R8A77995_CLK_S2D1 9 -#define R8A77995_CLK_S2D2 10 -#define R8A77995_CLK_S2D4 11 -#define R8A77995_CLK_S3D1 12 -#define R8A77995_CLK_S3D2 13 -#define R8A77995_CLK_S3D4 14 -#define R8A77995_CLK_S1D4C 15 -#define R8A77995_CLK_S3D1C 16 -#define R8A77995_CLK_S3D2C 17 -#define R8A77995_CLK_S3D4C 18 -#define R8A77995_CLK_LB 19 -#define R8A77995_CLK_CL 20 -#define R8A77995_CLK_ZB3 21 -#define R8A77995_CLK_ZB3D2 22 -#define R8A77995_CLK_CR 23 -#define R8A77995_CLK_CRD2 24 -#define R8A77995_CLK_SD0H 25 -#define R8A77995_CLK_SD0 26 -/* CLK_SSP2 was removed */ -/* CLK_SSP1 was removed */ -#define R8A77995_CLK_RPC 29 -#define R8A77995_CLK_RPCD2 30 -#define R8A77995_CLK_ZA2 31 -#define R8A77995_CLK_ZA8 32 -#define R8A77995_CLK_Z2D 33 -#define R8A77995_CLK_CANFD 34 -#define R8A77995_CLK_MSO 35 -#define R8A77995_CLK_R 36 -#define R8A77995_CLK_OSC 37 -#define R8A77995_CLK_LV0 38 -#define R8A77995_CLK_LV1 39 -#define R8A77995_CLK_CP 40 -#define R8A77995_CLK_CPEX 41 - -#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h deleted file mode 100644 index f1d737ca7ca1..000000000000 --- a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2020 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a779A0 CPG Core Clocks */ -#define R8A779A0_CLK_Z0 0 -#define R8A779A0_CLK_ZX 1 -#define R8A779A0_CLK_Z1 2 -#define R8A779A0_CLK_ZR 3 -#define R8A779A0_CLK_ZS 4 -#define R8A779A0_CLK_ZT 5 -#define R8A779A0_CLK_ZTR 6 -#define R8A779A0_CLK_S1D1 7 -#define R8A779A0_CLK_S1D2 8 -#define R8A779A0_CLK_S1D4 9 -#define R8A779A0_CLK_S1D8 10 -#define R8A779A0_CLK_S1D12 11 -#define R8A779A0_CLK_S3D1 12 -#define R8A779A0_CLK_S3D2 13 -#define R8A779A0_CLK_S3D4 14 -#define R8A779A0_CLK_LB 15 -#define R8A779A0_CLK_CP 16 -#define R8A779A0_CLK_CL 17 -#define R8A779A0_CLK_CL16MCK 18 -#define R8A779A0_CLK_ZB30 19 -#define R8A779A0_CLK_ZB30D2 20 -#define R8A779A0_CLK_ZB30D4 21 -#define R8A779A0_CLK_ZB31 22 -#define R8A779A0_CLK_ZB31D2 23 -#define R8A779A0_CLK_ZB31D4 24 -#define R8A779A0_CLK_SD0H 25 -#define R8A779A0_CLK_SD0 26 -#define R8A779A0_CLK_RPC 27 -#define R8A779A0_CLK_RPCD2 28 -#define R8A779A0_CLK_MSO 29 -#define R8A779A0_CLK_CANFD 30 -#define R8A779A0_CLK_CSI0 31 -#define R8A779A0_CLK_FRAY 32 -#define R8A779A0_CLK_DSI 33 -#define R8A779A0_CLK_VIP 34 -#define R8A779A0_CLK_ADGH 35 -#define R8A779A0_CLK_CNNDSP 36 -#define R8A779A0_CLK_ICU 37 -#define R8A779A0_CLK_ICUD2 38 -#define R8A779A0_CLK_VCBUS 39 -#define R8A779A0_CLK_CBFUSA 40 -#define R8A779A0_CLK_R 41 -#define R8A779A0_CLK_OSC 42 - -#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h deleted file mode 100644 index c34be5624954..000000000000 --- a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (C) 2021 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a779f0 CPG Core Clocks */ - -#define R8A779F0_CLK_ZX 0 -#define R8A779F0_CLK_ZS 1 -#define R8A779F0_CLK_ZT 2 -#define R8A779F0_CLK_ZTR 3 -#define R8A779F0_CLK_S0D2 4 -#define R8A779F0_CLK_S0D3 5 -#define R8A779F0_CLK_S0D4 6 -#define R8A779F0_CLK_S0D2_MM 7 -#define R8A779F0_CLK_S0D3_MM 8 -#define R8A779F0_CLK_S0D4_MM 9 -#define R8A779F0_CLK_S0D2_RT 10 -#define R8A779F0_CLK_S0D3_RT 11 -#define R8A779F0_CLK_S0D4_RT 12 -#define R8A779F0_CLK_S0D6_RT 13 -#define R8A779F0_CLK_S0D3_PER 14 -#define R8A779F0_CLK_S0D6_PER 15 -#define R8A779F0_CLK_S0D12_PER 16 -#define R8A779F0_CLK_S0D24_PER 17 -#define R8A779F0_CLK_S0D2_HSC 18 -#define R8A779F0_CLK_S0D3_HSC 19 -#define R8A779F0_CLK_S0D4_HSC 20 -#define R8A779F0_CLK_S0D6_HSC 21 -#define R8A779F0_CLK_S0D12_HSC 22 -#define R8A779F0_CLK_S0D2_CC 23 -#define R8A779F0_CLK_CL 24 -#define R8A779F0_CLK_CL16M 25 -#define R8A779F0_CLK_CL16M_MM 26 -#define R8A779F0_CLK_CL16M_RT 27 -#define R8A779F0_CLK_CL16M_PER 28 -#define R8A779F0_CLK_CL16M_HSC 29 -#define R8A779F0_CLK_Z0 30 -#define R8A779F0_CLK_Z1 31 -#define R8A779F0_CLK_ZB3 32 -#define R8A779F0_CLK_ZB3D2 33 -#define R8A779F0_CLK_ZB3D4 34 -#define R8A779F0_CLK_SD0H 35 -#define R8A779F0_CLK_SD0 36 -#define R8A779F0_CLK_RPC 37 -#define R8A779F0_CLK_RPCD2 38 -#define R8A779F0_CLK_MSO 39 -#define R8A779F0_CLK_SASYNCRT 40 -#define R8A779F0_CLK_SASYNCPERD1 41 -#define R8A779F0_CLK_SASYNCPERD2 42 -#define R8A779F0_CLK_SASYNCPERD4 43 -#define R8A779F0_CLK_DBGSOC_HSC 44 -#define R8A779F0_CLK_RSW2 45 -#define R8A779F0_CLK_OSC 46 -#define R8A779F0_CLK_ZR 47 -#define R8A779F0_CLK_CPEX 48 -#define R8A779F0_CLK_CBFUSA 49 -#define R8A779F0_CLK_R 50 - -#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h deleted file mode 100644 index 754c54a6eb06..000000000000 --- a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (C) 2022 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* r8a779g0 CPG Core Clocks */ - -#define R8A779G0_CLK_ZX 0 -#define R8A779G0_CLK_ZS 1 -#define R8A779G0_CLK_ZT 2 -#define R8A779G0_CLK_ZTR 3 -#define R8A779G0_CLK_S0D2 4 -#define R8A779G0_CLK_S0D3 5 -#define R8A779G0_CLK_S0D4 6 -#define R8A779G0_CLK_S0D1_VIO 7 -#define R8A779G0_CLK_S0D2_VIO 8 -#define R8A779G0_CLK_S0D4_VIO 9 -#define R8A779G0_CLK_S0D8_VIO 10 -#define R8A779G0_CLK_S0D1_VC 11 -#define R8A779G0_CLK_S0D2_VC 12 -#define R8A779G0_CLK_S0D4_VC 13 -#define R8A779G0_CLK_S0D2_MM 14 -#define R8A779G0_CLK_S0D4_MM 15 -#define R8A779G0_CLK_S0D2_U3DG 16 -#define R8A779G0_CLK_S0D4_U3DG 17 -#define R8A779G0_CLK_S0D2_RT 18 -#define R8A779G0_CLK_S0D3_RT 19 -#define R8A779G0_CLK_S0D4_RT 20 -#define R8A779G0_CLK_S0D6_RT 21 -#define R8A779G0_CLK_S0D24_RT 22 -#define R8A779G0_CLK_S0D2_PER 23 -#define R8A779G0_CLK_S0D3_PER 24 -#define R8A779G0_CLK_S0D4_PER 25 -#define R8A779G0_CLK_S0D6_PER 26 -#define R8A779G0_CLK_S0D12_PER 27 -#define R8A779G0_CLK_S0D24_PER 28 -#define R8A779G0_CLK_S0D1_HSC 29 -#define R8A779G0_CLK_S0D2_HSC 30 -#define R8A779G0_CLK_S0D4_HSC 31 -#define R8A779G0_CLK_S0D2_CC 32 -#define R8A779G0_CLK_SVD1_IR 33 -#define R8A779G0_CLK_SVD2_IR 34 -#define R8A779G0_CLK_SVD1_VIP 35 -#define R8A779G0_CLK_SVD2_VIP 36 -#define R8A779G0_CLK_CL 37 -#define R8A779G0_CLK_CL16M 38 -#define R8A779G0_CLK_CL16M_MM 39 -#define R8A779G0_CLK_CL16M_RT 40 -#define R8A779G0_CLK_CL16M_PER 41 -#define R8A779G0_CLK_CL16M_HSC 42 -#define R8A779G0_CLK_Z0 43 -#define R8A779G0_CLK_ZB3 44 -#define R8A779G0_CLK_ZB3D2 45 -#define R8A779G0_CLK_ZB3D4 46 -#define R8A779G0_CLK_ZG 47 -#define R8A779G0_CLK_SD0H 48 -#define R8A779G0_CLK_SD0 49 -#define R8A779G0_CLK_RPC 50 -#define R8A779G0_CLK_RPCD2 51 -#define R8A779G0_CLK_MSO 52 -#define R8A779G0_CLK_CANFD 53 -#define R8A779G0_CLK_CSI 54 -#define R8A779G0_CLK_FRAY 55 -#define R8A779G0_CLK_IPC 56 -#define R8A779G0_CLK_SASYNCRT 57 -#define R8A779G0_CLK_SASYNCPERD1 58 -#define R8A779G0_CLK_SASYNCPERD2 59 -#define R8A779G0_CLK_SASYNCPERD4 60 -#define R8A779G0_CLK_VIOBUS 61 -#define R8A779G0_CLK_VIOBUSD2 62 -#define R8A779G0_CLK_VCBUS 63 -#define R8A779G0_CLK_VCBUSD2 64 -#define R8A779G0_CLK_DSIEXT 65 -#define R8A779G0_CLK_DSIREF 66 -#define R8A779G0_CLK_ADGH 67 -#define R8A779G0_CLK_OSC 68 -#define R8A779G0_CLK_ZR0 69 -#define R8A779G0_CLK_ZR1 70 -#define R8A779G0_CLK_ZR2 71 -#define R8A779G0_CLK_IMPA 72 -#define R8A779G0_CLK_IMPAD4 73 -#define R8A779G0_CLK_CPEX 74 -#define R8A779G0_CLK_CBFUSA 75 -#define R8A779G0_CLK_R 76 - -#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h b/include/dt-bindings/clock/r9a06g032-sysctrl.h deleted file mode 100644 index d9d7b8b4f426..000000000000 --- a/include/dt-bindings/clock/r9a06g032-sysctrl.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * R9A06G032 sysctrl IDs - * - * Copyright (C) 2018 Renesas Electronics Europe Limited - * - * Michel Pollet michel.pollet@bp.renesas.com, buserror@gmail.com - */ - -#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ -#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ - -#define R9A06G032_CLK_PLL_USB 1 -#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ -#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ -#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ -#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ -#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ -#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ -#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ -#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ -#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ -#define R9A06G032_CLK_25_PG4 26 -#define R9A06G032_CLK_25_PG5 27 -#define R9A06G032_CLK_25_PG6 28 -#define R9A06G032_CLK_25_PG7 29 -#define R9A06G032_CLK_25_PG8 30 -#define R9A06G032_CLK_ADC 31 -#define R9A06G032_CLK_ECAT100 32 -#define R9A06G032_CLK_HSR100 33 -#define R9A06G032_CLK_I2C0 34 -#define R9A06G032_CLK_I2C1 35 -#define R9A06G032_CLK_MII_REF 36 -#define R9A06G032_CLK_NAND 37 -#define R9A06G032_CLK_NOUSBP2_PG6 38 -#define R9A06G032_CLK_P1_PG2 39 -#define R9A06G032_CLK_P1_PG3 40 -#define R9A06G032_CLK_P1_PG4 41 -#define R9A06G032_CLK_P4_PG3 42 -#define R9A06G032_CLK_P4_PG4 43 -#define R9A06G032_CLK_P6_PG1 44 -#define R9A06G032_CLK_P6_PG2 45 -#define R9A06G032_CLK_P6_PG3 46 -#define R9A06G032_CLK_P6_PG4 47 -#define R9A06G032_CLK_PCI_USB 48 -#define R9A06G032_CLK_QSPI0 49 -#define R9A06G032_CLK_QSPI1 50 -#define R9A06G032_CLK_RGMII_REF 51 -#define R9A06G032_CLK_RMII_REF 52 -#define R9A06G032_CLK_SDIO0 53 -#define R9A06G032_CLK_SDIO1 54 -#define R9A06G032_CLK_SERCOS100 55 -#define R9A06G032_CLK_SLCD 56 -#define R9A06G032_CLK_SPI0 57 -#define R9A06G032_CLK_SPI1 58 -#define R9A06G032_CLK_SPI2 59 -#define R9A06G032_CLK_SPI3 60 -#define R9A06G032_CLK_SPI4 61 -#define R9A06G032_CLK_SPI5 62 -#define R9A06G032_CLK_SWITCH 63 -#define R9A06G032_HCLK_ECAT125 65 -#define R9A06G032_HCLK_PINCONFIG 66 -#define R9A06G032_HCLK_SERCOS 67 -#define R9A06G032_HCLK_SGPIO2 68 -#define R9A06G032_HCLK_SGPIO3 69 -#define R9A06G032_HCLK_SGPIO4 70 -#define R9A06G032_HCLK_TIMER0 71 -#define R9A06G032_HCLK_TIMER1 72 -#define R9A06G032_HCLK_USBF 73 -#define R9A06G032_HCLK_USBH 74 -#define R9A06G032_HCLK_USBPM 75 -#define R9A06G032_CLK_48_PG_F 76 -#define R9A06G032_CLK_48_PG4 77 -#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */ -#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ -#define R9A06G032_HCLK_CAN0 85 -#define R9A06G032_HCLK_CAN1 86 -#define R9A06G032_HCLK_DELTASIGMA 87 -#define R9A06G032_HCLK_PWMPTO 88 -#define R9A06G032_HCLK_RSV 89 -#define R9A06G032_HCLK_SGPIO0 90 -#define R9A06G032_HCLK_SGPIO1 91 -#define R9A06G032_RTOS_MDC 92 -#define R9A06G032_CLK_CM3 93 -#define R9A06G032_CLK_DDRC 94 -#define R9A06G032_CLK_ECAT25 95 -#define R9A06G032_CLK_HSR50 96 -#define R9A06G032_CLK_HW_RTOS 97 -#define R9A06G032_CLK_SERCOS50 98 -#define R9A06G032_HCLK_ADC 99 -#define R9A06G032_HCLK_CM3 100 -#define R9A06G032_HCLK_CRYPTO_EIP150 101 -#define R9A06G032_HCLK_CRYPTO_EIP93 102 -#define R9A06G032_HCLK_DDRC 103 -#define R9A06G032_HCLK_DMA0 104 -#define R9A06G032_HCLK_DMA1 105 -#define R9A06G032_HCLK_GMAC0 106 -#define R9A06G032_HCLK_GMAC1 107 -#define R9A06G032_HCLK_GPIO0 108 -#define R9A06G032_HCLK_GPIO1 109 -#define R9A06G032_HCLK_GPIO2 110 -#define R9A06G032_HCLK_HSR 111 -#define R9A06G032_HCLK_I2C0 112 -#define R9A06G032_HCLK_I2C1 113 -#define R9A06G032_HCLK_LCD 114 -#define R9A06G032_HCLK_MSEBI_M 115 -#define R9A06G032_HCLK_MSEBI_S 116 -#define R9A06G032_HCLK_NAND 117 -#define R9A06G032_HCLK_PG_I 118 -#define R9A06G032_HCLK_PG19 119 -#define R9A06G032_HCLK_PG20 120 -#define R9A06G032_HCLK_PG3 121 -#define R9A06G032_HCLK_PG4 122 -#define R9A06G032_HCLK_QSPI0 123 -#define R9A06G032_HCLK_QSPI1 124 -#define R9A06G032_HCLK_ROM 125 -#define R9A06G032_HCLK_RTC 126 -#define R9A06G032_HCLK_SDIO0 127 -#define R9A06G032_HCLK_SDIO1 128 -#define R9A06G032_HCLK_SEMAP 129 -#define R9A06G032_HCLK_SPI0 130 -#define R9A06G032_HCLK_SPI1 131 -#define R9A06G032_HCLK_SPI2 132 -#define R9A06G032_HCLK_SPI3 133 -#define R9A06G032_HCLK_SPI4 134 -#define R9A06G032_HCLK_SPI5 135 -#define R9A06G032_HCLK_SWITCH 136 -#define R9A06G032_HCLK_SWITCH_RG 137 -#define R9A06G032_HCLK_UART0 138 -#define R9A06G032_HCLK_UART1 139 -#define R9A06G032_HCLK_UART2 140 -#define R9A06G032_HCLK_UART3 141 -#define R9A06G032_HCLK_UART4 142 -#define R9A06G032_HCLK_UART5 143 -#define R9A06G032_HCLK_UART6 144 -#define R9A06G032_HCLK_UART7 145 -#define R9A06G032_CLK_UART0 146 -#define R9A06G032_CLK_UART1 147 -#define R9A06G032_CLK_UART2 148 -#define R9A06G032_CLK_UART3 149 -#define R9A06G032_CLK_UART4 150 -#define R9A06G032_CLK_UART5 151 -#define R9A06G032_CLK_UART6 152 -#define R9A06G032_CLK_UART7 153 - -#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h deleted file mode 100644 index 0bb17ff1a01a..000000000000 --- a/include/dt-bindings/clock/r9a07g044-cpg.h +++ /dev/null @@ -1,220 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ -#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ -#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ - -#include <dt-bindings/clock/renesas-cpg-mssr.h> - -/* R9A07G044 CPG Core Clocks */ -#define R9A07G044_CLK_I 0 -#define R9A07G044_CLK_I2 1 -#define R9A07G044_CLK_G 2 -#define R9A07G044_CLK_S0 3 -#define R9A07G044_CLK_S1 4 -#define R9A07G044_CLK_SPI0 5 -#define R9A07G044_CLK_SPI1 6 -#define R9A07G044_CLK_SD0 7 -#define R9A07G044_CLK_SD1 8 -#define R9A07G044_CLK_M0 9 -#define R9A07G044_CLK_M1 10 -#define R9A07G044_CLK_M2 11 -#define R9A07G044_CLK_M3 12 -#define R9A07G044_CLK_M4 13 -#define R9A07G044_CLK_HP 14 -#define R9A07G044_CLK_TSU 15 -#define R9A07G044_CLK_ZT 16 -#define R9A07G044_CLK_P0 17 -#define R9A07G044_CLK_P1 18 -#define R9A07G044_CLK_P2 19 -#define R9A07G044_CLK_AT 20 -#define R9A07G044_OSCCLK 21 -#define R9A07G044_CLK_P0_DIV2 22 - -/* R9A07G044 Module Clocks */ -#define R9A07G044_CA55_SCLK 0 -#define R9A07G044_CA55_PCLK 1 -#define R9A07G044_CA55_ATCLK 2 -#define R9A07G044_CA55_GICCLK 3 -#define R9A07G044_CA55_PERICLK 4 -#define R9A07G044_CA55_ACLK 5 -#define R9A07G044_CA55_TSCLK 6 -#define R9A07G044_GIC600_GICCLK 7 -#define R9A07G044_IA55_CLK 8 -#define R9A07G044_IA55_PCLK 9 -#define R9A07G044_MHU_PCLK 10 -#define R9A07G044_SYC_CNT_CLK 11 -#define R9A07G044_DMAC_ACLK 12 -#define R9A07G044_DMAC_PCLK 13 -#define R9A07G044_OSTM0_PCLK 14 -#define R9A07G044_OSTM1_PCLK 15 -#define R9A07G044_OSTM2_PCLK 16 -#define R9A07G044_MTU_X_MCK_MTU3 17 -#define R9A07G044_POE3_CLKM_POE 18 -#define R9A07G044_GPT_PCLK 19 -#define R9A07G044_POEG_A_CLKP 20 -#define R9A07G044_POEG_B_CLKP 21 -#define R9A07G044_POEG_C_CLKP 22 -#define R9A07G044_POEG_D_CLKP 23 -#define R9A07G044_WDT0_PCLK 24 -#define R9A07G044_WDT0_CLK 25 -#define R9A07G044_WDT1_PCLK 26 -#define R9A07G044_WDT1_CLK 27 -#define R9A07G044_WDT2_PCLK 28 -#define R9A07G044_WDT2_CLK 29 -#define R9A07G044_SPI_CLK2 30 -#define R9A07G044_SPI_CLK 31 -#define R9A07G044_SDHI0_IMCLK 32 -#define R9A07G044_SDHI0_IMCLK2 33 -#define R9A07G044_SDHI0_CLK_HS 34 -#define R9A07G044_SDHI0_ACLK 35 -#define R9A07G044_SDHI1_IMCLK 36 -#define R9A07G044_SDHI1_IMCLK2 37 -#define R9A07G044_SDHI1_CLK_HS 38 -#define R9A07G044_SDHI1_ACLK 39 -#define R9A07G044_GPU_CLK 40 -#define R9A07G044_GPU_AXI_CLK 41 -#define R9A07G044_GPU_ACE_CLK 42 -#define R9A07G044_ISU_ACLK 43 -#define R9A07G044_ISU_PCLK 44 -#define R9A07G044_H264_CLK_A 45 -#define R9A07G044_H264_CLK_P 46 -#define R9A07G044_CRU_SYSCLK 47 -#define R9A07G044_CRU_VCLK 48 -#define R9A07G044_CRU_PCLK 49 -#define R9A07G044_CRU_ACLK 50 -#define R9A07G044_MIPI_DSI_PLLCLK 51 -#define R9A07G044_MIPI_DSI_SYSCLK 52 -#define R9A07G044_MIPI_DSI_ACLK 53 -#define R9A07G044_MIPI_DSI_PCLK 54 -#define R9A07G044_MIPI_DSI_VCLK 55 -#define R9A07G044_MIPI_DSI_LPCLK 56 -#define R9A07G044_LCDC_CLK_A 57 -#define R9A07G044_LCDC_CLK_P 58 -#define R9A07G044_LCDC_CLK_D 59 -#define R9A07G044_SSI0_PCLK2 60 -#define R9A07G044_SSI0_PCLK_SFR 61 -#define R9A07G044_SSI1_PCLK2 62 -#define R9A07G044_SSI1_PCLK_SFR 63 -#define R9A07G044_SSI2_PCLK2 64 -#define R9A07G044_SSI2_PCLK_SFR 65 -#define R9A07G044_SSI3_PCLK2 66 -#define R9A07G044_SSI3_PCLK_SFR 67 -#define R9A07G044_SRC_CLKP 68 -#define R9A07G044_USB_U2H0_HCLK 69 -#define R9A07G044_USB_U2H1_HCLK 70 -#define R9A07G044_USB_U2P_EXR_CPUCLK 71 -#define R9A07G044_USB_PCLK 72 -#define R9A07G044_ETH0_CLK_AXI 73 -#define R9A07G044_ETH0_CLK_CHI 74 -#define R9A07G044_ETH1_CLK_AXI 75 -#define R9A07G044_ETH1_CLK_CHI 76 -#define R9A07G044_I2C0_PCLK 77 -#define R9A07G044_I2C1_PCLK 78 -#define R9A07G044_I2C2_PCLK 79 -#define R9A07G044_I2C3_PCLK 80 -#define R9A07G044_SCIF0_CLK_PCK 81 -#define R9A07G044_SCIF1_CLK_PCK 82 -#define R9A07G044_SCIF2_CLK_PCK 83 -#define R9A07G044_SCIF3_CLK_PCK 84 -#define R9A07G044_SCIF4_CLK_PCK 85 -#define R9A07G044_SCI0_CLKP 86 -#define R9A07G044_SCI1_CLKP 87 -#define R9A07G044_IRDA_CLKP 88 -#define R9A07G044_RSPI0_CLKB 89 -#define R9A07G044_RSPI1_CLKB 90 -#define R9A07G044_RSPI2_CLKB 91 -#define R9A07G044_CANFD_PCLK 92 -#define R9A07G044_GPIO_HCLK 93 -#define R9A07G044_ADC_ADCLK 94 -#define R9A07G044_ADC_PCLK 95 -#define R9A07G044_TSU_PCLK 96 - -/* R9A07G044 Resets */ -#define R9A07G044_CA55_RST_1_0 0 -#define R9A07G044_CA55_RST_1_1 1 -#define R9A07G044_CA55_RST_3_0 2 -#define R9A07G044_CA55_RST_3_1 3 -#define R9A07G044_CA55_RST_4 4 -#define R9A07G044_CA55_RST_5 5 -#define R9A07G044_CA55_RST_6 6 -#define R9A07G044_CA55_RST_7 7 -#define R9A07G044_CA55_RST_8 8 -#define R9A07G044_CA55_RST_9 9 -#define R9A07G044_CA55_RST_10 10 -#define R9A07G044_CA55_RST_11 11 -#define R9A07G044_CA55_RST_12 12 -#define R9A07G044_GIC600_GICRESET_N 13 -#define R9A07G044_GIC600_DBG_GICRESET_N 14 -#define R9A07G044_IA55_RESETN 15 -#define R9A07G044_MHU_RESETN 16 -#define R9A07G044_DMAC_ARESETN 17 -#define R9A07G044_DMAC_RST_ASYNC 18 -#define R9A07G044_SYC_RESETN 19 -#define R9A07G044_OSTM0_PRESETZ 20 -#define R9A07G044_OSTM1_PRESETZ 21 -#define R9A07G044_OSTM2_PRESETZ 22 -#define R9A07G044_MTU_X_PRESET_MTU3 23 -#define R9A07G044_POE3_RST_M_REG 24 -#define R9A07G044_GPT_RST_C 25 -#define R9A07G044_POEG_A_RST 26 -#define R9A07G044_POEG_B_RST 27 -#define R9A07G044_POEG_C_RST 28 -#define R9A07G044_POEG_D_RST 29 -#define R9A07G044_WDT0_PRESETN 30 -#define R9A07G044_WDT1_PRESETN 31 -#define R9A07G044_WDT2_PRESETN 32 -#define R9A07G044_SPI_RST 33 -#define R9A07G044_SDHI0_IXRST 34 -#define R9A07G044_SDHI1_IXRST 35 -#define R9A07G044_GPU_RESETN 36 -#define R9A07G044_GPU_AXI_RESETN 37 -#define R9A07G044_GPU_ACE_RESETN 38 -#define R9A07G044_ISU_ARESETN 39 -#define R9A07G044_ISU_PRESETN 40 -#define R9A07G044_H264_X_RESET_VCP 41 -#define R9A07G044_H264_CP_PRESET_P 42 -#define R9A07G044_CRU_CMN_RSTB 43 -#define R9A07G044_CRU_PRESETN 44 -#define R9A07G044_CRU_ARESETN 45 -#define R9A07G044_MIPI_DSI_CMN_RSTB 46 -#define R9A07G044_MIPI_DSI_ARESET_N 47 -#define R9A07G044_MIPI_DSI_PRESET_N 48 -#define R9A07G044_LCDC_RESET_N 49 -#define R9A07G044_SSI0_RST_M2_REG 50 -#define R9A07G044_SSI1_RST_M2_REG 51 -#define R9A07G044_SSI2_RST_M2_REG 52 -#define R9A07G044_SSI3_RST_M2_REG 53 -#define R9A07G044_SRC_RST 54 -#define R9A07G044_USB_U2H0_HRESETN 55 -#define R9A07G044_USB_U2H1_HRESETN 56 -#define R9A07G044_USB_U2P_EXL_SYSRST 57 -#define R9A07G044_USB_PRESETN 58 -#define R9A07G044_ETH0_RST_HW_N 59 -#define R9A07G044_ETH1_RST_HW_N 60 -#define R9A07G044_I2C0_MRST 61 -#define R9A07G044_I2C1_MRST 62 -#define R9A07G044_I2C2_MRST 63 -#define R9A07G044_I2C3_MRST 64 -#define R9A07G044_SCIF0_RST_SYSTEM_N 65 -#define R9A07G044_SCIF1_RST_SYSTEM_N 66 -#define R9A07G044_SCIF2_RST_SYSTEM_N 67 -#define R9A07G044_SCIF3_RST_SYSTEM_N 68 -#define R9A07G044_SCIF4_RST_SYSTEM_N 69 -#define R9A07G044_SCI0_RST 70 -#define R9A07G044_SCI1_RST 71 -#define R9A07G044_IRDA_RST 72 -#define R9A07G044_RSPI0_RST 73 -#define R9A07G044_RSPI1_RST 74 -#define R9A07G044_RSPI2_RST 75 -#define R9A07G044_CANFD_RSTP_N 76 -#define R9A07G044_CANFD_RSTC_N 77 -#define R9A07G044_GPIO_RSTN 78 -#define R9A07G044_GPIO_PORT_RESETN 79 -#define R9A07G044_GPIO_SPARE_RESETN 80 -#define R9A07G044_ADC_PRESETN 81 -#define R9A07G044_ADC_ADRST_N 82 -#define R9A07G044_TSU_PRESETN 83 - -#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h deleted file mode 100644 index 569a3cc33ffb..000000000000 --- a/include/dt-bindings/clock/renesas-cpg-mssr.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ -#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ - -#define CPG_CORE 0 /* Core Clock */ -#define CPG_MOD 1 /* Module Clock */ - -#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */

Drop in favour of dts/upstream

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/mt7621-clk.h | 46 -- include/dt-bindings/clock/mt7622-clk.h | 270 ------- include/dt-bindings/clock/mt7629-clk.h | 206 ------ include/dt-bindings/clock/mt8183-clk.h | 329 --------- include/dt-bindings/pinctrl/mt65xx.h | 41 -- include/dt-bindings/pinctrl/mt8365-pinfunc.h | 858 ---------------------- include/dt-bindings/power/mediatek,mt8365-power.h | 19 - include/dt-bindings/reset/mt7621-reset.h | 38 - 8 files changed, 1807 deletions(-)

diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h deleted file mode 100644 index 978c67951ba4..000000000000 --- a/include/dt-bindings/clock/mt7621-clk.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 MediaTek Inc. All rights reserved. - * - * Author: Weijie Gao weijie.gao@mediatek.com - */ - -#ifndef _DT_BINDINGS_MT7621_CLK_H_ -#define _DT_BINDINGS_MT7621_CLK_H_ - -#define MT7621_CLK_XTAL 0 -#define MT7621_CLK_CPU 1 -#define MT7621_CLK_BUS 2 -#define MT7621_CLK_50M 3 -#define MT7621_CLK_125M 4 -#define MT7621_CLK_150M 5 -#define MT7621_CLK_250M 6 -#define MT7621_CLK_270M 7 - -#define MT7621_CLK_HSDMA 8 -#define MT7621_CLK_FE 9 -#define MT7621_CLK_SP_DIVTX 10 -#define MT7621_CLK_TIMER 11 -#define MT7621_CLK_PCM 12 -#define MT7621_CLK_PIO 13 -#define MT7621_CLK_GDMA 14 -#define MT7621_CLK_NAND 15 -#define MT7621_CLK_I2C 16 -#define MT7621_CLK_I2S 17 -#define MT7621_CLK_SPI 18 -#define MT7621_CLK_UART1 19 -#define MT7621_CLK_UART2 20 -#define MT7621_CLK_UART3 21 -#define MT7621_CLK_ETH 22 -#define MT7621_CLK_PCIE0 23 -#define MT7621_CLK_PCIE1 24 -#define MT7621_CLK_PCIE2 25 -#define MT7621_CLK_CRYPTO 26 -#define MT7621_CLK_SHXC 27 - -#define MT7621_CLK_MAX 28 - -/* for u-boot only */ -#define MT7621_CLK_DDR 29 - -#endif /* _DT_BINDINGS_MT7621_CLK_H_ */ diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h deleted file mode 100644 index 76fcaff0e42e..000000000000 --- a/include/dt-bindings/clock/mt7622-clk.h +++ /dev/null @@ -1,270 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2019 MediaTek Inc. - */ -#ifndef _DT_BINDINGS_CLK_MT7622_H -#define _DT_BINDINGS_CLK_MT7622_H - -/* TOPCKGEN */ - -/* FIXED_CLKS */ -#define CLK_TOP_TO_U2_PHY 0 -#define CLK_TOP_TO_U2_PHY_1P 1 -#define CLK_TOP_PCIE0_PIPE_EN 2 -#define CLK_TOP_PCIE1_PIPE_EN 3 -#define CLK_TOP_SSUSB_TX250M 4 -#define CLK_TOP_SSUSB_EQ_RX250M 5 -#define CLK_TOP_SSUSB_CDR_REF 6 -#define CLK_TOP_SSUSB_CDR_FB 7 -#define CLK_TOP_SATA_ASIC 8 -#define CLK_TOP_SATA_RBC 9 -/* FIXED_DIVS */ -#define CLK_TOP_TO_USB3_SYS 10 -#define CLK_TOP_P1_1MHZ 11 -#define CLK_TOP_4MHZ 12 -#define CLK_TOP_P0_1MHZ 13 -#define CLK_TOP_TXCLK_SRC_PRE 14 -#define CLK_TOP_RTC 15 -#define CLK_TOP_MEMPLL 16 -#define CLK_TOP_DMPLL 17 -#define CLK_TOP_SYSPLL_D2 18 -#define CLK_TOP_SYSPLL1_D2 19 -#define CLK_TOP_SYSPLL1_D4 20 -#define CLK_TOP_SYSPLL1_D8 21 -#define CLK_TOP_SYSPLL2_D4 22 -#define CLK_TOP_SYSPLL2_D8 23 -#define CLK_TOP_SYSPLL_D5 24 -#define CLK_TOP_SYSPLL3_D2 25 -#define CLK_TOP_SYSPLL3_D4 26 -#define CLK_TOP_SYSPLL4_D2 27 -#define CLK_TOP_SYSPLL4_D4 28 -#define CLK_TOP_SYSPLL4_D16 29 -#define CLK_TOP_UNIVPLL 30 -#define CLK_TOP_UNIVPLL_D2 31 -#define CLK_TOP_UNIVPLL1_D2 32 -#define CLK_TOP_UNIVPLL1_D4 33 -#define CLK_TOP_UNIVPLL1_D8 34 -#define CLK_TOP_UNIVPLL1_D16 35 -#define CLK_TOP_UNIVPLL2_D2 36 -#define CLK_TOP_UNIVPLL2_D4 37 -#define CLK_TOP_UNIVPLL2_D8 38 -#define CLK_TOP_UNIVPLL2_D16 39 -#define CLK_TOP_UNIVPLL_D5 40 -#define CLK_TOP_UNIVPLL3_D2 41 -#define CLK_TOP_UNIVPLL3_D4 42 -#define CLK_TOP_UNIVPLL3_D16 43 -#define CLK_TOP_UNIVPLL_D7 44 -#define CLK_TOP_UNIVPLL_D80_D4 45 -#define CLK_TOP_UNIV48M 46 -#define CLK_TOP_SGMIIPLL 47 -#define CLK_TOP_SGMIIPLL_D2 48 -#define CLK_TOP_AUD1PLL 49 -#define CLK_TOP_AUD2PLL 50 -#define CLK_TOP_AUD_I2S2_MCK 51 -#define CLK_TOP_TO_USB3_REF 52 -#define CLK_TOP_PCIE1_MAC_EN 53 -#define CLK_TOP_PCIE0_MAC_EN 54 -#define CLK_TOP_ETH_500M 55 -/* TOP_MUXES */ -#define CLK_TOP_AXI_SEL 56 -#define CLK_TOP_MEM_SEL 57 -#define CLK_TOP_DDRPHYCFG_SEL 58 -#define CLK_TOP_ETH_SEL 59 -#define CLK_TOP_PWM_SEL 60 -#define CLK_TOP_F10M_REF_SEL 61 -#define CLK_TOP_NFI_INFRA_SEL 62 -#define CLK_TOP_FLASH_SEL 63 -#define CLK_TOP_UART_SEL 64 -#define CLK_TOP_SPI0_SEL 65 -#define CLK_TOP_SPI1_SEL 66 -#define CLK_TOP_MSDC50_0_SEL 67 -#define CLK_TOP_MSDC30_0_SEL 68 -#define CLK_TOP_MSDC30_1_SEL 69 -#define CLK_TOP_A1SYS_HP_SEL 70 -#define CLK_TOP_A2SYS_HP_SEL 71 -#define CLK_TOP_INTDIR_SEL 72 -#define CLK_TOP_AUD_INTBUS_SEL 73 -#define CLK_TOP_PMICSPI_SEL 74 -#define CLK_TOP_SCP_SEL 75 -#define CLK_TOP_ATB_SEL 76 -#define CLK_TOP_HIF_SEL 77 -#define CLK_TOP_AUDIO_SEL 78 -#define CLK_TOP_U2_SEL 79 -#define CLK_TOP_AUD1_SEL 80 -#define CLK_TOP_AUD2_SEL 81 -#define CLK_TOP_IRRX_SEL 82 -#define CLK_TOP_IRTX_SEL 83 -#define CLK_TOP_ASM_L_SEL 84 -#define CLK_TOP_ASM_M_SEL 85 -#define CLK_TOP_ASM_H_SEL 86 -#define CLK_TOP_APLL1_SEL 87 -#define CLK_TOP_APLL2_SEL 88 -#define CLK_TOP_I2S0_MCK_SEL 89 -#define CLK_TOP_I2S1_MCK_SEL 90 -#define CLK_TOP_I2S2_MCK_SEL 91 -#define CLK_TOP_I2S3_MCK_SEL 92 -#define CLK_TOP_APLL1_DIV 93 -#define CLK_TOP_APLL2_DIV 94 -#define CLK_TOP_I2S0_MCK_DIV 95 -#define CLK_TOP_I2S1_MCK_DIV 96 -#define CLK_TOP_I2S2_MCK_DIV 97 -#define CLK_TOP_I2S3_MCK_DIV 98 -#define CLK_TOP_A1SYS_HP_DIV 99 -#define CLK_TOP_A2SYS_HP_DIV 100 -#define CLK_TOP_APLL1_DIV_PD 101 -#define CLK_TOP_APLL2_DIV_PD 102 -#define CLK_TOP_I2S0_MCK_DIV_PD 103 -#define CLK_TOP_I2S1_MCK_DIV_PD 104 -#define CLK_TOP_I2S2_MCK_DIV_PD 105 -#define CLK_TOP_I2S3_MCK_DIV_PD 106 - -/* INFRACFG */ - -#define CLK_INFRA_DBGCLK_PD 0 -#define CLK_INFRA_TRNG 1 -#define CLK_INFRA_AUDIO_PD 2 -#define CLK_INFRA_IRRX_PD 3 -#define CLK_INFRA_APXGPT_PD 4 -#define CLK_INFRA_PMIC_PD 5 - -/* PERICFG */ - -#define CLK_PERI_THERM_PD 0 -#define CLK_PERI_PWM1_PD 1 -#define CLK_PERI_PWM2_PD 2 -#define CLK_PERI_PWM3_PD 3 -#define CLK_PERI_PWM4_PD 4 -#define CLK_PERI_PWM5_PD 5 -#define CLK_PERI_PWM6_PD 6 -#define CLK_PERI_PWM7_PD 7 -#define CLK_PERI_PWM_PD 8 -#define CLK_PERI_AP_DMA_PD 9 -#define CLK_PERI_MSDC30_0_PD 10 -#define CLK_PERI_MSDC30_1_PD 11 -#define CLK_PERI_UART0_PD 12 -#define CLK_PERI_UART1_PD 13 -#define CLK_PERI_UART2_PD 14 -#define CLK_PERI_UART3_PD 15 -#define CLK_PERI_BTIF_PD 16 -#define CLK_PERI_I2C0_PD 17 -#define CLK_PERI_I2C1_PD 18 -#define CLK_PERI_I2C2_PD 19 -#define CLK_PERI_SPI1_PD 20 -#define CLK_PERI_AUXADC_PD 21 -#define CLK_PERI_SPI0_PD 22 -#define CLK_PERI_SNFI_PD 23 -#define CLK_PERI_NFI_PD 24 -#define CLK_PERI_NFIECC_PD 25 -#define CLK_PERI_FLASH_PD 26 -#define CLK_PERI_IRTX_PD 27 - -/* APMIXEDSYS */ - -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIV2PLL 2 -#define CLK_APMIXED_ETH1PLL 3 -#define CLK_APMIXED_ETH2PLL 4 -#define CLK_APMIXED_AUD1PLL 5 -#define CLK_APMIXED_AUD2PLL 6 -#define CLK_APMIXED_TRGPLL 7 -#define CLK_APMIXED_SGMIPLL 8 - -/* AUDIOSYS */ - -#define CLK_AUDIO_AFE 0 -#define CLK_AUDIO_HDMI 1 -#define CLK_AUDIO_SPDF 2 -#define CLK_AUDIO_APLL 3 -#define CLK_AUDIO_I2SIN1 4 -#define CLK_AUDIO_I2SIN2 5 -#define CLK_AUDIO_I2SIN3 6 -#define CLK_AUDIO_I2SIN4 7 -#define CLK_AUDIO_I2SO1 8 -#define CLK_AUDIO_I2SO2 9 -#define CLK_AUDIO_I2SO3 10 -#define CLK_AUDIO_I2SO4 11 -#define CLK_AUDIO_ASRCI1 12 -#define CLK_AUDIO_ASRCI2 13 -#define CLK_AUDIO_ASRCO1 14 -#define CLK_AUDIO_ASRCO2 15 -#define CLK_AUDIO_INTDIR 16 -#define CLK_AUDIO_A1SYS 17 -#define CLK_AUDIO_A2SYS 18 -#define CLK_AUDIO_UL1 19 -#define CLK_AUDIO_UL2 20 -#define CLK_AUDIO_UL3 21 -#define CLK_AUDIO_UL4 22 -#define CLK_AUDIO_UL5 23 -#define CLK_AUDIO_UL6 24 -#define CLK_AUDIO_DL1 25 -#define CLK_AUDIO_DL2 26 -#define CLK_AUDIO_DL3 27 -#define CLK_AUDIO_DL4 28 -#define CLK_AUDIO_DL5 29 -#define CLK_AUDIO_DL6 30 -#define CLK_AUDIO_DLMCH 31 -#define CLK_AUDIO_ARB1 32 -#define CLK_AUDIO_AWB 33 -#define CLK_AUDIO_AWB3 34 -#define CLK_AUDIO_DAI 35 -#define CLK_AUDIO_MOD 36 -#define CLK_AUDIO_ASRCI3 37 -#define CLK_AUDIO_ASRCI4 38 -#define CLK_AUDIO_ASRCO3 39 -#define CLK_AUDIO_ASRCO4 40 -#define CLK_AUDIO_MEM_ASRC1 41 -#define CLK_AUDIO_MEM_ASRC2 42 -#define CLK_AUDIO_MEM_ASRC3 43 -#define CLK_AUDIO_MEM_ASRC4 44 -#define CLK_AUDIO_MEM_ASRC5 45 -#define CLK_AUDIO_AFE_CONN 46 -#define CLK_AUDIO_NR_CLK 47 - -/* SSUSBSYS */ - -#define CLK_SSUSB_U2_PHY_1P_EN 0 -#define CLK_SSUSB_U2_PHY_EN 1 -#define CLK_SSUSB_REF_EN 2 -#define CLK_SSUSB_SYS_EN 3 -#define CLK_SSUSB_MCU_EN 4 -#define CLK_SSUSB_DMA_EN 5 -#define CLK_SSUSB_NR_CLK 6 - -/* PCIESYS */ - -#define CLK_PCIE_P1_AUX_EN 0 -#define CLK_PCIE_P1_OBFF_EN 1 -#define CLK_PCIE_P1_AHB_EN 2 -#define CLK_PCIE_P1_AXI_EN 3 -#define CLK_PCIE_P1_MAC_EN 4 -#define CLK_PCIE_P1_PIPE_EN 5 -#define CLK_PCIE_P0_AUX_EN 6 -#define CLK_PCIE_P0_OBFF_EN 7 -#define CLK_PCIE_P0_AHB_EN 8 -#define CLK_PCIE_P0_AXI_EN 9 -#define CLK_PCIE_P0_MAC_EN 10 -#define CLK_PCIE_P0_PIPE_EN 11 -#define CLK_SATA_AHB_EN 12 -#define CLK_SATA_AXI_EN 13 -#define CLK_SATA_ASIC_EN 14 -#define CLK_SATA_RBC_EN 15 -#define CLK_SATA_PM_EN 16 -#define CLK_PCIE_NR_CLK 17 - -/* ETHSYS */ - -#define CLK_ETH_HSDMA_EN 0 -#define CLK_ETH_ESW_EN 1 -#define CLK_ETH_GP2_EN 2 -#define CLK_ETH_GP1_EN 3 -#define CLK_ETH_GP0_EN 4 - -/* SGMIISYS */ - -#define CLK_SGMII_TX250M_EN 0 -#define CLK_SGMII_RX250M_EN 1 -#define CLK_SGMII_CDR_REF 2 -#define CLK_SGMII_CDR_FB 3 - -#endif /* _DT_BINDINGS_CLK_MT7622_H */ diff --git a/include/dt-bindings/clock/mt7629-clk.h b/include/dt-bindings/clock/mt7629-clk.h deleted file mode 100644 index 0bbfbfa744aa..000000000000 --- a/include/dt-bindings/clock/mt7629-clk.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - */ - -#ifndef _DT_BINDINGS_CLK_MT7629_H -#define _DT_BINDINGS_CLK_MT7629_H - -/* TOPCKGEN */ -#define CLK_TOP_FCLKS_OFF 0 - -#define CLK_TOP_TO_U2_PHY 0 -#define CLK_TOP_TO_U2_PHY_1P 1 -#define CLK_TOP_PCIE0_PIPE_EN 2 -#define CLK_TOP_PCIE1_PIPE_EN 3 -#define CLK_TOP_SSUSB_TX250M 4 -#define CLK_TOP_SSUSB_EQ_RX250M 5 -#define CLK_TOP_SSUSB_CDR_REF 6 -#define CLK_TOP_SSUSB_CDR_FB 7 -#define CLK_TOP_SATA_ASIC 8 -#define CLK_TOP_SATA_RBC 9 - -#define CLK_TOP_TO_USB3_SYS 10 -#define CLK_TOP_P1_1MHZ 11 -#define CLK_TOP_4MHZ 12 -#define CLK_TOP_P0_1MHZ 13 -#define CLK_TOP_ETH_500M 14 -#define CLK_TOP_TXCLK_SRC_PRE 15 -#define CLK_TOP_RTC 16 -#define CLK_TOP_PWM_QTR_26M 17 -#define CLK_TOP_CPUM_TCK_IN 18 -#define CLK_TOP_TO_USB3_DA_TOP 19 -#define CLK_TOP_MEMPLL 20 -#define CLK_TOP_DMPLL 21 -#define CLK_TOP_DMPLL_D4 22 -#define CLK_TOP_DMPLL_D8 23 -#define CLK_TOP_SYSPLL_D2 24 -#define CLK_TOP_SYSPLL1_D2 25 -#define CLK_TOP_SYSPLL1_D4 26 -#define CLK_TOP_SYSPLL1_D8 27 -#define CLK_TOP_SYSPLL1_D16 28 -#define CLK_TOP_SYSPLL2_D2 29 -#define CLK_TOP_SYSPLL2_D4 30 -#define CLK_TOP_SYSPLL2_D8 31 -#define CLK_TOP_SYSPLL_D5 32 -#define CLK_TOP_SYSPLL3_D2 33 -#define CLK_TOP_SYSPLL3_D4 34 -#define CLK_TOP_SYSPLL_D7 35 -#define CLK_TOP_SYSPLL4_D2 36 -#define CLK_TOP_SYSPLL4_D4 37 -#define CLK_TOP_SYSPLL4_D16 38 -#define CLK_TOP_UNIVPLL 39 -#define CLK_TOP_UNIVPLL1_D2 40 -#define CLK_TOP_UNIVPLL1_D4 41 -#define CLK_TOP_UNIVPLL1_D8 42 -#define CLK_TOP_UNIVPLL_D3 43 -#define CLK_TOP_UNIVPLL2_D2 44 -#define CLK_TOP_UNIVPLL2_D4 45 -#define CLK_TOP_UNIVPLL2_D8 46 -#define CLK_TOP_UNIVPLL2_D16 47 -#define CLK_TOP_UNIVPLL_D5 48 -#define CLK_TOP_UNIVPLL3_D2 49 -#define CLK_TOP_UNIVPLL3_D4 50 -#define CLK_TOP_UNIVPLL3_D16 51 -#define CLK_TOP_UNIVPLL_D7 52 -#define CLK_TOP_UNIVPLL_D80_D4 53 -#define CLK_TOP_UNIV48M 54 -#define CLK_TOP_SGMIIPLL_D2 55 -#define CLK_TOP_CLKXTAL_D4 56 -#define CLK_TOP_HD_FAXI 57 -#define CLK_TOP_FAXI 58 -#define CLK_TOP_F_FAUD_INTBUS 59 -#define CLK_TOP_AP2WBHIF_HCLK 60 -#define CLK_TOP_10M_INFRAO 61 -#define CLK_TOP_MSDC30_1 62 -#define CLK_TOP_SPI 63 -#define CLK_TOP_SF 64 -#define CLK_TOP_FLASH 65 -#define CLK_TOP_TO_USB3_REF 66 -#define CLK_TOP_TO_USB3_MCU 67 -#define CLK_TOP_TO_USB3_DMA 68 -#define CLK_TOP_FROM_TOP_AHB 69 -#define CLK_TOP_FROM_TOP_AXI 70 -#define CLK_TOP_PCIE1_MAC_EN 71 -#define CLK_TOP_PCIE0_MAC_EN 72 - -#define CLK_TOP_AXI_SEL 73 -#define CLK_TOP_MEM_SEL 74 -#define CLK_TOP_DDRPHYCFG_SEL 75 -#define CLK_TOP_ETH_SEL 76 -#define CLK_TOP_PWM_SEL 77 -#define CLK_TOP_F10M_REF_SEL 78 -#define CLK_TOP_NFI_INFRA_SEL 79 -#define CLK_TOP_FLASH_SEL 80 -#define CLK_TOP_UART_SEL 81 -#define CLK_TOP_SPI0_SEL 82 -#define CLK_TOP_SPI1_SEL 83 -#define CLK_TOP_MSDC50_0_SEL 84 -#define CLK_TOP_MSDC30_0_SEL 85 -#define CLK_TOP_MSDC30_1_SEL 86 -#define CLK_TOP_AP2WBMCU_SEL 87 -#define CLK_TOP_AP2WBHIF_SEL 88 -#define CLK_TOP_AUDIO_SEL 89 -#define CLK_TOP_AUD_INTBUS_SEL 90 -#define CLK_TOP_PMICSPI_SEL 91 -#define CLK_TOP_SCP_SEL 92 -#define CLK_TOP_ATB_SEL 93 -#define CLK_TOP_HIF_SEL 94 -#define CLK_TOP_SATA_SEL 95 -#define CLK_TOP_U2_SEL 96 -#define CLK_TOP_AUD1_SEL 97 -#define CLK_TOP_AUD2_SEL 98 -#define CLK_TOP_IRRX_SEL 99 -#define CLK_TOP_IRTX_SEL 100 -#define CLK_TOP_SATA_MCU_SEL 101 -#define CLK_TOP_PCIE0_MCU_SEL 102 -#define CLK_TOP_PCIE1_MCU_SEL 103 -#define CLK_TOP_SSUSB_MCU_SEL 104 -#define CLK_TOP_CRYPTO_SEL 105 -#define CLK_TOP_SGMII_REF_1_SEL 106 -#define CLK_TOP_10M_SEL 107 -#define CLK_TOP_NR_CLK 108 - -/* INFRACFG */ -#define CLK_INFRA_MUX1_SEL 0 -#define CLK_INFRA_DBGCLK_PD 1 -#define CLK_INFRA_TRNG_PD 2 -#define CLK_INFRA_DEVAPC_PD 3 -#define CLK_INFRA_APXGPT_PD 4 -#define CLK_INFRA_SEJ_PD 5 -#define CLK_INFRA_NR_CLK 6 - -/* PERICFG */ -#define CLK_PERIBUS_SEL 0 -#define CLK_PERI_PWM1_PD 1 -#define CLK_PERI_PWM2_PD 2 -#define CLK_PERI_PWM3_PD 3 -#define CLK_PERI_PWM4_PD 4 -#define CLK_PERI_PWM5_PD 5 -#define CLK_PERI_PWM6_PD 6 -#define CLK_PERI_PWM7_PD 7 -#define CLK_PERI_PWM_PD 8 -#define CLK_PERI_AP_DMA_PD 9 -#define CLK_PERI_MSDC30_1_PD 10 -#define CLK_PERI_UART0_PD 11 -#define CLK_PERI_UART1_PD 12 -#define CLK_PERI_UART2_PD 13 -#define CLK_PERI_UART3_PD 14 -#define CLK_PERI_BTIF_PD 15 -#define CLK_PERI_I2C0_PD 16 -#define CLK_PERI_SPI0_PD 17 -#define CLK_PERI_SNFI_PD 18 -#define CLK_PERI_NFI_PD 19 -#define CLK_PERI_NFIECC_PD 20 -#define CLK_PERI_FLASH_PD 21 -#define CLK_PERI_NR_CLK 22 - -/* APMIXEDSYS */ -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIV2PLL 2 -#define CLK_APMIXED_ETH1PLL 3 -#define CLK_APMIXED_ETH2PLL 4 -#define CLK_APMIXED_SGMIPLL 5 -#define CLK_APMIXED_NR_CLK 6 - -/* SSUSBSYS */ -#define CLK_SSUSB_U2_PHY_1P_EN 0 -#define CLK_SSUSB_U2_PHY_EN 1 -#define CLK_SSUSB_REF_EN 2 -#define CLK_SSUSB_SYS_EN 3 -#define CLK_SSUSB_MCU_EN 4 -#define CLK_SSUSB_DMA_EN 5 -#define CLK_SSUSB_NR_CLK 6 - -/* PCIESYS */ -#define CLK_PCIE_P1_AUX_EN 0 -#define CLK_PCIE_P1_OBFF_EN 1 -#define CLK_PCIE_P1_AHB_EN 2 -#define CLK_PCIE_P1_AXI_EN 3 -#define CLK_PCIE_P1_MAC_EN 4 -#define CLK_PCIE_P1_PIPE_EN 5 -#define CLK_PCIE_P0_AUX_EN 6 -#define CLK_PCIE_P0_OBFF_EN 7 -#define CLK_PCIE_P0_AHB_EN 8 -#define CLK_PCIE_P0_AXI_EN 9 -#define CLK_PCIE_P0_MAC_EN 10 -#define CLK_PCIE_P0_PIPE_EN 11 -#define CLK_PCIE_NR_CLK 12 - -/* ETHSYS */ -#define CLK_ETH_FE_EN 0 -#define CLK_ETH_GP2_EN 1 -#define CLK_ETH_GP1_EN 2 -#define CLK_ETH_GP0_EN 3 -#define CLK_ETH_ESW_EN 4 -#define CLK_ETH_NR_CLK 5 - -/* SGMIISYS */ -#define CLK_SGMII_TX_EN 0 -#define CLK_SGMII_RX_EN 1 -#define CLK_SGMII_CDR_REF 2 -#define CLK_SGMII_CDR_FB 3 -#define CLK_SGMII_NR_CLK 4 - -#endif /* _DT_BINDINGS_CLK_MT7629_H */ diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h deleted file mode 100644 index f7e6367ce844..000000000000 --- a/include/dt-bindings/clock/mt8183-clk.h +++ /dev/null @@ -1,329 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 MediaTek Inc. - * Author: Weiyi Lu weiyi.lu@mediatek.com - */ - -#ifndef _DT_BINDINGS_CLK_MT8183_H -#define _DT_BINDINGS_CLK_MT8183_H - -/* APMIXED */ -#define CLK_APMIXED_ARMPLL_LL 0 -#define CLK_APMIXED_ARMPLL_L 1 -#define CLK_APMIXED_CCIPLL 2 -#define CLK_APMIXED_MAINPLL 3 -#define CLK_APMIXED_UNIV2PLL 4 -#define CLK_APMIXED_MSDCPLL 5 -#define CLK_APMIXED_MMPLL 6 -#define CLK_APMIXED_MFGPLL 7 -#define CLK_APMIXED_TVDPLL 8 -#define CLK_APMIXED_APLL1 9 -#define CLK_APMIXED_APLL2 10 -#define CLK_APMIXED_SSUSB_26M 11 -#define CLK_APMIXED_APPLL_26M 12 -#define CLK_APMIXED_MIPIC0_26M 13 -#define CLK_APMIXED_MDPLLGP_26M 14 -#define CLK_APMIXED_MMSYS_26M 15 -#define CLK_APMIXED_UFS_26M 16 -#define CLK_APMIXED_MIPIC1_26M 17 -#define CLK_APMIXED_MEMPLL_26M 18 -#define CLK_APMIXED_CLKSQ_LVPLL_26M 19 -#define CLK_APMIXED_MIPID0_26M 20 -#define CLK_APMIXED_MIPID1_26M 21 -#define CLK_APMIXED_NR_CLK 22 - -/* TOPCKGEN */ -#define CLK_TOP_CLK26M 0 -#define CLK_TOP_ULPOSC 1 -#define CLK_TOP_UNIVP_192M 2 -#define CLK_TOP_CLK13M 3 -#define CLK_TOP_F26M_CK_D2 4 -#define CLK_TOP_SYSPLL_CK 5 -#define CLK_TOP_SYSPLL_D2 6 -#define CLK_TOP_SYSPLL_D3 7 -#define CLK_TOP_SYSPLL_D5 8 -#define CLK_TOP_SYSPLL_D7 9 -#define CLK_TOP_SYSPLL_D2_D2 10 -#define CLK_TOP_SYSPLL_D2_D4 11 -#define CLK_TOP_SYSPLL_D2_D8 12 -#define CLK_TOP_SYSPLL_D2_D16 13 -#define CLK_TOP_SYSPLL_D3_D2 14 -#define CLK_TOP_SYSPLL_D3_D4 15 -#define CLK_TOP_SYSPLL_D3_D8 16 -#define CLK_TOP_SYSPLL_D5_D2 17 -#define CLK_TOP_SYSPLL_D5_D4 18 -#define CLK_TOP_SYSPLL_D7_D2 19 -#define CLK_TOP_SYSPLL_D7_D4 20 -#define CLK_TOP_UNIVPLL_CK 21 -#define CLK_TOP_UNIVPLL_D2 22 -#define CLK_TOP_UNIVPLL_D3 23 -#define CLK_TOP_UNIVPLL_D5 24 -#define CLK_TOP_UNIVPLL_D7 25 -#define CLK_TOP_UNIVPLL_D2_D2 26 -#define CLK_TOP_UNIVPLL_D2_D4 27 -#define CLK_TOP_UNIVPLL_D2_D8 28 -#define CLK_TOP_UNIVPLL_D3_D2 29 -#define CLK_TOP_UNIVPLL_D3_D4 30 -#define CLK_TOP_UNIVPLL_D3_D8 31 -#define CLK_TOP_UNIVPLL_D5_D2 32 -#define CLK_TOP_UNIVPLL_D5_D4 33 -#define CLK_TOP_UNIVPLL_D5_D8 34 -#define CLK_TOP_UNIVP_192M_CK 35 -#define CLK_TOP_UNIVP_192M_D2 36 -#define CLK_TOP_UNIVP_192M_D4 37 -#define CLK_TOP_UNIVP_192M_D8 38 -#define CLK_TOP_UNIVP_192M_D16 39 -#define CLK_TOP_UNIVP_192M_D32 40 -#define CLK_TOP_APLL1_CK 41 -#define CLK_TOP_APLL1_D2 42 -#define CLK_TOP_APLL1_D4 43 -#define CLK_TOP_APLL1_D8 44 -#define CLK_TOP_APLL2_CK 45 -#define CLK_TOP_APLL2_D2 46 -#define CLK_TOP_APLL2_D4 47 -#define CLK_TOP_APLL2_D8 48 -#define CLK_TOP_TVDPLL_CK 49 -#define CLK_TOP_TVDPLL_D2 50 -#define CLK_TOP_TVDPLL_D4 51 -#define CLK_TOP_TVDPLL_D8 52 -#define CLK_TOP_TVDPLL_D16 53 -#define CLK_TOP_MMPLL_CK 54 -#define CLK_TOP_MMPLL_D4 55 -#define CLK_TOP_MMPLL_D4_D2 56 -#define CLK_TOP_MMPLL_D4_D4 57 -#define CLK_TOP_MMPLL_D5 58 -#define CLK_TOP_MMPLL_D5_D2 59 -#define CLK_TOP_MMPLL_D5_D4 60 -#define CLK_TOP_MMPLL_D6 61 -#define CLK_TOP_MMPLL_D7 62 -#define CLK_TOP_MFGPLL_CK 63 -#define CLK_TOP_MSDCPLL_CK 64 -#define CLK_TOP_MSDCPLL_D2 65 -#define CLK_TOP_MSDCPLL_D4 66 -#define CLK_TOP_MSDCPLL_D8 67 -#define CLK_TOP_MSDCPLL_D16 68 -#define CLK_TOP_AD_OSC_CK 69 -#define CLK_TOP_OSC_D2 70 -#define CLK_TOP_OSC_D4 71 -#define CLK_TOP_OSC_D8 72 -#define CLK_TOP_OSC_D16 73 -#define CLK_TOP_UNIVPLL 74 -#define CLK_TOP_UNIVPLL_D3_D16 75 -#define CLK_TOP_APLL12_DIV0 76 -#define CLK_TOP_APLL12_DIV1 77 -#define CLK_TOP_APLL12_DIV2 78 -#define CLK_TOP_APLL12_DIV3 79 -#define CLK_TOP_APLL12_DIV4 80 -#define CLK_TOP_APLL12_DIVB 81 -#define CLK_TOP_ARMPLL_DIV_PLL1 82 -#define CLK_TOP_ARMPLL_DIV_PLL2 83 -#define CLK_TOP_MUX_AXI 84 -#define CLK_TOP_MUX_MM 85 -#define CLK_TOP_MUX_IMG 86 -#define CLK_TOP_MUX_CAM 87 -#define CLK_TOP_MUX_DSP 88 -#define CLK_TOP_MUX_DSP1 89 -#define CLK_TOP_MUX_DSP2 90 -#define CLK_TOP_MUX_IPU_IF 91 -#define CLK_TOP_MUX_MFG 92 -#define CLK_TOP_MUX_F52M_MFG 93 -#define CLK_TOP_MUX_CAMTG 94 -#define CLK_TOP_MUX_CAMTG2 95 -#define CLK_TOP_MUX_CAMTG3 96 -#define CLK_TOP_MUX_CAMTG4 97 -#define CLK_TOP_MUX_UART 98 -#define CLK_TOP_MUX_SPI 99 -#define CLK_TOP_MUX_MSDC50_0_HCLK 100 -#define CLK_TOP_MUX_MSDC50_0 101 -#define CLK_TOP_MUX_MSDC30_1 102 -#define CLK_TOP_MUX_MSDC30_2 103 -#define CLK_TOP_MUX_AUDIO 104 -#define CLK_TOP_MUX_AUD_INTBUS 105 -#define CLK_TOP_MUX_PMICSPI 106 -#define CLK_TOP_MUX_FPWRAP_ULPOSC 107 -#define CLK_TOP_MUX_ATB 108 -#define CLK_TOP_MUX_SSPM 109 -#define CLK_TOP_MUX_DPI0 110 -#define CLK_TOP_MUX_SCAM 111 -#define CLK_TOP_MUX_DISP_PWM 112 -#define CLK_TOP_MUX_USB_TOP 113 -#define CLK_TOP_MUX_SSUSB_TOP_XHCI 114 -#define CLK_TOP_MUX_SPM 115 -#define CLK_TOP_MUX_I2C 116 -#define CLK_TOP_MUX_SCP 117 -#define CLK_TOP_MUX_SENINF 118 -#define CLK_TOP_MUX_DXCC 119 -#define CLK_TOP_MUX_AUD_ENG1 120 -#define CLK_TOP_MUX_AUD_ENG2 121 -#define CLK_TOP_MUX_FAES_UFSFDE 122 -#define CLK_TOP_MUX_FUFS 123 -#define CLK_TOP_MUX_AUD_1 124 -#define CLK_TOP_MUX_AUD_2 125 -#define CLK_TOP_MUX_APLL_I2S0 126 -#define CLK_TOP_MUX_APLL_I2S1 127 -#define CLK_TOP_MUX_APLL_I2S2 128 -#define CLK_TOP_MUX_APLL_I2S3 129 -#define CLK_TOP_MUX_APLL_I2S4 130 -#define CLK_TOP_MUX_APLL_I2S5 131 -#define CLK_TOP_NR_CLK 132 - -/* INFRACFG_AO */ -#define CLK_INFRA_PMIC_TMR 0 -#define CLK_INFRA_PMIC_AP 1 -#define CLK_INFRA_PMIC_MD 2 -#define CLK_INFRA_PMIC_CONN 3 -#define CLK_INFRA_SCPSYS 4 -#define CLK_INFRA_SEJ 5 -#define CLK_INFRA_APXGPT 6 -#define CLK_INFRA_ICUSB 7 -#define CLK_INFRA_GCE 8 -#define CLK_INFRA_THERM 9 -#define CLK_INFRA_I2C0 10 -#define CLK_INFRA_I2C1 11 -#define CLK_INFRA_I2C2 12 -#define CLK_INFRA_I2C3 13 -#define CLK_INFRA_PWM_HCLK 14 -#define CLK_INFRA_PWM1 15 -#define CLK_INFRA_PWM2 16 -#define CLK_INFRA_PWM3 17 -#define CLK_INFRA_PWM4 18 -#define CLK_INFRA_PWM 19 -#define CLK_INFRA_UART0 20 -#define CLK_INFRA_UART1 21 -#define CLK_INFRA_UART2 22 -#define CLK_INFRA_UART3 23 -#define CLK_INFRA_GCE_26M 24 -#define CLK_INFRA_CQ_DMA_FPC 25 -#define CLK_INFRA_BTIF 26 -#define CLK_INFRA_SPI0 27 -#define CLK_INFRA_MSDC0 28 -#define CLK_INFRA_MSDC1 29 -#define CLK_INFRA_MSDC2 30 -#define CLK_INFRA_MSDC0_SCK 31 -#define CLK_INFRA_DVFSRC 32 -#define CLK_INFRA_GCPU 33 -#define CLK_INFRA_TRNG 34 -#define CLK_INFRA_AUXADC 35 -#define CLK_INFRA_CPUM 36 -#define CLK_INFRA_CCIF1_AP 37 -#define CLK_INFRA_CCIF1_MD 38 -#define CLK_INFRA_AUXADC_MD 39 -#define CLK_INFRA_MSDC1_SCK 40 -#define CLK_INFRA_MSDC2_SCK 41 -#define CLK_INFRA_AP_DMA 42 -#define CLK_INFRA_XIU 43 -#define CLK_INFRA_DEVICE_APC 44 -#define CLK_INFRA_CCIF_AP 45 -#define CLK_INFRA_DEBUGSYS 46 -#define CLK_INFRA_AUDIO 47 -#define CLK_INFRA_CCIF_MD 48 -#define CLK_INFRA_DXCC_SEC_CORE 49 -#define CLK_INFRA_DXCC_AO 50 -#define CLK_INFRA_DRAMC_F26M 51 -#define CLK_INFRA_IRTX 52 -#define CLK_INFRA_DISP_PWM 53 -#define CLK_INFRA_CLDMA_BCLK 54 -#define CLK_INFRA_AUDIO_26M_BCLK 55 -#define CLK_INFRA_SPI1 56 -#define CLK_INFRA_I2C4 57 -#define CLK_INFRA_MODEM_TEMP_SHARE 58 -#define CLK_INFRA_SPI2 59 -#define CLK_INFRA_SPI3 60 -#define CLK_INFRA_UNIPRO_SCK 61 -#define CLK_INFRA_UNIPRO_TICK 62 -#define CLK_INFRA_UFS_MP_SAP_BCLK 63 -#define CLK_INFRA_MD32_BCLK 64 -#define CLK_INFRA_SSPM 65 -#define CLK_INFRA_UNIPRO_MBIST 66 -#define CLK_INFRA_SSPM_BUS_HCLK 67 -#define CLK_INFRA_I2C5 68 -#define CLK_INFRA_I2C5_ARBITER 69 -#define CLK_INFRA_I2C5_IMM 70 -#define CLK_INFRA_I2C1_ARBITER 71 -#define CLK_INFRA_I2C1_IMM 72 -#define CLK_INFRA_I2C2_ARBITER 73 -#define CLK_INFRA_I2C2_IMM 74 -#define CLK_INFRA_SPI4 75 -#define CLK_INFRA_SPI5 76 -#define CLK_INFRA_CQ_DMA 77 -#define CLK_INFRA_UFS 78 -#define CLK_INFRA_AES_UFSFDE 79 -#define CLK_INFRA_UFS_TICK 80 -#define CLK_INFRA_MSDC0_SELF 81 -#define CLK_INFRA_MSDC1_SELF 82 -#define CLK_INFRA_MSDC2_SELF 83 -#define CLK_INFRA_SSPM_26M_SELF 84 -#define CLK_INFRA_SSPM_32K_SELF 85 -#define CLK_INFRA_UFS_AXI 86 -#define CLK_INFRA_I2C6 87 -#define CLK_INFRA_AP_MSDC0 88 -#define CLK_INFRA_MD_MSDC0 89 -#define CLK_INFRA_USB 90 -#define CLK_INFRA_DEVMPU_BCLK 91 -#define CLK_INFRA_CCIF2_AP 92 -#define CLK_INFRA_CCIF2_MD 93 -#define CLK_INFRA_CCIF3_AP 94 -#define CLK_INFRA_CCIF3_MD 95 -#define CLK_INFRA_SEJ_F13M 96 -#define CLK_INFRA_AES_BCLK 97 -#define CLK_INFRA_I2C7 98 -#define CLK_INFRA_I2C8 99 -#define CLK_INFRA_FBIST2FPC 100 -#define CLK_INFRA_NR_CLK 101 - -/* MMSYS_CONFIG */ -#define CLK_MM_SMI_COMMON 0 -#define CLK_MM_SMI_LARB0 1 -#define CLK_MM_SMI_LARB1 2 -#define CLK_MM_GALS_COMM0 3 -#define CLK_MM_GALS_COMM1 4 -#define CLK_MM_GALS_CCU2MM 5 -#define CLK_MM_GALS_IPU12MM 6 -#define CLK_MM_GALS_IMG2MM 7 -#define CLK_MM_GALS_CAM2MM 8 -#define CLK_MM_GALS_IPU2MM 9 -#define CLK_MM_MDP_DL_TXCK 10 -#define CLK_MM_IPU_DL_TXCK 11 -#define CLK_MM_MDP_RDMA0 12 -#define CLK_MM_MDP_RDMA1 13 -#define CLK_MM_MDP_RSZ0 14 -#define CLK_MM_MDP_RSZ1 15 -#define CLK_MM_MDP_TDSHP 16 -#define CLK_MM_MDP_WROT0 17 -#define CLK_MM_FAKE_ENG 18 -#define CLK_MM_DISP_OVL0 19 -#define CLK_MM_DISP_OVL0_2L 20 -#define CLK_MM_DISP_OVL1_2L 21 -#define CLK_MM_DISP_RDMA0 22 -#define CLK_MM_DISP_RDMA1 23 -#define CLK_MM_DISP_WDMA0 24 -#define CLK_MM_DISP_COLOR0 25 -#define CLK_MM_DISP_CCORR0 26 -#define CLK_MM_DISP_AAL0 27 -#define CLK_MM_DISP_GAMMA0 28 -#define CLK_MM_DISP_DITHER0 29 -#define CLK_MM_DISP_SPLIT 30 -#define CLK_MM_DSI0_MM 31 -#define CLK_MM_DSI0_IF 32 -#define CLK_MM_DPI_MM 33 -#define CLK_MM_DPI_IF 34 -#define CLK_MM_FAKE_ENG2 35 -#define CLK_MM_MDP_DL_RX 36 -#define CLK_MM_IPU_DL_RX 37 -#define CLK_MM_26M 38 -#define CLK_MM_MMSYS_R2Y 39 -#define CLK_MM_DISP_RSZ 40 -#define CLK_MM_MDP_WDMA0 41 -#define CLK_MM_MDP_AAL 42 -#define CLK_MM_MDP_CCORR 43 -#define CLK_MM_DBI_MM 44 -#define CLK_MM_DBI_IF 45 -#define CLK_MM_NR_CLK 46 - -/* MCUCFG */ -#define CLK_MCU_MP0_SEL 0 -#define CLK_MCU_MP2_SEL 1 -#define CLK_MCU_BUS_SEL 2 -#define CLK_MCU_NR_CLK 3 - -#endif /* _DT_BINDINGS_CLK_MT8183_H */ diff --git a/include/dt-bindings/pinctrl/mt65xx.h b/include/dt-bindings/pinctrl/mt65xx.h deleted file mode 100644 index fbea8d35bcf1..000000000000 --- a/include/dt-bindings/pinctrl/mt65xx.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Hongzhou.Yang hongzhou.yang@mediatek.com - */ - -#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H -#define _DT_BINDINGS_PINCTRL_MT65XX_H - -#define MTK_PIN_NO(x) ((x) << 8) -#define MTK_GET_PIN_NO(x) ((x) >> 8) -#define MTK_GET_PIN_FUNC(x) ((x) & 0xf) - -#define MTK_PUPD_SET_R1R0_00 100 -#define MTK_PUPD_SET_R1R0_01 101 -#define MTK_PUPD_SET_R1R0_10 102 -#define MTK_PUPD_SET_R1R0_11 103 - -#define MTK_PULL_SET_RSEL_000 200 -#define MTK_PULL_SET_RSEL_001 201 -#define MTK_PULL_SET_RSEL_010 202 -#define MTK_PULL_SET_RSEL_011 203 -#define MTK_PULL_SET_RSEL_100 204 -#define MTK_PULL_SET_RSEL_101 205 -#define MTK_PULL_SET_RSEL_110 206 -#define MTK_PULL_SET_RSEL_111 207 - -#define MTK_DRIVE_2mA 2 -#define MTK_DRIVE_4mA 4 -#define MTK_DRIVE_6mA 6 -#define MTK_DRIVE_8mA 8 -#define MTK_DRIVE_10mA 10 -#define MTK_DRIVE_12mA 12 -#define MTK_DRIVE_14mA 14 -#define MTK_DRIVE_16mA 16 -#define MTK_DRIVE_20mA 20 -#define MTK_DRIVE_24mA 24 -#define MTK_DRIVE_28mA 28 -#define MTK_DRIVE_32mA 32 - -#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */ diff --git a/include/dt-bindings/pinctrl/mt8365-pinfunc.h b/include/dt-bindings/pinctrl/mt8365-pinfunc.h deleted file mode 100644 index e2ec8af57dcf..000000000000 --- a/include/dt-bindings/pinctrl/mt8365-pinfunc.h +++ /dev/null @@ -1,858 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 MediaTek Inc. - */ -#ifndef __MT8365_PINFUNC_H -#define __MT8365_PINFUNC_H - -#include <dt-bindings/pinctrl/mt65xx.h> - -#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1) -#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2) -#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) -#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) -#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5) -#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) - -#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1) -#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2) -#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3) -#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) -#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5) -#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7) - -#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1) -#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2) -#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3) -#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) -#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5) -#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7) - -#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1) -#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2) -#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3) -#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) -#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5) -#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6) -#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7) - -#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1) -#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2) -#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3) -#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) -#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5) -#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6) -#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7) - -#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1) -#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2) -#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3) -#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) -#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5) -#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6) -#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7) - -#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1) -#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2) -#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3) -#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) -#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5) -#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6) -#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7) - -#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1) -#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3) -#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) -#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5) -#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7) - -#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1) -#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2) -#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3) -#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) -#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5) -#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7) - -#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1) -#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2) -#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3) -#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) -#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5) -#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7) - -#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1) -#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2) -#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3) -#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) -#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5) -#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7) - -#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1) -#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2) -#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3) -#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4) -#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5) -#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7) - -#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1) -#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2) -#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3) -#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4) -#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5) -#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7) - -#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1) -#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2) -#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3) -#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4) -#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5) -#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7) - -#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1) -#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2) -#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3) -#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4) -#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5) -#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6) -#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7) - -#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1) -#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2) -#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3) -#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4) -#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5) -#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6) -#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7) - -#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1) -#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2) -#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3) -#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4) -#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5) -#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6) -#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7) - -#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1) -#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2) -#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3) -#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4) -#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5) -#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6) -#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7) - -#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1) -#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2) -#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3) -#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4) -#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5) -#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6) -#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7) - -#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1) -#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2) -#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7) - -#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1) -#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2) -#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7) - -#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1) -#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2) -#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3) -#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4) -#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7) - -#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1) -#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7) - -#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1) -#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2) -#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3) -#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4) -#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5) -#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6) -#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7) - -#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1) -#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7) - -#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1) -#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2) -#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3) -#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4) -#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5) -#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6) -#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7) - -#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1) -#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3) -#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4) -#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5) -#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6) -#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7) - -#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1) -#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3) -#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4) -#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5) -#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6) -#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7) - -#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1) -#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2) -#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3) -#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4) -#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5) -#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6) -#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7) - -#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1) -#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2) -#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3) -#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4) -#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5) -#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6) -#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7) - -#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1) -#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2) -#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3) -#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4) -#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5) -#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6) - -#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1) -#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2) -#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3) -#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4) -#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5) -#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6) - -#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1) -#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2) -#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3) -#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4) -#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5) - -#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1) -#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2) -#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3) -#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4) -#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5) - -#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1) -#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2) -#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3) -#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4) -#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) - -#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1) -#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2) -#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7) - -#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1) -#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2) -#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7) - -#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1) -#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2) -#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3) -#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4) -#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5) -#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6) -#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7) - -#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1) -#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2) -#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3) -#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4) -#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5) -#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6) -#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7) - -#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1) -#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2) -#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3) -#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4) -#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5) -#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6) -#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7) - -#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1) -#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2) -#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3) -#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4) -#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5) -#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6) -#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7) - -#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1) -#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2) - -#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1) -#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2) - -#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1) - -#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1) - -#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1) - -#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1) - -#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1) -#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2) - -#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1) - -#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1) -#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2) -#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3) - -#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1) -#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2) -#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3) - -#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1) -#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2) -#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3) - -#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1) -#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2) -#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3) - -#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1) -#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2) -#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3) - -#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1) -#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2) -#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3) - -#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1) -#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2) -#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3) - -#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1) -#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2) -#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3) - -#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1) - -#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1) - -#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1) -#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6) -#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7) - -#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1) -#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6) -#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7) - -#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1) - -#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1) - -#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1) - -#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1) - -#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1) -#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2) -#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7) - -#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1) -#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2) -#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7) - -#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1) -#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2) -#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4) -#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5) -#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7) - -#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1) -#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2) -#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4) -#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5) -#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7) - -#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1) -#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2) -#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3) -#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4) -#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5) -#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7) - -#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1) -#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2) -#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4) -#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5) -#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7) - -#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1) -#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2) -#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7) - -#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1) -#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2) -#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5) -#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7) - -#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1) -#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2) -#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5) -#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7) - -#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1) -#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2) -#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5) -#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7) - -#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1) -#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5) -#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7) - -#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1) -#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5) -#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7) - -#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1) -#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5) -#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7) - -#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1) -#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5) -#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7) - -#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1) -#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5) -#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7) - -#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6) - -#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6) - -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6) - -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6) - -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6) - -#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1) -#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2) -#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3) -#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5) - -#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1) -#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2) -#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3) - -#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7) - -#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7) - -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7) - -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7) - -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7) - -#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1) -#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2) -#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3) - -#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1) -#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2) - -#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1) -#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2) - -#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1) -#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2) - -#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1) -#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2) - -#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1) -#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2) - -#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1) -#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2) - -#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1) -#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2) - -#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1) -#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2) - -#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1) -#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2) - -#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1) -#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2) - -#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1) -#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2) - -#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1) - -#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1) -#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2) -#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7) - -#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1) -#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2) -#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7) - -#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1) -#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2) -#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7) - -#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1) -#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2) -#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7) - -#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1) -#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2) -#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7) - -#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1) -#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2) -#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3) -#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4) -#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5) - -#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1) -#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2) -#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3) -#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4) -#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5) - -#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1) -#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) -#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3) -#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4) -#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5) - -#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1) -#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2) -#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3) -#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4) -#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5) - -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7) - -#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1) -#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2) -#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3) -#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4) -#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5) -#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6) -#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7) - -#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1) -#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2) -#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3) -#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4) -#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5) -#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6) -#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7) - -#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1) -#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2) -#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7) - -#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1) -#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2) -#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7) - -#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1) -#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2) -#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7) - -#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1) -#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2) -#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7) - -#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1) -#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2) -#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7) - -#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1) -#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2) -#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7) - -#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1) -#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2) -#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7) - -#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1) -#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2) -#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7) - -#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1) -#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2) -#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7) - -#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1) -#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2) - -#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1) -#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2) - -#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1) -#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2) -#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3) - -#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1) -#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2) -#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3) - -#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1) -#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2) -#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3) - -#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1) -#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2) -#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3) - -#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1) -#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2) -#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3) -#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7) - -#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1) -#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7) - -#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1) -#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7) - -#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1) -#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7) - -#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1) - -#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1) - -#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1) - -#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1) - -#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1) - -#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1) - -#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1) - -#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1) - -#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1) - -#endif /* __MT8365_PINFUNC_H */ diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt-bindings/power/mediatek,mt8365-power.h deleted file mode 100644 index e6cfd0ec7871..000000000000 --- a/include/dt-bindings/power/mediatek,mt8365-power.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2022 MediaTek Inc. - */ - -#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H -#define _DT_BINDINGS_POWER_MT8365_POWER_H - -#define MT8365_POWER_DOMAIN_MM 0 -#define MT8365_POWER_DOMAIN_CONN 1 -#define MT8365_POWER_DOMAIN_MFG 2 -#define MT8365_POWER_DOMAIN_AUDIO 3 -#define MT8365_POWER_DOMAIN_CAM 4 -#define MT8365_POWER_DOMAIN_DSP 5 -#define MT8365_POWER_DOMAIN_VDEC 6 -#define MT8365_POWER_DOMAIN_VENC 7 -#define MT8365_POWER_DOMAIN_APU 8 - -#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h deleted file mode 100644 index 8e4341f04074..000000000000 --- a/include/dt-bindings/reset/mt7621-reset.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 MediaTek Inc. All rights reserved. - * - * Author: Weijie Gao weijie.gao@mediatek.com - */ - -#ifndef _DT_BINDINGS_MT7621_RESET_H_ -#define _DT_BINDINGS_MT7621_RESET_H_ - -#define RST_PPE 31 -#define RST_SDXC 30 -#define RST_CRYPTO 29 -#define RST_AUX_STCK 28 -#define RST_PCIE2 26 -#define RST_PCIE1 25 -#define RST_PCIE0 24 -#define RST_GMAC 23 -#define RST_UART3 21 -#define RST_UART2 20 -#define RST_UART1 19 -#define RST_SPI 18 -#define RST_I2S 17 -#define RST_I2C 16 -#define RST_NFI 15 -#define RST_GDMA 14 -#define RST_PIO 13 -#define RST_PCM 11 -#define RST_MC 10 -#define RST_INTC 9 -#define RST_TIMER 8 -#define RST_SPDIFTX 7 -#define RST_FE 6 -#define RST_HSDMA 5 -#define RST_MCM 2 -#define RST_SYS 0 - -#endif /* _DT_BINDINGS_MT7621_RESET_H_ */

Drop in favour of dts/upstream

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/hi3660-clock.h | 214 ------------------------------- include/dt-bindings/clock/hi6220-clock.h | 173 ------------------------- include/dt-bindings/pinctrl/hisi.h | 74 ----------- 3 files changed, 461 deletions(-)

diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h deleted file mode 100644 index e1374e180943..000000000000 --- a/include/dt-bindings/clock/hi3660-clock.h +++ /dev/null @@ -1,214 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016-2017 Linaro Ltd. - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - */ - -#ifndef __DTS_HI3660_CLOCK_H -#define __DTS_HI3660_CLOCK_H - -/* fixed rate clocks */ -#define HI3660_CLKIN_SYS 0 -#define HI3660_CLKIN_REF 1 -#define HI3660_CLK_FLL_SRC 2 -#define HI3660_CLK_PPLL0 3 -#define HI3660_CLK_PPLL1 4 -#define HI3660_CLK_PPLL2 5 -#define HI3660_CLK_PPLL3 6 -#define HI3660_CLK_SCPLL 7 -#define HI3660_PCLK 8 -#define HI3660_CLK_UART0_DBG 9 -#define HI3660_CLK_UART6 10 -#define HI3660_OSC32K 11 -#define HI3660_OSC19M 12 -#define HI3660_CLK_480M 13 -#define HI3660_CLK_INV 14 - -/* clk in crgctrl */ -#define HI3660_FACTOR_UART3 15 -#define HI3660_CLK_FACTOR_MMC 16 -#define HI3660_CLK_GATE_I2C0 17 -#define HI3660_CLK_GATE_I2C1 18 -#define HI3660_CLK_GATE_I2C2 19 -#define HI3660_CLK_GATE_I2C6 20 -#define HI3660_CLK_DIV_SYSBUS 21 -#define HI3660_CLK_DIV_320M 22 -#define HI3660_CLK_DIV_A53 23 -#define HI3660_CLK_GATE_SPI0 24 -#define HI3660_CLK_GATE_SPI2 25 -#define HI3660_PCIEPHY_REF 26 -#define HI3660_CLK_ABB_USB 27 -#define HI3660_HCLK_GATE_SDIO0 28 -#define HI3660_HCLK_GATE_SD 29 -#define HI3660_CLK_GATE_AOMM 30 -#define HI3660_PCLK_GPIO0 31 -#define HI3660_PCLK_GPIO1 32 -#define HI3660_PCLK_GPIO2 33 -#define HI3660_PCLK_GPIO3 34 -#define HI3660_PCLK_GPIO4 35 -#define HI3660_PCLK_GPIO5 36 -#define HI3660_PCLK_GPIO6 37 -#define HI3660_PCLK_GPIO7 38 -#define HI3660_PCLK_GPIO8 39 -#define HI3660_PCLK_GPIO9 40 -#define HI3660_PCLK_GPIO10 41 -#define HI3660_PCLK_GPIO11 42 -#define HI3660_PCLK_GPIO12 43 -#define HI3660_PCLK_GPIO13 44 -#define HI3660_PCLK_GPIO14 45 -#define HI3660_PCLK_GPIO15 46 -#define HI3660_PCLK_GPIO16 47 -#define HI3660_PCLK_GPIO17 48 -#define HI3660_PCLK_GPIO18 49 -#define HI3660_PCLK_GPIO19 50 -#define HI3660_PCLK_GPIO20 51 -#define HI3660_PCLK_GPIO21 52 -#define HI3660_CLK_GATE_SPI3 53 -#define HI3660_CLK_GATE_I2C7 54 -#define HI3660_CLK_GATE_I2C3 55 -#define HI3660_CLK_GATE_SPI1 56 -#define HI3660_CLK_GATE_UART1 57 -#define HI3660_CLK_GATE_UART2 58 -#define HI3660_CLK_GATE_UART4 59 -#define HI3660_CLK_GATE_UART5 60 -#define HI3660_CLK_GATE_I2C4 61 -#define HI3660_CLK_GATE_DMAC 62 -#define HI3660_PCLK_GATE_DSS 63 -#define HI3660_ACLK_GATE_DSS 64 -#define HI3660_CLK_GATE_LDI1 65 -#define HI3660_CLK_GATE_LDI0 66 -#define HI3660_CLK_GATE_VIVOBUS 67 -#define HI3660_CLK_GATE_EDC0 68 -#define HI3660_CLK_GATE_TXDPHY0_CFG 69 -#define HI3660_CLK_GATE_TXDPHY0_REF 70 -#define HI3660_CLK_GATE_TXDPHY1_CFG 71 -#define HI3660_CLK_GATE_TXDPHY1_REF 72 -#define HI3660_ACLK_GATE_USB3OTG 73 -#define HI3660_CLK_GATE_SPI4 74 -#define HI3660_CLK_GATE_SD 75 -#define HI3660_CLK_GATE_SDIO0 76 -#define HI3660_CLK_GATE_UFS_SUBSYS 77 -#define HI3660_PCLK_GATE_DSI0 78 -#define HI3660_PCLK_GATE_DSI1 79 -#define HI3660_ACLK_GATE_PCIE 80 -#define HI3660_PCLK_GATE_PCIE_SYS 81 -#define HI3660_CLK_GATE_PCIEAUX 82 -#define HI3660_PCLK_GATE_PCIE_PHY 83 -#define HI3660_CLK_ANDGT_LDI0 84 -#define HI3660_CLK_ANDGT_LDI1 85 -#define HI3660_CLK_ANDGT_EDC0 86 -#define HI3660_CLK_GATE_UFSPHY_GT 87 -#define HI3660_CLK_ANDGT_MMC 88 -#define HI3660_CLK_ANDGT_SD 89 -#define HI3660_CLK_A53HPM_ANDGT 90 -#define HI3660_CLK_ANDGT_SDIO 91 -#define HI3660_CLK_ANDGT_UART0 92 -#define HI3660_CLK_ANDGT_UART1 93 -#define HI3660_CLK_ANDGT_UARTH 94 -#define HI3660_CLK_ANDGT_SPI 95 -#define HI3660_CLK_VIVOBUS_ANDGT 96 -#define HI3660_CLK_AOMM_ANDGT 97 -#define HI3660_CLK_320M_PLL_GT 98 -#define HI3660_AUTODIV_EMMC0BUS 99 -#define HI3660_AUTODIV_SYSBUS 100 -#define HI3660_CLK_GATE_UFSPHY_CFG 101 -#define HI3660_CLK_GATE_UFSIO_REF 102 -#define HI3660_CLK_MUX_SYSBUS 103 -#define HI3660_CLK_MUX_UART0 104 -#define HI3660_CLK_MUX_UART1 105 -#define HI3660_CLK_MUX_UARTH 106 -#define HI3660_CLK_MUX_SPI 107 -#define HI3660_CLK_MUX_I2C 108 -#define HI3660_CLK_MUX_MMC_PLL 109 -#define HI3660_CLK_MUX_LDI1 110 -#define HI3660_CLK_MUX_LDI0 111 -#define HI3660_CLK_MUX_SD_PLL 112 -#define HI3660_CLK_MUX_SD_SYS 113 -#define HI3660_CLK_MUX_EDC0 114 -#define HI3660_CLK_MUX_SDIO_SYS 115 -#define HI3660_CLK_MUX_SDIO_PLL 116 -#define HI3660_CLK_MUX_VIVOBUS 117 -#define HI3660_CLK_MUX_A53HPM 118 -#define HI3660_CLK_MUX_320M 119 -#define HI3660_CLK_MUX_IOPERI 120 -#define HI3660_CLK_DIV_UART0 121 -#define HI3660_CLK_DIV_UART1 122 -#define HI3660_CLK_DIV_UARTH 123 -#define HI3660_CLK_DIV_MMC 124 -#define HI3660_CLK_DIV_SD 125 -#define HI3660_CLK_DIV_EDC0 126 -#define HI3660_CLK_DIV_LDI0 127 -#define HI3660_CLK_DIV_SDIO 128 -#define HI3660_CLK_DIV_LDI1 129 -#define HI3660_CLK_DIV_SPI 130 -#define HI3660_CLK_DIV_VIVOBUS 131 -#define HI3660_CLK_DIV_I2C 132 -#define HI3660_CLK_DIV_UFSPHY 133 -#define HI3660_CLK_DIV_CFGBUS 134 -#define HI3660_CLK_DIV_MMC0BUS 135 -#define HI3660_CLK_DIV_MMC1BUS 136 -#define HI3660_CLK_DIV_UFSPERI 137 -#define HI3660_CLK_DIV_AOMM 138 -#define HI3660_CLK_DIV_IOPERI 139 -#define HI3660_VENC_VOLT_HOLD 140 -#define HI3660_PERI_VOLT_HOLD 141 -#define HI3660_CLK_GATE_VENC 142 -#define HI3660_CLK_GATE_VDEC 143 -#define HI3660_CLK_ANDGT_VENC 144 -#define HI3660_CLK_ANDGT_VDEC 145 -#define HI3660_CLK_MUX_VENC 146 -#define HI3660_CLK_MUX_VDEC 147 -#define HI3660_CLK_DIV_VENC 148 -#define HI3660_CLK_DIV_VDEC 149 -#define HI3660_CLK_FAC_ISP_SNCLK 150 -#define HI3660_CLK_GATE_ISP_SNCLK0 151 -#define HI3660_CLK_GATE_ISP_SNCLK1 152 -#define HI3660_CLK_GATE_ISP_SNCLK2 153 -#define HI3660_CLK_ANGT_ISP_SNCLK 154 -#define HI3660_CLK_MUX_ISP_SNCLK 155 -#define HI3660_CLK_DIV_ISP_SNCLK 156 - -/* clk in pmuctrl */ -#define HI3660_GATE_ABB_192 0 - -/* clk in pctrl */ -#define HI3660_GATE_UFS_TCXO_EN 0 -#define HI3660_GATE_USB_TCXO_EN 1 - -/* clk in sctrl */ -#define HI3660_PCLK_AO_GPIO0 0 -#define HI3660_PCLK_AO_GPIO1 1 -#define HI3660_PCLK_AO_GPIO2 2 -#define HI3660_PCLK_AO_GPIO3 3 -#define HI3660_PCLK_AO_GPIO4 4 -#define HI3660_PCLK_AO_GPIO5 5 -#define HI3660_PCLK_AO_GPIO6 6 -#define HI3660_PCLK_GATE_MMBUF 7 -#define HI3660_CLK_GATE_DSS_AXI_MM 8 -#define HI3660_PCLK_MMBUF_ANDGT 9 -#define HI3660_CLK_MMBUF_PLL_ANDGT 10 -#define HI3660_CLK_FLL_MMBUF_ANDGT 11 -#define HI3660_CLK_SYS_MMBUF_ANDGT 12 -#define HI3660_CLK_GATE_PCIEPHY_GT 13 -#define HI3660_ACLK_MUX_MMBUF 14 -#define HI3660_CLK_SW_MMBUF 15 -#define HI3660_CLK_DIV_AOBUS 16 -#define HI3660_PCLK_DIV_MMBUF 17 -#define HI3660_ACLK_DIV_MMBUF 18 -#define HI3660_CLK_DIV_PCIEPHY 19 - -/* clk in iomcu */ -#define HI3660_CLK_I2C0_IOMCU 0 -#define HI3660_CLK_I2C1_IOMCU 1 -#define HI3660_CLK_I2C2_IOMCU 2 -#define HI3660_CLK_I2C6_IOMCU 3 -#define HI3660_CLK_IOMCU_PERI0 4 - -/* clk in stub clock */ -#define HI3660_CLK_STUB_CLUSTER0 0 -#define HI3660_CLK_STUB_CLUSTER1 1 -#define HI3660_CLK_STUB_GPU 2 -#define HI3660_CLK_STUB_DDR 3 -#define HI3660_CLK_STUB_NUM 4 - -#endif /* __DTS_HI3660_CLOCK_H */ diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h deleted file mode 100644 index 70ee3833a7a0..000000000000 --- a/include/dt-bindings/clock/hi6220-clock.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (c) 2015 Hisilicon Limited. - * - * Author: Bintian Wang bintian.wang@huawei.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __DT_BINDINGS_CLOCK_HI6220_H -#define __DT_BINDINGS_CLOCK_HI6220_H - -/* clk in Hi6220 AO (always on) controller */ -#define HI6220_NONE_CLOCK 0 - -/* fixed rate clocks */ -#define HI6220_REF32K 1 -#define HI6220_CLK_TCXO 2 -#define HI6220_MMC1_PAD 3 -#define HI6220_MMC2_PAD 4 -#define HI6220_MMC0_PAD 5 -#define HI6220_PLL_BBP 6 -#define HI6220_PLL_GPU 7 -#define HI6220_PLL1_DDR 8 -#define HI6220_PLL_SYS 9 -#define HI6220_PLL_SYS_MEDIA 10 -#define HI6220_DDR_SRC 11 -#define HI6220_PLL_MEDIA 12 -#define HI6220_PLL_DDR 13 - -/* fixed factor clocks */ -#define HI6220_300M 14 -#define HI6220_150M 15 -#define HI6220_PICOPHY_SRC 16 -#define HI6220_MMC0_SRC_SEL 17 -#define HI6220_MMC1_SRC_SEL 18 -#define HI6220_MMC2_SRC_SEL 19 -#define HI6220_VPU_CODEC 20 -#define HI6220_MMC0_SMP 21 -#define HI6220_MMC1_SMP 22 -#define HI6220_MMC2_SMP 23 - -/* gate clocks */ -#define HI6220_WDT0_PCLK 24 -#define HI6220_WDT1_PCLK 25 -#define HI6220_WDT2_PCLK 26 -#define HI6220_TIMER0_PCLK 27 -#define HI6220_TIMER1_PCLK 28 -#define HI6220_TIMER2_PCLK 29 -#define HI6220_TIMER3_PCLK 30 -#define HI6220_TIMER4_PCLK 31 -#define HI6220_TIMER5_PCLK 32 -#define HI6220_TIMER6_PCLK 33 -#define HI6220_TIMER7_PCLK 34 -#define HI6220_TIMER8_PCLK 35 -#define HI6220_UART0_PCLK 36 - -#define HI6220_AO_NR_CLKS 37 - -/* clk in Hi6220 systrl */ -/* gate clock */ -#define HI6220_MMC0_CLK 1 -#define HI6220_MMC0_CIUCLK 2 -#define HI6220_MMC1_CLK 3 -#define HI6220_MMC1_CIUCLK 4 -#define HI6220_MMC2_CLK 5 -#define HI6220_MMC2_CIUCLK 6 -#define HI6220_USBOTG_HCLK 7 -#define HI6220_CLK_PICOPHY 8 -#define HI6220_HIFI 9 -#define HI6220_DACODEC_PCLK 10 -#define HI6220_EDMAC_ACLK 11 -#define HI6220_CS_ATB 12 -#define HI6220_I2C0_CLK 13 -#define HI6220_I2C1_CLK 14 -#define HI6220_I2C2_CLK 15 -#define HI6220_I2C3_CLK 16 -#define HI6220_UART1_PCLK 17 -#define HI6220_UART2_PCLK 18 -#define HI6220_UART3_PCLK 19 -#define HI6220_UART4_PCLK 20 -#define HI6220_SPI_CLK 21 -#define HI6220_TSENSOR_CLK 22 -#define HI6220_MMU_CLK 23 -#define HI6220_HIFI_SEL 24 -#define HI6220_MMC0_SYSPLL 25 -#define HI6220_MMC1_SYSPLL 26 -#define HI6220_MMC2_SYSPLL 27 -#define HI6220_MMC0_SEL 28 -#define HI6220_MMC1_SEL 29 -#define HI6220_BBPPLL_SEL 30 -#define HI6220_MEDIA_PLL_SRC 31 -#define HI6220_MMC2_SEL 32 -#define HI6220_CS_ATB_SYSPLL 33 - -/* mux clocks */ -#define HI6220_MMC0_SRC 34 -#define HI6220_MMC0_SMP_IN 35 -#define HI6220_MMC1_SRC 36 -#define HI6220_MMC1_SMP_IN 37 -#define HI6220_MMC2_SRC 38 -#define HI6220_MMC2_SMP_IN 39 -#define HI6220_HIFI_SRC 40 -#define HI6220_UART1_SRC 41 -#define HI6220_UART2_SRC 42 -#define HI6220_UART3_SRC 43 -#define HI6220_UART4_SRC 44 -#define HI6220_MMC0_MUX0 45 -#define HI6220_MMC1_MUX0 46 -#define HI6220_MMC2_MUX0 47 -#define HI6220_MMC0_MUX1 48 -#define HI6220_MMC1_MUX1 49 -#define HI6220_MMC2_MUX1 50 - -/* divider clocks */ -#define HI6220_CLK_BUS 51 -#define HI6220_MMC0_DIV 52 -#define HI6220_MMC1_DIV 53 -#define HI6220_MMC2_DIV 54 -#define HI6220_HIFI_DIV 55 -#define HI6220_BBPPLL0_DIV 56 -#define HI6220_CS_DAPB 57 -#define HI6220_CS_ATB_DIV 58 - -#define HI6220_SYS_NR_CLKS 59 - -/* clk in Hi6220 media controller */ -/* gate clocks */ -#define HI6220_DSI_PCLK 1 -#define HI6220_G3D_PCLK 2 -#define HI6220_ACLK_CODEC_VPU 3 -#define HI6220_ISP_SCLK 4 -#define HI6220_ADE_CORE 5 -#define HI6220_MED_MMU 6 -#define HI6220_CFG_CSI4PHY 7 -#define HI6220_CFG_CSI2PHY 8 -#define HI6220_ISP_SCLK_GATE 9 -#define HI6220_ISP_SCLK_GATE1 10 -#define HI6220_ADE_CORE_GATE 11 -#define HI6220_CODEC_VPU_GATE 12 -#define HI6220_MED_SYSPLL 13 - -/* mux clocks */ -#define HI6220_1440_1200 14 -#define HI6220_1000_1200 15 -#define HI6220_1000_1440 16 - -/* divider clocks */ -#define HI6220_CODEC_JPEG 17 -#define HI6220_ISP_SCLK_SRC 18 -#define HI6220_ISP_SCLK1 19 -#define HI6220_ADE_CORE_SRC 20 -#define HI6220_ADE_PIX_SRC 21 -#define HI6220_G3D_CLK 22 -#define HI6220_CODEC_VPU_SRC 23 - -#define HI6220_MEDIA_NR_CLKS 24 - -/* clk in Hi6220 power controller */ -/* gate clocks */ -#define HI6220_PLL_GPU_GATE 1 -#define HI6220_PLL1_DDR_GATE 2 -#define HI6220_PLL_DDR_GATE 3 -#define HI6220_PLL_MEDIA_GATE 4 -#define HI6220_PLL0_BBP_GATE 5 - -/* divider clocks */ -#define HI6220_DDRC_SRC 6 -#define HI6220_DDRC_AXI1 7 - -#define HI6220_POWER_NR_CLKS 8 -#endif diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h deleted file mode 100644 index 0359bfdc9119..000000000000 --- a/include/dt-bindings/pinctrl/hisi.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This header provides constants for hisilicon pinctrl bindings. - * - * Copyright (c) 2015 Hisilicon Limited. - * Copyright (c) 2015 Linaro Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_PINCTRL_HISI_H -#define _DT_BINDINGS_PINCTRL_HISI_H - -/* iomg bit definition */ -#define MUX_M0 0 -#define MUX_M1 1 -#define MUX_M2 2 -#define MUX_M3 3 -#define MUX_M4 4 -#define MUX_M5 5 -#define MUX_M6 6 -#define MUX_M7 7 - -/* iocg bit definition */ -#define PULL_MASK (3) -#define PULL_DIS (0) -#define PULL_UP (1 << 0) -#define PULL_DOWN (1 << 1) - -/* drive strength definition */ -#define DRIVE_MASK (7 << 4) -#define DRIVE1_02MA (0 << 4) -#define DRIVE1_04MA (1 << 4) -#define DRIVE1_08MA (2 << 4) -#define DRIVE1_10MA (3 << 4) -#define DRIVE2_02MA (0 << 4) -#define DRIVE2_04MA (1 << 4) -#define DRIVE2_08MA (2 << 4) -#define DRIVE2_10MA (3 << 4) -#define DRIVE3_04MA (0 << 4) -#define DRIVE3_08MA (1 << 4) -#define DRIVE3_12MA (2 << 4) -#define DRIVE3_16MA (3 << 4) -#define DRIVE3_20MA (4 << 4) -#define DRIVE3_24MA (5 << 4) -#define DRIVE3_32MA (6 << 4) -#define DRIVE3_40MA (7 << 4) -#define DRIVE4_02MA (0 << 4) -#define DRIVE4_04MA (2 << 4) -#define DRIVE4_08MA (4 << 4) -#define DRIVE4_10MA (6 << 4) - -/* drive strength definition for hi3660 */ -#define DRIVE6_MASK (15 << 4) -#define DRIVE6_04MA (0 << 4) -#define DRIVE6_12MA (4 << 4) -#define DRIVE6_19MA (8 << 4) -#define DRIVE6_27MA (10 << 4) -#define DRIVE6_32MA (15 << 4) -#define DRIVE7_02MA (0 << 4) -#define DRIVE7_04MA (1 << 4) -#define DRIVE7_06MA (2 << 4) -#define DRIVE7_08MA (3 << 4) -#define DRIVE7_10MA (4 << 4) -#define DRIVE7_12MA (5 << 4) -#define DRIVE7_14MA (6 << 4) -#define DRIVE7_16MA (7 << 4) -#endif

Drop in favour of dts/upstream.

Clock headers for remaining smaller vendors that are compatible with dts/upstream.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/clock/actions,s700-cmu.h | 118 ------- include/dt-bindings/clock/actions,s900-cmu.h | 129 -------- include/dt-bindings/clock/agilex-clock.h | 71 ----- include/dt-bindings/clock/ast2600-clock.h | 62 ---- include/dt-bindings/clock/boston-clock.h | 12 - include/dt-bindings/clock/fsl,qoriq-clockgen.h | 15 - include/dt-bindings/clock/lpc32xx-clock.h | 58 ---- include/dt-bindings/clock/maxim,max77802.h | 22 -- include/dt-bindings/clock/nuvoton,npcm7xx-clock.h | 46 --- include/dt-bindings/clock/rv1108-cru.h | 356 ---------------------- include/dt-bindings/clock/starfive,jh7110-crg.h | 258 ---------------- include/dt-bindings/clock/versaclock.h | 13 - include/dt-bindings/clock/vf610-clock.h | 202 ------------ 13 files changed, 1362 deletions(-)

diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h deleted file mode 100644 index 3e1942996724..000000000000 --- a/include/dt-bindings/clock/actions,s700-cmu.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Device Tree binding constants for Actions Semi S700 Clock Management Unit - * - * Copyright (c) 2014 Actions Semi Inc. - * Author: David Liu liuwei@actions-semi.com - * - * Author: Pathiban Nallathambi pn@denx.de - * Author: Saravanan Sekar sravanhome@gmail.com - */ - -#ifndef __DT_BINDINGS_CLOCK_S700_H -#define __DT_BINDINGS_CLOCK_S700_H - -#define CLK_NONE 0 - -/* pll clocks */ -#define CLK_CORE_PLL 1 -#define CLK_DEV_PLL 2 -#define CLK_DDR_PLL 3 -#define CLK_NAND_PLL 4 -#define CLK_DISPLAY_PLL 5 -#define CLK_TVOUT_PLL 6 -#define CLK_CVBS_PLL 7 -#define CLK_AUDIO_PLL 8 -#define CLK_ETHERNET_PLL 9 - -/* system clock */ -#define CLK_CPU 10 -#define CLK_DEV 11 -#define CLK_AHB 12 -#define CLK_APB 13 -#define CLK_DMAC 14 -#define CLK_NOC0_CLK_MUX 15 -#define CLK_NOC1_CLK_MUX 16 -#define CLK_HP_CLK_MUX 17 -#define CLK_HP_CLK_DIV 18 -#define CLK_NOC1_CLK_DIV 19 -#define CLK_NOC0 20 -#define CLK_NOC1 21 -#define CLK_SENOR_SRC 22 - -/* peripheral device clock */ -#define CLK_GPIO 23 -#define CLK_TIMER 24 -#define CLK_DSI 25 -#define CLK_CSI 26 -#define CLK_SI 27 -#define CLK_DE 28 -#define CLK_HDE 29 -#define CLK_VDE 30 -#define CLK_VCE 31 -#define CLK_NAND 32 -#define CLK_SD0 33 -#define CLK_SD1 34 -#define CLK_SD2 35 - -#define CLK_UART0 36 -#define CLK_UART1 37 -#define CLK_UART2 38 -#define CLK_UART3 39 -#define CLK_UART4 40 -#define CLK_UART5 41 -#define CLK_UART6 42 - -#define CLK_PWM0 43 -#define CLK_PWM1 44 -#define CLK_PWM2 45 -#define CLK_PWM3 46 -#define CLK_PWM4 47 -#define CLK_PWM5 48 -#define CLK_GPU3D 49 - -#define CLK_I2C0 50 -#define CLK_I2C1 51 -#define CLK_I2C2 52 -#define CLK_I2C3 53 - -#define CLK_SPI0 54 -#define CLK_SPI1 55 -#define CLK_SPI2 56 -#define CLK_SPI3 57 - -#define CLK_USB3_480MPLL0 58 -#define CLK_USB3_480MPHY0 59 -#define CLK_USB3_5GPHY 60 -#define CLK_USB3_CCE 61 -#define CLK_USB3_MAC 62 - -#define CLK_LCD 63 -#define CLK_HDMI_AUDIO 64 -#define CLK_I2SRX 65 -#define CLK_I2STX 66 - -#define CLK_SENSOR0 67 -#define CLK_SENSOR1 68 - -#define CLK_HDMI_DEV 69 - -#define CLK_ETHERNET 70 -#define CLK_RMII_REF 71 - -#define CLK_USB2H0_PLLEN 72 -#define CLK_USB2H0_PHY 73 -#define CLK_USB2H0_CCE 74 -#define CLK_USB2H1_PLLEN 75 -#define CLK_USB2H1_PHY 76 -#define CLK_USB2H1_CCE 77 - -#define CLK_TVOUT 78 - -#define CLK_THERMAL_SENSOR 79 - -#define CLK_IRC_SWITCH 80 -#define CLK_PCM1 81 -#define CLK_NR_CLKS (CLK_PCM1 + 1) - -#endif /* __DT_BINDINGS_CLOCK_S700_H */ diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h deleted file mode 100644 index 7c1251565f43..000000000000 --- a/include/dt-bindings/clock/actions,s900-cmu.h +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Device Tree binding constants for Actions Semi S900 Clock Management Unit -// -// Copyright (c) 2014 Actions Semi Inc. -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H -#define __DT_BINDINGS_CLOCK_S900_CMU_H - -#define CLK_NONE 0 - -/* fixed rate clocks */ -#define CLK_LOSC 1 -#define CLK_HOSC 2 - -/* pll clocks */ -#define CLK_CORE_PLL 3 -#define CLK_DEV_PLL 4 -#define CLK_DDR_PLL 5 -#define CLK_NAND_PLL 6 -#define CLK_DISPLAY_PLL 7 -#define CLK_DSI_PLL 8 -#define CLK_ASSIST_PLL 9 -#define CLK_AUDIO_PLL 10 - -/* system clock */ -#define CLK_CPU 15 -#define CLK_DEV 16 -#define CLK_NOC 17 -#define CLK_NOC_MUX 18 -#define CLK_NOC_DIV 19 -#define CLK_AHB 20 -#define CLK_APB 21 -#define CLK_DMAC 22 - -/* peripheral device clock */ -#define CLK_GPIO 23 - -#define CLK_BISP 24 -#define CLK_CSI0 25 -#define CLK_CSI1 26 - -#define CLK_DE0 27 -#define CLK_DE1 28 -#define CLK_DE2 29 -#define CLK_DE3 30 -#define CLK_DSI 32 - -#define CLK_GPU 33 -#define CLK_GPU_CORE 34 -#define CLK_GPU_MEM 35 -#define CLK_GPU_SYS 36 - -#define CLK_HDE 37 -#define CLK_I2C0 38 -#define CLK_I2C1 39 -#define CLK_I2C2 40 -#define CLK_I2C3 41 -#define CLK_I2C4 42 -#define CLK_I2C5 43 -#define CLK_I2SRX 44 -#define CLK_I2STX 45 -#define CLK_IMX 46 -#define CLK_LCD 47 -#define CLK_NAND0 48 -#define CLK_NAND1 49 -#define CLK_PWM0 50 -#define CLK_PWM1 51 -#define CLK_PWM2 52 -#define CLK_PWM3 53 -#define CLK_PWM4 54 -#define CLK_PWM5 55 -#define CLK_SD0 56 -#define CLK_SD1 57 -#define CLK_SD2 58 -#define CLK_SD3 59 -#define CLK_SENSOR 60 -#define CLK_SPEED_SENSOR 61 -#define CLK_SPI0 62 -#define CLK_SPI1 63 -#define CLK_SPI2 64 -#define CLK_SPI3 65 -#define CLK_THERMAL_SENSOR 66 -#define CLK_UART0 67 -#define CLK_UART1 68 -#define CLK_UART2 69 -#define CLK_UART3 70 -#define CLK_UART4 71 -#define CLK_UART5 72 -#define CLK_UART6 73 -#define CLK_VCE 74 -#define CLK_VDE 75 - -#define CLK_USB3_480MPLL0 76 -#define CLK_USB3_480MPHY0 77 -#define CLK_USB3_5GPHY 78 -#define CLK_USB3_CCE 79 -#define CLK_USB3_MAC 80 - -#define CLK_TIMER 83 - -#define CLK_HDMI_AUDIO 84 - -#define CLK_24M 85 - -#define CLK_EDP 86 - -#define CLK_24M_EDP 87 -#define CLK_EDP_PLL 88 -#define CLK_EDP_LINK 89 - -#define CLK_USB2H0_PLLEN 90 -#define CLK_USB2H0_PHY 91 -#define CLK_USB2H0_CCE 92 -#define CLK_USB2H1_PLLEN 93 -#define CLK_USB2H1_PHY 94 -#define CLK_USB2H1_CCE 95 - -#define CLK_DDR0 96 -#define CLK_DDR1 97 -#define CLK_DMM 98 - -#define CLK_ETH_MAC 99 -#define CLK_RMII_REF 100 - -#define CLK_NR_CLKS (CLK_RMII_REF + 1) - -#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */ diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h deleted file mode 100644 index f751aad4dafc..000000000000 --- a/include/dt-bindings/clock/agilex-clock.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019, Intel Corporation - */ - -#ifndef __AGILEX_CLOCK_H -#define __AGILEX_CLOCK_H - -/* fixed rate clocks */ -#define AGILEX_OSC1 0 -#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 -#define AGILEX_CB_INTOSC_LS_CLK 2 -#define AGILEX_L4_SYS_FREE_CLK 3 -#define AGILEX_F2S_FREE_CLK 4 - -/* PLL clocks */ -#define AGILEX_MAIN_PLL_CLK 5 -#define AGILEX_MAIN_PLL_C0_CLK 6 -#define AGILEX_MAIN_PLL_C1_CLK 7 -#define AGILEX_MAIN_PLL_C2_CLK 8 -#define AGILEX_MAIN_PLL_C3_CLK 9 -#define AGILEX_PERIPH_PLL_CLK 10 -#define AGILEX_PERIPH_PLL_C0_CLK 11 -#define AGILEX_PERIPH_PLL_C1_CLK 12 -#define AGILEX_PERIPH_PLL_C2_CLK 13 -#define AGILEX_PERIPH_PLL_C3_CLK 14 -#define AGILEX_MPU_FREE_CLK 15 -#define AGILEX_MPU_CCU_CLK 16 -#define AGILEX_BOOT_CLK 17 - -/* fixed factor clocks */ -#define AGILEX_L3_MAIN_FREE_CLK 18 -#define AGILEX_NOC_FREE_CLK 19 -#define AGILEX_S2F_USR0_CLK 20 -#define AGILEX_NOC_CLK 21 -#define AGILEX_EMAC_A_FREE_CLK 22 -#define AGILEX_EMAC_B_FREE_CLK 23 -#define AGILEX_EMAC_PTP_FREE_CLK 24 -#define AGILEX_GPIO_DB_FREE_CLK 25 -#define AGILEX_SDMMC_FREE_CLK 26 -#define AGILEX_S2F_USER0_FREE_CLK 27 -#define AGILEX_S2F_USER1_FREE_CLK 28 -#define AGILEX_PSI_REF_FREE_CLK 29 - -/* Gate clocks */ -#define AGILEX_MPU_CLK 30 -#define AGILEX_MPU_PERIPH_CLK 31 -#define AGILEX_L4_MAIN_CLK 32 -#define AGILEX_L4_MP_CLK 33 -#define AGILEX_L4_SP_CLK 34 -#define AGILEX_CS_AT_CLK 35 -#define AGILEX_CS_TRACE_CLK 36 -#define AGILEX_CS_PDBG_CLK 37 -#define AGILEX_CS_TIMER_CLK 38 -#define AGILEX_S2F_USER0_CLK 39 -#define AGILEX_EMAC0_CLK 40 -#define AGILEX_EMAC1_CLK 41 -#define AGILEX_EMAC2_CLK 42 -#define AGILEX_EMAC_PTP_CLK 43 -#define AGILEX_GPIO_DB_CLK 44 -#define AGILEX_NAND_CLK 45 -#define AGILEX_PSI_REF_CLK 46 -#define AGILEX_S2F_USER1_CLK 47 -#define AGILEX_SDMMC_CLK 48 -#define AGILEX_SPI_M_CLK 49 -#define AGILEX_USB_CLK 50 -#define AGILEX_NAND_X_CLK 51 -#define AGILEX_NAND_ECC_CLK 52 -#define AGILEX_NUM_CLKS 53 - -#endif /* __AGILEX_CLOCK_H */ diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h deleted file mode 100644 index 36294a5140b0..000000000000 --- a/include/dt-bindings/clock/ast2600-clock.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) ASPEED Technology Inc. - */ - -#define ASPEED_CLK_GATE_ECLK 0 -#define ASPEED_CLK_GATE_GCLK 1 -#define ASPEED_CLK_GATE_MCLK 2 -#define ASPEED_CLK_GATE_VCLK 3 -#define ASPEED_CLK_GATE_BCLK 4 -#define ASPEED_CLK_GATE_DCLK 5 -#define ASPEED_CLK_GATE_LCLK 6 -#define ASPEED_CLK_GATE_YCLK 7 -#define ASPEED_CLK_GATE_LHCCLK 8 -#define ASPEED_CLK_GATE_REFCLK 9 -#define ASPEED_CLK_GATE_ESPICLK 10 -#define ASPEED_CLK_GATE_UART1CLK 11 -#define ASPEED_CLK_GATE_UART2CLK 12 -#define ASPEED_CLK_GATE_UART3CLK 13 -#define ASPEED_CLK_GATE_UART4CLK 14 -#define ASPEED_CLK_GATE_UART5CLK 15 -#define ASPEED_CLK_GATE_UART6CLK 16 -#define ASPEED_CLK_GATE_UART7CLK 17 -#define ASPEED_CLK_GATE_UART8CLK 18 -#define ASPEED_CLK_GATE_UART9CLK 19 -#define ASPEED_CLK_GATE_UART10CLK 20 -#define ASPEED_CLK_GATE_UART11CLK 21 -#define ASPEED_CLK_GATE_UART12CLK 22 -#define ASPEED_CLK_GATE_UART13CLK 23 -#define ASPEED_CLK_GATE_MAC1CLK 24 -#define ASPEED_CLK_GATE_MAC2CLK 25 -#define ASPEED_CLK_GATE_MAC3CLK 26 -#define ASPEED_CLK_GATE_MAC4CLK 27 -#define ASPEED_CLK_GATE_RSACLK 28 -#define ASPEED_CLK_GATE_SDCLK 29 -#define ASPEED_CLK_GATE_SDEXTCLK 30 -#define ASPEED_CLK_GATE_EMMCCLK 31 -#define ASPEED_CLK_GATE_EMMCEXTCLK 32 -#define ASPEED_CLK_GATE_USBUHCICLK 33 -#define ASPEED_CLK_GATE_USBPORT1CLK 34 -#define ASPEED_CLK_GATE_USBPORT2CLK 35 -#define ASPEED_CLK_GATE_FSICLK 36 - -#define ASPEED_CLK_APLL 37 -#define ASPEED_CLK_EPLL 38 -#define ASPEED_CLK_DPLL 39 -#define ASPEED_CLK_HPLL 40 -#define ASPEED_CLK_AHB 41 -#define ASPEED_CLK_APB1 42 -#define ASPEED_CLK_APB2 43 -#define ASPEED_CLK_UART 44 -#define ASPEED_CLK_SDIO 45 -#define ASPEED_CLK_ECLK 46 -#define ASPEED_CLK_ECLK_MUX 47 -#define ASPEED_CLK_LHCLK 48 -#define ASPEED_CLK_MAC 49 -#define ASPEED_CLK_BCLK 50 -#define ASPEED_CLK_MPLL 51 -#define ASPEED_CLK_24M 52 -#define ASPEED_CLK_EMMC 53 -#define ASPEED_CLK_UARTX 54 -#define ASPEED_CLK_HUARTX 55 diff --git a/include/dt-bindings/clock/boston-clock.h b/include/dt-bindings/clock/boston-clock.h deleted file mode 100644 index 0b3906247c8b..000000000000 --- a/include/dt-bindings/clock/boston-clock.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Imagination Technologies - */ - -#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ -#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ - -#define BOSTON_CLK_SYS 0 -#define BOSTON_CLK_CPU 1 - -#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */ diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h deleted file mode 100644 index ddec7d0bdc7f..000000000000 --- a/include/dt-bindings/clock/fsl,qoriq-clockgen.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H -#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H - -#define QORIQ_CLK_SYSCLK 0 -#define QORIQ_CLK_CMUX 1 -#define QORIQ_CLK_HWACCEL 2 -#define QORIQ_CLK_FMAN 3 -#define QORIQ_CLK_PLATFORM_PLL 4 -#define QORIQ_CLK_CORECLK 5 - -#define QORIQ_CLK_PLL_DIV(x) ((x) - 1) - -#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */ diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h deleted file mode 100644 index e624d3a52798..000000000000 --- a/include/dt-bindings/clock/lpc32xx-clock.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2015 Vladimir Zapolskiy vz@mleia.com - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H -#define __DT_BINDINGS_LPC32XX_CLOCK_H - -/* LPC32XX System Control Block clocks */ -#define LPC32XX_CLK_RTC 1 -#define LPC32XX_CLK_DMA 2 -#define LPC32XX_CLK_MLC 3 -#define LPC32XX_CLK_SLC 4 -#define LPC32XX_CLK_LCD 5 -#define LPC32XX_CLK_MAC 6 -#define LPC32XX_CLK_SD 7 -#define LPC32XX_CLK_DDRAM 8 -#define LPC32XX_CLK_SSP0 9 -#define LPC32XX_CLK_SSP1 10 -#define LPC32XX_CLK_UART3 11 -#define LPC32XX_CLK_UART4 12 -#define LPC32XX_CLK_UART5 13 -#define LPC32XX_CLK_UART6 14 -#define LPC32XX_CLK_IRDA 15 -#define LPC32XX_CLK_I2C1 16 -#define LPC32XX_CLK_I2C2 17 -#define LPC32XX_CLK_TIMER0 18 -#define LPC32XX_CLK_TIMER1 19 -#define LPC32XX_CLK_TIMER2 20 -#define LPC32XX_CLK_TIMER3 21 -#define LPC32XX_CLK_TIMER4 22 -#define LPC32XX_CLK_TIMER5 23 -#define LPC32XX_CLK_WDOG 24 -#define LPC32XX_CLK_I2S0 25 -#define LPC32XX_CLK_I2S1 26 -#define LPC32XX_CLK_SPI1 27 -#define LPC32XX_CLK_SPI2 28 -#define LPC32XX_CLK_MCPWM 29 -#define LPC32XX_CLK_HSTIMER 30 -#define LPC32XX_CLK_KEY 31 -#define LPC32XX_CLK_PWM1 32 -#define LPC32XX_CLK_PWM2 33 -#define LPC32XX_CLK_ADC 34 -#define LPC32XX_CLK_HCLK_PLL 35 -#define LPC32XX_CLK_PERIPH 36 - -/* LPC32XX USB clocks */ -#define LPC32XX_USB_CLK_I2C 1 -#define LPC32XX_USB_CLK_DEVICE 2 -#define LPC32XX_USB_CLK_HOST 3 - -#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */ diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h deleted file mode 100644 index 997312edcbb5..000000000000 --- a/include/dt-bindings/clock/maxim,max77802.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants clocks for the Maxim 77802 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H -#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H - -/* Fixed rate clocks. */ - -#define MAX77802_CLK_32K_AP 0 -#define MAX77802_CLK_32K_CP 1 - -/* Total number of clocks. */ -#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1) - -#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */ diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h deleted file mode 100644 index 65e6bc4eeea0..000000000000 --- a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Nuvoton NPCM7xx Clock Generator binding - * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk - * - * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com - * - */ - -#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H -#define __DT_BINDINGS_CLOCK_NPCM7XX_H - -#define NPCM7XX_CLK_CPU 0 -#define NPCM7XX_CLK_GFX_PIXEL 1 -#define NPCM7XX_CLK_MC 2 -#define NPCM7XX_CLK_ADC 3 -#define NPCM7XX_CLK_AHB 4 -#define NPCM7XX_CLK_TIMER 5 -#define NPCM7XX_CLK_UART 6 -#define NPCM7XX_CLK_MMC 7 -#define NPCM7XX_CLK_SPI3 8 -#define NPCM7XX_CLK_PCI 9 -#define NPCM7XX_CLK_AXI 10 -#define NPCM7XX_CLK_APB4 11 -#define NPCM7XX_CLK_APB3 12 -#define NPCM7XX_CLK_APB2 13 -#define NPCM7XX_CLK_APB1 14 -#define NPCM7XX_CLK_APB5 15 -#define NPCM7XX_CLK_CLKOUT 16 -#define NPCM7XX_CLK_GFX 17 -#define NPCM7XX_CLK_SU 18 -#define NPCM7XX_CLK_SU48 19 -#define NPCM7XX_CLK_SDHC 20 -#define NPCM7XX_CLK_SPI0 21 -#define NPCM7XX_CLK_SPIX 22 -#define NPCM7XX_CLK_REFCLK 23 -#define NPCM7XX_CLK_SYSBYPCK 24 -#define NPCM7XX_CLK_MCBYPCK 25 -#define NPCM7XX_CLK_PLL0 26 -#define NPCM7XX_CLK_PLL1 27 -#define NPCM7XX_CLK_PLL2 28 -#define NPCM7XX_CLK_PLL2DIV2 29 -#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_PLL2DIV2 + 1) - -#endif - diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h deleted file mode 100644 index 10ed9d140f4b..000000000000 --- a/include/dt-bindings/clock/rv1108-cru.h +++ /dev/null @@ -1,356 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. - * Author: Shawn Lin shawn.lin@rock-chips.com - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H - -/* pll id */ -#define PLL_APLL 0 -#define PLL_DPLL 1 -#define PLL_GPLL 2 -#define ARMCLK 3 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_UART0 72 -#define SCLK_UART1 73 -#define SCLK_UART2 74 -#define SCLK_I2S0 75 -#define SCLK_I2S1 76 -#define SCLK_I2S2 77 -#define SCLK_TIMER0 78 -#define SCLK_TIMER1 79 -#define SCLK_SFC 80 -#define SCLK_SDMMC_DRV 81 -#define SCLK_SDIO_DRV 82 -#define SCLK_EMMC_DRV 83 -#define SCLK_SDMMC_SAMPLE 84 -#define SCLK_SDIO_SAMPLE 85 -#define SCLK_EMMC_SAMPLE 86 -#define SCLK_VENC_CORE 87 -#define SCLK_HEVC_CORE 88 -#define SCLK_HEVC_CABAC 89 -#define SCLK_PWM0_PMU 90 -#define SCLK_I2C0_PMU 91 -#define SCLK_WIFI 92 -#define SCLK_CIFOUT 93 -#define SCLK_MIPI_CSI_OUT 94 -#define SCLK_CIF0 95 -#define SCLK_CIF1 96 -#define SCLK_CIF2 97 -#define SCLK_CIF3 98 -#define SCLK_DSP 99 -#define SCLK_DSP_IOP 100 -#define SCLK_DSP_EPP 101 -#define SCLK_DSP_EDP 102 -#define SCLK_DSP_EDAP 103 -#define SCLK_CVBS_HOST 104 -#define SCLK_HDMI_SFR 105 -#define SCLK_HDMI_CEC 106 -#define SCLK_CRYPTO 107 -#define SCLK_SPI 108 -#define SCLK_SARADC 109 -#define SCLK_TSADC 110 -#define SCLK_MAC_PRE 111 -#define SCLK_MAC 112 -#define SCLK_MAC_RX 113 -#define SCLK_MAC_REF 114 -#define SCLK_MAC_REFOUT 115 -#define SCLK_DSP_PFM 116 -#define SCLK_RGA 117 -#define SCLK_I2C1 118 -#define SCLK_I2C2 119 -#define SCLK_I2C3 120 -#define SCLK_PWM 121 -#define SCLK_ISP 122 -#define SCLK_USBPHY 123 -#define SCLK_I2S0_SRC 124 -#define SCLK_I2S1_SRC 125 -#define SCLK_I2S2_SRC 126 -#define SCLK_UART0_SRC 127 -#define SCLK_UART1_SRC 128 -#define SCLK_UART2_SRC 129 -#define SCLK_MAC_TX 130 -#define SCLK_MACREF 131 -#define SCLK_MACREF_OUT 132 - -#define DCLK_VOP_SRC 185 -#define DCLK_HDMIPHY 186 -#define DCLK_VOP 187 - -/* aclk gates */ -#define ACLK_DMAC 192 -#define ACLK_PRE 193 -#define ACLK_CORE 194 -#define ACLK_ENMCORE 195 -#define ACLK_RKVENC 196 -#define ACLK_RKVDEC 197 -#define ACLK_VPU 198 -#define ACLK_CIF0 199 -#define ACLK_VIO0 200 -#define ACLK_VIO1 201 -#define ACLK_VOP 202 -#define ACLK_IEP 203 -#define ACLK_RGA 204 -#define ACLK_ISP 205 -#define ACLK_CIF1 206 -#define ACLK_CIF2 207 -#define ACLK_CIF3 208 -#define ACLK_PERI 209 -#define ACLK_GMAC 210 - -/* pclk gates */ -#define PCLK_GPIO1 256 -#define PCLK_GPIO2 257 -#define PCLK_GPIO3 258 -#define PCLK_GRF 259 -#define PCLK_I2C1 260 -#define PCLK_I2C2 261 -#define PCLK_I2C3 262 -#define PCLK_SPI 263 -#define PCLK_SFC 264 -#define PCLK_UART0 265 -#define PCLK_UART1 266 -#define PCLK_UART2 267 -#define PCLK_TSADC 268 -#define PCLK_PWM 269 -#define PCLK_TIMER 270 -#define PCLK_PERI 271 -#define PCLK_GPIO0_PMU 272 -#define PCLK_I2C0_PMU 273 -#define PCLK_PWM0_PMU 274 -#define PCLK_ISP 275 -#define PCLK_VIO 276 -#define PCLK_MIPI_DSI 277 -#define PCLK_HDMI_CTRL 278 -#define PCLK_SARADC 279 -#define PCLK_DSP_CFG 280 -#define PCLK_BUS 281 -#define PCLK_EFUSE0 282 -#define PCLK_EFUSE1 283 -#define PCLK_WDT 284 -#define PCLK_GMAC 285 - -/* hclk gates */ -#define HCLK_I2S0_8CH 320 -#define HCLK_I2S1_2CH 321 -#define HCLK_I2S2_2CH 322 -#define HCLK_NANDC 323 -#define HCLK_SDMMC 324 -#define HCLK_SDIO 325 -#define HCLK_EMMC 326 -#define HCLK_PERI 327 -#define HCLK_SFC 328 -#define HCLK_RKVENC 329 -#define HCLK_RKVDEC 330 -#define HCLK_CIF0 331 -#define HCLK_VIO 332 -#define HCLK_VOP 333 -#define HCLK_IEP 334 -#define HCLK_RGA 335 -#define HCLK_ISP 336 -#define HCLK_CRYPTO_MST 337 -#define HCLK_CRYPTO_SLV 338 -#define HCLK_HOST0 339 -#define HCLK_OTG 340 -#define HCLK_CIF1 341 -#define HCLK_CIF2 342 -#define HCLK_CIF3 343 -#define HCLK_BUS 344 -#define HCLK_VPU 345 - -#define CLK_NR_CLKS (HCLK_VPU + 1) - -/* reset id */ -#define SRST_CORE_PO_AD 0 -#define SRST_CORE_AD 1 -#define SRST_L2_AD 2 -#define SRST_CPU_NIU_AD 3 -#define SRST_CORE_PO 4 -#define SRST_CORE 5 -#define SRST_L2 6 -#define SRST_CORE_DBG 8 -#define PRST_DBG 9 -#define RST_DAP 10 -#define PRST_DBG_NIU 11 -#define ARST_STRC_SYS_AD 15 - -#define SRST_DDRPHY_CLKDIV 16 -#define SRST_DDRPHY 17 -#define PRST_DDRPHY 18 -#define PRST_HDMIPHY 19 -#define PRST_VDACPHY 20 -#define PRST_VADCPHY 21 -#define PRST_MIPI_CSI_PHY 22 -#define PRST_MIPI_DSI_PHY 23 -#define PRST_ACODEC 24 -#define ARST_BUS_NIU 25 -#define PRST_TOP_NIU 26 -#define ARST_INTMEM 27 -#define HRST_ROM 28 -#define ARST_DMAC 29 -#define SRST_MSCH_NIU 30 -#define PRST_MSCH_NIU 31 - -#define PRST_DDRUPCTL 32 -#define NRST_DDRUPCTL 33 -#define PRST_DDRMON 34 -#define HRST_I2S0_8CH 35 -#define MRST_I2S0_8CH 36 -#define HRST_I2S1_2CH 37 -#define MRST_IS21_2CH 38 -#define HRST_I2S2_2CH 39 -#define MRST_I2S2_2CH 40 -#define HRST_CRYPTO 41 -#define SRST_CRYPTO 42 -#define PRST_SPI 43 -#define SRST_SPI 44 -#define PRST_UART0 45 -#define PRST_UART1 46 -#define PRST_UART2 47 - -#define SRST_UART0 48 -#define SRST_UART1 49 -#define SRST_UART2 50 -#define PRST_I2C1 51 -#define PRST_I2C2 52 -#define PRST_I2C3 53 -#define SRST_I2C1 54 -#define SRST_I2C2 55 -#define SRST_I2C3 56 -#define PRST_PWM1 58 -#define SRST_PWM1 60 -#define PRST_WDT 61 -#define PRST_GPIO1 62 -#define PRST_GPIO2 63 - -#define PRST_GPIO3 64 -#define PRST_GRF 65 -#define PRST_EFUSE 66 -#define PRST_EFUSE512 67 -#define PRST_TIMER0 68 -#define SRST_TIMER0 69 -#define SRST_TIMER1 70 -#define PRST_TSADC 71 -#define SRST_TSADC 72 -#define PRST_SARADC 73 -#define SRST_SARADC 74 -#define HRST_SYSBUS 75 -#define PRST_USBGRF 76 - -#define ARST_PERIPH_NIU 80 -#define HRST_PERIPH_NIU 81 -#define PRST_PERIPH_NIU 82 -#define HRST_PERIPH 83 -#define HRST_SDMMC 84 -#define HRST_SDIO 85 -#define HRST_EMMC 86 -#define HRST_NANDC 87 -#define NRST_NANDC 88 -#define HRST_SFC 89 -#define SRST_SFC 90 -#define ARST_GMAC 91 -#define HRST_OTG 92 -#define SRST_OTG 93 -#define SRST_OTG_ADP 94 -#define HRST_HOST0 95 - -#define HRST_HOST0_AUX 96 -#define HRST_HOST0_ARB 97 -#define SRST_HOST0_EHCIPHY 98 -#define SRST_HOST0_UTMI 99 -#define SRST_USBPOR 100 -#define SRST_UTMI0 101 -#define SRST_UTMI1 102 - -#define ARST_VIO0_NIU 102 -#define ARST_VIO1_NIU 103 -#define HRST_VIO_NIU 104 -#define PRST_VIO_NIU 105 -#define ARST_VOP 106 -#define HRST_VOP 107 -#define DRST_VOP 108 -#define ARST_IEP 109 -#define HRST_IEP 110 -#define ARST_RGA 111 -#define HRST_RGA 112 -#define SRST_RGA 113 -#define PRST_CVBS 114 -#define PRST_HDMI 115 -#define SRST_HDMI 116 -#define PRST_MIPI_DSI 117 - -#define ARST_ISP_NIU 118 -#define HRST_ISP_NIU 119 -#define HRST_ISP 120 -#define SRST_ISP 121 -#define ARST_VIP0 122 -#define HRST_VIP0 123 -#define PRST_VIP0 124 -#define ARST_VIP1 125 -#define HRST_VIP1 126 -#define PRST_VIP1 127 -#define ARST_VIP2 128 -#define HRST_VIP2 129 -#define PRST_VIP2 120 -#define ARST_VIP3 121 -#define HRST_VIP3 122 -#define PRST_VIP4 123 - -#define PRST_CIF1TO4 124 -#define SRST_CVBS_CLK 125 -#define HRST_CVBS 126 - -#define ARST_VPU_NIU 140 -#define HRST_VPU_NIU 141 -#define ARST_VPU 142 -#define HRST_VPU 143 -#define ARST_RKVDEC_NIU 144 -#define HRST_RKVDEC_NIU 145 -#define ARST_RKVDEC 146 -#define HRST_RKVDEC 147 -#define SRST_RKVDEC_CABAC 148 -#define SRST_RKVDEC_CORE 149 -#define ARST_RKVENC_NIU 150 -#define HRST_RKVENC_NIU 151 -#define ARST_RKVENC 152 -#define HRST_RKVENC 153 -#define SRST_RKVENC_CORE 154 - -#define SRST_DSP_CORE 156 -#define SRST_DSP_SYS 157 -#define SRST_DSP_GLOBAL 158 -#define SRST_DSP_OECM 159 -#define PRST_DSP_IOP_NIU 160 -#define ARST_DSP_EPP_NIU 161 -#define ARST_DSP_EDP_NIU 162 -#define PRST_DSP_DBG_NIU 163 -#define PRST_DSP_CFG_NIU 164 -#define PRST_DSP_GRF 165 -#define PRST_DSP_MAILBOX 166 -#define PRST_DSP_INTC 167 -#define PRST_DSP_PFM_MON 169 -#define SRST_DSP_PFM_MON 170 -#define ARST_DSP_EDAP_NIU 171 - -#define SRST_PMU 172 -#define SRST_PMU_I2C0 173 -#define PRST_PMU_I2C0 174 -#define PRST_PMU_GPIO0 175 -#define PRST_PMU_INTMEM 176 -#define PRST_PMU_PWM0 177 -#define SRST_PMU_PWM0 178 -#define PRST_PMU_GRF 179 -#define SRST_PMU_NIU 180 -#define SRST_PMU_PVTM 181 -#define ARST_DSP_EDP_PERF 184 -#define ARST_DSP_EPP_PERF 185 - -#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h deleted file mode 100644 index b51e3829ff48..000000000000 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang yanhong.wang@starfivetech.com - */ - -#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ - -#define JH7110_SYSCLK_PLL0_OUT 0 -#define JH7110_SYSCLK_PLL1_OUT 1 -#define JH7110_SYSCLK_PLL2_OUT 2 -#define JH7110_PLLCLK_END 3 - -#define JH7110_SYSCLK_CPU_ROOT 0 -#define JH7110_SYSCLK_CPU_CORE 1 -#define JH7110_SYSCLK_CPU_BUS 2 -#define JH7110_SYSCLK_GPU_ROOT 3 -#define JH7110_SYSCLK_PERH_ROOT 4 -#define JH7110_SYSCLK_BUS_ROOT 5 -#define JH7110_SYSCLK_NOCSTG_BUS 6 -#define JH7110_SYSCLK_AXI_CFG0 7 -#define JH7110_SYSCLK_STG_AXIAHB 8 -#define JH7110_SYSCLK_AHB0 9 -#define JH7110_SYSCLK_AHB1 10 -#define JH7110_SYSCLK_APB_BUS 11 -#define JH7110_SYSCLK_APB0 12 -#define JH7110_SYSCLK_PLL0_DIV2 13 -#define JH7110_SYSCLK_PLL1_DIV2 14 -#define JH7110_SYSCLK_PLL2_DIV2 15 -#define JH7110_SYSCLK_AUDIO_ROOT 16 -#define JH7110_SYSCLK_MCLK_INNER 17 -#define JH7110_SYSCLK_MCLK 18 -#define JH7110_SYSCLK_MCLK_OUT 19 -#define JH7110_SYSCLK_ISP_2X 20 -#define JH7110_SYSCLK_ISP_AXI 21 -#define JH7110_SYSCLK_GCLK0 22 -#define JH7110_SYSCLK_GCLK1 23 -#define JH7110_SYSCLK_GCLK2 24 -#define JH7110_SYSCLK_CORE 25 -#define JH7110_SYSCLK_CORE1 26 -#define JH7110_SYSCLK_CORE2 27 -#define JH7110_SYSCLK_CORE3 28 -#define JH7110_SYSCLK_CORE4 29 -#define JH7110_SYSCLK_DEBUG 30 -#define JH7110_SYSCLK_RTC_TOGGLE 31 -#define JH7110_SYSCLK_TRACE0 32 -#define JH7110_SYSCLK_TRACE1 33 -#define JH7110_SYSCLK_TRACE2 34 -#define JH7110_SYSCLK_TRACE3 35 -#define JH7110_SYSCLK_TRACE4 36 -#define JH7110_SYSCLK_TRACE_COM 37 -#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 -#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 -#define JH7110_SYSCLK_OSC_DIV2 40 -#define JH7110_SYSCLK_PLL1_DIV4 41 -#define JH7110_SYSCLK_PLL1_DIV8 42 -#define JH7110_SYSCLK_DDR_BUS 43 -#define JH7110_SYSCLK_DDR_AXI 44 -#define JH7110_SYSCLK_GPU_CORE 45 -#define JH7110_SYSCLK_GPU_CORE_CLK 46 -#define JH7110_SYSCLK_GPU_SYS_CLK 47 -#define JH7110_SYSCLK_GPU_APB 48 -#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 -#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 -#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 -#define JH7110_SYSCLK_HIFI4_CORE 54 -#define JH7110_SYSCLK_HIFI4_AXI 55 -#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 -#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 -#define JH7110_SYSCLK_VOUT_SRC 58 -#define JH7110_SYSCLK_VOUT_AXI 59 -#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 -#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 -#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 -#define JH7110_SYSCLK_JPEGC_AXI 65 -#define JH7110_SYSCLK_CODAJ12_AXI 66 -#define JH7110_SYSCLK_CODAJ12_CORE 67 -#define JH7110_SYSCLK_CODAJ12_APB 68 -#define JH7110_SYSCLK_VDEC_AXI 69 -#define JH7110_SYSCLK_WAVE511_AXI 70 -#define JH7110_SYSCLK_WAVE511_BPU 71 -#define JH7110_SYSCLK_WAVE511_VCE 72 -#define JH7110_SYSCLK_WAVE511_APB 73 -#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 -#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 -#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 -#define JH7110_SYSCLK_VENC_AXI 77 -#define JH7110_SYSCLK_WAVE420L_AXI 78 -#define JH7110_SYSCLK_WAVE420L_BPU 79 -#define JH7110_SYSCLK_WAVE420L_VCE 80 -#define JH7110_SYSCLK_WAVE420L_APB 81 -#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 -#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 -#define JH7110_SYSCLK_AXIMEM2_AXI 86 -#define JH7110_SYSCLK_QSPI_AHB 87 -#define JH7110_SYSCLK_QSPI_APB 88 -#define JH7110_SYSCLK_QSPI_REF_SRC 89 -#define JH7110_SYSCLK_QSPI_REF 90 -#define JH7110_SYSCLK_SDIO0_AHB 91 -#define JH7110_SYSCLK_SDIO1_AHB 92 -#define JH7110_SYSCLK_SDIO0_SDCARD 93 -#define JH7110_SYSCLK_SDIO1_SDCARD 94 -#define JH7110_SYSCLK_USB_125M 95 -#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 -#define JH7110_SYSCLK_GMAC1_AHB 97 -#define JH7110_SYSCLK_GMAC1_AXI 98 -#define JH7110_SYSCLK_GMAC_SRC 99 -#define JH7110_SYSCLK_GMAC1_GTXCLK 100 -#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 -#define JH7110_SYSCLK_GMAC1_PTP 102 -#define JH7110_SYSCLK_GMAC1_RX 103 -#define JH7110_SYSCLK_GMAC1_RX_INV 104 -#define JH7110_SYSCLK_GMAC1_TX 105 -#define JH7110_SYSCLK_GMAC1_TX_INV 106 -#define JH7110_SYSCLK_GMAC1_GTXC 107 -#define JH7110_SYSCLK_GMAC0_GTXCLK 108 -#define JH7110_SYSCLK_GMAC0_PTP 109 -#define JH7110_SYSCLK_GMAC_PHY 110 -#define JH7110_SYSCLK_GMAC0_GTXC 111 -#define JH7110_SYSCLK_IOMUX_APB 112 -#define JH7110_SYSCLK_MAILBOX 113 -#define JH7110_SYSCLK_INT_CTRL_APB 114 -#define JH7110_SYSCLK_CAN0_APB 115 -#define JH7110_SYSCLK_CAN0_TIMER 116 -#define JH7110_SYSCLK_CAN0_CAN 117 -#define JH7110_SYSCLK_CAN1_APB 118 -#define JH7110_SYSCLK_CAN1_TIMER 119 -#define JH7110_SYSCLK_CAN1_CAN 120 -#define JH7110_SYSCLK_PWM_APB 121 -#define JH7110_SYSCLK_WDT_APB 122 -#define JH7110_SYSCLK_WDT_CORE 123 -#define JH7110_SYSCLK_TIMER_APB 124 -#define JH7110_SYSCLK_TIMER0 125 -#define JH7110_SYSCLK_TIMER1 126 -#define JH7110_SYSCLK_TIMER2 127 -#define JH7110_SYSCLK_TIMER3 128 -#define JH7110_SYSCLK_TEMP_APB 129 -#define JH7110_SYSCLK_TEMP_CORE 130 -#define JH7110_SYSCLK_SPI0_APB 131 -#define JH7110_SYSCLK_SPI1_APB 132 -#define JH7110_SYSCLK_SPI2_APB 133 -#define JH7110_SYSCLK_SPI3_APB 134 -#define JH7110_SYSCLK_SPI4_APB 135 -#define JH7110_SYSCLK_SPI5_APB 136 -#define JH7110_SYSCLK_SPI6_APB 137 -#define JH7110_SYSCLK_I2C0_APB 138 -#define JH7110_SYSCLK_I2C1_APB 139 -#define JH7110_SYSCLK_I2C2_APB 140 -#define JH7110_SYSCLK_I2C3_APB 141 -#define JH7110_SYSCLK_I2C4_APB 142 -#define JH7110_SYSCLK_I2C5_APB 143 -#define JH7110_SYSCLK_I2C6_APB 144 -#define JH7110_SYSCLK_UART0_APB 145 -#define JH7110_SYSCLK_UART0_CORE 146 -#define JH7110_SYSCLK_UART1_APB 147 -#define JH7110_SYSCLK_UART1_CORE 148 -#define JH7110_SYSCLK_UART2_APB 149 -#define JH7110_SYSCLK_UART2_CORE 150 -#define JH7110_SYSCLK_UART3_APB 151 -#define JH7110_SYSCLK_UART3_CORE 152 -#define JH7110_SYSCLK_UART4_APB 153 -#define JH7110_SYSCLK_UART4_CORE 154 -#define JH7110_SYSCLK_UART5_APB 155 -#define JH7110_SYSCLK_UART5_CORE 156 -#define JH7110_SYSCLK_PWMDAC_APB 157 -#define JH7110_SYSCLK_PWMDAC_CORE 158 -#define JH7110_SYSCLK_SPDIF_APB 159 -#define JH7110_SYSCLK_SPDIF_CORE 160 -#define JH7110_SYSCLK_I2STX0_APB 161 -#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 -#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 -#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 -#define JH7110_SYSCLK_I2STX0_BCLK 165 -#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 -#define JH7110_SYSCLK_I2STX0_LRCK 167 -#define JH7110_SYSCLK_I2STX1_APB 168 -#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 -#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 -#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 -#define JH7110_SYSCLK_I2STX1_BCLK 172 -#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 -#define JH7110_SYSCLK_I2STX1_LRCK 174 -#define JH7110_SYSCLK_I2SRX_APB 175 -#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 -#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 -#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 -#define JH7110_SYSCLK_I2SRX_BCLK 179 -#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 -#define JH7110_SYSCLK_I2SRX_LRCK 181 -#define JH7110_SYSCLK_PDM_DMIC 182 -#define JH7110_SYSCLK_PDM_APB 183 -#define JH7110_SYSCLK_TDM_AHB 184 -#define JH7110_SYSCLK_TDM_APB 185 -#define JH7110_SYSCLK_TDM_INTERNAL 186 -#define JH7110_SYSCLK_TDM_CLK_TDM 187 -#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 -#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 - -#define JH7110_SYSCLK_END 190 - -#define JH7110_AONCLK_OSC_DIV4 0 -#define JH7110_AONCLK_APB_FUNC 1 -#define JH7110_AONCLK_GMAC0_AHB 2 -#define JH7110_AONCLK_GMAC0_AXI 3 -#define JH7110_AONCLK_GMAC0_RMII_RTX 4 -#define JH7110_AONCLK_GMAC0_TX 5 -#define JH7110_AONCLK_GMAC0_TX_INV 6 -#define JH7110_AONCLK_GMAC0_RX 7 -#define JH7110_AONCLK_GMAC0_RX_INV 8 -#define JH7110_AONCLK_OTPC_APB 9 -#define JH7110_AONCLK_RTC_APB 10 -#define JH7110_AONCLK_RTC_INTERNAL 11 -#define JH7110_AONCLK_RTC_32K 12 -#define JH7110_AONCLK_RTC_CAL 13 - -#define JH7110_AONCLK_END 14 - -#define JH7110_STGCLK_HIFI4_CORE 0 -#define JH7110_STGCLK_USB_APB 1 -#define JH7110_STGCLK_USB_UTMI_APB 2 -#define JH7110_STGCLK_USB_AXI 3 -#define JH7110_STGCLK_USB_LPM 4 -#define JH7110_STGCLK_USB_STB 5 -#define JH7110_STGCLK_USB_APP_125 6 -#define JH7110_STGCLK_USB_REFCLK 7 -#define JH7110_STGCLK_PCIE0_AXI 8 -#define JH7110_STGCLK_PCIE0_APB 9 -#define JH7110_STGCLK_PCIE0_TL 10 -#define JH7110_STGCLK_PCIE1_AXI 11 -#define JH7110_STGCLK_PCIE1_APB 12 -#define JH7110_STGCLK_PCIE1_TL 13 -#define JH7110_STGCLK_PCIE01_MAIN 14 -#define JH7110_STGCLK_SEC_HCLK 15 -#define JH7110_STGCLK_SEC_MISCAHB 16 -#define JH7110_STGCLK_MTRX_GRP0_MAIN 17 -#define JH7110_STGCLK_MTRX_GRP0_BUS 18 -#define JH7110_STGCLK_MTRX_GRP0_STG 19 -#define JH7110_STGCLK_MTRX_GRP1_MAIN 20 -#define JH7110_STGCLK_MTRX_GRP1_BUS 21 -#define JH7110_STGCLK_MTRX_GRP1_STG 22 -#define JH7110_STGCLK_MTRX_GRP1_HIFI 23 -#define JH7110_STGCLK_E2_RTC 24 -#define JH7110_STGCLK_E2_CORE 25 -#define JH7110_STGCLK_E2_DBG 26 -#define JH7110_STGCLK_DMA1P_AXI 27 -#define JH7110_STGCLK_DMA1P_AHB 28 - -#define JH7110_STGCLK_END 29 - -#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/clock/versaclock.h b/include/dt-bindings/clock/versaclock.h deleted file mode 100644 index c6a6a0946564..000000000000 --- a/include/dt-bindings/clock/versaclock.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -/* This file defines field values used by the versaclock 6 family - * for defining output type - */ - -#define VC5_LVPECL 0 -#define VC5_CMOS 1 -#define VC5_HCSL33 2 -#define VC5_LVDS 3 -#define VC5_CMOS2 4 -#define VC5_CMOSD 5 -#define VC5_HCSL25 6 diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h deleted file mode 100644 index 373644e46747..000000000000 --- a/include/dt-bindings/clock/vf610-clock.h +++ /dev/null @@ -1,202 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_VF610_H -#define __DT_BINDINGS_CLOCK_VF610_H - -#define VF610_CLK_DUMMY 0 -#define VF610_CLK_SIRC_128K 1 -#define VF610_CLK_SIRC_32K 2 -#define VF610_CLK_FIRC 3 -#define VF610_CLK_SXOSC 4 -#define VF610_CLK_FXOSC 5 -#define VF610_CLK_FXOSC_HALF 6 -#define VF610_CLK_SLOW_CLK_SEL 7 -#define VF610_CLK_FASK_CLK_SEL 8 -#define VF610_CLK_AUDIO_EXT 9 -#define VF610_CLK_ENET_EXT 10 -#define VF610_CLK_PLL1_SYS 11 -#define VF610_CLK_PLL1_PFD1 12 -#define VF610_CLK_PLL1_PFD2 13 -#define VF610_CLK_PLL1_PFD3 14 -#define VF610_CLK_PLL1_PFD4 15 -#define VF610_CLK_PLL2_BUS 16 -#define VF610_CLK_PLL2_PFD1 17 -#define VF610_CLK_PLL2_PFD2 18 -#define VF610_CLK_PLL2_PFD3 19 -#define VF610_CLK_PLL2_PFD4 20 -#define VF610_CLK_PLL3_USB_OTG 21 -#define VF610_CLK_PLL3_PFD1 22 -#define VF610_CLK_PLL3_PFD2 23 -#define VF610_CLK_PLL3_PFD3 24 -#define VF610_CLK_PLL3_PFD4 25 -#define VF610_CLK_PLL4_AUDIO 26 -#define VF610_CLK_PLL5_ENET 27 -#define VF610_CLK_PLL6_VIDEO 28 -#define VF610_CLK_PLL3_MAIN_DIV 29 -#define VF610_CLK_PLL4_MAIN_DIV 30 -#define VF610_CLK_PLL6_MAIN_DIV 31 -#define VF610_CLK_PLL1_PFD_SEL 32 -#define VF610_CLK_PLL2_PFD_SEL 33 -#define VF610_CLK_SYS_SEL 34 -#define VF610_CLK_DDR_SEL 35 -#define VF610_CLK_SYS_BUS 36 -#define VF610_CLK_PLATFORM_BUS 37 -#define VF610_CLK_IPG_BUS 38 -#define VF610_CLK_UART0 39 -#define VF610_CLK_UART1 40 -#define VF610_CLK_UART2 41 -#define VF610_CLK_UART3 42 -#define VF610_CLK_UART4 43 -#define VF610_CLK_UART5 44 -#define VF610_CLK_PIT 45 -#define VF610_CLK_I2C0 46 -#define VF610_CLK_I2C1 47 -#define VF610_CLK_I2C2 48 -#define VF610_CLK_I2C3 49 -#define VF610_CLK_FTM0_EXT_SEL 50 -#define VF610_CLK_FTM0_FIX_SEL 51 -#define VF610_CLK_FTM0_EXT_FIX_EN 52 -#define VF610_CLK_FTM1_EXT_SEL 53 -#define VF610_CLK_FTM1_FIX_SEL 54 -#define VF610_CLK_FTM1_EXT_FIX_EN 55 -#define VF610_CLK_FTM2_EXT_SEL 56 -#define VF610_CLK_FTM2_FIX_SEL 57 -#define VF610_CLK_FTM2_EXT_FIX_EN 58 -#define VF610_CLK_FTM3_EXT_SEL 59 -#define VF610_CLK_FTM3_FIX_SEL 60 -#define VF610_CLK_FTM3_EXT_FIX_EN 61 -#define VF610_CLK_FTM0 62 -#define VF610_CLK_FTM1 63 -#define VF610_CLK_FTM2 64 -#define VF610_CLK_FTM3 65 -#define VF610_CLK_ENET_50M 66 -#define VF610_CLK_ENET_25M 67 -#define VF610_CLK_ENET_SEL 68 -#define VF610_CLK_ENET 69 -#define VF610_CLK_ENET_TS_SEL 70 -#define VF610_CLK_ENET_TS 71 -#define VF610_CLK_DSPI0 72 -#define VF610_CLK_DSPI1 73 -#define VF610_CLK_DSPI2 74 -#define VF610_CLK_DSPI3 75 -#define VF610_CLK_WDT 76 -#define VF610_CLK_ESDHC0_SEL 77 -#define VF610_CLK_ESDHC0_EN 78 -#define VF610_CLK_ESDHC0_DIV 79 -#define VF610_CLK_ESDHC0 80 -#define VF610_CLK_ESDHC1_SEL 81 -#define VF610_CLK_ESDHC1_EN 82 -#define VF610_CLK_ESDHC1_DIV 83 -#define VF610_CLK_ESDHC1 84 -#define VF610_CLK_DCU0_SEL 85 -#define VF610_CLK_DCU0_EN 86 -#define VF610_CLK_DCU0_DIV 87 -#define VF610_CLK_DCU0 88 -#define VF610_CLK_DCU1_SEL 89 -#define VF610_CLK_DCU1_EN 90 -#define VF610_CLK_DCU1_DIV 91 -#define VF610_CLK_DCU1 92 -#define VF610_CLK_ESAI_SEL 93 -#define VF610_CLK_ESAI_EN 94 -#define VF610_CLK_ESAI_DIV 95 -#define VF610_CLK_ESAI 96 -#define VF610_CLK_SAI0_SEL 97 -#define VF610_CLK_SAI0_EN 98 -#define VF610_CLK_SAI0_DIV 99 -#define VF610_CLK_SAI0 100 -#define VF610_CLK_SAI1_SEL 101 -#define VF610_CLK_SAI1_EN 102 -#define VF610_CLK_SAI1_DIV 103 -#define VF610_CLK_SAI1 104 -#define VF610_CLK_SAI2_SEL 105 -#define VF610_CLK_SAI2_EN 106 -#define VF610_CLK_SAI2_DIV 107 -#define VF610_CLK_SAI2 108 -#define VF610_CLK_SAI3_SEL 109 -#define VF610_CLK_SAI3_EN 110 -#define VF610_CLK_SAI3_DIV 111 -#define VF610_CLK_SAI3 112 -#define VF610_CLK_USBC0 113 -#define VF610_CLK_USBC1 114 -#define VF610_CLK_QSPI0_SEL 115 -#define VF610_CLK_QSPI0_EN 116 -#define VF610_CLK_QSPI0_X4_DIV 117 -#define VF610_CLK_QSPI0_X2_DIV 118 -#define VF610_CLK_QSPI0_X1_DIV 119 -#define VF610_CLK_QSPI1_SEL 120 -#define VF610_CLK_QSPI1_EN 121 -#define VF610_CLK_QSPI1_X4_DIV 122 -#define VF610_CLK_QSPI1_X2_DIV 123 -#define VF610_CLK_QSPI1_X1_DIV 124 -#define VF610_CLK_QSPI0 125 -#define VF610_CLK_QSPI1 126 -#define VF610_CLK_NFC_SEL 127 -#define VF610_CLK_NFC_EN 128 -#define VF610_CLK_NFC_PRE_DIV 129 -#define VF610_CLK_NFC_FRAC_DIV 130 -#define VF610_CLK_NFC_INV 131 -#define VF610_CLK_NFC 132 -#define VF610_CLK_VADC_SEL 133 -#define VF610_CLK_VADC_EN 134 -#define VF610_CLK_VADC_DIV 135 -#define VF610_CLK_VADC_DIV_HALF 136 -#define VF610_CLK_VADC 137 -#define VF610_CLK_ADC0 138 -#define VF610_CLK_ADC1 139 -#define VF610_CLK_DAC0 140 -#define VF610_CLK_DAC1 141 -#define VF610_CLK_FLEXCAN0 142 -#define VF610_CLK_FLEXCAN1 143 -#define VF610_CLK_ASRC 144 -#define VF610_CLK_GPU_SEL 145 -#define VF610_CLK_GPU_EN 146 -#define VF610_CLK_GPU2D 147 -#define VF610_CLK_ENET0 148 -#define VF610_CLK_ENET1 149 -#define VF610_CLK_DMAMUX0 150 -#define VF610_CLK_DMAMUX1 151 -#define VF610_CLK_DMAMUX2 152 -#define VF610_CLK_DMAMUX3 153 -#define VF610_CLK_FLEXCAN0_EN 154 -#define VF610_CLK_FLEXCAN1_EN 155 -#define VF610_CLK_PLL7_USB_HOST 156 -#define VF610_CLK_USBPHY0 157 -#define VF610_CLK_USBPHY1 158 -#define VF610_CLK_LVDS1_IN 159 -#define VF610_CLK_ANACLK1 160 -#define VF610_CLK_PLL1_BYPASS_SRC 161 -#define VF610_CLK_PLL2_BYPASS_SRC 162 -#define VF610_CLK_PLL3_BYPASS_SRC 163 -#define VF610_CLK_PLL4_BYPASS_SRC 164 -#define VF610_CLK_PLL5_BYPASS_SRC 165 -#define VF610_CLK_PLL6_BYPASS_SRC 166 -#define VF610_CLK_PLL7_BYPASS_SRC 167 -#define VF610_CLK_PLL1 168 -#define VF610_CLK_PLL2 169 -#define VF610_CLK_PLL3 170 -#define VF610_CLK_PLL4 171 -#define VF610_CLK_PLL5 172 -#define VF610_CLK_PLL6 173 -#define VF610_CLK_PLL7 174 -#define VF610_PLL1_BYPASS 175 -#define VF610_PLL2_BYPASS 176 -#define VF610_PLL3_BYPASS 177 -#define VF610_PLL4_BYPASS 178 -#define VF610_PLL5_BYPASS 179 -#define VF610_PLL6_BYPASS 180 -#define VF610_PLL7_BYPASS 181 -#define VF610_CLK_SNVS 182 -#define VF610_CLK_DAP 183 -#define VF610_CLK_OCOTP 184 -#define VF610_CLK_DDRMC 185 -#define VF610_CLK_WKPU 186 -#define VF610_CLK_TCON0 187 -#define VF610_CLK_TCON1 188 -#define VF610_CLK_CAAM 189 -#define VF610_CLK_CRC 190 -#define VF610_CLK_END 191 - -#endif /* __DT_BINDINGS_CLOCK_VF610_H */

Drop all the subsystem headers that are compatible with the headers in dts/upstream.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- include/dt-bindings/ata/ahci.h | 20 - include/dt-bindings/gpio/gpio.h | 42 -- include/dt-bindings/input/gpio-keys.h | 13 - include/dt-bindings/input/input.h | 17 - include/dt-bindings/input/linux-event-codes.h | 806 ------------------------- include/dt-bindings/interrupt-controller/irq.h | 19 - include/dt-bindings/leds/common.h | 106 ---- include/dt-bindings/mux/mux.h | 17 - include/dt-bindings/phy/phy.h | 26 - include/dt-bindings/pwm/pwm.h | 14 - include/dt-bindings/spmi/spmi.h | 10 - include/dt-bindings/thermal/thermal.h | 15 - include/dt-bindings/usb/pd.h | 88 --- 13 files changed, 1193 deletions(-)

diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h deleted file mode 100644 index b3f3b7cf9af8..000000000000 --- a/include/dt-bindings/ata/ahci.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * This header provides constants for most AHCI bindings. - */ - -#ifndef _DT_BINDINGS_ATA_AHCI_H -#define _DT_BINDINGS_ATA_AHCI_H - -/* Host Bus Adapter generic platform capabilities */ -#define HBA_SSS (1 << 27) -#define HBA_SMPS (1 << 28) - -/* Host Bus Adapter port-specific platform capabilities */ -#define HBA_PORT_HPCP (1 << 18) -#define HBA_PORT_MPSP (1 << 19) -#define HBA_PORT_CPD (1 << 20) -#define HBA_PORT_ESP (1 << 21) -#define HBA_PORT_FBSCP (1 << 22) - -#endif diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h deleted file mode 100644 index c029467e828b..000000000000 --- a/include/dt-bindings/gpio/gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for most GPIO bindings. - * - * Most GPIO bindings include a flags cell as part of the GPIO specifier. - * In most cases, the format of the flags cell uses the standard values - * defined in this header. - */ - -#ifndef _DT_BINDINGS_GPIO_GPIO_H -#define _DT_BINDINGS_GPIO_GPIO_H - -/* Bit 0 express polarity */ -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - -/* Bit 1 express single-endedness */ -#define GPIO_PUSH_PULL 0 -#define GPIO_SINGLE_ENDED 2 - -/* Bit 2 express Open drain or open source */ -#define GPIO_LINE_OPEN_SOURCE 0 -#define GPIO_LINE_OPEN_DRAIN 4 - -/* - * Open Drain/Collector is the combination of single-ended open drain interface. - * Open Source/Emitter is the combination of single-ended open source interface. - */ -#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) -#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) - -/* Bit 3 express GPIO suspend/resume and reset persistence */ -#define GPIO_PERSISTENT 0 -#define GPIO_TRANSITORY 8 - -/* Bit 4 express pull up */ -#define GPIO_PULL_UP 16 - -/* Bit 5 express pull down */ -#define GPIO_PULL_DOWN 32 - -#endif diff --git a/include/dt-bindings/input/gpio-keys.h b/include/dt-bindings/input/gpio-keys.h deleted file mode 100644 index 8962df79e753..000000000000 --- a/include/dt-bindings/input/gpio-keys.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for gpio keys bindings. - */ - -#ifndef _DT_BINDINGS_GPIO_KEYS_H -#define _DT_BINDINGS_GPIO_KEYS_H - -#define EV_ACT_ANY 0x00 /* asserted or deasserted */ -#define EV_ACT_ASSERTED 0x01 /* asserted */ -#define EV_ACT_DEASSERTED 0x02 /* deasserted */ - -#endif /* _DT_BINDINGS_GPIO_KEYS_H */ diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h deleted file mode 100644 index a21413324a3f..000000000000 --- a/include/dt-bindings/input/input.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This header provides constants for most input bindings. - * - * Most input bindings include key code, matrix key code format. - * In most cases, key code and matrix key code format uses - * the standard values/macro defined in this header. - */ - -#ifndef _DT_BINDINGS_INPUT_INPUT_H -#define _DT_BINDINGS_INPUT_INPUT_H - -#include "linux-event-codes.h" - -#define MATRIX_KEY(row, col, code) \ - ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) - -#endif /* _DT_BINDINGS_INPUT_INPUT_H */ diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h deleted file mode 100644 index 331458c0e710..000000000000 --- a/include/dt-bindings/input/linux-event-codes.h +++ /dev/null @@ -1,806 +0,0 @@ -/* - * Input event codes - * - * *** IMPORTANT *** - * This file is not only included from C-code but also from devicetree source - * files. As such this file MUST only contain comments and defines. - * - * Copyright (c) 1999-2002 Vojtech Pavlik - * Copyright (c) 2015 Hans de Goede hdegoede@redhat.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef _UAPI_INPUT_EVENT_CODES_H -#define _UAPI_INPUT_EVENT_CODES_H - -/* - * Device properties and quirks - */ - -#define INPUT_PROP_POINTER 0x00 /* needs a pointer */ -#define INPUT_PROP_DIRECT 0x01 /* direct input devices */ -#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ -#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ -#define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ -#define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ -#define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ - -#define INPUT_PROP_MAX 0x1f -#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) - -/* - * Event types - */ - -#define EV_SYN 0x00 -#define EV_KEY 0x01 -#define EV_REL 0x02 -#define EV_ABS 0x03 -#define EV_MSC 0x04 -#define EV_SW 0x05 -#define EV_LED 0x11 -#define EV_SND 0x12 -#define EV_REP 0x14 -#define EV_FF 0x15 -#define EV_PWR 0x16 -#define EV_FF_STATUS 0x17 -#define EV_MAX 0x1f -#define EV_CNT (EV_MAX+1) - -/* - * Synchronization events. - */ - -#define SYN_REPORT 0 -#define SYN_CONFIG 1 -#define SYN_MT_REPORT 2 -#define SYN_DROPPED 3 -#define SYN_MAX 0xf -#define SYN_CNT (SYN_MAX+1) - -/* - * Keys and buttons - * - * Most of the keys/buttons are modeled after USB HUT 1.12 - * (see http://www.usb.org/developers/hidpage). - * Abbreviations in the comments: - * AC - Application Control - * AL - Application Launch Button - * SC - System Control - */ - -#define KEY_RESERVED 0 -#define KEY_ESC 1 -#define KEY_1 2 -#define KEY_2 3 -#define KEY_3 4 -#define KEY_4 5 -#define KEY_5 6 -#define KEY_6 7 -#define KEY_7 8 -#define KEY_8 9 -#define KEY_9 10 -#define KEY_0 11 -#define KEY_MINUS 12 -#define KEY_EQUAL 13 -#define KEY_BACKSPACE 14 -#define KEY_TAB 15 -#define KEY_Q 16 -#define KEY_W 17 -#define KEY_E 18 -#define KEY_R 19 -#define KEY_T 20 -#define KEY_Y 21 -#define KEY_U 22 -#define KEY_I 23 -#define KEY_O 24 -#define KEY_P 25 -#define KEY_LEFTBRACE 26 -#define KEY_RIGHTBRACE 27 -#define KEY_ENTER 28 -#define KEY_LEFTCTRL 29 -#define KEY_A 30 -#define KEY_S 31 -#define KEY_D 32 -#define KEY_F 33 -#define KEY_G 34 -#define KEY_H 35 -#define KEY_J 36 -#define KEY_K 37 -#define KEY_L 38 -#define KEY_SEMICOLON 39 -#define KEY_APOSTROPHE 40 -#define KEY_GRAVE 41 -#define KEY_LEFTSHIFT 42 -#define KEY_BACKSLASH 43 -#define KEY_Z 44 -#define KEY_X 45 -#define KEY_C 46 -#define KEY_V 47 -#define KEY_B 48 -#define KEY_N 49 -#define KEY_M 50 -#define KEY_COMMA 51 -#define KEY_DOT 52 -#define KEY_SLASH 53 -#define KEY_RIGHTSHIFT 54 -#define KEY_KPASTERISK 55 -#define KEY_LEFTALT 56 -#define KEY_SPACE 57 -#define KEY_CAPSLOCK 58 -#define KEY_F1 59 -#define KEY_F2 60 -#define KEY_F3 61 -#define KEY_F4 62 -#define KEY_F5 63 -#define KEY_F6 64 -#define KEY_F7 65 -#define KEY_F8 66 -#define KEY_F9 67 -#define KEY_F10 68 -#define KEY_NUMLOCK 69 -#define KEY_SCROLLLOCK 70 -#define KEY_KP7 71 -#define KEY_KP8 72 -#define KEY_KP9 73 -#define KEY_KPMINUS 74 -#define KEY_KP4 75 -#define KEY_KP5 76 -#define KEY_KP6 77 -#define KEY_KPPLUS 78 -#define KEY_KP1 79 -#define KEY_KP2 80 -#define KEY_KP3 81 -#define KEY_KP0 82 -#define KEY_KPDOT 83 - -#define KEY_ZENKAKUHANKAKU 85 -#define KEY_102ND 86 -#define KEY_F11 87 -#define KEY_F12 88 -#define KEY_RO 89 -#define KEY_KATAKANA 90 -#define KEY_HIRAGANA 91 -#define KEY_HENKAN 92 -#define KEY_KATAKANAHIRAGANA 93 -#define KEY_MUHENKAN 94 -#define KEY_KPJPCOMMA 95 -#define KEY_KPENTER 96 -#define KEY_RIGHTCTRL 97 -#define KEY_KPSLASH 98 -#define KEY_SYSRQ 99 -#define KEY_RIGHTALT 100 -#define KEY_LINEFEED 101 -#define KEY_HOME 102 -#define KEY_UP 103 -#define KEY_PAGEUP 104 -#define KEY_LEFT 105 -#define KEY_RIGHT 106 -#define KEY_END 107 -#define KEY_DOWN 108 -#define KEY_PAGEDOWN 109 -#define KEY_INSERT 110 -#define KEY_DELETE 111 -#define KEY_MACRO 112 -#define KEY_MUTE 113 -#define KEY_VOLUMEDOWN 114 -#define KEY_VOLUMEUP 115 -#define KEY_POWER 116 /* SC System Power Down */ -#define KEY_KPEQUAL 117 -#define KEY_KPPLUSMINUS 118 -#define KEY_PAUSE 119 -#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ - -#define KEY_KPCOMMA 121 -#define KEY_HANGEUL 122 -#define KEY_HANGUEL KEY_HANGEUL -#define KEY_HANJA 123 -#define KEY_YEN 124 -#define KEY_LEFTMETA 125 -#define KEY_RIGHTMETA 126 -#define KEY_COMPOSE 127 - -#define KEY_STOP 128 /* AC Stop */ -#define KEY_AGAIN 129 -#define KEY_PROPS 130 /* AC Properties */ -#define KEY_UNDO 131 /* AC Undo */ -#define KEY_FRONT 132 -#define KEY_COPY 133 /* AC Copy */ -#define KEY_OPEN 134 /* AC Open */ -#define KEY_PASTE 135 /* AC Paste */ -#define KEY_FIND 136 /* AC Search */ -#define KEY_CUT 137 /* AC Cut */ -#define KEY_HELP 138 /* AL Integrated Help Center */ -#define KEY_MENU 139 /* Menu (show menu) */ -#define KEY_CALC 140 /* AL Calculator */ -#define KEY_SETUP 141 -#define KEY_SLEEP 142 /* SC System Sleep */ -#define KEY_WAKEUP 143 /* System Wake Up */ -#define KEY_FILE 144 /* AL Local Machine Browser */ -#define KEY_SENDFILE 145 -#define KEY_DELETEFILE 146 -#define KEY_XFER 147 -#define KEY_PROG1 148 -#define KEY_PROG2 149 -#define KEY_WWW 150 /* AL Internet Browser */ -#define KEY_MSDOS 151 -#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ -#define KEY_SCREENLOCK KEY_COFFEE -#define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ -#define KEY_DIRECTION KEY_ROTATE_DISPLAY -#define KEY_CYCLEWINDOWS 154 -#define KEY_MAIL 155 -#define KEY_BOOKMARKS 156 /* AC Bookmarks */ -#define KEY_COMPUTER 157 -#define KEY_BACK 158 /* AC Back */ -#define KEY_FORWARD 159 /* AC Forward */ -#define KEY_CLOSECD 160 -#define KEY_EJECTCD 161 -#define KEY_EJECTCLOSECD 162 -#define KEY_NEXTSONG 163 -#define KEY_PLAYPAUSE 164 -#define KEY_PREVIOUSSONG 165 -#define KEY_STOPCD 166 -#define KEY_RECORD 167 -#define KEY_REWIND 168 -#define KEY_PHONE 169 /* Media Select Telephone */ -#define KEY_ISO 170 -#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ -#define KEY_HOMEPAGE 172 /* AC Home */ -#define KEY_REFRESH 173 /* AC Refresh */ -#define KEY_EXIT 174 /* AC Exit */ -#define KEY_MOVE 175 -#define KEY_EDIT 176 -#define KEY_SCROLLUP 177 -#define KEY_SCROLLDOWN 178 -#define KEY_KPLEFTPAREN 179 -#define KEY_KPRIGHTPAREN 180 -#define KEY_NEW 181 /* AC New */ -#define KEY_REDO 182 /* AC Redo/Repeat */ - -#define KEY_F13 183 -#define KEY_F14 184 -#define KEY_F15 185 -#define KEY_F16 186 -#define KEY_F17 187 -#define KEY_F18 188 -#define KEY_F19 189 -#define KEY_F20 190 -#define KEY_F21 191 -#define KEY_F22 192 -#define KEY_F23 193 -#define KEY_F24 194 - -#define KEY_PLAYCD 200 -#define KEY_PAUSECD 201 -#define KEY_PROG3 202 -#define KEY_PROG4 203 -#define KEY_DASHBOARD 204 /* AL Dashboard */ -#define KEY_SUSPEND 205 -#define KEY_CLOSE 206 /* AC Close */ -#define KEY_PLAY 207 -#define KEY_FASTFORWARD 208 -#define KEY_BASSBOOST 209 -#define KEY_PRINT 210 /* AC Print */ -#define KEY_HP 211 -#define KEY_CAMERA 212 -#define KEY_SOUND 213 -#define KEY_QUESTION 214 -#define KEY_EMAIL 215 -#define KEY_CHAT 216 -#define KEY_SEARCH 217 -#define KEY_CONNECT 218 -#define KEY_FINANCE 219 /* AL Checkbook/Finance */ -#define KEY_SPORT 220 -#define KEY_SHOP 221 -#define KEY_ALTERASE 222 -#define KEY_CANCEL 223 /* AC Cancel */ -#define KEY_BRIGHTNESSDOWN 224 -#define KEY_BRIGHTNESSUP 225 -#define KEY_MEDIA 226 - -#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video - outputs (Monitor/LCD/TV-out/etc) */ -#define KEY_KBDILLUMTOGGLE 228 -#define KEY_KBDILLUMDOWN 229 -#define KEY_KBDILLUMUP 230 - -#define KEY_SEND 231 /* AC Send */ -#define KEY_REPLY 232 /* AC Reply */ -#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ -#define KEY_SAVE 234 /* AC Save */ -#define KEY_DOCUMENTS 235 - -#define KEY_BATTERY 236 - -#define KEY_BLUETOOTH 237 -#define KEY_WLAN 238 -#define KEY_UWB 239 - -#define KEY_UNKNOWN 240 - -#define KEY_VIDEO_NEXT 241 /* drive next video source */ -#define KEY_VIDEO_PREV 242 /* drive previous video source */ -#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ -#define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual - brightness control is off, - rely on ambient */ -#define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO -#define KEY_DISPLAY_OFF 245 /* display device to off state */ - -#define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ -#define KEY_WIMAX KEY_WWAN -#define KEY_RFKILL 247 /* Key that controls all radios */ - -#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ - -/* Code 255 is reserved for special needs of AT keyboard driver */ - -#define BTN_MISC 0x100 -#define BTN_0 0x100 -#define BTN_1 0x101 -#define BTN_2 0x102 -#define BTN_3 0x103 -#define BTN_4 0x104 -#define BTN_5 0x105 -#define BTN_6 0x106 -#define BTN_7 0x107 -#define BTN_8 0x108 -#define BTN_9 0x109 - -#define BTN_MOUSE 0x110 -#define BTN_LEFT 0x110 -#define BTN_RIGHT 0x111 -#define BTN_MIDDLE 0x112 -#define BTN_SIDE 0x113 -#define BTN_EXTRA 0x114 -#define BTN_FORWARD 0x115 -#define BTN_BACK 0x116 -#define BTN_TASK 0x117 - -#define BTN_JOYSTICK 0x120 -#define BTN_TRIGGER 0x120 -#define BTN_THUMB 0x121 -#define BTN_THUMB2 0x122 -#define BTN_TOP 0x123 -#define BTN_TOP2 0x124 -#define BTN_PINKIE 0x125 -#define BTN_BASE 0x126 -#define BTN_BASE2 0x127 -#define BTN_BASE3 0x128 -#define BTN_BASE4 0x129 -#define BTN_BASE5 0x12a -#define BTN_BASE6 0x12b -#define BTN_DEAD 0x12f - -#define BTN_GAMEPAD 0x130 -#define BTN_SOUTH 0x130 -#define BTN_A BTN_SOUTH -#define BTN_EAST 0x131 -#define BTN_B BTN_EAST -#define BTN_C 0x132 -#define BTN_NORTH 0x133 -#define BTN_X BTN_NORTH -#define BTN_WEST 0x134 -#define BTN_Y BTN_WEST -#define BTN_Z 0x135 -#define BTN_TL 0x136 -#define BTN_TR 0x137 -#define BTN_TL2 0x138 -#define BTN_TR2 0x139 -#define BTN_SELECT 0x13a -#define BTN_START 0x13b -#define BTN_MODE 0x13c -#define BTN_THUMBL 0x13d -#define BTN_THUMBR 0x13e - -#define BTN_DIGI 0x140 -#define BTN_TOOL_PEN 0x140 -#define BTN_TOOL_RUBBER 0x141 -#define BTN_TOOL_BRUSH 0x142 -#define BTN_TOOL_PENCIL 0x143 -#define BTN_TOOL_AIRBRUSH 0x144 -#define BTN_TOOL_FINGER 0x145 -#define BTN_TOOL_MOUSE 0x146 -#define BTN_TOOL_LENS 0x147 -#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ -#define BTN_TOUCH 0x14a -#define BTN_STYLUS 0x14b -#define BTN_STYLUS2 0x14c -#define BTN_TOOL_DOUBLETAP 0x14d -#define BTN_TOOL_TRIPLETAP 0x14e -#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ - -#define BTN_WHEEL 0x150 -#define BTN_GEAR_DOWN 0x150 -#define BTN_GEAR_UP 0x151 - -#define KEY_OK 0x160 -#define KEY_SELECT 0x161 -#define KEY_GOTO 0x162 -#define KEY_CLEAR 0x163 -#define KEY_POWER2 0x164 -#define KEY_OPTION 0x165 -#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ -#define KEY_TIME 0x167 -#define KEY_VENDOR 0x168 -#define KEY_ARCHIVE 0x169 -#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ -#define KEY_CHANNEL 0x16b -#define KEY_FAVORITES 0x16c -#define KEY_EPG 0x16d -#define KEY_PVR 0x16e /* Media Select Home */ -#define KEY_MHP 0x16f -#define KEY_LANGUAGE 0x170 -#define KEY_TITLE 0x171 -#define KEY_SUBTITLE 0x172 -#define KEY_ANGLE 0x173 -#define KEY_ZOOM 0x174 -#define KEY_MODE 0x175 -#define KEY_KEYBOARD 0x176 -#define KEY_SCREEN 0x177 -#define KEY_PC 0x178 /* Media Select Computer */ -#define KEY_TV 0x179 /* Media Select TV */ -#define KEY_TV2 0x17a /* Media Select Cable */ -#define KEY_VCR 0x17b /* Media Select VCR */ -#define KEY_VCR2 0x17c /* VCR Plus */ -#define KEY_SAT 0x17d /* Media Select Satellite */ -#define KEY_SAT2 0x17e -#define KEY_CD 0x17f /* Media Select CD */ -#define KEY_TAPE 0x180 /* Media Select Tape */ -#define KEY_RADIO 0x181 -#define KEY_TUNER 0x182 /* Media Select Tuner */ -#define KEY_PLAYER 0x183 -#define KEY_TEXT 0x184 -#define KEY_DVD 0x185 /* Media Select DVD */ -#define KEY_AUX 0x186 -#define KEY_MP3 0x187 -#define KEY_AUDIO 0x188 /* AL Audio Browser */ -#define KEY_VIDEO 0x189 /* AL Movie Browser */ -#define KEY_DIRECTORY 0x18a -#define KEY_LIST 0x18b -#define KEY_MEMO 0x18c /* Media Select Messages */ -#define KEY_CALENDAR 0x18d -#define KEY_RED 0x18e -#define KEY_GREEN 0x18f -#define KEY_YELLOW 0x190 -#define KEY_BLUE 0x191 -#define KEY_CHANNELUP 0x192 /* Channel Increment */ -#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ -#define KEY_FIRST 0x194 -#define KEY_LAST 0x195 /* Recall Last */ -#define KEY_AB 0x196 -#define KEY_NEXT 0x197 -#define KEY_RESTART 0x198 -#define KEY_SLOW 0x199 -#define KEY_SHUFFLE 0x19a -#define KEY_BREAK 0x19b -#define KEY_PREVIOUS 0x19c -#define KEY_DIGITS 0x19d -#define KEY_TEEN 0x19e -#define KEY_TWEN 0x19f -#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ -#define KEY_GAMES 0x1a1 /* Media Select Games */ -#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ -#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ -#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ -#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ -#define KEY_EDITOR 0x1a6 /* AL Text Editor */ -#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ -#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ -#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ -#define KEY_DATABASE 0x1aa /* AL Database App */ -#define KEY_NEWS 0x1ab /* AL Newsreader */ -#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ -#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ -#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ -#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ -#define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE -#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ -#define KEY_LOGOFF 0x1b1 /* AL Logoff */ - -#define KEY_DOLLAR 0x1b2 -#define KEY_EURO 0x1b3 - -#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ -#define KEY_FRAMEFORWARD 0x1b5 -#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ -#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ -#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ -#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ -#define KEY_IMAGES 0x1ba /* AL Image Browser */ - -#define KEY_DEL_EOL 0x1c0 -#define KEY_DEL_EOS 0x1c1 -#define KEY_INS_LINE 0x1c2 -#define KEY_DEL_LINE 0x1c3 - -#define KEY_FN 0x1d0 -#define KEY_FN_ESC 0x1d1 -#define KEY_FN_F1 0x1d2 -#define KEY_FN_F2 0x1d3 -#define KEY_FN_F3 0x1d4 -#define KEY_FN_F4 0x1d5 -#define KEY_FN_F5 0x1d6 -#define KEY_FN_F6 0x1d7 -#define KEY_FN_F7 0x1d8 -#define KEY_FN_F8 0x1d9 -#define KEY_FN_F9 0x1da -#define KEY_FN_F10 0x1db -#define KEY_FN_F11 0x1dc -#define KEY_FN_F12 0x1dd -#define KEY_FN_1 0x1de -#define KEY_FN_2 0x1df -#define KEY_FN_D 0x1e0 -#define KEY_FN_E 0x1e1 -#define KEY_FN_F 0x1e2 -#define KEY_FN_S 0x1e3 -#define KEY_FN_B 0x1e4 - -#define KEY_BRL_DOT1 0x1f1 -#define KEY_BRL_DOT2 0x1f2 -#define KEY_BRL_DOT3 0x1f3 -#define KEY_BRL_DOT4 0x1f4 -#define KEY_BRL_DOT5 0x1f5 -#define KEY_BRL_DOT6 0x1f6 -#define KEY_BRL_DOT7 0x1f7 -#define KEY_BRL_DOT8 0x1f8 -#define KEY_BRL_DOT9 0x1f9 -#define KEY_BRL_DOT10 0x1fa - -#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ -#define KEY_NUMERIC_1 0x201 /* and other keypads */ -#define KEY_NUMERIC_2 0x202 -#define KEY_NUMERIC_3 0x203 -#define KEY_NUMERIC_4 0x204 -#define KEY_NUMERIC_5 0x205 -#define KEY_NUMERIC_6 0x206 -#define KEY_NUMERIC_7 0x207 -#define KEY_NUMERIC_8 0x208 -#define KEY_NUMERIC_9 0x209 -#define KEY_NUMERIC_STAR 0x20a -#define KEY_NUMERIC_POUND 0x20b -#define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ -#define KEY_NUMERIC_B 0x20d -#define KEY_NUMERIC_C 0x20e -#define KEY_NUMERIC_D 0x20f - -#define KEY_CAMERA_FOCUS 0x210 -#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ - -#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ -#define KEY_TOUCHPAD_ON 0x213 -#define KEY_TOUCHPAD_OFF 0x214 - -#define KEY_CAMERA_ZOOMIN 0x215 -#define KEY_CAMERA_ZOOMOUT 0x216 -#define KEY_CAMERA_UP 0x217 -#define KEY_CAMERA_DOWN 0x218 -#define KEY_CAMERA_LEFT 0x219 -#define KEY_CAMERA_RIGHT 0x21a - -#define KEY_ATTENDANT_ON 0x21b -#define KEY_ATTENDANT_OFF 0x21c -#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ -#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ - -#define BTN_DPAD_UP 0x220 -#define BTN_DPAD_DOWN 0x221 -#define BTN_DPAD_LEFT 0x222 -#define BTN_DPAD_RIGHT 0x223 - -#define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ - -#define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ -#define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ -#define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ -#define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ -#define KEY_APPSELECT 0x244 /* AL Select Task/Application */ -#define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ -#define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ - -#define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ -#define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ - -#define KEY_KBDINPUTASSIST_PREV 0x260 -#define KEY_KBDINPUTASSIST_NEXT 0x261 -#define KEY_KBDINPUTASSIST_PREVGROUP 0x262 -#define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 -#define KEY_KBDINPUTASSIST_ACCEPT 0x264 -#define KEY_KBDINPUTASSIST_CANCEL 0x265 - -#define BTN_TRIGGER_HAPPY 0x2c0 -#define BTN_TRIGGER_HAPPY1 0x2c0 -#define BTN_TRIGGER_HAPPY2 0x2c1 -#define BTN_TRIGGER_HAPPY3 0x2c2 -#define BTN_TRIGGER_HAPPY4 0x2c3 -#define BTN_TRIGGER_HAPPY5 0x2c4 -#define BTN_TRIGGER_HAPPY6 0x2c5 -#define BTN_TRIGGER_HAPPY7 0x2c6 -#define BTN_TRIGGER_HAPPY8 0x2c7 -#define BTN_TRIGGER_HAPPY9 0x2c8 -#define BTN_TRIGGER_HAPPY10 0x2c9 -#define BTN_TRIGGER_HAPPY11 0x2ca -#define BTN_TRIGGER_HAPPY12 0x2cb -#define BTN_TRIGGER_HAPPY13 0x2cc -#define BTN_TRIGGER_HAPPY14 0x2cd -#define BTN_TRIGGER_HAPPY15 0x2ce -#define BTN_TRIGGER_HAPPY16 0x2cf -#define BTN_TRIGGER_HAPPY17 0x2d0 -#define BTN_TRIGGER_HAPPY18 0x2d1 -#define BTN_TRIGGER_HAPPY19 0x2d2 -#define BTN_TRIGGER_HAPPY20 0x2d3 -#define BTN_TRIGGER_HAPPY21 0x2d4 -#define BTN_TRIGGER_HAPPY22 0x2d5 -#define BTN_TRIGGER_HAPPY23 0x2d6 -#define BTN_TRIGGER_HAPPY24 0x2d7 -#define BTN_TRIGGER_HAPPY25 0x2d8 -#define BTN_TRIGGER_HAPPY26 0x2d9 -#define BTN_TRIGGER_HAPPY27 0x2da -#define BTN_TRIGGER_HAPPY28 0x2db -#define BTN_TRIGGER_HAPPY29 0x2dc -#define BTN_TRIGGER_HAPPY30 0x2dd -#define BTN_TRIGGER_HAPPY31 0x2de -#define BTN_TRIGGER_HAPPY32 0x2df -#define BTN_TRIGGER_HAPPY33 0x2e0 -#define BTN_TRIGGER_HAPPY34 0x2e1 -#define BTN_TRIGGER_HAPPY35 0x2e2 -#define BTN_TRIGGER_HAPPY36 0x2e3 -#define BTN_TRIGGER_HAPPY37 0x2e4 -#define BTN_TRIGGER_HAPPY38 0x2e5 -#define BTN_TRIGGER_HAPPY39 0x2e6 -#define BTN_TRIGGER_HAPPY40 0x2e7 - -/* We avoid low common keys in module aliases so they don't get huge. */ -#define KEY_MIN_INTERESTING KEY_MUTE -#define KEY_MAX 0x2ff -#define KEY_CNT (KEY_MAX+1) - -/* - * Relative axes - */ - -#define REL_X 0x00 -#define REL_Y 0x01 -#define REL_Z 0x02 -#define REL_RX 0x03 -#define REL_RY 0x04 -#define REL_RZ 0x05 -#define REL_HWHEEL 0x06 -#define REL_DIAL 0x07 -#define REL_WHEEL 0x08 -#define REL_MISC 0x09 -#define REL_MAX 0x0f -#define REL_CNT (REL_MAX+1) - -/* - * Absolute axes - */ - -#define ABS_X 0x00 -#define ABS_Y 0x01 -#define ABS_Z 0x02 -#define ABS_RX 0x03 -#define ABS_RY 0x04 -#define ABS_RZ 0x05 -#define ABS_THROTTLE 0x06 -#define ABS_RUDDER 0x07 -#define ABS_WHEEL 0x08 -#define ABS_GAS 0x09 -#define ABS_BRAKE 0x0a -#define ABS_HAT0X 0x10 -#define ABS_HAT0Y 0x11 -#define ABS_HAT1X 0x12 -#define ABS_HAT1Y 0x13 -#define ABS_HAT2X 0x14 -#define ABS_HAT2Y 0x15 -#define ABS_HAT3X 0x16 -#define ABS_HAT3Y 0x17 -#define ABS_PRESSURE 0x18 -#define ABS_DISTANCE 0x19 -#define ABS_TILT_X 0x1a -#define ABS_TILT_Y 0x1b -#define ABS_TOOL_WIDTH 0x1c - -#define ABS_VOLUME 0x20 - -#define ABS_MISC 0x28 - -#define ABS_MT_SLOT 0x2f /* MT slot being modified */ -#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ -#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ -#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ -#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ -#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ -#define ABS_MT_POSITION_X 0x35 /* Center X touch position */ -#define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ -#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ -#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ -#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ -#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ -#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ -#define ABS_MT_TOOL_X 0x3c /* Center X tool position */ -#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ - - -#define ABS_MAX 0x3f -#define ABS_CNT (ABS_MAX+1) - -/* - * Switch events - */ - -#define SW_LID 0x00 /* set = lid shut */ -#define SW_TABLET_MODE 0x01 /* set = tablet mode */ -#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ -#define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" - set = radio enabled */ -#define SW_RADIO SW_RFKILL_ALL /* deprecated */ -#define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ -#define SW_DOCK 0x05 /* set = plugged into dock */ -#define SW_LINEOUT_INSERT 0x06 /* set = inserted */ -#define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ -#define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ -#define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ -#define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ -#define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ -#define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ -#define SW_LINEIN_INSERT 0x0d /* set = inserted */ -#define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_PEN_INSERTED 0x0f /* set = pen inserted */ -#define SW_MAX 0x10 -#define SW_CNT (SW_MAX+1) - -/* - * Misc events - */ - -#define MSC_SERIAL 0x00 -#define MSC_PULSELED 0x01 -#define MSC_GESTURE 0x02 -#define MSC_RAW 0x03 -#define MSC_SCAN 0x04 -#define MSC_TIMESTAMP 0x05 -#define MSC_MAX 0x07 -#define MSC_CNT (MSC_MAX+1) - -/* - * LEDs - */ - -#define LED_NUML 0x00 -#define LED_CAPSL 0x01 -#define LED_SCROLLL 0x02 -#define LED_COMPOSE 0x03 -#define LED_KANA 0x04 -#define LED_SLEEP 0x05 -#define LED_SUSPEND 0x06 -#define LED_MUTE 0x07 -#define LED_MISC 0x08 -#define LED_MAIL 0x09 -#define LED_CHARGING 0x0a -#define LED_MAX 0x0f -#define LED_CNT (LED_MAX+1) - -/* - * Autorepeat values - */ - -#define REP_DELAY 0x00 -#define REP_PERIOD 0x01 -#define REP_MAX 0x01 -#define REP_CNT (REP_MAX+1) - -/* - * Sounds - */ - -#define SND_CLICK 0x00 -#define SND_BELL 0x01 -#define SND_TONE 0x02 -#define SND_MAX 0x07 -#define SND_CNT (SND_MAX+1) - -#endif diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h deleted file mode 100644 index 33a1003c55aa..000000000000 --- a/include/dt-bindings/interrupt-controller/irq.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This header provides constants for most IRQ bindings. - * - * Most IRQ bindings include a flags cell as part of the IRQ specifier. - * In most cases, the format of the flags cell uses the standard values - * defined in this header. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H - -#define IRQ_TYPE_NONE 0 -#define IRQ_TYPE_EDGE_RISING 1 -#define IRQ_TYPE_EDGE_FALLING 2 -#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 4 -#define IRQ_TYPE_LEVEL_LOW 8 - -#endif diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h deleted file mode 100644 index 9a0d33d027ff..000000000000 --- a/include/dt-bindings/leds/common.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for the common LEDs device tree bindings. - * - * Copyright (C) 2015, Samsung Electronics Co., Ltd. - * Author: Jacek Anaszewski j.anaszewski@samsung.com - * - * Copyright (C) 2019 Jacek Anaszewski jacek.anaszewski@gmail.com - * Copyright (C) 2020 Pavel Machek pavel@ucw.cz - */ - -#ifndef __DT_BINDINGS_LEDS_H -#define __DT_BINDINGS_LEDS_H - -/* External trigger type */ -#define LEDS_TRIG_TYPE_EDGE 0 -#define LEDS_TRIG_TYPE_LEVEL 1 - -/* Boost modes */ -#define LEDS_BOOST_OFF 0 -#define LEDS_BOOST_ADAPTIVE 1 -#define LEDS_BOOST_FIXED 2 - -/* Standard LED colors */ -#define LED_COLOR_ID_WHITE 0 -#define LED_COLOR_ID_RED 1 -#define LED_COLOR_ID_GREEN 2 -#define LED_COLOR_ID_BLUE 3 -#define LED_COLOR_ID_AMBER 4 -#define LED_COLOR_ID_VIOLET 5 -#define LED_COLOR_ID_YELLOW 6 -#define LED_COLOR_ID_IR 7 -#define LED_COLOR_ID_MULTI 8 /* For multicolor LEDs */ -#define LED_COLOR_ID_RGB 9 /* For multicolor LEDs that can do arbitrary color, - so this would include RGBW and similar */ -#define LED_COLOR_ID_PURPLE 10 -#define LED_COLOR_ID_ORANGE 11 -#define LED_COLOR_ID_PINK 12 -#define LED_COLOR_ID_CYAN 13 -#define LED_COLOR_ID_LIME 14 -#define LED_COLOR_ID_MAX 15 - -/* Standard LED functions */ -/* Keyboard LEDs, usually it would be input4::capslock etc. */ -/* Obsolete equivalent: "shift-key-light" */ -#define LED_FUNCTION_CAPSLOCK "capslock" -#define LED_FUNCTION_SCROLLLOCK "scrolllock" -#define LED_FUNCTION_NUMLOCK "numlock" -/* Obsolete equivalents: "tpacpi::thinklight" (IBM/Lenovo Thinkpads), - "lp5523:kb{1,2,3,4,5,6}" (Nokia N900) */ -#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" - -/* System LEDs, usually found on system body. - platform::mute (etc) is sometimes seen, :mute would be better */ -#define LED_FUNCTION_POWER "power" -#define LED_FUNCTION_DISK "disk" - -/* Obsolete: "platform:*:charging" (allwinner sun50i) */ -#define LED_FUNCTION_CHARGING "charging" -/* Used RGB notification LEDs common on phones. - Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4), - "lp5523:{r,g,b}" (Nokia N900) */ -#define LED_FUNCTION_STATUS "status" - -#define LED_FUNCTION_MICMUTE "micmute" -#define LED_FUNCTION_MUTE "mute" - -/* Used for player LEDs as found on game controllers from e.g. Nintendo, Sony. */ -#define LED_FUNCTION_PLAYER1 "player-1" -#define LED_FUNCTION_PLAYER2 "player-2" -#define LED_FUNCTION_PLAYER3 "player-3" -#define LED_FUNCTION_PLAYER4 "player-4" -#define LED_FUNCTION_PLAYER5 "player-5" - -/* Miscelleaus functions. Use functions above if you can. */ -#define LED_FUNCTION_ACTIVITY "activity" -#define LED_FUNCTION_ALARM "alarm" -#define LED_FUNCTION_BACKLIGHT "backlight" -#define LED_FUNCTION_BLUETOOTH "bluetooth" -#define LED_FUNCTION_BOOT "boot" -#define LED_FUNCTION_CPU "cpu" -#define LED_FUNCTION_DEBUG "debug" -#define LED_FUNCTION_DISK_ACTIVITY "disk-activity" -#define LED_FUNCTION_DISK_ERR "disk-err" -#define LED_FUNCTION_DISK_READ "disk-read" -#define LED_FUNCTION_DISK_WRITE "disk-write" -#define LED_FUNCTION_FAULT "fault" -#define LED_FUNCTION_FLASH "flash" -#define LED_FUNCTION_HEARTBEAT "heartbeat" -#define LED_FUNCTION_INDICATOR "indicator" -#define LED_FUNCTION_LAN "lan" -#define LED_FUNCTION_MAIL "mail" -#define LED_FUNCTION_MTD "mtd" -#define LED_FUNCTION_PANIC "panic" -#define LED_FUNCTION_PROGRAMMING "programming" -#define LED_FUNCTION_RX "rx" -#define LED_FUNCTION_SD "sd" -#define LED_FUNCTION_STANDBY "standby" -#define LED_FUNCTION_TORCH "torch" -#define LED_FUNCTION_TX "tx" -#define LED_FUNCTION_USB "usb" -#define LED_FUNCTION_WAN "wan" -#define LED_FUNCTION_WLAN "wlan" -#define LED_FUNCTION_WPS "wps" - -#endif /* __DT_BINDINGS_LEDS_H */ diff --git a/include/dt-bindings/mux/mux.h b/include/dt-bindings/mux/mux.h deleted file mode 100644 index 042719218dbf..000000000000 --- a/include/dt-bindings/mux/mux.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for most Multiplexer bindings. - * - * Most Multiplexer bindings specify an idle state. In most cases, the - * the multiplexer can be left as is when idle, and in some cases it can - * disconnect the input/output and leave the multiplexer in a high - * impedance state. - */ - -#ifndef _DT_BINDINGS_MUX_MUX_H -#define _DT_BINDINGS_MUX_MUX_H - -#define MUX_IDLE_AS_IS (-1) -#define MUX_IDLE_DISCONNECT (-2) - -#endif diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h deleted file mode 100644 index f48c9acf251e..000000000000 --- a/include/dt-bindings/phy/phy.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * - * This header provides constants for the phy framework - * - * Copyright (C) 2014 STMicroelectronics - * Author: Gabriel Fernandez gabriel.fernandez@st.com - */ - -#ifndef _DT_BINDINGS_PHY -#define _DT_BINDINGS_PHY - -#define PHY_NONE 0 -#define PHY_TYPE_SATA 1 -#define PHY_TYPE_PCIE 2 -#define PHY_TYPE_USB2 3 -#define PHY_TYPE_USB3 4 -#define PHY_TYPE_UFS 5 -#define PHY_TYPE_DP 6 -#define PHY_TYPE_XPCS 7 -#define PHY_TYPE_SGMII 8 -#define PHY_TYPE_QSGMII 9 -#define PHY_TYPE_DPHY 10 -#define PHY_TYPE_CPHY 11 - -#endif /* _DT_BINDINGS_PHY */ diff --git a/include/dt-bindings/pwm/pwm.h b/include/dt-bindings/pwm/pwm.h deleted file mode 100644 index 96f49e82253e..000000000000 --- a/include/dt-bindings/pwm/pwm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This header provides constants for most PWM bindings. - * - * Most PWM bindings can include a flags cell as part of the PWM specifier. - * In most cases, the format of the flags cell uses the standard values - * defined in this header. - */ - -#ifndef _DT_BINDINGS_PWM_PWM_H -#define _DT_BINDINGS_PWM_PWM_H - -#define PWM_POLARITY_INVERTED (1 << 0) - -#endif diff --git a/include/dt-bindings/spmi/spmi.h b/include/dt-bindings/spmi/spmi.h deleted file mode 100644 index ad4a43481de4..000000000000 --- a/include/dt-bindings/spmi/spmi.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ -#ifndef __DT_BINDINGS_SPMI_H -#define __DT_BINDINGS_SPMI_H - -#define SPMI_USID 0 -#define SPMI_GSID 1 - -#endif diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h deleted file mode 100644 index 7871e5f52b1c..000000000000 --- a/include/dt-bindings/thermal/thermal.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides constants for most thermal bindings. - * - * Copyright (C) 2013 Texas Instruments - * Eduardo Valentin eduardo.valentin@ti.com - */ - -#ifndef _DT_BINDINGS_THERMAL_THERMAL_H -#define _DT_BINDINGS_THERMAL_THERMAL_H - -/* On cooling devices upper and lower limits */ -#define THERMAL_NO_LIMIT (~0) - -#endif diff --git a/include/dt-bindings/usb/pd.h b/include/dt-bindings/usb/pd.h deleted file mode 100644 index 985f2bbd4d24..000000000000 --- a/include/dt-bindings/usb/pd.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_POWER_DELIVERY_H -#define __DT_POWER_DELIVERY_H - -/* Power delivery Power Data Object definitions */ -#define PDO_TYPE_FIXED 0 -#define PDO_TYPE_BATT 1 -#define PDO_TYPE_VAR 2 -#define PDO_TYPE_APDO 3 - -#define PDO_TYPE_SHIFT 30 -#define PDO_TYPE_MASK 0x3 - -#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) - -#define PDO_VOLT_MASK 0x3ff -#define PDO_CURR_MASK 0x3ff -#define PDO_PWR_MASK 0x3ff - -#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */ -#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */ -#define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */ -#define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */ -#define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */ -#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */ -#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ -#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ - -#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) -#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) - -#define PDO_FIXED(mv, ma, flags) \ - (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ - PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) - -#define VSAFE5V 5000 /* mv units */ - -#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ -#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ -#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ - -#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) -#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) -#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) - -#define PDO_BATT(min_mv, max_mv, max_mw) \ - (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ - PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) - -#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ -#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ -#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ - -#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) -#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) -#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) - -#define PDO_VAR(min_mv, max_mv, max_ma) \ - (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ - PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) - -#define APDO_TYPE_PPS 0 - -#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */ -#define PDO_APDO_TYPE_MASK 0x3 - -#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT) - -#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */ -#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */ -#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */ - -#define PDO_PPS_APDO_VOLT_MASK 0xff -#define PDO_PPS_APDO_CURR_MASK 0x7f - -#define PDO_PPS_APDO_MIN_VOLT(mv) \ - ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT) -#define PDO_PPS_APDO_MAX_VOLT(mv) \ - ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT) -#define PDO_PPS_APDO_MAX_CURR(ma) \ - ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT) - -#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \ - (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \ - PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \ - PDO_PPS_APDO_MAX_CURR(max_ma)) - - #endif /* __DT_POWER_DELIVERY_H */