In LS2080, SFP is Little Endian and Verion is 3.4 . The base address is 0x01e80200. SFP will be used in Secure Boot to read fuses.

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message Changes for v5: - Cleaned up commit message

arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++ include/fsl_sfp.h | 3 ++- 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 0ef7c9d..380d5ac 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -67,6 +67,10 @@ /* SMMU Defintions */ #define SMMU_BASE 0x05000000 /* GR0 Base */

+/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE + /* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 #define CCI_MN_RNF_NODEID_LIST 0x180 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 91f3ce8..f1b021f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -73,6 +73,9 @@ #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)

+/* SFP */ +#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) + /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index 353a123..2976a2c 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -32,7 +32,8 @@ /* Number of SRKH registers */ #define NUM_SRKH_REGS 8

-#ifdef CONFIG_SYS_FSL_SFP_VER_3_2 +#if defined(CONFIG_SYS_FSL_SFP_VER_3_2) || \ + defined(CONFIG_SYS_FSL_SFP_VER_3_4) struct ccsr_sfp_regs { u32 ospr; /* 0x200 */ u32 ospr1; /* 0x204 */

For ls2080, Added configs for various IPs used during secure boot. Added address and endianness for SEC and Security Monitor. SRK are Fuses in SFP (Fuses for public key's hash). These are stored in Little Endian format.

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: -Cleaned up commit message Changes for v5: -Cleaned up commit message

arch/arm/include/asm/arch-fsl-layerscape/config.h | 10 ++++++++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 ++++++++++ 2 files changed, 20 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 380d5ac..34851a9 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -70,6 +70,16 @@ /* SFP */ #define CONFIG_SYS_FSL_SFP_VER_3_4 #define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* SEC */ +#define CONFIG_SYS_FSL_SEC_LE +#define CONFIG_SYS_FSL_SEC_COMPAT 5 + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +

/* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index f1b021f..1fc51e0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -76,6 +76,14 @@ /* SFP */ #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)

+/* SEC */ +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x07000000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x07010000) + +/* Security Monitor */ +#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) + + /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) @@ -204,6 +212,8 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 +#define RCW_SB_EN_REG_INDEX 9 +#define RCW_SB_EN_MASK 0x00000400

u8 res_180[0x200-0x180]; u32 scratchrw[32]; /* Scratch Read/Write */

For Secure Boot, a header is used to identify key table, signature and image address. For Ls-Ch3, there is a new header structure being used.

Currently Key extension (IE) feature is not supported. Single Key feature is not supported. Keys must be in table format. Hence, SRK (Key table) is by default currently always present. Max Key number has increase from 4 to 8. 8th Key is irrevocable. A New Barker Code is being used.

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message Changes for v5: - Cleaned up commit message

arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +- arch/arm/include/asm/fsl_secure_boot.h | 4 ++ board/freescale/common/fsl_validate.c | 35 +++++++++++-- include/fsl_secboot_err.h | 3 ++ include/fsl_validate.h | 60 ++++++++++++++++++++--- 5 files changed, 91 insertions(+), 14 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 34851a9..0445dbd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -79,7 +79,8 @@ /* Security Monitor */ #define CONFIG_SYS_FSL_SEC_MON_LE

- +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS

/* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index a32a1d7..4eb3b15 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -35,9 +35,13 @@ * The feature is only applicable in case of NOR boot and is * not applicable in case of RAMBOOT (NAND, SD, SPI). */ +#ifndef CONFIG_ESBC_HDR_LS +/* Current Key EXT feature not available in LS ESBC Header */ #define CONFIG_FSL_ISBC_KEY_EXT #endif

+#endif + #ifdef CONFIG_LS1043A /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ #define CONFIG_ESBC_ADDR_64BIT diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 8fd6dd6..c12b9c9 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -35,7 +35,13 @@ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, };

static u8 hash_val[SHA256_BYTES]; + +#ifdef CONFIG_ESBC_HDR_LS +/* New Barker Code for LS ESBC Header */ +static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 }; +#else static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 }; +#endif

void branch_to_self(void) __attribute__ ((noreturn));

@@ -157,10 +163,15 @@ static int get_ie_info_addr(u32 *ie_addr) /* This function checks srk_table_flag in header and set/reset srk_flag.*/ static u32 check_srk(struct fsl_secboot_img_priv *img) { +#ifdef CONFIG_ESBC_HDR_LS + /* In LS, No SRK Flag as SRK is always present*/ + return 1; +#else if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) return 1;

return 0; +#endif }

/* This function returns ospr's key_revoc values.*/ @@ -223,6 +234,7 @@ static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img) } #endif

+#ifndef CONFIG_ESBC_HDR_LS static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) { struct fsl_secboot_img_hdr *hdr = &img->hdr; @@ -238,6 +250,7 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)

return 0; } +#endif /* CONFIG_ESBC_HDR_LS */

#if defined(CONFIG_FSL_ISBC_KEY_EXT) static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) @@ -388,6 +401,7 @@ void fsl_secboot_handle_error(int error) case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD: case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP: case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD: + case ERROR_KEY_TABLE_NOT_FOUND: #ifdef CONFIG_KEY_REVOCATION case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED: case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY: @@ -536,11 +550,18 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) if (!key_hash && check_ie(img)) key_hash = 1; #endif - if (!key_hash) +#ifndef CONFIG_ESBC_HDR_LS +/* No single key support in LS ESBC header */ + if (!key_hash) { ret = algo->hash_update(algo, ctx, img->img_key, img->hdr.key_len, 0); + key_hash = 1; + } +#endif if (ret) return ret; + if (!key_hash) + return ERROR_KEY_TABLE_NOT_FOUND;

/* Update hash for actual Image */ ret = algo->hash_update(algo, ctx, @@ -626,8 +647,6 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) u8 *k, *s; u32 ret = 0;

-#ifdef CONFIG_KEY_REVOCATION -#endif int key_found = 0;

/* check barker code */ @@ -671,13 +690,17 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) key_found = 1; } #endif - +#ifndef CONFIG_ESBC_HDR_LS +/* Single Key Feature not available in LS ESBC Header */ if (key_found == 0) { ret = read_validate_single_key(img); if (ret != 0) return ret; key_found = 1; } +#endif + if (!key_found) + return ERROR_KEY_TABLE_NOT_FOUND;

/* check signaure */ if (get_key_len(img) == 2 * hdr->sign_len) { @@ -691,10 +714,12 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) }

memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len); - +/* No SG support in LS-CH3 */ +#ifndef CONFIG_ESBC_HDR_LS /* No SG support */ if (hdr->sg_flag) return ERROR_ESBC_CLIENT_HEADER_SG; +#endif

/* modulus most significant bit should be set */ k = (u8 *)&img->img_key; diff --git a/include/fsl_secboot_err.h b/include/fsl_secboot_err.h index afc50a8..95d890b 100644 --- a/include/fsl_secboot_err.h +++ b/include/fsl_secboot_err.h @@ -29,6 +29,7 @@ #define ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN 0x18 #define ERROR_IE_TABLE_NOT_FOUND 0x19 #define ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN 0x20 +#define ERROR_KEY_TABLE_NOT_FOUND 0x21 #define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1 0x40 #define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2 0x80 #define ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD 0x100 @@ -121,6 +122,8 @@ static const struct fsl_secboot_errcode fsl_secboot_errcodes[] = { "Wrong IE public key len in header" }, { ERROR_IE_TABLE_NOT_FOUND, "Information about IE Table missing" }, + { ERROR_KEY_TABLE_NOT_FOUND, + "No Key/ Key Table Found in header"}, { ERROR_ESBC_CLIENT_MAX, "NULL" } };

diff --git a/include/fsl_validate.h b/include/fsl_validate.h index 83efcf4..f812c1a 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -21,14 +21,6 @@

extern struct jobring jr;

-#ifdef CONFIG_KEY_REVOCATION -/* Srk table and key revocation check */ -#define SRK_FLAG 0x01 -#define UNREVOCABLE_KEY 4 -#define ALIGN_REVOC_KEY 3 -#define MAX_KEY_ENTRIES 4 -#endif - /* Barker code size in bytes */ #define ESBC_BARKER_LEN 4 /* barker code length in ESBC uboot client */ /* header */ @@ -39,6 +31,47 @@ extern struct jobring jr; /* Maximum number of SG entries allowed */ #define MAX_SG_ENTRIES 8

+/* Different Header Struct for LS-CH3 */ +#ifdef CONFIG_ESBC_HDR_LS +struct fsl_secboot_img_hdr { + u8 barker[ESBC_BARKER_LEN]; /* barker code */ + u32 srk_tbl_off; + struct { + u8 num_srk; + u8 srk_sel; + u8 reserve; + u8 ie_flag; + } len_kr; + + u32 uid_flag; + + u32 psign; /* signature offset */ + u32 sign_len; /* length of the signature in bytes */ + + u64 pimg64; /* 64 bit pointer to ESBC Image */ + u32 img_size; /* ESBC client image size in bytes */ + u32 ie_key_sel; + + u32 fsl_uid_0; + u32 fsl_uid_1; + u32 oem_uid_0; + u32 oem_uid_1; + u32 oem_uid_2; + u32 oem_uid_3; + u32 oem_uid_4; + u32 reserved1[3]; +}; + +#ifdef CONFIG_KEY_REVOCATION +/* Srk table and key revocation check */ +#define UNREVOCABLE_KEY 8 +#define ALIGN_REVOC_KEY 7 +#define MAX_KEY_ENTRIES 8 +#endif + + +#else /* CONFIG_ESBC_HDR_LS */ + /* * ESBC uboot client header structure. * The struct contain the following fields @@ -109,6 +142,17 @@ struct fsl_secboot_img_hdr { u32 ie_key_sel; };

+#ifdef CONFIG_KEY_REVOCATION +/* Srk table and key revocation check */ +#define SRK_FLAG 0x01 +#define UNREVOCABLE_KEY 4 +#define ALIGN_REVOC_KEY 3 +#define MAX_KEY_ENTRIES 4 +#endif + +#endif /* CONFIG_ESBC_HDR_LS */ + + #if defined(CONFIG_FSL_ISBC_KEY_EXT) struct ie_key_table { u32 key_len;

Sec_init has been called in the starting to initialize SEC Block (CAAM) which will be used for Secure Boot validation later for both ls2080a qds and rdb. 64-bit address in ESBC Header has been enabled as this SoC is based on armv8. Secure Boot defconfigs created for boards (NOR Boot).

Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message Changes for v5: - Cleaned up commit message - Added new configs in defconfigs as per new intermediate patches

arch/arm/include/asm/fsl_secure_boot.h | 9 +++++++-- board/freescale/ls2080aqds/MAINTAINERS | 6 ++++++ board/freescale/ls2080aqds/ls2080aqds.c | 5 ++++- board/freescale/ls2080ardb/MAINTAINERS | 6 ++++++ board/freescale/ls2080ardb/ls2080ardb.c | 5 ++++- configs/ls2080aqds_SECURE_BOOT_defconfig | 20 ++++++++++++++++++++ configs/ls2080ardb_SECURE_BOOT_defconfig | 20 ++++++++++++++++++++ configs/ls2085aqds_SECURE_BOOT_defconfig | 20 ++++++++++++++++++++ configs/ls2085ardb_SECURE_BOOT_defconfig | 20 ++++++++++++++++++++ include/configs/ls2080aqds.h | 2 ++ include/configs/ls2080ardb.h | 2 ++ 11 files changed, 111 insertions(+), 4 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig

diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 4eb3b15..b745194 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -18,7 +18,9 @@ #ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB +#define CONFIG_CMD_HASH #define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_HW_ACCEL #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA_FREESCALE_EXP

@@ -42,8 +44,11 @@

#endif

-#ifdef CONFIG_LS1043A -/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit + * Similiarly for LS2080 and LS2085 + */ #define CONFIG_ESBC_ADDR_64BIT #endif

diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 6f99ad0..558cef1 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -8,3 +8,9 @@ F: configs/ls2080aqds_defconfig F: configs/ls2080aqds_nand_defconfig F: configs/ls2085aqds_defconfig F: configs/ls2085aqds_nand_defconfig + +LS2080A_SECURE_BOOT BOARD +M: Saksham Jain saksham.jain@nxp.freescale.com +S: Maintained +F: configs/ls2080aqds_SECURE_BOOT_defconfig +F: configs/ls2085aqds_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index aa256a2..ab101a4 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -19,6 +19,7 @@ #include <rtc.h> #include <asm/arch/soc.h> #include <hwconfig.h> +#include <fsl_sec.h>

#include "../common/qixis.h" #include "ls2080aqds_qixis.h" @@ -248,7 +249,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index c9f3459..0817711d 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -8,3 +8,9 @@ F: configs/ls2080ardb_defconfig F: configs/ls2080ardb_nand_defconfig F: configs/ls2085ardb_defconfig F: configs/ls2085ardb_nand_defconfig + +LS2080A_SECURE_BOOT BOARD +M: Saksham Jain saksham.jain@nxp.freescale.com +S: Maintained +F: configs/ls2080ardb_SECURE_BOOT_defconfig +F: configs/ls2085ardb_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c63b639..0c78a41 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -18,6 +18,7 @@ #include <environment.h> #include <i2c.h> #include <asm/arch/soc.h> +#include <fsl_sec.h>

#include "../common/qixis.h" #include "ls2080ardb_qixis.h" @@ -214,7 +215,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig new file mode 100644 index 0000000..408d1ee --- /dev/null +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_RSA=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig new file mode 100644 index 0000000..dde3311 --- /dev/null +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080ARDB=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_RSA=y diff --git a/configs/ls2085aqds_SECURE_BOOT_defconfig b/configs/ls2085aqds_SECURE_BOOT_defconfig new file mode 100644 index 0000000..f13ee41 --- /dev/null +++ b/configs/ls2085aqds_SECURE_BOOT_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_RSA=y diff --git a/configs/ls2085ardb_SECURE_BOOT_defconfig b/configs/ls2085ardb_SECURE_BOOT_defconfig new file mode 100644 index 0000000..aa66508 --- /dev/null +++ b/configs/ls2085ardb_SECURE_BOOT_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080ARDB=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A, SECURE_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_RSA=y diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index dab3820..91fad0a 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -399,4 +399,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_USB_STORAGE #define CONFIG_CMD_EXT2

+#include <asm/fsl_secure_boot.h> + #endif /* __LS2_QDS_H */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index b2c0181..81b9b8d 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -362,4 +362,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_PHY_AQUANTIA #endif

+#include <asm/fsl_secure_boot.h> + #endif /* __LS2_RDB_H */

During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it is executed. This requires a header for bootscript.

When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script.

For ls2080, NOR memory map is different from earlier arm SoCs. So a new address on NOR is used for this bootscript header (0x583920000). The Bootscript address is mentioned in this header along with addresses of other images.

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: -Cleaned up commit message Changes for v5: -Cleaned up commit message

arch/arm/include/asm/fsl_secure_boot.h | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index b745194..5575934 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -58,7 +58,11 @@ "setenv hwconfig 'fsl_ddr:ctlr_intlv=null,bank_intlv=null';"

/* The address needs to be modified according to NOR memory map */ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x583920000 +#else #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000 +#endif

#include <config_fsl_chain_trust.h> #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */

During Secure Boot, a bootscript is validated using its header. This patch copies both these images to DDR from NOR and then validates and executed them from DDR. (If NOR is the boot source for LS2080).

This copy step is done to make this step common across booting sources. Because in case of non-xip memories (e.g. NAND, SD) it is neccessary to copy both these images to DDR.

For other ARM Platforms (ls1043 and ls1020), header is not copied from NOR to DDR (otherwise customers will need to modify the existing headers).

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - for platform such as ls1043 and ls1021, boot header in NOR. Not copied to NOR. For them, fixed CONFIG_BOOTSCRIPT_HDR_ADDR to CONFIG_BS_HDR_ADDR_FLASH. Changes for v3: - No change Changes for v4: -Cleaned up commit message Changes for v5: - Cleaned up commit message

arch/arm/include/asm/fsl_secure_boot.h | 28 +++++++++++++++++++++++++--- include/config_fsl_chain_trust.h | 11 +++++++---- 2 files changed, 32 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 5575934..4d04eea 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -57,11 +57,33 @@ "setenv initrd_high 0xcfffffff;" \ "setenv hwconfig 'fsl_ddr:ctlr_intlv=null,bank_intlv=null';"

-/* The address needs to be modified according to NOR memory map */ +/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from + * Non-XIP Memory (Nand/SD)*/ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\ + defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif +/* The address needs to be modified according to NOR and DDR memory map */ #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x583920000 +#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000 +#define CONFIG_BS_ADDR_FLASH 0x583900000 +#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 +#define CONFIG_BS_ADDR_RAM 0xa3900000 +#else +#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000 +#define CONFIG_BS_ADDR_FLASH 0x60060000 +#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000 +#define CONFIG_BS_ADDR_RAM 0xa0060000 +#endif + +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM +#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM +#define CONFIG_BS_SIZE 0x00001000 #else -#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000 +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH +/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */ #endif

#include <config_fsl_chain_trust.h> diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 45dda56..aa222bb 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -65,8 +65,6 @@ "esbc_halt\0" #endif

-/* For secure boot flow, default environment used will be used */ -#if defined(CONFIG_SYS_RAMBOOT) #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ @@ -76,14 +74,19 @@ "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";"

+/* For secure boot flow, default environment used will be used */ +#if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_BS_COPY_CMD \ "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ "nand read $bs_ram $bs_flash $bs_size ;" #endif /* CONFIG_RAMBOOT_NAND */ -#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ - +#else +#define CONFIG_BS_COPY_CMD \ + "cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \ + "cp.b $bs_flash $bs_ram $bs_size ;" #endif +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */

#ifndef CONFIG_BS_COPY_ENV #define CONFIG_BS_COPY_ENV

"fdt_high" env variable has been changed to 0xa0000000 for ls2080 during Secure Boot. This env_varible is used to specify the upper limit to be used for copying flat device tree. This address must be visible to kernel.

The "fdt_high" value has been set during Secure Boot to same value as it's default value during non-secure boot.

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes Changes for v5: - Cleaned up commit message

arch/arm/include/asm/fsl_secure_boot.h | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 4d04eea..d576f2e 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -52,10 +52,17 @@ #define CONFIG_ESBC_ADDR_64BIT #endif

+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xa0000000;" \ + "setenv initrd_high 0xcfffffff;" \ + "setenv hwconfig 'fsl_ddr:ctlr_intlv=null,bank_intlv=null';" +#else #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfffffff;" \ "setenv initrd_high 0xcfffffff;" \ "setenv hwconfig 'fsl_ddr:ctlr_intlv=null,bank_intlv=null';" +#endif

/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/

The GUR (DCFG) registers in CCSR space are in Little Endian format for ls2080. Defined a config CONFIG_SYS_FSL_CCSR_GUR_LE in arch/arm/include/asm/arch-fsl-layerscape/config.h

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes Changes for v5: - Cleaned up commit message

arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 0445dbd..057912f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -82,6 +82,9 @@ /* Secure Boot */ #define CONFIG_ESBC_HDR_LS

+/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + /* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 #define CCI_MN_RNF_NODEID_LIST 0x180

During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs to be put in Bypass mode in uboot to enable CAAM transcations to pass through.

During Nonsecure Boot, SP BootROM doesn't enable SMMU and at reset SMMU is in bypass mode.

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes Changes for v5: - Cleaned up commit message

arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 +++++++++++++++++- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 213ce3a..a39d08d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -151,7 +151,14 @@ static void erratum_a009203(void) #endif #endif } - +void bypass_smmu(void) +{ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +} void fsl_lsch3_early_init_f(void) { erratum_a008751(); @@ -160,6 +167,15 @@ void fsl_lsch3_early_init_f(void) erratum_a009203(); erratum_a008514(); erratum_a008336(); +#ifdef CONFIG_CHAIN_OF_TRUST + /* In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + if (fsl_check_boot_mode_secure() == 1) + bypass_smmu(); +#endif }

#ifdef CONFIG_SCSI_AHCI_PLAT diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 1fc51e0..06d4856 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -83,6 +83,21 @@ /* Security Monitor */ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)

+/* MMU 500 */ +#define SMMU_SCR0 (SMMU_BASE + 0x0) +#define SMMU_SCR1 (SMMU_BASE + 0x4) +#define SMMU_SCR2 (SMMU_BASE + 0x8) +#define SMMU_SACR (SMMU_BASE + 0x10) +#define SMMU_IDR0 (SMMU_BASE + 0x20) +#define SMMU_IDR1 (SMMU_BASE + 0x24) + +#define SMMU_NSCR0 (SMMU_BASE + 0x400) +#define SMMU_NSCR2 (SMMU_BASE + 0x408) +#define SMMU_NSACR (SMMU_BASE + 0x410) + +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 +

/* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)

When MMU is disabled, 64bit Write must be at a memory aligned at 64-bit Boundary. So, this commit splits the 64-bit write into two 32-bit writes as the memory location is not guaranteed to be 64-bit aligned. The alignment exception only occurs when MMU is disabled.

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - No changes Changes for v5: - Cleaned up commit message

drivers/crypto/fsl/desc_constr.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index 2559ccd..db6ddee 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -85,10 +85,9 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) #ifdef CONFIG_PHYS_64BIT /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ - union ptr_addr_t ptr_addr; - ptr_addr.m_halfs.high = (u32)(ptr >> 32); - ptr_addr.m_halfs.low = (u32)ptr; - *offset = ptr_addr.m_whole; + union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset; + ptr_addr->m_halfs.high = (u32)(ptr >> 32); + ptr_addr->m_halfs.low = (u32)ptr; #else *offset = ptr; #endif

This commit solves CAAM coherency issue on ls2080. When Caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/write data from/to Caches and CAAM does from Main Memory. This forces data flushes to synchronize various data structures. But even if any data in proximity of these structures is read by core, these structures again are fetched in caches.

To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable.

So, this commit makes CAAM transcations as Write Back with Write and Read Allocate.

Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message Changes for v5: - Cleaned up commit message

drivers/crypto/fsl/jr.c | 13 +++++++++++++ drivers/crypto/fsl/jr.h | 3 +++ 2 files changed, 16 insertions(+)

diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b766470..894fa03 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -543,7 +543,20 @@ int sec_init(void) uint32_t liodn_s; #endif

+ /* + * Modifying CAAM Read/Write Attributes + * For LS2080A and LS2085A + * For AXI Write - Cacheable, Write Back, Write allocate + * For AXI Read - Cacheable, Read allocate + * Only For LS2080a and LS2085a, to solve CAAM coherency issues + */ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); + mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); +#else mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); +#endif + #ifdef CONFIG_PHYS_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 545d964..1642dbb 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -23,6 +23,9 @@ #define MCFGR_PS_SHIFT 16 #define MCFGR_AWCACHE_SHIFT 8 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_ARCACHE_SHIFT 12 +#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) + #define JR_INTMASK 0x00000001 #define JRCR_RESET 0x01 #define JRINT_ERR_HALT_INPROGRESS 0x4

For secure boot, currently we were using fixed bootargs for all SoCs. This is not needed and we can use the bootargs which are used in non-secure boot. Incase bootargs are not defined for non-secure boot of any platform, we use default bootargs.

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message Changes for v5: - Cleaned up commit message

include/config_fsl_chain_trust.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index aa222bb..566fd80 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -44,11 +44,18 @@ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" */

+#ifdef CONFIG_BOOTARGS +#define CONFIG_SET_BOOTARGS "setenv bootargs '" CONFIG_BOOTARGS" ';" +#else +#define CONFIG_SET_BOOTARGS "setenv bootargs 'root=/dev/ram " \ + "rw console=ttyS0,115200 ramdisk_size=600000';" +#endif + + #ifdef CONFIG_BOOTSCRIPT_KEY_HASH #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs 'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=600000';" \ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV \ "esbc_validate $bs_hdraddr " \ __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ @@ -57,8 +64,7 @@ #else #define CONFIG_SECBOOT \ "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs 'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=600000';" \ + CONFIG_SET_BOOTARGS \ CONFIG_EXTRA_ENV \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \

In case of fatal failure during secure boot execution (e.g. header not found), it is needed that the execution stops. Earlier, we assert reset request in case in case of failure. But if the RESET_REQ is not tied off to HRESET, this allows the execution to continue.

This can either be taken care in bootscript (Execute esbc_halt command in case of image verification process) or it can be taken care in Uboot Code. In this commit, doing the latter via esbc_halt().

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Chnages for v4: - Cleaned up commit message Changes for v5: - Cleaned up commit message

board/freescale/common/cmd_esbc_validate.c | 2 +- board/freescale/common/fsl_validate.c | 5 +++++ include/fsl_validate.h | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index dfa3e21..375bc24 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -8,7 +8,7 @@ #include <command.h> #include <fsl_validate.h>

-static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, +int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (fsl_check_boot_mode_secure() == 0) { diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index c12b9c9..95059c7 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -325,6 +325,8 @@ static void fsl_secboot_header_verification_failure(void)

printf("Generating reset request\n"); do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); }

/* @@ -355,6 +357,9 @@ static void fsl_secboot_image_verification_failure(void)

printf("Generating reset request\n"); do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); + } else { change_sec_mon_state(HPSR_SSM_ST_TRUST, HPSR_SSM_ST_NON_SECURE); diff --git a/include/fsl_validate.h b/include/fsl_validate.h index f812c1a..ff6f6b7 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -242,6 +242,9 @@ struct fsl_secboot_img_priv { uint32_t img_size; /* ESBC Image Size */ };

+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]); + int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, uintptr_t img_loc); int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,

Currently, fsl_secboot_validate function used to set env variable "img_addr" to contain address of image being validated.

The function has been changed to output image addr via argument img_addr_ptr. The command esbc_validate sets the env variable "img_addr".

This change helps when fsl_secboot_validate function is called from within UBOOT (because now instead of calling function "getenv("img_addr")" we can directly get the image address).

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes Changes for v4: - Cleaned up commit message Changes for v5: - Cleaned up commit message board/freescale/common/cmd_esbc_validate.c | 12 +++++++++++- board/freescale/common/fsl_validate.c | 26 +++++++++++++++----------- include/fsl_validate.h | 4 ++-- 3 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index 375bc24..cefe3cc 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -29,6 +29,8 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, char *hash_str = NULL; uintptr_t haddr; int ret; + uintptr_t img_addr = 0; + char buf[20];

if (argc < 2) return cmd_usage(cmdtp); @@ -43,7 +45,15 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, * part of header. So, the function is called * by passing this argument as 0. */ - ret = fsl_secboot_validate(haddr, hash_str, 0); + ret = fsl_secboot_validate(haddr, hash_str, &img_addr); + + /* Need to set "img_addr" even if validation failure. + * Required when SB_EN in RCW set and non-fatal error + * to continue U-Boot + */ + sprintf(buf, "%lx", img_addr); + setenv("img_addr", buf); + if (ret) return 1;

diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 95059c7..64e4e30 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -570,7 +570,7 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)

/* Update hash for actual Image */ ret = algo->hash_update(algo, ctx, - (u8 *)img->img_addr, img->img_size, 1); + (u8 *)(*(img->img_addr_ptr)), img->img_size, 1); if (ret) return ret;

@@ -646,7 +646,6 @@ static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img) */ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) { - char buf[20]; struct fsl_secboot_img_hdr *hdr = &img->hdr; void *esbc = (u8 *)(uintptr_t)img->ehdrloc; u8 *k, *s; @@ -661,17 +660,14 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) /* If Image Address is not passed as argument to function, * then Address and Size must be read from the Header. */ - if (img->img_addr == 0) { + if (*(img->img_addr_ptr) == 0) { #ifdef CONFIG_ESBC_ADDR_64BIT - img->img_addr = hdr->pimg64; + *(img->img_addr_ptr) = hdr->pimg64; #else - img->img_addr = hdr->pimg; + *(img->img_addr_ptr) = hdr->pimg; #endif }

- sprintf(buf, "%lx", img->img_addr); - setenv("img_addr", buf); - if (!hdr->img_size) return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE;

@@ -814,9 +810,17 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)

return 0; } - +/* haddr - Address of the header of image to be validated. + * arg_hash_str - Option hash string. If provided, this + * overides the key hash in the SFP fuses. + * img_addr_ptr - Optional pointer to address of image to be validated. + * If non zero addr, this overides the addr of image in header, + * otherwise updated to image addr in header. + * Acts as both input and output of function. + * This pointer shouldn't be NULL. + */ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, - uintptr_t img_addr) + uintptr_t *img_addr_ptr) { struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ulong hash[SHA256_BYTES/sizeof(ulong)]; @@ -869,7 +873,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, /* Update the information in Private Struct */ hdr = &img->hdr; img->ehdrloc = haddr; - img->img_addr = img_addr; + img->img_addr_ptr = img_addr_ptr; esbc = (u8 *)img->ehdrloc;

memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); diff --git a/include/fsl_validate.h b/include/fsl_validate.h index ff6f6b7..a71e1ce 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -238,7 +238,7 @@ struct fsl_secboot_img_priv {

struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */ uintptr_t ehdrloc; /* ESBC Header location */ - uintptr_t img_addr; /* ESBC Image Location */ + uintptr_t *img_addr_ptr; /* ESBC Image Location */ uint32_t img_size; /* ESBC Image Size */ };

@@ -246,7 +246,7 @@ int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);

int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, - uintptr_t img_loc); + uintptr_t *img_addr_ptr); int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,