From: Bartosz Golaszewski bgolaszewski@baylibre.com

This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski bgolaszewski@baylibre.com --- arch/arm/include/asm/mach-types.h | 1 - arch/arm/mach-davinci/Kconfig | 5 - board/omicron/calimain/Kconfig | 12 -- board/omicron/calimain/MAINTAINERS | 7 - board/omicron/calimain/Makefile | 8 - board/omicron/calimain/calimain.c | 145 --------------- configs/calimain_defconfig | 37 ---- include/configs/calimain.h | 272 ----------------------------- 8 files changed, 487 deletions(-) delete mode 100644 board/omicron/calimain/Kconfig delete mode 100644 board/omicron/calimain/MAINTAINERS delete mode 100644 board/omicron/calimain/Makefile delete mode 100644 board/omicron/calimain/calimain.c delete mode 100644 configs/calimain_defconfig delete mode 100644 include/configs/calimain.h

diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 9f82efe007..da2cc565f2 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -3475,7 +3475,6 @@ #define MACH_TYPE_SGH_I710 3525 #define MACH_TYPE_INTEGREPROSCB 3526 #define MACH_TYPE_MONZA 3527 -#define MACH_TYPE_CALIMAIN 3528 #define MACH_TYPE_MX6Q_SABREAUTO 3529 #define MACH_TYPE_GMA01X 3530 #define MACH_TYPE_SBC51 3531 diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 12b1e682e6..6031a0c0c7 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -27,10 +27,6 @@ config TARGET_OMAPL138_LCDK select SOC_DA8XX select SUPPORT_SPL

-config TARGET_CALIMAIN - bool "Calimain board" - select SOC_DA850 - config TARGET_LEGOEV3 bool "LEGO MINDSTORMS EV3" select MACH_DAVINCI_DA850_EVM @@ -149,7 +145,6 @@ endif source "board/Barix/ipam390/Kconfig" source "board/davinci/da8xxevm/Kconfig" source "board/davinci/ea20/Kconfig" -source "board/omicron/calimain/Kconfig" source "board/lego/ev3/Kconfig"

config SPL_LDSCRIPT diff --git a/board/omicron/calimain/Kconfig b/board/omicron/calimain/Kconfig deleted file mode 100644 index 1ec48e6b55..0000000000 --- a/board/omicron/calimain/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CALIMAIN - -config SYS_BOARD - default "calimain" - -config SYS_VENDOR - default "omicron" - -config SYS_CONFIG_NAME - default "calimain" - -endif diff --git a/board/omicron/calimain/MAINTAINERS b/board/omicron/calimain/MAINTAINERS deleted file mode 100644 index ad788a6dba..0000000000 --- a/board/omicron/calimain/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -CALIMAIN BOARD -M: Manfred Rudigier manfred.rudigier@omicronenergy.com -M: Christoph Rüdisser christoph.ruedisser@omicronenergy.com -S: Maintained -F: board/omicron/calimain/ -F: include/configs/calimain.h -F: configs/calimain_defconfig diff --git a/board/omicron/calimain/Makefile b/board/omicron/calimain/Makefile deleted file mode 100644 index d873f0d736..0000000000 --- a/board/omicron/calimain/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net - -obj-y := calimain.o diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c deleted file mode 100644 index 6f7b2b8cb1..0000000000 --- a/board/omicron/calimain/calimain.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 OMICRON electronics GmbH - * - * Based on da850evm.c. Original Copyrights follow: - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. nick.thompson@gefanuc.com - * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net - */ - -#include <common.h> -#include <i2c.h> -#include <net.h> -#include <netdev.h> -#include <watchdog.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/gpio.h> -#include <asm/ti-common/davinci_nand.h> -#include <asm/arch/emac_defs.h> -#include <asm/arch/pinmux_defs.h> -#include <asm/arch/davinci_misc.h> -#include <asm/arch/timer_defs.h> -#include "../../../drivers/gpio/da8xx_gpio.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define CALIMAIN_HWVERSION_MASK 0x7f000000 -#define CALIMAIN_HWVERSION_SHIFT 24 - -/* Hardware version pinmux settings */ -const struct pinmux_config hwversion_pins[] = { - { pinmux(16), 8, 2 }, /* GP7[15] */ - { pinmux(16), 8, 3 }, /* GP7[14] */ - { pinmux(16), 8, 4 }, /* GP7[13] */ - { pinmux(16), 8, 5 }, /* GP7[12] */ - { pinmux(16), 8, 6 }, /* GP7[11] */ - { pinmux(16), 8, 7 }, /* GP7[10] */ - { pinmux(17), 8, 0 }, /* GP7[9] */ - { pinmux(17), 8, 1 } /* GP7[8] */ -}; - -const struct pinmux_resource pinmuxes[] = { - PINMUX_ITEM(uart2_pins_txrx), - PINMUX_ITEM(emac_pins_mii), - PINMUX_ITEM(emac_pins_mdio), - PINMUX_ITEM(emifa_pins_nor), - PINMUX_ITEM(emifa_pins_cs2), - PINMUX_ITEM(emifa_pins_cs3), -}; - -const int pinmuxes_size = ARRAY_SIZE(pinmuxes); - -const struct lpsc_resource lpsc[] = { - { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ - { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART2 }, /* console */ - { DAVINCI_LPSC_GPIO }, -}; - -const int lpsc_size = ARRAY_SIZE(lpsc); - -/* read board revision from GPIO7[8..14] */ -u32 get_board_rev(void) -{ - lpsc_on(DAVINCI_LPSC_GPIO); - if (davinci_configure_pin_mux(hwversion_pins, - ARRAY_SIZE(hwversion_pins)) != 0) - return 0xffffffff; - - return (davinci_gpio_bank67->in_data & CALIMAIN_HWVERSION_MASK) - >> CALIMAIN_HWVERSION_SHIFT; -} - -/* - * determine the oscillator frequency depending on the board revision - * - * rev 0x00 ... 25 MHz oscillator - * rev 0x01 ... 24 MHz oscillator - */ -int calimain_get_osc_freq(void) -{ - u32 rev; - int freq; - - rev = get_board_rev(); - switch (rev) { - case 0x00: - freq = 25000000; - break; - default: - freq = 24000000; - break; - } - return freq; -} - -int board_init(void) -{ - int val; - - irq_init(); - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - -#ifdef CONFIG_DRIVER_TI_EMAC - /* select emac MII mode */ - val = readl(&davinci_syscfg_regs->cfgchip3); - val &= ~(1 << 8); - writel(val, &davinci_syscfg_regs->cfgchip3); -#endif /* CONFIG_DRIVER_TI_EMAC */ - -#ifdef CONFIG_HW_WATCHDOG - davinci_hw_watchdog_enable(); -#endif - - printf("Input clock frequency: %d Hz\n", calimain_get_osc_freq()); - printf("Board revision: %d\n", get_board_rev()); - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_EMAC -/* - * Initializes on-board ethernet controllers. - */ -int board_eth_init(bd_t *bis) -{ - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - - return 0; -} -#endif /* CONFIG_DRIVER_TI_EMAC */ - -#ifdef CONFIG_HW_WATCHDOG -void hw_watchdog_reset(void) -{ - davinci_hw_watchdog_reset(); -} -#endif diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig deleted file mode 100644 index f2b0814acf..0000000000 --- a/configs/calimain_defconfig +++ /dev/null @@ -1,37 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_SYS_TEXT_BASE=0x60000000 -CONFIG_TARGET_CALIMAIN=y -CONFIG_DA850_LOWLEVEL=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_BOOTDELAY=0 -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Calimain > " -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_STOP_STR="\x0b" -CONFIG_CMD_IMLS=y -CONFIG_CMD_ASKENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DIAG=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0x01C23000 -CONFIG_DA8XX_GPIO=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MII=y -CONFIG_DRIVER_TI_EMAC=y -CONFIG_SYS_NS16550=y diff --git a/include/configs/calimain.h b/include/configs/calimain.h deleted file mode 100644 index e77218466f..0000000000 --- a/include/configs/calimain.h +++ /dev/null @@ -1,272 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011-2014 OMICRON electronics GmbH - * - * Based on da850evm.h. Original Copyrights follow: - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ -#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN - -/* - * SoC Configuration - */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_HW_WATCHDOG -#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE -#define CONFIG_SYS_WDT_PERIOD_LOW \ - (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */ -#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 -#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) - -/* - * PLL configuration - */ - -#define CONFIG_SYS_DA850_PLL0_PLLM \ - ((calimain_get_osc_freq() == 25000000) ? 23 : 24) -#define CONFIG_SYS_DA850_PLL1_PLLM \ - ((calimain_get_osc_freq() == 25000000) ? 20 : 21) - -/* - * DDR2 memory configuration - */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ - DV_DDR_PHY_EXT_STRBEN | \ - (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ - (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ - (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ - (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ - (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ - (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ - (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ - (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \ - (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) - -/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 - -#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ - (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ - (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ - (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ - (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ - (1 << DV_DDR_SDTMR1_WTR_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ - (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ - (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ - (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ - (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ - (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ - (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ - (2 << DV_DDR_SDTMR2_CKE_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 - -/* - * Flash memory timing - */ - -#define CONFIG_SYS_DA850_CS2CFG ( \ - DAVINCI_ABCR_WSETUP(2) | \ - DAVINCI_ABCR_WSTROBE(5) | \ - DAVINCI_ABCR_WHOLD(3) | \ - DAVINCI_ABCR_RSETUP(1) | \ - DAVINCI_ABCR_RSTROBE(14) | \ - DAVINCI_ABCR_RHOLD(0) | \ - DAVINCI_ABCR_TA(3) | \ - DAVINCI_ABCR_ASIZE_16BIT) - -/* single 64 MB NOR flash device connected to CS2 and CS3 */ -#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ - DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ - DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ - DAVINCI_SYSCFG_SUSPSRC_UART2 | \ - DAVINCI_SYSCFG_SUSPSRC_EMAC | \ - DAVINCI_SYSCFG_SUSPSRC_I2C) - -/* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) - -/* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20)) - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ -#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ -#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ -#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2) -#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */ -#define CONFIG_SYS_MAX_FLASH_SECT \ - ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3) - -/* - * Network & Ethernet Configuration - */ -#ifdef CONFIG_DRIVER_TI_EMAC -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -/* - * U-Boot general configuration - */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_LOADADDR 0xc0700000 -#define CONFIG_MX_CYCLIC - -/* - * Linux Information - */ -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;" -#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ -#define CONFIG_RESET_TO_RETRY - -/* - * Default environment settings - * gpio0 = button, gpio1 = led green, gpio2 = led red - * verify = n ... disable kernel checksum verification for faster booting - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "tftpdir=calimero\0" \ - "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \ - "erase 0x60800000 +0x400000; " \ - "cp.b $loadaddr 0x60800000 $filesize\0" \ - "flashrootfs=" \ - "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \ - "erase 0x60c00000 +0x2e00000; " \ - "cp.b $loadaddr 0x60c00000 $filesize\0" \ - "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \ - "protect off all; " \ - "erase 0x60000000 +0x80000; " \ - "cp.b $loadaddr 0x60000000 $filesize\0" \ - "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \ - "erase 0x60080000 +0x780000; " \ - "cp.b $loadaddr 0x60080000 $filesize\0" \ - "erase_persistent=erase 0x63a00000 +0x600000;\0" \ - "bootnor=setenv bootargs console=ttyS2,115200n8 " \ - "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ - "rootwait ethaddr=$ethaddr; " \ - "gpio c 1; gpio s 2; bootm 0x60800000\0" \ - "bootrlk=gpio s 1; gpio s 2;" \ - "setenv bootargs console=ttyS2,115200n8 " \ - "ethaddr=$ethaddr; bootm 0x60080000\0" \ - "boottftp=setenv bootargs console=ttyS2,115200n8 " \ - "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ - "rootwait ethaddr=$ethaddr; " \ - "tftpboot $loadaddr $tftpdir/uImage;" \ - "gpio c 1; gpio s 2; bootm $loadaddr\0" \ - "checkupdate=if test -n $update_flag; then " \ - "echo Previous update failed - starting RLK; " \ - "run bootrlk; fi; " \ - "if test -n $initial_setup; then " \ - "echo Running initial setup procedure; " \ - "sleep 1; run flashall; fi\0" \ - "product=accessory\0" \ - "serial=XX12345\0" \ - "checknor=" \ - "if gpio i 0; then run bootnor; fi;\0" \ - "checkrlk=" \ - "if gpio i 0; then run bootrlk; fi;\0" \ - "checkbutton=" \ - "run checknor; sleep 1;" \ - "run checknor; sleep 1;" \ - "run checknor; sleep 1;" \ - "run checknor; sleep 1;" \ - "run checknor;" \ - "gpio s 1; gpio s 2;" \ - "echo ---- Release button to boot RLK ----;" \ - "run checkrlk; sleep 1;" \ - "run checkrlk; sleep 1;" \ - "run checkrlk; sleep 1;" \ - "run checkrlk; sleep 1;" \ - "run checkrlk; sleep 1;" \ - "run checkrlk;" \ - "echo ---- Factory reset requested ----;" \ - "gpio c 1;" \ - "setenv factory_reset true;" \ - "saveenv;" \ - "run bootnor;\0" \ - "flashall=run flashrlk;" \ - "run flashkernel;" \ - "run flashrootfs;" \ - "setenv erase_datafs true;" \ - "setenv initial_setup;" \ - "saveenv;" \ - "run bootnor;\0" \ - "verify=n\0" \ - "clearenv=protect off all;" \ - "erase 0x60040000 +0x40000;\0" \ - "altbootcmd=run bootrlk\0" - -#define CONFIG_PREBOOT \ - "echo Version: $ver; " \ - "echo Serial: $serial; " \ - "echo MAC: $ethaddr; " \ - "echo Product: $product; " \ - "gpio c 1; gpio c 2;" - -/* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 -/* initial stack pointer in internal SRAM */ -#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) - -#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ - -#ifndef __ASSEMBLY__ -int calimain_get_osc_freq(void); -#endif - -#include <asm/arch/hardware.h> - -#endif /* __CONFIG_H */

From: Bartosz Golaszewski bgolaszewski@baylibre.com

This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski bgolaszewski@baylibre.com --- arch/arm/include/asm/mach-types.h | 1 - arch/arm/mach-davinci/Kconfig | 7 - board/davinci/ea20/Kconfig | 12 -- board/davinci/ea20/MAINTAINERS | 6 - board/davinci/ea20/Makefile | 8 - board/davinci/ea20/ea20.c | 337 ------------------------------ configs/ea20_defconfig | 48 ----- include/configs/ea20.h | 227 -------------------- 8 files changed, 646 deletions(-) delete mode 100644 board/davinci/ea20/Kconfig delete mode 100644 board/davinci/ea20/MAINTAINERS delete mode 100644 board/davinci/ea20/Makefile delete mode 100644 board/davinci/ea20/ea20.c delete mode 100644 configs/ea20_defconfig delete mode 100644 include/configs/ea20.h

diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index da2cc565f2..d882f19b81 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -2960,7 +2960,6 @@ #define MACH_TYPE_AX8008 2999 #define MACH_TYPE_GNET_SGCE 3000 #define MACH_TYPE_PXWNAS_500_1000 3001 -#define MACH_TYPE_EA20 3002 #define MACH_TYPE_AWM2 3003 #define MACH_TYPE_TI8148EVM 3004 #define MACH_TYPE_SEABOARD 3005 diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 6031a0c0c7..c2a5759f45 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -16,12 +16,6 @@ config TARGET_DA850EVM select SOC_DA850 select SUPPORT_SPL

-config TARGET_EA20 - bool "EA20 board" - select BOARD_LATE_INIT - select MACH_DAVINCI_DA850_EVM - select SOC_DA850 - config TARGET_OMAPL138_LCDK bool "OMAPL138 LCDK" select SOC_DA8XX @@ -144,7 +138,6 @@ endif

source "board/Barix/ipam390/Kconfig" source "board/davinci/da8xxevm/Kconfig" -source "board/davinci/ea20/Kconfig" source "board/lego/ev3/Kconfig"

config SPL_LDSCRIPT diff --git a/board/davinci/ea20/Kconfig b/board/davinci/ea20/Kconfig deleted file mode 100644 index ae5b16e142..0000000000 --- a/board/davinci/ea20/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_EA20 - -config SYS_BOARD - default "ea20" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "ea20" - -endif diff --git a/board/davinci/ea20/MAINTAINERS b/board/davinci/ea20/MAINTAINERS deleted file mode 100644 index 5c300a3cbf..0000000000 --- a/board/davinci/ea20/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EA20 BOARD -M: Stefano Babic sbabic@denx.de -S: Maintained -F: board/davinci/ea20/ -F: include/configs/ea20.h -F: configs/ea20_defconfig diff --git a/board/davinci/ea20/Makefile b/board/davinci/ea20/Makefile deleted file mode 100644 index 2ea42d9967..0000000000 --- a/board/davinci/ea20/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net - -obj-y += ea20.o diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c deleted file mode 100644 index 573e0ae97a..0000000000 --- a/board/davinci/ea20/ea20.c +++ /dev/null @@ -1,337 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de - * - * Based on da850evm.c, original Copyrights follow: - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on da830evm.c. Original Copyrights follow: - * - * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. nick.thompson@gefanuc.com - * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net - */ - -#include <common.h> -#include <i2c.h> -#include <net.h> -#include <netdev.h> -#include <asm/mach-types.h> -#include <asm/arch/hardware.h> -#include <asm/ti-common/davinci_nand.h> -#include <asm/arch/emac_defs.h> -#include <asm/io.h> -#include <asm/arch/davinci_misc.h> -#include <asm/gpio.h> -#include "../../../drivers/video/da8xx-fb.h" - -DECLARE_GLOBAL_DATA_PTR; - -static const struct da8xx_panel lcd_panel = { - /* Casio COM57H531x */ - .name = "Casio_COM57H531x", - .width = 640, - .height = 480, - .hfp = 12, - .hbp = 144, - .hsw = 30, - .vfp = 10, - .vbp = 35, - .vsw = 3, - .pxl_clk = 25000000, - .invert_pxl_clk = 0, -}; - -static const struct display_panel disp_panel = { - QVGA, - 16, - 16, - COLOR_ACTIVE, -}; - -static const struct lcd_ctrl_config lcd_cfg = { - &disp_panel, - .ac_bias = 255, - .ac_bias_intrpt = 0, - .dma_burst_sz = 16, - .bpp = 16, - .fdd = 255, - .tft_alt_mode = 0, - .stn_565_mode = 0, - .mono_8bit_mode = 0, - .invert_line_clock = 1, - .invert_frm_clock = 1, - .sync_edge = 0, - .sync_ctrl = 1, - .raster_order = 0, -}; - -/* SPI0 pin muxer settings */ -static const struct pinmux_config spi1_pins[] = { - { pinmux(5), 1, 1 }, - { pinmux(5), 1, 2 }, - { pinmux(5), 1, 4 }, - { pinmux(5), 1, 5 } -}; - -/* I2C pin muxer settings */ -static const struct pinmux_config i2c_pins[] = { - { pinmux(4), 2, 2 }, - { pinmux(4), 2, 3 } -}; - -/* UART0 pin muxer settings */ -static const struct pinmux_config uart_pins[] = { - { pinmux(3), 2, 7 }, - { pinmux(3), 2, 6 }, - { pinmux(3), 2, 4 }, - { pinmux(3), 2, 5 } -}; - -#ifdef CONFIG_DRIVER_TI_EMAC -#define HAS_RMII 1 -static const struct pinmux_config emac_pins[] = { - { pinmux(14), 8, 2 }, - { pinmux(14), 8, 3 }, - { pinmux(14), 8, 4 }, - { pinmux(14), 8, 5 }, - { pinmux(14), 8, 6 }, - { pinmux(14), 8, 7 }, - { pinmux(15), 8, 1 }, - { pinmux(4), 8, 0 }, - { pinmux(4), 8, 1 } -}; -#endif - -#ifdef CONFIG_NAND_DAVINCI -const struct pinmux_config nand_pins[] = { - { pinmux(7), 1, 0}, /* CS2 */ - { pinmux(7), 0, 1}, /* CS3 in three state*/ - { pinmux(7), 1, 4 }, /* EMA_WE */ - { pinmux(7), 1, 5 }, /* EMA_OE */ - { pinmux(9), 1, 0 }, /* EMA_D[7] */ - { pinmux(9), 1, 1 }, /* EMA_D[6] */ - { pinmux(9), 1, 2 }, /* EMA_D[5] */ - { pinmux(9), 1, 3 }, /* EMA_D[4] */ - { pinmux(9), 1, 4 }, /* EMA_D[3] */ - { pinmux(9), 1, 5 }, /* EMA_D[2] */ - { pinmux(9), 1, 6 }, /* EMA_D[1] */ - { pinmux(9), 1, 7 }, /* EMA_D[0] */ - { pinmux(12), 1, 5 }, /* EMA_A[2] */ - { pinmux(12), 1, 6 }, /* EMA_A[1] */ - { pinmux(6), 1, 0 } /* EMA_CLK */ -}; -#endif - -const struct pinmux_config gpio_pins[] = { - { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/ - { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/ - { pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/ - { pinmux(19), 8, 5 }, /* GPIO6[1] DISP_ON */ - { pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/ -}; - -const struct pinmux_config lcd_pins[] = { - { pinmux(17), 2, 1 }, /* LCD_D_0 */ - { pinmux(17), 2, 0 }, /* LCD_D_1 */ - { pinmux(16), 2, 7 }, /* LCD_D_2 */ - { pinmux(16), 2, 6 }, /* LCD_D_3 */ - { pinmux(16), 2, 5 }, /* LCD_D_4 */ - { pinmux(16), 2, 4 }, /* LCD_D_5 */ - { pinmux(16), 2, 3 }, /* LCD_D_6 */ - { pinmux(16), 2, 2 }, /* LCD_D_7 */ - { pinmux(18), 2, 1 }, /* LCD_D_8 */ - { pinmux(18), 2, 0 }, /* LCD_D_9 */ - { pinmux(17), 2, 7 }, /* LCD_D_10 */ - { pinmux(17), 2, 6 }, /* LCD_D_11 */ - { pinmux(17), 2, 5 }, /* LCD_D_12 */ - { pinmux(17), 2, 4 }, /* LCD_D_13 */ - { pinmux(17), 2, 3 }, /* LCD_D_14 */ - { pinmux(17), 2, 2 }, /* LCD_D_15 */ - { pinmux(18), 2, 6 }, /* LCD_PCLK */ - { pinmux(19), 2, 0 }, /* LCD_HSYNC */ - { pinmux(19), 2, 1 }, /* LCD_VSYNC */ - { pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */ -}; - -const struct pinmux_config halten_pin[] = { - { pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */ -}; - -static const struct pinmux_resource pinmuxes[] = { -#ifdef CONFIG_SPI_FLASH - PINMUX_ITEM(spi1_pins), -#endif - PINMUX_ITEM(uart_pins), - PINMUX_ITEM(i2c_pins), -#ifdef CONFIG_NAND_DAVINCI - PINMUX_ITEM(nand_pins), -#endif -#ifdef CONFIG_VIDEO - PINMUX_ITEM(lcd_pins), -#endif -}; - -static const struct lpsc_resource lpsc[] = { - { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ - { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ - { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART0 }, /* console */ - { DAVINCI_LPSC_GPIO }, - { DAVINCI_LPSC_LCDC }, /* LCD */ -}; - -int board_early_init_f(void) -{ - /* PinMux for GPIO */ - if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) - return 1; - - /* Set DISP_ON high to enable LCD output*/ - gpio_direction_output(97, 1); - - /* Set the RESETOUTn low */ - gpio_direction_output(111, 0); - - /* Set U0_SW0 low for UART0 as console*/ - gpio_direction_output(106, 0); - - /* Set U0_SW1 low for UART0 as console*/ - gpio_direction_output(108, 0); - - /* Set LCD_B_PWR low to power down LCD Backlight*/ - gpio_direction_output(102, 0); - - irq_init(); - - /* - * NAND CS setup - cycle counts based on da850evm NAND timings in the - * Linux kernel @ 25MHz EMIFA - */ -#ifdef CONFIG_NAND_DAVINCI - writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(1) | - DAVINCI_ABCR_WHOLD(0) | - DAVINCI_ABCR_RSETUP(0) | - DAVINCI_ABCR_RSTROBE(1) | - DAVINCI_ABCR_RHOLD(0) | - DAVINCI_ABCR_TA(0) | - DAVINCI_ABCR_ASIZE_8BIT), - &davinci_emif_regs->ab1cr); /* CS2 */ -#endif - - /* - * Power on required peripherals - * ARM does not have access by default to PSC0 and PSC1 - * assuming here that the DSP bootloader has set the IOPU - * such that PSC access is available to ARM - */ - if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) - return 1; - - /* setup the SUSPSRC for ARM to control emulation suspend */ - writel(readl(&davinci_syscfg_regs->suspsrc) & - ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | - DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | - DAVINCI_SYSCFG_SUSPSRC_UART0), - &davinci_syscfg_regs->suspsrc); - - /* configure pinmux settings */ - if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) - return 1; - -#ifdef CONFIG_DRIVER_TI_EMAC - if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) - return 1; - - davinci_emac_mii_mode_sel(HAS_RMII); -#endif /* CONFIG_DRIVER_TI_EMAC */ - - /* enable the console UART */ - writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | - DAVINCI_UART_PWREMU_MGMT_UTRST), - &davinci_uart0_ctrl_regs->pwremu_mgmt); - - /* - * Reconfigure the LCDC priority to the highest to ensure that - * the throughput/latency requirements for the LCDC are met. - */ - writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff, - &davinci_syscfg_regs->mstpri[2]); - - - return 0; -} - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_init(void) -{ - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_EA20; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - da8xx_video_init(&lcd_panel, &lcd_cfg, 16); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT - -int board_late_init(void) -{ - unsigned char buf[2]; - int ret; - - /* PinMux for HALTEN */ - if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0) - return 1; - - /* Set HALTEN to high */ - gpio_direction_output(134, 1); - - /* Set fixed contrast settings for LCD via I2C potentiometer */ - buf[0] = 0x00; - buf[1] = 0xd7; - ret = i2c_write(0x2e, 6, 1, buf, 2); - if (ret) - puts("\nContrast Settings FAILED\n"); - - /* Set LCD_B_PWR high to power up LCD Backlight*/ - gpio_set_value(102, 1); - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ - -#ifdef CONFIG_DRIVER_TI_EMAC - -/* - * Initializes on-board ethernet controllers. - */ -int board_eth_init(bd_t *bis) -{ - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - - /* - * This board has a RMII PHY. However, the MDC line on the SOM - * must not be disabled (there is no MII PHY on the - * baseboard) via the GPIO2[6], because this pin - * disables at the same time the SPI flash. - */ - - return 0; -} -#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig deleted file mode 100644 index ceab73d982..0000000000 --- a/configs/ea20_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_SYS_TEXT_BASE=0xc1080000 -CONFIG_TARGET_EA20=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="ea20 > " -CONFIG_CMD_ASKENV=y -CONFIG_CRC32_VERIFY=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_DIAG=y -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_DA8XX_GPIO=y -CONFIG_SYS_I2C_DAVINCI=y -# CONFIG_MMC is not set -CONFIG_NAND=y -CONFIG_NAND_DAVINCI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MII=y -CONFIG_DRIVER_TI_EMAC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DAVINCI_SPI=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/include/configs/ea20.h b/include/configs/ea20.h deleted file mode 100644 index 88f2e17d40..0000000000 --- a/include/configs/ea20.h +++ /dev/null @@ -1,227 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ -#define CONFIG_USE_SPIFLASH -#define CONFIG_SYS_USE_NAND -#define CONFIG_DRIVER_TI_EMAC_USE_RMII -#define CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE -#define CONFIG_PREBOOT - -/* - * SoC Configuration - */ -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 4*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - -/* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) - -/* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ -#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) - -#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) - -/* - * I2C Configuration - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ - -/* - * Network & Ethernet Configuration - */ -#ifdef CONFIG_DRIVER_TI_EMAC -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -#ifdef CONFIG_USE_SPIFLASH -#define CONFIG_ENV_SIZE (8 << 10) -#define CONFIG_ENV_OFFSET 0x80000 -#define CONFIG_ENV_SECT_SIZE (64 << 10) -#endif - -#if defined(CONFIG_VIDEO) -#define CONFIG_VIDEO_DA8XX -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#endif - -/* - * U-Boot general configuration - */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_MX_CYCLIC - -/* - * Linux Information - */ -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -/* NAND Setup */ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_NO_SUBPAGE -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE -#undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#endif - -#if !defined(CONFIG_SYS_USE_NAND) && \ - !defined(CONFIG_USE_NOR) && \ - !defined(CONFIG_USE_SPIFLASH) -#define CONFIG_ENV_SIZE (16 << 10) -#endif - -/* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) -/* - * Default environment and default scripts - * to update uboot and load kernel - */ - -#define CONFIG_HOSTNAME "ea20" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "as=3\0" \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "rfsbargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rfsbpath}\0" \ - "testrfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${testrfspath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw initrd=" \ - "0x${ramdisk_addr_r},4M\0" \ - "mtdids=nand0=davinci_nand.0\0" \ - "serverip=192.168.5.249\0" \ - "ipaddr=192.168.5.248\0" \ - "rootpath=/opt/eldk/arm\0" \ - "splashpos=230,180\0" \ - "testrfspath=/opt/eldk/test_arm\0" \ - "nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc " \ - "ubi.mtd=${as} root=ubi0:rootfs\0" \ - "nandrwargs=setenv bootargs rootfstype=ubifs rw chk_data_crc " \ - "ubi.mtd=${as} root=ubi0:rootfs\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=${consoledev},${baudrate}n8\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "addmem=setenv bootargs ${bootargs} mem=${memory}\0" \ - "consoledev=ttyS0\0" \ - "loadaddr=c0000014\0" \ - "memory=32M\0" \ - "kernel_addr_r=c0700000\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "ramdisk_file=" CONFIG_HOSTNAME "/image.ext2\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc addmem;" \ - "bootm ${kernel_addr_r}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run nfsargs addip addtty addmtd addmisc addmem;" \ - "bootm ${kernel_addr_r}\0" \ - "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \ - "run rfsbargs addip addtty addmtd addmisc addmem; " \ - "bootm ${kernel_addr_r}\0" \ - "net_testrfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run testrfsargs addip addtty addmtd addmisc addmem; " \ - "bootm ${kernel_addr_r}\0" \ - "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ - "nand_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \ - "ubifsload ${kernel_addr_r} /boot/uImage;" \ - "ubifsumount; run nandargs addip addtty " \ - "addmtd addmisc addmem;clrlogo;" \ - "bootm ${kernel_addr_r}\0" \ - "nand_nandrw=ubi part nand0,${as};ubifsmount ubi:rootfs;" \ - "ubifsload ${kernel_addr_r} /boot/uImage;" \ - "ubifsumount; run nandrwargs addip addtty " \ - "addmtd addmisc addmem;clrlogo;" \ - "bootm ${kernel_addr_r}\0" \ - "net_nandrw=tftp ${kernel_addr_r} ${bootfile}; run nandrwargs" \ - " addip addtty addmtd addmisc addmem;" \ - "clrlogo;bootm ${kernel_addr_r}\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "load_magic=if sf probe 0;then sf " \ - "read c0000000 0x10000 0x60000;fi\0" \ - "load_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \ - "if ubifsload c0000014 /boot/u-boot.bin;" \ - "then mw c0000008 ${filesize};else echo Error reading" \ - " u-boot from nand!;fi\0" \ - "load_net=if sf probe 0;then sf read c0000000 0x10000 " \ - "0x60000;tftp c0000014 ${u-boot};" \ - "mw c0000008 ${filesize};fi\0" \ - "upd=if sf probe 0;then sf erase 10000 60000;" \ - "sf write c0000000 10000 60000;fi\0" \ - "ublupdate=if tftp C0700000 ${ublname};then sf probe 0; " \ - "sf erase 0 10000;" \ - "sf write 0xc0700000 0 ${filesize};fi\0" \ - "ubootupd_net=if run load_net;then echo Updating u-boot;" \ - "if run upd; then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \ - "bootcmd=run net_testrfs\0" - -#include <asm/arch/hardware.h> - -#endif /* __CONFIG_H */

From: Bartosz Golaszewski bgolaszewski@baylibre.com

This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski bgolaszewski@baylibre.com --- arch/arm/include/asm/mach-types.h | 1 - arch/arm/mach-omap2/omap3/Kconfig | 7 - board/compulab/cm_t3517/Kconfig | 12 -- board/compulab/cm_t3517/MAINTAINERS | 6 - board/compulab/cm_t3517/Makefile | 7 - board/compulab/cm_t3517/cm_t3517.c | 240 ---------------------------- board/compulab/cm_t3517/mux.c | 235 --------------------------- board/compulab/common/eeprom.c | 2 +- configs/cm_t3517_defconfig | 60 ------- include/configs/cm_t3517.h | 219 ------------------------- scripts/config_whitelist.txt | 1 - 11 files changed, 1 insertion(+), 789 deletions(-) delete mode 100644 board/compulab/cm_t3517/Kconfig delete mode 100644 board/compulab/cm_t3517/MAINTAINERS delete mode 100644 board/compulab/cm_t3517/Makefile delete mode 100644 board/compulab/cm_t3517/cm_t3517.c delete mode 100644 board/compulab/cm_t3517/mux.c delete mode 100644 configs/cm_t3517_defconfig delete mode 100644 include/configs/cm_t3517.h

diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index d882f19b81..a3a2b729b1 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -2716,7 +2716,6 @@ #define MACH_TYPE_VPNEXT_MPU 2747 #define MACH_TYPE_BCMRING_TABLET_V1 2748 #define MACH_TYPE_SGARM10 2749 -#define MACH_TYPE_CM_T3517 2750 #define MACH_TYPE_OMAP3_CPS 2751 #define MACH_TYPE_AXAR1500_RECEIVER 2752 #define MACH_TYPE_WBD222 2753 diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index bc2b6f180c..9bc616c286 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -54,12 +54,6 @@ config TARGET_CM_T35 select OMAP3_GPIO_5 select OMAP3_GPIO_6 if LED_STATUS

-config TARGET_CM_T3517 - bool "CompuLab CM-T3517 boards" - select OMAP3_GPIO_2 - select OMAP3_GPIO_5 - select OMAP3_GPIO_6 if LED_STATUS - config TARGET_DEVKIT8000 bool "TimLL OMAP3 Devkit8000" select DM @@ -198,7 +192,6 @@ source "board/logicpd/am3517evm/Kconfig" source "board/teejet/mt_ventoux/Kconfig" source "board/ti/beagle/Kconfig" source "board/compulab/cm_t35/Kconfig" -source "board/compulab/cm_t3517/Kconfig" source "board/timll/devkit8000/Kconfig" source "board/ti/evm/Kconfig" source "board/isee/igep00x0/Kconfig" diff --git a/board/compulab/cm_t3517/Kconfig b/board/compulab/cm_t3517/Kconfig deleted file mode 100644 index 2f5473d76a..0000000000 --- a/board/compulab/cm_t3517/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CM_T3517 - -config SYS_BOARD - default "cm_t3517" - -config SYS_VENDOR - default "compulab" - -config SYS_CONFIG_NAME - default "cm_t3517" - -endif diff --git a/board/compulab/cm_t3517/MAINTAINERS b/board/compulab/cm_t3517/MAINTAINERS deleted file mode 100644 index fbb6882138..0000000000 --- a/board/compulab/cm_t3517/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM_T3517 BOARD -M: Igor Grinberg grinberg@compulab.co.il -S: Maintained -F: board/compulab/cm_t3517/ -F: include/configs/cm_t3517.h -F: configs/cm_t3517_defconfig diff --git a/board/compulab/cm_t3517/Makefile b/board/compulab/cm_t3517/Makefile deleted file mode 100644 index bfcb75f98f..0000000000 --- a/board/compulab/cm_t3517/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> -# -# Authors: Igor Grinberg grinberg@compulab.co.il - -obj-y += cm_t3517.o mux.o diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c deleted file mode 100644 index 668bb7631a..0000000000 --- a/board/compulab/cm_t3517/cm_t3517.c +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> - * - * Authors: Igor Grinberg grinberg@compulab.co.il - */ - -#include <common.h> -#include <environment.h> -#include <status_led.h> -#include <net.h> -#include <netdev.h> -#include <usb.h> -#include <mmc.h> -#include <linux/compiler.h> -#include <linux/usb/musb.h> - -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/am35x_def.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/musb.h> -#include <asm/omap_musb.h> -#include <asm/ehci-omap.h> - -#include "../common/common.h" -#include "../common/eeprom.h" - -DECLARE_GLOBAL_DATA_PTR; - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "CM-T3517 board", - "NAND 128/512M", -}; - -#ifdef CONFIG_USB_MUSB_AM35X -static struct musb_hdrc_config cm_t3517_musb_config = { - .multipoint = 1, - .dyn_fifo = 1, - .num_eps = 16, - .ram_bits = 12, -}; - -static struct omap_musb_board_data cm_t3517_musb_board_data = { - .set_phy_power = am35x_musb_phy_power, - .clear_irq = am35x_musb_clear_irq, - .reset = am35x_musb_reset, -}; - -static struct musb_hdrc_platform_data cm_t3517_musb_pdata = { -#if defined(CONFIG_USB_MUSB_HOST) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_MUSB_GADGET) - .mode = MUSB_PERIPHERAL, -#else -#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" -#endif - .config = &cm_t3517_musb_config, - .power = 250, - .platform_ops = &am35x_ops, - .board_data = &cm_t3517_musb_board_data, -}; - -static void cm_t3517_musb_init(void) -{ - /* - * Set up USB clock/mode in the DEVCONF2 register. - * USB2.0 PHY reference clock is 13 MHz - */ - clrsetbits_le32(&am35x_scm_general_regs->devconf2, - CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE, - CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | - CONF2_VBDTCTEN | CONF2_DATPOL); - - if (!musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data, - (void *)AM35XX_IPSS_USBOTGSS_BASE)) - printf("Failed initializing AM35x MUSB!\n"); -} -#else -static inline void am3517_evm_musb_init(void) {} -#endif - -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON); -#endif - - cm_t3517_musb_init(); - - return 0; -} - -/* - * Routine: get_board_rev - * Description: read system revision - */ -u32 get_board_rev(void) -{ - return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS); -}; - -int misc_init_r(void) -{ - cl_print_pcb_info(); - omap_die_id_display(); - - return 0; -} - -#if defined(CONFIG_MMC) -#define SB_T35_CD_GPIO 144 -#define SB_T35_WP_GPIO 59 - -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO); -} -#endif - -#ifdef CONFIG_DRIVER_TI_EMAC -#define CONTROL_EFUSE_EMAC_LSB 0x48002380 -#define CONTROL_EFUSE_EMAC_MSB 0x48002384 - -static int am3517_get_efuse_enetaddr(u8 *enetaddr) -{ - u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB); - u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB); - - enetaddr[0] = (u8)((msb >> 16) & 0xff); - enetaddr[1] = (u8)((msb >> 8) & 0xff); - enetaddr[2] = (u8)(msb & 0xff); - enetaddr[3] = (u8)((lsb >> 16) & 0xff); - enetaddr[4] = (u8)((lsb >> 8) & 0xff); - enetaddr[5] = (u8)(lsb & 0xff); - - return is_valid_ethaddr(enetaddr); -} - -static inline int cm_t3517_init_emac(bd_t *bis) -{ - int ret = cpu_eth_init(bis); - - if (ret > 0) - return ret; - - printf("Failed initializing EMAC! "); - return 0; -} -#else /* !CONFIG_DRIVER_TI_EMAC */ -static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; } -static inline int cm_t3517_init_emac(bd_t *bis) { return 0; } -#endif /* CONFIG_DRIVER_TI_EMAC */ - -/* - * Routine: handle_mac_address - * Description: prepare MAC address for on-board Ethernet. - */ -static int cm_t3517_handle_mac_address(void) -{ - unsigned char enetaddr[6]; - int ret; - - ret = eth_env_get_enetaddr("ethaddr", enetaddr); - if (ret) - return 0; - - ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); - if (ret) { - ret = am3517_get_efuse_enetaddr(enetaddr); - if (ret) - return ret; - } - - if (!is_valid_ethaddr(enetaddr)) - return -1; - - return eth_env_set_enetaddr("ethaddr", enetaddr); -} - -#define SB_T35_ETH_RST_GPIO 164 - -/* - * Routine: board_eth_init - * Description: initialize module and base-board Ethernet chips - */ -int board_eth_init(bd_t *bis) -{ - int rc = 0, rc1 = 0; - - rc1 = cm_t3517_handle_mac_address(); - if (rc1) - printf("No MAC address found! "); - - rc1 = cm_t3517_init_emac(bis); - if (rc1 > 0) - rc++; - - rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE, - NULL, SB_T35_ETH_RST_GPIO); - if (rc1 > 0) - rc++; - - return rc; -} - -#ifdef CONFIG_USB_EHCI_OMAP -static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, -}; - -#define CM_T3517_USB_HUB_RESET_GPIO 152 -#define SB_T35_USB_HUB_RESET_GPIO 98 - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst"); - cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); - - return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(void) -{ - cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO); - cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); - - return omap_ehci_hcd_stop(); -} -#endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/compulab/cm_t3517/mux.c b/board/compulab/cm_t3517/mux.c deleted file mode 100644 index 89f2477a2e..0000000000 --- a/board/compulab/cm_t3517/mux.c +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> - * - * Authors: Igor Grinberg grinberg@compulab.co.il - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mux.h> -#include <asm/io.h> - -void set_muxconf_regs(void) -{ - /* SDRC */ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); - - /* GPMC */ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); - - /* SB-T35 Ethernet */ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); - /* DVI enable */ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/ - /* DataImage backlight */ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ - - /* SB-T35 SD/MMC WP GPIO59 */ - MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); - /* SB-T35 Audio Enable GPIO61 */ - MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); - /* SB-T35 Ethernet IRQ GPIO65 */ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/ - - /* UART3 Console */ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); - /* RTC V3020 nCS GPIO163 */ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ - /* SB-T35 Ethernet nRESET GPIO164 */ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/ - - /* SB-T35 SD/MMC CD GPIO144 */ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ - /* WIFI nRESET GPIO145 */ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ - /* USB1 PHY Reset GPIO 146 */ - MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ - /* USB2 PHY Reset GPIO 147 */ - MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/ - - /* MMC1 */ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)); - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)); - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)); - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)); - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)); - - /* DSS */ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); - - /* I2C */ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); - - /* SB-T35 USB HUB Reset GPIO98 */ - MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/ - /* CM-T3517 USB HUB Reset GPIO152 */ - MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ - - /* RMII */ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0)); - MUX_VAL(CP(RMII_MDIO_CLK), (M0)); - MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(RMII_TXD0), (IDIS | M0)); - MUX_VAL(CP(RMII_TXD1), (IDIS | M0)); - MUX_VAL(CP(RMII_TXEN), (IDIS | M0)); - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0)); - - /* Green LED GPIO186 */ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/ - - /* SPI */ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ - /* LCD reset GPIO157 */ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ - - /* RTC V3020 CS Enable GPIO160 */ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/ - /* SB-T35 LVDS Transmitter SHDN GPIO162 */ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/ - - /* USB0 - mUSB */ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)); - /* USB1 EHCI */ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ - /* USB2 EHCI */ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ - - /* SYS_BOOT */ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/ -} diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index a2e386f67d..81f69d3850 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -410,7 +410,7 @@ struct eeprom_field layout_legacy[5] = { #define layout_legacy layout_unknown #endif

-#if defined(CONFIG_CM_T3X) || defined(CONFIG_CM_T3517) +#if defined(CONFIG_CM_T3X) struct eeprom_field layout_v1[12] = { { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig deleted file mode 100644 index c204a29081..0000000000 --- a/configs/cm_t3517_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARM=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80008000 -CONFIG_TARGET_CM_T3517=y -CONFIG_EMIF4=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="CM-T3517 # " -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_EEPROM_LAYOUT=y -CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3" -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),256k(u-boot-env),4m(kernel),-(fs)" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_OMAP24_I2C_SPEED=400000 -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS_GPIO=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=186 -CONFIG_LED_STATUS_STATE=2 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_MII=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x2D000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_DRIVER_TI_EMAC=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_AM35X=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_VIDEO_OMAP3=y -CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h deleted file mode 100644 index c876853cd5..0000000000 --- a/include/configs/cm_t3517.h +++ /dev/null @@ -1,219 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 CompuLab, Ltd. - * Author: Igor Grinberg grinberg@compulab.co.il - * - * Configuration settings for the CompuLab CM-T3517 board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_CM_T3517 /* working with CM-T3517 */ - -/* - * This is needed for the DMA stuff. - * Although the default iss 64, we still define it - * to be on the safe side once the default is changed. - */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -/* - * The early kernel mapping on ARM currently only maps from the base of DRAM - * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. - * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, - * so that leaves DRAM base to DRAM base + 0x4000 available. - */ -#define CONFIG_SYS_BOOTMAPSZ 0x4000 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* USB */ - -#ifndef CONFIG_USB_MUSB_AM35X -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 -#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 -#endif /* CONFIG_USB_MUSB_AM35X */ - -/* commands to include */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 0 -#define CONFIG_I2C_MULTI_BUS - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ - -/* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "baudrate=115200\0" \ - "console=ttyO2,115200n8\0" \ - "netretry=yes\0" \ - "mpurate=auto\0" \ - "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ - "mmcrootfstype=ext4\0" \ - "nandroot=/dev/mtdblock4 rw\0" \ - "nandrootfstype=ubifs\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 2a0000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_TIMESTAMP -#define CONFIG_SYS_AUTOLOAD "no" -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) - -/* - * AM3517 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define CONFIG_SYS_CS0_SIZE (256 << 20) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_ENV_OFFSET 0x260000 -#define CONFIG_ENV_ADDR 0x260000 - -#if defined(CONFIG_CMD_NET) -#define CONFIG_DRIVER_TI_EMAC_USE_RMII -#define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_NET_RETRY_COUNT 5 -#endif /* CONFIG_CMD_NET */ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Status LED */ -#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ - -/* Display Configuration */ -#define LCD_BPP LCD_COLOR16 - -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASHIMAGE_GUARD -#define CONFIG_BMP_16BPP -#define CONFIG_SCF0403_LCD - -/* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 - -#endif /* __CONFIG_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b16bc6ae34..d24b549319 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -219,7 +219,6 @@ CONFIG_CM_MULTIPLE_SSRAM CONFIG_CM_REMAP CONFIG_CM_SPD_DETECT CONFIG_CM_T335 -CONFIG_CM_T3517 CONFIG_CM_T3X CONFIG_CM_T43 CONFIG_CM_T54

From: Bartosz Golaszewski bgolaszewski@baylibre.com

This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski bgolaszewski@baylibre.com --- arch/arm/include/asm/mach-types.h | 1 - arch/arm/mach-omap2/omap3/Kconfig | 6 - board/teejet/mt_ventoux/Kconfig | 12 - board/teejet/mt_ventoux/MAINTAINERS | 6 - board/teejet/mt_ventoux/Makefile | 7 - board/teejet/mt_ventoux/mt_ventoux.c | 342 ----------------------- board/teejet/mt_ventoux/mt_ventoux.h | 403 --------------------------- configs/mt_ventoux_defconfig | 54 ---- include/configs/mt_ventoux.h | 46 --- 9 files changed, 877 deletions(-) delete mode 100644 board/teejet/mt_ventoux/Kconfig delete mode 100644 board/teejet/mt_ventoux/MAINTAINERS delete mode 100644 board/teejet/mt_ventoux/Makefile delete mode 100644 board/teejet/mt_ventoux/mt_ventoux.c delete mode 100644 board/teejet/mt_ventoux/mt_ventoux.h delete mode 100644 configs/mt_ventoux_defconfig delete mode 100644 include/configs/mt_ventoux.h

diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index a3a2b729b1..9b38e36c87 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -3772,7 +3772,6 @@ #define MACH_TYPE_IMXT_NAV 3829 #define MACH_TYPE_IMXT_FULL 3830 #define MACH_TYPE_AG09015 3831 -#define MACH_TYPE_AM3517_MT_VENTOUX 3832 #define MACH_TYPE_DP1ARM9 3833 #define MACH_TYPE_PICASSO_M 3834 #define MACH_TYPE_VIDEO_GADGET 3835 diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 9bc616c286..96579e5de9 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -34,11 +34,6 @@ config TARGET_AM3517_EVM select DM_SERIAL imply CMD_DM

-config TARGET_MT_VENTOUX - bool "TeeJet Mt.Ventoux" - select OMAP3_GPIO_4 - select OMAP3_GPIO_5 if USB_EHCI_HCD - config TARGET_OMAP3_BEAGLE bool "TI OMAP3 BeagleBoard" select DM @@ -189,7 +184,6 @@ config SYS_SOC default "omap3"

source "board/logicpd/am3517evm/Kconfig" -source "board/teejet/mt_ventoux/Kconfig" source "board/ti/beagle/Kconfig" source "board/compulab/cm_t35/Kconfig" source "board/timll/devkit8000/Kconfig" diff --git a/board/teejet/mt_ventoux/Kconfig b/board/teejet/mt_ventoux/Kconfig deleted file mode 100644 index fd7196a6f9..0000000000 --- a/board/teejet/mt_ventoux/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MT_VENTOUX - -config SYS_BOARD - default "mt_ventoux" - -config SYS_VENDOR - default "teejet" - -config SYS_CONFIG_NAME - default "mt_ventoux" - -endif diff --git a/board/teejet/mt_ventoux/MAINTAINERS b/board/teejet/mt_ventoux/MAINTAINERS deleted file mode 100644 index d23464c20f..0000000000 --- a/board/teejet/mt_ventoux/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MT_VENTOUX BOARD -M: Stefano Babic sbabic@denx.de -S: Maintained -F: board/teejet/mt_ventoux/ -F: include/configs/mt_ventoux.h -F: configs/mt_ventoux_defconfig diff --git a/board/teejet/mt_ventoux/Makefile b/board/teejet/mt_ventoux/Makefile deleted file mode 100644 index f007156286..0000000000 --- a/board/teejet/mt_ventoux/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Ilya Yanok, Emcraft Systems -# -# Based on ti/evm/Makefile - -obj-y := mt_ventoux.o diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c deleted file mode 100644 index 33de7a2131..0000000000 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ /dev/null @@ -1,342 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * Copyright (C) 2009 TechNexion Ltd. - */ - -#include <common.h> -#include <netdev.h> -#include <malloc.h> -#include <fpga.h> -#include <video_fb.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/omap_gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/dss.h> -#include <asm/arch/clock.h> -#include <i2c.h> -#include <spartan3.h> -#include <asm/gpio.h> -#ifdef CONFIG_USB_EHCI_HCD -#include <usb.h> -#include <asm/ehci-omap.h> -#endif -#include "mt_ventoux.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define BUZZER 140 -#define SPEAKER 141 -#define USB1_PWR 127 -#define USB2_PWR 149 - -#ifndef CONFIG_FPGA -#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled" -#endif - -#define FPGA_RESET 62 -#define FPGA_PROG 116 -#define FPGA_CCLK 117 -#define FPGA_DIN 118 -#define FPGA_INIT 119 -#define FPGA_DONE 154 - -#define LCD_PWR 138 -#define LCD_PON_PIN 139 - -#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) -static struct { - u32 xres; - u32 yres; -} panel_resolution[] = { - { 480, 272 }, - { 800, 480 } -}; - -static struct panel_config lcd_cfg[] = { - { - .timing_h = PANEL_TIMING_H(40, 5, 2), - .timing_v = PANEL_TIMING_V(8, 8, 2), - .pol_freq = 0x00003000, /* Pol Freq */ - .divisor = 0x00010033, /* 9 Mhz Pixel Clock */ - .panel_type = 0x01, /* TFT */ - .data_lines = 0x03, /* 24 Bit RGB */ - .load_mode = 0x02, /* Frame Mode */ - .panel_color = 0, - .gfx_format = GFXFORMAT_RGB24_UNPACKED, - }, - { - .timing_h = PANEL_TIMING_H(20, 192, 4), - .timing_v = PANEL_TIMING_V(2, 20, 10), - .pol_freq = 0x00004000, /* Pol Freq */ - .divisor = 0x0001000E, /* 36Mhz Pixel Clock */ - .panel_type = 0x01, /* TFT */ - .data_lines = 0x03, /* 24 Bit RGB */ - .load_mode = 0x02, /* Frame Mode */ - .panel_color = 0, - .gfx_format = GFXFORMAT_RGB24_UNPACKED, - } -}; -#endif - -/* Timing definitions for FPGA */ -static const u32 gpmc_fpga[] = { - FPGA_GPMC_CONFIG1, - FPGA_GPMC_CONFIG2, - FPGA_GPMC_CONFIG3, - FPGA_GPMC_CONFIG4, - FPGA_GPMC_CONFIG5, - FPGA_GPMC_CONFIG6, -}; - -#ifdef CONFIG_USB_EHCI_HCD -static struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - return omap_ehci_hcd_stop(); -} -#endif - - -static inline void fpga_reset(int nassert) -{ - gpio_set_value(FPGA_RESET, !nassert); -} - -int fpga_pgm_fn(int nassert, int nflush, int cookie) -{ - debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__); - - gpio_set_value(FPGA_PROG, !nassert); - - return nassert; -} - -int fpga_init_fn(int cookie) -{ - return !gpio_get_value(FPGA_INIT); -} - -int fpga_done_fn(int cookie) -{ - return gpio_get_value(FPGA_DONE); -} - -int fpga_pre_config_fn(int cookie) -{ - debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); - - /* Setting GPIOs for programming Mode */ - gpio_request(FPGA_RESET, "FPGA_RESET"); - gpio_direction_output(FPGA_RESET, 1); - gpio_request(FPGA_PROG, "FPGA_PROG"); - gpio_direction_output(FPGA_PROG, 1); - gpio_request(FPGA_CCLK, "FPGA_CCLK"); - gpio_direction_output(FPGA_CCLK, 1); - gpio_request(FPGA_DIN, "FPGA_DIN"); - gpio_direction_output(FPGA_DIN, 0); - gpio_request(FPGA_INIT, "FPGA_INIT"); - gpio_direction_input(FPGA_INIT); - gpio_request(FPGA_DONE, "FPGA_DONE"); - gpio_direction_input(FPGA_DONE); - - /* Be sure that signal are deasserted */ - gpio_set_value(FPGA_RESET, 1); - gpio_set_value(FPGA_PROG, 1); - - return 0; -} - -int fpga_post_config_fn(int cookie) -{ - debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__); - - fpga_reset(true); - udelay(100); - fpga_reset(false); - - return 0; -} - -/* Write program to the FPGA */ -int fpga_wr_fn(int nassert_write, int flush, int cookie) -{ - gpio_set_value(FPGA_DIN, nassert_write); - - return nassert_write; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - gpio_set_value(FPGA_CCLK, assert_clk); - - return assert_clk; -} - -xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_clk_fn, - fpga_init_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_post_config_fn, -}; - -xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, - (void *)&mt_ventoux_fpga_fns, 0); - -/* Initialize the FPGA */ -static void mt_ventoux_init_fpga(void) -{ - fpga_pre_config_fn(0); - - /* Setting CS1 for FPGA access */ - enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1], - FPGA_BASE_ADDR, GPMC_SIZE_128M); - - fpga_init(); - fpga_add(fpga_xilinx, &fpga); -} - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - mt_ventoux_init_fpga(); - - /* GPIO_140: speaker #mute */ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) - /* GPIO_141: Buzz Hi */ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) - - /* Turning off the buzzer */ - gpio_request(BUZZER, "BUZZER_MUTE"); - gpio_request(SPEAKER, "SPEAKER"); - gpio_direction_output(BUZZER, 0); - gpio_direction_output(SPEAKER, 0); - - /* Activate USB power */ - gpio_request(USB1_PWR, "USB1_PWR"); - gpio_request(USB2_PWR, "USB2_PWR"); - gpio_direction_output(USB1_PWR, 1); - gpio_direction_output(USB2_PWR, 1); - - return 0; -} - -#ifndef CONFIG_SPL_BUILD -int misc_init_r(void) -{ - char *eth_addr; - struct tam3517_module_info info; - int ret; - - TAM3517_READ_EEPROM(&info, ret); - omap_die_id_display(); - - if (ret) - return 0; - eth_addr = env_get("ethaddr"); - if (!eth_addr) - TAM3517_READ_MAC_FROM_EEPROM(&info); - - TAM3517_PRINT_SOM_INFO(&info); - return 0; -} -#endif - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_MT_VENTOUX(); -} - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int board_eth_init(bd_t *bis) -{ - davinci_emac_initialize(); - return 0; -} - -#if defined(CONFIG_MMC_OMAP_HS) && \ - !defined(CONFIG_SPL_BUILD) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) -int board_video_init(void) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - struct panel_config *panel = &lcd_cfg[0]; - char *s; - u32 index = 0; - - void *fb; - - fb = (void *)0x88000000; - - s = env_get("panel"); - if (s) { - index = simple_strtoul(s, NULL, 10); - if (index < ARRAY_SIZE(lcd_cfg)) - panel = &lcd_cfg[index]; - else - return 0; - } - - panel->frame_buffer = fb; - printf("Panel: %dx%d\n", panel_resolution[index].xres, - panel_resolution[index].yres); - panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | - (panel_resolution[index].xres - 1); - - gpio_request(LCD_PWR, "LCD Power"); - gpio_request(LCD_PON_PIN, "LCD Pon"); - gpio_direction_output(LCD_PWR, 0); - gpio_direction_output(LCD_PON_PIN, 1); - - - setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); - setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); - - omap3_dss_panel_config(panel); - omap3_dss_enable(); - - return 0; -} -#endif diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h deleted file mode 100644 index 5e01774234..0000000000 --- a/board/teejet/mt_ventoux/mt_ventoux.h +++ /dev/null @@ -1,403 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Stefano Babic sbabic@denx.de - * - * Author: Hardy Weng hardy.weng@technexion.com - * - * Copyright (C) 2010 TechNexion Ltd. - */ - -#ifndef _MT_VENTOUX_H_ -#define _MT_VENTOUX_H_ - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "Teejet MT_VENTOUX Board", - "NAND", -}; - -/* FPGA CS1 configuration */ -#define FPGA_GPMC_CONFIG1 0x00001200 -#define FPGA_GPMC_CONFIG2 0x00161f00 -#define FPGA_GPMC_CONFIG3 0x00040400 -#define FPGA_GPMC_CONFIG4 0x120c1f08 -#define FPGA_GPMC_CONFIG5 0x001e161f -#define FPGA_GPMC_CONFIG6 0x96080fcf - -#define FPGA_BASE_ADDR 0x20000000 - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_MT_VENTOUX() \ - /* SDRC */\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_CKE0), (M0)) \ - MUX_VAL(CP(SDRC_CKE1), (M0)) \ - MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ - /* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\ - MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \ - /* GPIO 55 : NFS */\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \ - /*GPIO_62: FPGA_RESET */ \ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \ - /* GPIO_64*/ \ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ - /* DSS */\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ - /* CAMERA */\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ - /* MMC */\ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ - /* GPIO_126: CardDetect */\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ - /*GPIO_128 */ \ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\ - MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \ - /* GPIO_138: LCD_ENVD */\ - MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \ - /* GPIO_139: LCD_PON */\ - /* McBSP */\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) \ - /* GPIO_116: FPGA_PROG */ \ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \ - /* GPIO_117: FPGA_CCLK */ \ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \ - /* GPIO_118: FPGA_DIN */ \ - MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \ - /* GPIO_119: FPGA_INIT */ \ - \ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \ - /*GPIO_152: Ignition Sense */ \ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \ - /*GPIO_153: Power Button Sense */ \ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \ - /* GPIO_154: FPGA_DONE */ \ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) \ - /* GPIO_155: CA8_irq */ \ - /* UART */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \ - /* GPIO_149: USB status 2 */\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \ - /* GPIO_150: USB status 1 */\ - \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \ - /* gpt9_pwm */\ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \ - /* gpt10_pwm */\ - MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \ - /* gpt8_pwm */\ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \ - /* gpt11_pwm */\ - \ - MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \ - /*GPIO_163 : TS_PENIRQ*/ \ - MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) \ - /*GPIO_164 : MMC */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ - /* I2C */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ - /* McSPI */\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \ - \ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \ - /* CCDC */\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \ - /* GPIO94 */\ - MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \ - /* GPIO95: #Enable Output */\ - MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \ - /* GPIO 99: #SOM_PWR_OFF */\ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \ - /* GPIO_100: #power out */\ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \ - /* GPIO_102 */\ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \ - /* RMII */\ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ - MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ - MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ - /* HECC */\ - MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ - /* HSUSB */\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ - /* HDQ */\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ - /* GPIO_170: auto update */\ - /* Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ - /* - GPIO30 */\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ - MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ - \ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \ - /* gpio_10 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ - /* JTAG */\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \ - MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \ - /* ETK (ES2 onwards) */\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ - /* hsusb1_stp */ \ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ - /* hsusb1_clk */\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \ - /* gpio_24 */\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ - /* gpio_26 */\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ - /* gpio_29 */\ - /* Die to Die */\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ - -#endif diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig deleted file mode 100644 index 4414875e09..0000000000 --- a/configs/mt_ventoux_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -CONFIG_ARM=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80008000 -CONFIG_TARGET_MT_VENTOUX=y -CONFIG_EMIF4=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL=y -CONFIG_BOOTDELAY=10 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SPL_TEXT_BASE=0x40200000 -# CONFIG_SPL_FS_EXT4 is not set -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="mt_ventoux => " -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),8m(ubisystem),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_SPARTAN3=y -CONFIG_SYS_OMAP24_I2C_SPEED=400000 -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_MII=y -CONFIG_DRIVER_TI_EMAC=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT_OMAP=y -CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_OMAP3=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h deleted file mode 100644 index e590364441..0000000000 --- a/include/configs/mt_ventoux.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * - * Configuration settings for the Teejet mt_ventoux board. - * - * Copyright (C) 2009 TechNexion Ltd. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tam3517-common.h" - -#undef CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ - 6 * 1024 * 1024) - -#define CONFIG_MACH_TYPE MACH_TYPE_AM3517_MT_VENTOUX - -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_HOSTNAME "mt_ventoux" - -/* - * Set its own mtdparts, different from common - */ - -/* - * FPGA - */ -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_WAIT 10000 -#define CONFIG_MAX_FPGA_DEVICES 1 -#define CONFIG_FPGA_DELAY() udelay(1) -#define CONFIG_SYS_FPGA_PROG_FEEDBACK - -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_RLE8 - -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \ - "bootcmd=run net_nfs\0" - -#endif /* __CONFIG_H */

From: Bartosz Golaszewski bgolaszewski@baylibre.com

This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski bgolaszewski@baylibre.com --- arch/arm/include/asm/mach-types.h | 1 - arch/arm/mach-omap2/omap3/Kconfig | 7 - board/htkw/mcx/Kconfig | 12 - board/htkw/mcx/MAINTAINERS | 6 - board/htkw/mcx/Makefile | 7 - board/htkw/mcx/mcx.c | 141 ----------- board/htkw/mcx/mcx.h | 400 ------------------------------ configs/mcx_defconfig | 58 ----- include/configs/mcx.h | 294 ---------------------- 9 files changed, 926 deletions(-) delete mode 100644 board/htkw/mcx/Kconfig delete mode 100644 board/htkw/mcx/MAINTAINERS delete mode 100644 board/htkw/mcx/Makefile delete mode 100644 board/htkw/mcx/mcx.c delete mode 100644 board/htkw/mcx/mcx.h delete mode 100644 configs/mcx_defconfig delete mode 100644 include/configs/mcx.h

diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index d6d9f71033..32532b3ca4 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -3596,7 +3596,6 @@ #define MACH_TYPE_TAISHAN 3653 #define MACH_TYPE_TOUCHLINK 3654 #define MACH_TYPE_STM32F103ZE 3655 -#define MACH_TYPE_MCX 3656 #define MACH_TYPE_STM_NMHDK_FLI7610 3657 #define MACH_TYPE_TOP28X 3658 #define MACH_TYPE_OKL4VP_MICROVISOR 3659 diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index f192b92626..d75fab1530 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -105,12 +105,6 @@ config TARGET_TRICORDER bool "Tricorder" select OMAP3_GPIO_2

-config TARGET_MCX - bool "MCX" - select BOARD_LATE_INIT - select OMAP3_GPIO_2 if USB_EHCI_HCD - select OMAP3_GPIO_5 if USB_EHCI_HCD - config TARGET_OMAP3_LOGIC bool "OMAP3 Logic" select BOARD_LATE_INIT @@ -189,7 +183,6 @@ source "board/logicpd/zoom1/Kconfig" source "board/ti/am3517crane/Kconfig" source "board/pandora/Kconfig" source "board/corscience/tricorder/Kconfig" -source "board/htkw/mcx/Kconfig" source "board/logicpd/omap3som/Kconfig" source "board/nokia/rx51/Kconfig" source "board/technexion/tao3530/Kconfig" diff --git a/board/htkw/mcx/Kconfig b/board/htkw/mcx/Kconfig deleted file mode 100644 index 25ba548dab..0000000000 --- a/board/htkw/mcx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MCX - -config SYS_BOARD - default "mcx" - -config SYS_VENDOR - default "htkw" - -config SYS_CONFIG_NAME - default "mcx" - -endif diff --git a/board/htkw/mcx/MAINTAINERS b/board/htkw/mcx/MAINTAINERS deleted file mode 100644 index 513d19daa7..0000000000 --- a/board/htkw/mcx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MCX BOARD -M: Anatolij Gustschin agust@denx.de -S: Maintained -F: board/htkw/mcx/ -F: include/configs/mcx.h -F: configs/mcx_defconfig diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile deleted file mode 100644 index 54bfc13781..0000000000 --- a/board/htkw/mcx/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Ilya Yanok, Emcraft Systems -# -# Based on ti/evm/Makefile - -obj-y := mcx.o diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c deleted file mode 100644 index ee29fe7cf9..0000000000 --- a/board/htkw/mcx/mcx.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 Ilya Yanok, Emcraft Systems - * - * Based on ti/evm/evm.c - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-types.h> -#include <asm/gpio.h> -#include <asm/omap_gpio.h> -#include <asm/arch/dss.h> -#include <asm/arch/clock.h> -#include <errno.h> -#include <i2c.h> -#ifdef CONFIG_USB_EHCI_HCD -#include <usb.h> -#include <asm/ehci-omap.h> -#endif -#include "mcx.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define HOT_WATER_BUTTON 42 -#define LCD_OUTPUT 55 - -/* Address of the framebuffer in RAM. */ -#define FB_START_ADDRESS 0x88000000 - -#ifdef CONFIG_USB_EHCI_HCD -static struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - return omap_ehci_hcd_stop(); -} -#endif - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - gpio_direction_output(LCD_OUTPUT, 0); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - if (gpio_request(HOT_WATER_BUTTON, "hot-water-button") < 0) { - puts("Failed to get hot-water-button pin\n"); - return -ENODEV; - } - gpio_direction_input(HOT_WATER_BUTTON); - - /* - * if hot-water-button is pressed - * change bootcmd - */ - if (gpio_get_value(HOT_WATER_BUTTON)) - return 0; - - env_set("bootcmd", "run swupdate"); - - return 0; -} -#endif - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_MCX(); -} - -#if defined(CONFIG_MMC_OMAP_HS) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) - -static struct panel_config lcd_cfg = { - .timing_h = PANEL_TIMING_H(40, 40, 48), - .timing_v = PANEL_TIMING_V(29, 13, 3), - .pol_freq = 0x00003000, /* Pol Freq */ - .divisor = 0x0001000E, - .panel_type = 0x01, /* TFT */ - .data_lines = 0x03, /* 24 Bit RGB */ - .load_mode = 0x02, /* Frame Mode */ - .panel_color = 0, - .lcd_size = PANEL_LCD_SIZE(800, 480), - .gfx_format = GFXFORMAT_RGB24_UNPACKED, -}; - -int board_video_init(void) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - void *fb; - - fb = (void *)FB_START_ADDRESS; - - lcd_cfg.frame_buffer = fb; - - setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); - setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); - - omap3_dss_panel_config(&lcd_cfg); - omap3_dss_enable(); - - return 0; -} -#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h deleted file mode 100644 index f9ff50f8a7..0000000000 --- a/board/htkw/mcx/mcx.h +++ /dev/null @@ -1,400 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Ilya Yanok, Emcraft Systems - * - * Based on ti/evm/evm.h - */ - -#ifndef _AM3517EVM_H_ -#define _AM3517EVM_H_ - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "HTKW mcx Board", - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_MCX() \ - /* SDRC */\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_CKE0), (M0)) \ - MUX_VAL(CP(SDRC_CKE1), (M0)) \ - MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ - /*sdrc_strben_dly0*/\ - MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ - /*sdrc_strben_dly1*/\ - /* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \ - /* GPIO_43 LCD buffer enable */ \ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \ - /* GPIO_57 TS_PenIRQn */\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \ - /* GPIO_58 ETHERNET RESET */\ - MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \ - /* GPIO_61 SD-CARD CD */ \ - MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \ - /* GPIO_62 Nand write protect, keep enabled */ \ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ - /* GPIO_65 SD-CARD WP */\ - /* DSS */\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ - /* CAMERA */\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \ - /* MMC */\ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \ - /* GPIO_131 LCD Enable */ \ - MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \ - /* GPIO_132 USB host Enable */\ - MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \ - /* GPIO_133 HDMI PD */\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\ - /* McBSP */\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\ - \ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\ - \ - MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \ - /* GPIO_152 USB phy2 reset */\ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \ - /* GPIO_153 */\ - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \ - /* GPIO_154 USB phy1 reset */\ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \ - /* GPIO_155 TS_BUSY */\ - /* UART */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ - /* I2C */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) \ - /* GPIO_170 Touchscreen ISR */\ - /* McSPI */\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \ - /* HSUSB2_dat7 */\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \ - /* HSUSB2_dat4 */\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \ - /* HSUSB2_dat5 */\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \ - /* HSUSB2_dat6 */\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \ - /* HSUSB2_dat3 */\ - /* CCDC */\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \ - /* CCDC_FIELD: gpio_95, uP-TXD4 */ \ - MUX_VAL(CP(CCDC_FIELD), (IDIS | PTD | DIS | M2)) \ - /* CCDC_HD: gpio_96, uP-RTS4# */ \ - MUX_VAL(CP(CCDC_HD), (IDIS | PTD | DIS | M2)) \ - /* CCDC_VD: gpio_97, uP-CTS4# */ \ - MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M2)) \ - /* CCDC_WEN: gpio_98, uP-RXD4 */ \ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M2)) \ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \ - /* RMII */\ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ - MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ - MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ - /* HECC */\ - MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M0)) \ - /* HSUSB */\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ - /* HDQ */\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ - /* Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\ - MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \ - \ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\ - /* JTAG */\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\ - /* ETK (ES2 onwards) */\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ - /* hsusb1_stp */ \ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ - /* hsusb1_clk */\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ - /* Die to Die */\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ - -#endif diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig deleted file mode 100644 index 58d0ac08bf..0000000000 --- a/configs/mcx_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80008000 -# CONFIG_SPL_GPIO_SUPPORT is not set -CONFIG_TARGET_MCX=y -CONFIG_EMIF4=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SPL_TEXT_BASE=0x40200000 -# CONFIG_SPL_FS_EXT4 is not set -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="mcx # " -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),6m(k_recovery),8m(fs_recovery),-(common_data)" -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SPL_NAND_SIMPLE=y -CONFIG_MII=y -CONFIG_DRIVER_TI_EMAC=y -CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ULPI_VIEWPORT_OMAP=y -CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_ETHER_MCS7830=y -CONFIG_VIDEO_OMAP3=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mcx.h b/include/configs/mcx.h deleted file mode 100644 index 411c27c4a8..0000000000 --- a/include/configs/mcx.h +++ /dev/null @@ -1,294 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Ilya Yanok, Emcraft Systems - * - * Based on omap3_evm_config.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MACH_TYPE MACH_TYPE_MCX - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -/* - * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader - * and older u-boot.bin with the new U-Boot SPL. - */ - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -/* - * DDR related - */ -#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* EHCI */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 - -/* commands to include */ - -#define CONFIG_SYS_I2C - -/* RTC */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access */ - /* nand at CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ - -/* Environment information */ - -#define CONFIG_BOOTFILE "uImage" - -/* Setup MTD for NAND on the SOM */ - -#define CONFIG_HOSTNAME "mcx" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ - "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "addfb=setenv bootargs ${bootargs} vram=6M " \ - "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:eth0:off\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consoledev},${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "baudrate=115200\0" \ - "consoledev=ttyO2\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - "loadaddr=0x82000000\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "load_k=tftp ${loadaddr} ${bootfile}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ - "loadmlo=tftp ${loadaddr} ${mlo}\0" \ - "mlo=" CONFIG_HOSTNAME "/MLO\0" \ - "mmcargs=root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "run addip addtty addmtd addfb addeth addmisc;" \ - "run loaduimage; " \ - "bootm ${loadaddr}\0" \ - "net_nfs=run load_k; " \ - "run nfsargs; " \ - "run addip addtty addmtd addfb addeth addmisc;" \ - "bootm ${loadaddr}\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \ - "uboot_addr=0x80000\0" \ - "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ - "nand write ${loadaddr} ${uboot_addr} 80000\0" \ - "updatemlo=nandecc hw;nand erase 0 20000;" \ - "nand write ${loadaddr} 0 20000\0" \ - "upd=if run load;then echo Updating u-boot;if run update;" \ - "then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "nandargs=setenv bootargs ubi.mtd=7 " \ - "root=ubi0:rootfs rootfstype=ubifs\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "ubi part nand0,4;" \ - "ubi readvol ${loadaddr} kernel;" \ - "run addtty addmtd addfb addeth addmisc;" \ - "bootm ${loadaddr}\0" \ - "preboot=ubi part nand0,7;" \ - "ubi readvol ${loadaddr} splash;" \ - "bmp display ${loadaddr};" \ - "gpio set 55\0" \ - "swupdate_args=setenv bootargs root=/dev/ram " \ - "quiet loglevel=1 " \ - "consoleblank=0 ${swupdate_misc}\0" \ - "swupdate=echo Running Sw-Update...;" \ - "if printenv mtdparts;then echo Starting SwUpdate...; " \ - "else mtdparts default;fi; " \ - "ubi part nand0,5;" \ - "ubi readvol 0x82000000 kernel_recovery;" \ - "ubi part nand0,6;" \ - "ubi readvol 0x84000000 fs_recovery;" \ - "run swupdate_args; " \ - "setenv bootargs ${bootargs} " \ - "${mtdparts} " \ - "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ - "omapdss.def_disp=lcd;" \ - "bootm 0x82000000 0x84000000\0" \ - "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ - "then source 82000000;else run nandboot;fi\0" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ -#define CONFIG_PREBOOT - -/* - * AM3517 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ - -/* Redundant Environment */ -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET 0x180000 -#define CONFIG_ENV_ADDR 0x180000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - 2 * CONFIG_SYS_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Defines for SPL */ - -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC - -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -/* move malloc and bss high to prevent clashing with the main image */ -#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -/* NAND boot config */ -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ - 48, 49, 50, 51, 52, 53, 54, 55,\ - 56, 57, 58, 59, 60, 61, 62, 63} -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW -#define CONFIG_SPL_NAND_SOFTECC - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -/* - * ethernet support - * - */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_DRIVER_TI_EMAC_USE_RMII -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_RLE8 - -#endif /* __CONFIG_H */