[PATCH v3 0/7] arm: mach-snapdragon: Qualcomm clock driver cleanup
This series begins making some headway towards cleaning up Qualcomm platform support in u-boot. The following is a rough overview of the changes:
* Move the Qualcomm clock drivers out of mach-snapdragon and into clk/qcom * Introduce per-platform clock driver configs to decouple Qualcomm platform support from mach-snapdragon targets. * Add the IPQ4019 clock driver, removing it from mach-ipq40xx and introducing the reset map. * Merge the qcom reset driver is into clk/qcom and rework it to be compatible with upstream devicetrees. * A callback model is added so that multiple clock drivers can be compiled in at once. * SDM845 gains support for enabling/disabling all gate clocks (CBC's) by way of a new "gate_clk" abstraction. * Preperatory cleanup work is done to simplify the bringup process for new platforms.
Further details are included in each commit.
The primary goal of this series is to prepare for enabling several new Qualcomm platforms in u-boot as well as additional peripherals, while minimising the amount of copy/pasted board-specific code.
This series conflicts with a previous series introducing support for the Qualcomm RB2 board [1], I plan to resend this initial support pending acceptance of this series and several other cleanups.
[1]: https://lore.kernel.org/u-boot/20230324080418.3856409-1-bhupesh.sharma@linar...
--- Changes in v3: * Rebased on qcom-next [1] * Dropped erroneous LOG_DEBUG define * Add drivers/clk/qcom to MAINTAINERS * Link to v2: https://lore.kernel.org/r/20231024-b4-qcom-clk-v2-0-6572bc2be690@linaro.org
Changes in v2: * Added missing headers in clock-qcom.c for "fix rcg divider value" patch * Use writel() instead of setbits_le32() in "fix rcg divider value" patch to ensure that writes are propagated to hardware. * Adjust RCG configuration to be more similar to Linux * Remove sysmap headers and define macros directly in platform clock code. * avoid renaming msm_* to qcom_* for now * only add relevant gate_clks for sdm845 * Link to v1: https://lore.kernel.org/r/20231024-b4-qcom-clk-v1-0-9d96359b9a82@linaro.org
[1]: https://source.denx.de/u-boot/custodians/u-boot-snapdragon
--- Caleb Connolly (6): clk/qcom: move from mach-snapdragon clk/qcom: move ipq4019 driver from mach-ipq40xx clk/qcom: sdm845: add register map for simple gate clocks clk/qcom: use function pointers for enable and set_rate clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() clk/qcom: fix rcg divider value
Konrad Dybcio (1): clk/qcom: handle resets and clocks in one device
MAINTAINERS | 1 + arch/arm/Kconfig | 2 + arch/arm/dts/qcom-ipq4019.dtsi | 14 +- arch/arm/dts/qcs404-evb.dts | 19 +- arch/arm/mach-ipq40xx/Makefile | 1 - arch/arm/mach-ipq40xx/clock-ipq4019.c | 88 ------ arch/arm/mach-snapdragon/Kconfig | 4 + arch/arm/mach-snapdragon/Makefile | 5 - arch/arm/mach-snapdragon/clock-sdm845.c | 98 ------- arch/arm/mach-snapdragon/clock-snapdragon.c | 181 ------------ arch/arm/mach-snapdragon/clock-snapdragon.h | 48 ---- .../mach-snapdragon/include/mach/sysmap-apq8016.h | 39 --- .../mach-snapdragon/include/mach/sysmap-apq8096.h | 37 --- .../mach-snapdragon/include/mach/sysmap-qcs404.h | 88 ------ .../mach-snapdragon/include/mach/sysmap-sdm845.h | 42 --- board/qualcomm/dragonboard820c/dragonboard820c.c | 6 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/qcom/Kconfig | 52 ++++ drivers/clk/qcom/Makefile | 10 + .../clk/qcom}/clock-apq8016.c | 60 +++- .../clk/qcom}/clock-apq8096.c | 56 +++- .../reset-qcom.c => clk/qcom/clock-ipq4019.c} | 160 ++++------- drivers/clk/qcom/clock-qcom.c | 307 +++++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 100 +++++++ .../clk/qcom}/clock-qcs404.c | 167 +++++++++-- drivers/clk/qcom/clock-sdm845.c | 187 +++++++++++++ drivers/reset/Kconfig | 7 - drivers/reset/Makefile | 1 - include/configs/dragonboard410c.h | 1 - include/configs/dragonboard820c.h | 1 - include/configs/dragonboard845c.h | 1 - include/configs/qcs404-evb.h | 1 - .../{qcom,ipq4019-gcc.h => qcom,gcc-ipq4019.h} | 73 +++++ include/dt-bindings/reset/qcom,ipq4019-reset.h | 92 ------ 35 files changed, 1053 insertions(+), 898 deletions(-) --- base-commit: b9221f7d86f9511ad2a816f589d41bc02dbcd6f8
// Caleb (they/them)
Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit.
To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target.
Reviewed-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- MAINTAINERS | 1 + arch/arm/mach-snapdragon/Kconfig | 4 ++ arch/arm/mach-snapdragon/Makefile | 5 --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/qcom/Kconfig | 44 ++++++++++++++++++++++ drivers/clk/qcom/Makefile | 9 +++++ .../clk/qcom}/clock-apq8016.c | 2 +- .../clk/qcom}/clock-apq8096.c | 3 +- .../clk/qcom/clock-qcom.c | 2 +- .../clk/qcom/clock-qcom.h | 0 .../clk/qcom}/clock-qcs404.c | 2 +- .../clk/qcom}/clock-sdm845.c | 2 +- 13 files changed, 66 insertions(+), 10 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS index 091e6bb5084d..b483fa2ea95a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -572,6 +572,7 @@ M: Neil Armstrong neil.armstrong@linaro.org R: Sumit Garg sumit.garg@linaro.org S: Maintained F: arch/arm/mach-snapdragon/ +F: drivers/clk/qcom/ F: drivers/gpio/msm_gpio.c F: drivers/mmc/msm_sdhci.c F: drivers/phy/msm8916-usbh-phy.c diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 2fc1521e2d30..dde37eccc55e 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -15,6 +15,7 @@ config SPL_SYS_MALLOC_F_LEN config SDM845 bool "Qualcomm Snapdragon 845 SoC" select LINUX_KERNEL_IMAGE_HEADER + imply CLK_QCOM_SDM845
config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000 @@ -26,6 +27,7 @@ config TARGET_DRAGONBOARD410C bool "96Boards Dragonboard 410C" select BOARD_LATE_INIT select ENABLE_ARM_SOC_BOOT0_HOOK + imply CLK_QCOM_APQ8016 help Support for 96Boards Dragonboard 410C. This board complies with 96Board Open Platform Specifications. Features: @@ -39,6 +41,7 @@ config TARGET_DRAGONBOARD410C
config TARGET_DRAGONBOARD820C bool "96Boards Dragonboard 820C" + imply CLK_QCOM_APQ8096 help Support for 96Boards Dragonboard 820C. This board complies with 96Board Open Platform Specifications. Features: @@ -72,6 +75,7 @@ config TARGET_STARQLTECHN config TARGET_QCS404EVB bool "Qualcomm Technologies, Inc. QCS404 EVB" select LINUX_KERNEL_IMAGE_HEADER + imply CLK_QCOM_QCS404 help Support for Qualcomm Technologies, Inc. QCS404 evaluation board. Features: diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index cbaaf23f6b56..497ee35cf7d3 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,20 +2,15 @@ # # (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com
-obj-$(CONFIG_SDM845) += clock-sdm845.o obj-$(CONFIG_SDM845) += sysmap-sdm845.o obj-$(CONFIG_SDM845) += init_sdm845.o -obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o obj-y += misc.o -obj-y += clock-snapdragon.o obj-y += dram.o obj-y += pinctrl-snapdragon.o obj-y += pinctrl-apq8016.o obj-y += pinctrl-apq8096.o obj-y += pinctrl-qcs404.o obj-y += pinctrl-sdm845.o -obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index bfd23a990469..017dd260a544 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -254,6 +254,7 @@ source "drivers/clk/meson/Kconfig" source "drivers/clk/microchip/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" +source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 26bf429acbc0..dd974742b6c8 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_CLK_MPFS) += microchip/ obj-$(CONFIG_CLK_MVEBU) += mvebu/ obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ +obj-$(CONFIG_CLK_QCOM) += qcom/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o obj-$(CONFIG_CLK_SIFIVE) += sifive/ diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig new file mode 100644 index 000000000000..a884f077d9b9 --- /dev/null +++ b/drivers/clk/qcom/Kconfig @@ -0,0 +1,44 @@ +if ARCH_SNAPDRAGON || ARCH_IPQ40XX + +config CLK_QCOM + bool + depends on CLK && DM_RESET + def_bool n + +menu "Qualcomm clock drivers" + +config CLK_QCOM_APQ8016 + bool "Qualcomm APQ8016 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon APQ8016 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + +config CLK_QCOM_APQ8096 + bool "Qualcomm APQ8096 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon APQ8096 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + +config CLK_QCOM_QCS404 + bool "Qualcomm QCS404 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon QCS404 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + +config CLK_QCOM_SDM845 + bool "Qualcomm SDM845 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon 845 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + +endmenu + +endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile new file mode 100644 index 000000000000..44d55583596d --- /dev/null +++ b/drivers/clk/qcom/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2023 Linaro + +obj-y += clock-qcom.o +obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o +obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o +obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o +obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c similarity index 98% rename from arch/arm/mach-snapdragon/clock-apq8016.c rename to drivers/clk/qcom/clock-apq8016.c index 23a37a1714dc..90f2a93d9ed5 100644 --- a/arch/arm/mach-snapdragon/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -13,7 +13,7 @@ #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> -#include "clock-snapdragon.h" +#include "clock-qcom.h"
/* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c similarity index 98% rename from arch/arm/mach-snapdragon/clock-apq8096.c rename to drivers/clk/qcom/clock-apq8096.c index 66184596d562..d5388c69aefe 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -13,7 +13,8 @@ #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> -#include "clock-snapdragon.h" + +#include "clock-qcom.h"
/* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(30) diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/drivers/clk/qcom/clock-qcom.c similarity index 99% rename from arch/arm/mach-snapdragon/clock-snapdragon.c rename to drivers/clk/qcom/clock-qcom.c index 0ac45dce9a92..5667abeb89a4 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -13,7 +13,7 @@ #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> -#include "clock-snapdragon.h" +#include "clock-qcom.h"
/* CBCR register fields */ #define CBCR_BRANCH_ENABLE_BIT BIT(0) diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/drivers/clk/qcom/clock-qcom.h similarity index 100% rename from arch/arm/mach-snapdragon/clock-snapdragon.h rename to drivers/clk/qcom/clock-qcom.h diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c similarity index 99% rename from arch/arm/mach-snapdragon/clock-qcs404.c rename to drivers/clk/qcom/clock-qcs404.c index 3357b54c30c0..80218af73ef6 100644 --- a/arch/arm/mach-snapdragon/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -11,7 +11,7 @@ #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> -#include "clock-snapdragon.h" +#include "clock-qcom.h"
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c similarity index 98% rename from arch/arm/mach-snapdragon/clock-sdm845.c rename to drivers/clk/qcom/clock-sdm845.c index d6df0365afca..95a057b82986 100644 --- a/arch/arm/mach-snapdragon/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -15,7 +15,7 @@ #include <asm/io.h> #include <linux/bitops.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> -#include "clock-snapdragon.h" +#include "clock-qcom.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
This driver is just a stub, but it's necessary to support the upcoming reset driver changes.
Reviewed-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/Kconfig | 1 + arch/arm/mach-ipq40xx/Makefile | 1 - drivers/clk/qcom/Kconfig | 8 +++++ drivers/clk/qcom/Makefile | 1 + .../clk/qcom}/clock-ipq4019.c | 41 ++-------------------- drivers/clk/qcom/clock-qcom.c | 1 + 6 files changed, 13 insertions(+), 40 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c9842..8833ee3e8654 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -766,6 +766,7 @@ config ARCH_IPQ40XX select CLK select SMEM select OF_CONTROL + select CLK_QCOM_IPQ4019 imply CMD_DM
config ARCH_KEYSTONE diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile index 08a65b8854d3..b36a935c6f9f 100644 --- a/arch/arm/mach-ipq40xx/Makefile +++ b/arch/arm/mach-ipq40xx/Makefile @@ -4,6 +4,5 @@ # # Author: Robert Marko robert.marko@sartura.hr
-obj-y += clock-ipq4019.o obj-y += pinctrl-snapdragon.o obj-y += pinctrl-ipq4019.o diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a884f077d9b9..0df0d1881a49 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -23,6 +23,14 @@ config CLK_QCOM_APQ8096 on the Snapdragon APQ8096 SoC. This driver supports the clocks and resets exposed by the GCC hardware block.
+config CLK_QCOM_IPQ4019 + bool "Qualcomm IPQ4019 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon IPQ4019 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_QCS404 bool "Qualcomm QCS404 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 44d55583596d..cb179fdac583 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -6,4 +6,5 @@ obj-y += clock-qcom.o obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o +obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c similarity index 56% rename from arch/arm/mach-ipq40xx/clock-ipq4019.c rename to drivers/clk/qcom/clock-ipq4019.c index c1d5c4ecdd81..04c99964df15 100644 --- a/arch/arm/mach-ipq40xx/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -12,12 +12,9 @@ #include <common.h> #include <dm.h> #include <errno.h> - #include <dt-bindings/clock/qcom,ipq4019-gcc.h>
-struct msm_clk_priv { - phys_addr_t base; -}; +#include "clock-qcom.h"
ulong msm_set_rate(struct clk *clk, ulong rate) { @@ -30,23 +27,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate) } }
-static int msm_clk_probe(struct udevice *dev) -{ - struct msm_clk_priv *priv = dev_get_priv(dev); - - priv->base = dev_read_addr(dev); - if (priv->base == FDT_ADDR_T_NONE) - return -EINVAL; - - return 0; -} - -static ulong msm_clk_set_rate(struct clk *clk, ulong rate) -{ - return msm_set_rate(clk, rate); -} - -static int msm_enable(struct clk *clk) +int msm_enable(struct clk *clk) { switch (clk->id) { case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/ @@ -68,21 +49,3 @@ static int msm_enable(struct clk *clk) } }
-static struct clk_ops msm_clk_ops = { - .set_rate = msm_clk_set_rate, - .enable = msm_enable, -}; - -static const struct udevice_id msm_clk_ids[] = { - { .compatible = "qcom,gcc-ipq4019" }, - { } -}; - -U_BOOT_DRIVER(clk_msm) = { - .name = "clk_msm", - .id = UCLASS_CLK, - .of_match = msm_clk_ids, - .ops = &msm_clk_ops, - .priv_auto = sizeof(struct msm_clk_priv), - .probe = msm_clk_probe, -}; diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 5667abeb89a4..5914616fba5d 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -166,6 +166,7 @@ static const struct udevice_id msm_clk_ids[] = { { .compatible = "qcom,gcc-apq8016" }, { .compatible = "qcom,gcc-msm8996" }, { .compatible = "qcom,gcc-apq8096" }, + { .compatible = "qcom,gcc-ipq4019" }, { .compatible = "qcom,gcc-sdm845" }, { .compatible = "qcom,gcc-qcs404" }, { }
From: Konrad Dybcio konrad.dybcio@linaro.org
Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver.
Heavily inspired by Renesas code for a similar hw block.
[caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux]
Signed-off-by: Konrad Dybcio konrad.dybcio@linaro.org Reviewed-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/Kconfig | 1 + arch/arm/dts/qcom-ipq4019.dtsi | 14 +- arch/arm/dts/qcs404-evb.dts | 19 +- drivers/clk/qcom/clock-apq8016.c | 17 ++ drivers/clk/qcom/clock-apq8096.c | 16 ++ drivers/clk/qcom/clock-ipq4019.c | 96 +++++++++- drivers/clk/qcom/clock-qcom.c | 119 +++++++++++-- drivers/clk/qcom/clock-qcom.h | 22 ++- drivers/clk/qcom/clock-qcs404.c | 50 +++++- drivers/clk/qcom/clock-sdm845.c | 42 +++++ drivers/reset/Kconfig | 7 - drivers/reset/Makefile | 1 - drivers/reset/reset-qcom.c | 195 --------------------- .../{qcom,ipq4019-gcc.h => qcom,gcc-ipq4019.h} | 73 ++++++++ include/dt-bindings/reset/qcom,ipq4019-reset.h | 92 ---------- 15 files changed, 422 insertions(+), 342 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8833ee3e8654..69144ff9cdab 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1067,6 +1067,7 @@ config ARCH_SNAPDRAGON select DM select DM_GPIO select DM_SERIAL + select DM_RESET select GPIO_EXTRA_HEADER select MSM_SMEM select OF_CONTROL diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi index 0850ae56e9a8..f9489e42ea2c 100644 --- a/arch/arm/dts/qcom-ipq4019.dtsi +++ b/arch/arm/dts/qcom-ipq4019.dtsi @@ -66,14 +66,6 @@ status = "disabled"; };
- reset: gcc-reset@1800000 { - compatible = "qcom,gcc-reset-ipq4019"; - reg = <0x1800000 0x60000>; - #clock-cells = <1>; - #reset-cells = <1>; - bootph-all; - }; - soc_gpios: pinctrl@1000000 { compatible = "qcom,ipq4019-pinctrl"; reg = <0x1000000 0x300000>; @@ -136,7 +128,7 @@ #phy-cells = <0>; reg = <0x9a000 0x800>; reg-names = "phy_base"; - resets = <&reset USB3_UNIPHY_PHY_ARES>; + resets = <&gcc USB3_UNIPHY_PHY_ARES>; reset-names = "por_rst"; status = "disabled"; }; @@ -146,7 +138,7 @@ #phy-cells = <0>; reg = <0xa6000 0x40>; reg-names = "phy_base"; - resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>; + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; reset-names = "por_rst", "srif_rst"; status = "disabled"; }; @@ -179,7 +171,7 @@ #phy-cells = <0>; reg = <0xa8000 0x40>; reg-names = "phy_base"; - resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>; + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; reset-names = "por_rst", "srif_rst"; status = "disabled"; }; diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 8d7893c11695..84224a8a3d39 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -208,11 +208,6 @@ #address-cells = <0x1>; #size-cells = <0x0>; #clock-cells = <1>; - }; - - reset: gcc-reset@1800000 { - compatible = "qcom,gcc-reset-qcs404"; - reg = <0x1800000 0x80000>; #reset-cells = <1>; };
@@ -245,8 +240,8 @@ clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, <&gcc GCC_USB3_PHY_PIPE_CLK>; clock-names = "ahb", "pipe"; - resets = <&reset GCC_USB3_PHY_BCR>, - <&reset GCC_USB3PHY_PHY_BCR>; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; reset-names = "com", "phy"; };
@@ -257,8 +252,8 @@ clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; clock-names = "ahb", "sleep"; - resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>, - <&reset GCC_USB2A_PHY_BCR>; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; reset-names = "phy", "por"; };
@@ -269,8 +264,8 @@ clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; clock-names = "ahb", "sleep"; - resets = <&reset GCC_QUSB2_PHY_BCR>, - <&reset GCC_USB2_HS_PHY_ONLY_BCR>; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; reset-names = "phy", "por"; };
@@ -335,7 +330,7 @@ <&gcc GCC_ETH_PTP_CLK>, <&gcc GCC_ETH_RGMII_CLK>;
- resets = <&reset GCC_EMAC_BCR>; + resets = <&gcc GCC_EMAC_BCR>; reset-names = "emac";
snps,tso; diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 90f2a93d9ed5..3bddbd275906 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -13,6 +13,7 @@ #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> + #include "clock-qcom.h"
/* GPLL0 clock control registers */ @@ -116,3 +117,19 @@ int msm_enable(struct clk *clk) { return 0; } + +static const struct udevice_id gcc_apq8016_of_match[] = { + { + .compatible = "qcom,gcc-apq8016", + /* TODO: add reset map */ + }, + { } +}; + +U_BOOT_DRIVER(gcc_apq8016) = { + .name = "gcc_apq8016", + .id = UCLASS_NOP, + .of_match = gcc_apq8016_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index d5388c69aefe..64b8cdf4c54b 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -99,3 +99,19 @@ int msm_enable(struct clk *clk) { return 0; } + +static const struct udevice_id gcc_apq8096_of_match[] = { + { + .compatible = "qcom,gcc-apq8096", + /* TODO: add reset map */ + }, + { } +}; + +U_BOOT_DRIVER(gcc_apq8096) = { + .name = "gcc_apq8096", + .id = UCLASS_NOP, + .of_match = gcc_apq8096_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index 04c99964df15..db869f874219 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -12,7 +12,7 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <dt-bindings/clock/qcom,ipq4019-gcc.h> +#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include "clock-qcom.h"
@@ -49,3 +49,97 @@ int msm_enable(struct clk *clk) } }
+static const struct qcom_reset_map gcc_ipq4019_resets[] = { + [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 }, + [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 }, + [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 }, + [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 }, + [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 }, + [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 }, + [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 }, + [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 }, + [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 }, + [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 }, + [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 }, + [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 }, + [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 }, + [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 }, + [USB3_HSPHY_S_ARES] = { 0x1e038, 2 }, + [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 }, + [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 }, + [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 }, + [PCIE_AHB_ARES] = { 0x1d010, 10 }, + [PCIE_PWR_ARES] = { 0x1d010, 9 }, + [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 }, + [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 }, + [PCIE_PHY_ARES] = { 0x1d010, 6 }, + [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 }, + [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 }, + [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 }, + [PCIE_PIPE_ARES] = { 0x1d010, 2 }, + [PCIE_AXI_S_ARES] = { 0x1d010, 1 }, + [PCIE_AXI_M_ARES] = { 0x1d010, 0 }, + [ESS_RESET] = { 0x12008, 0}, + [GCC_BLSP1_BCR] = {0x01000, 0}, + [GCC_BLSP1_QUP1_BCR] = {0x02000, 0}, + [GCC_BLSP1_UART1_BCR] = {0x02038, 0}, + [GCC_BLSP1_QUP2_BCR] = {0x03008, 0}, + [GCC_BLSP1_UART2_BCR] = {0x03028, 0}, + [GCC_BIMC_BCR] = {0x04000, 0}, + [GCC_TLMM_BCR] = {0x05000, 0}, + [GCC_IMEM_BCR] = {0x0E000, 0}, + [GCC_ESS_BCR] = {0x12008, 0}, + [GCC_PRNG_BCR] = {0x13000, 0}, + [GCC_BOOT_ROM_BCR] = {0x13008, 0}, + [GCC_CRYPTO_BCR] = {0x16000, 0}, + [GCC_SDCC1_BCR] = {0x18000, 0}, + [GCC_SEC_CTRL_BCR] = {0x1A000, 0}, + [GCC_AUDIO_BCR] = {0x1B008, 0}, + [GCC_QPIC_BCR] = {0x1C000, 0}, + [GCC_PCIE_BCR] = {0x1D000, 0}, + [GCC_USB2_BCR] = {0x1E008, 0}, + [GCC_USB2_PHY_BCR] = {0x1E018, 0}, + [GCC_USB3_BCR] = {0x1E024, 0}, + [GCC_USB3_PHY_BCR] = {0x1E034, 0}, + [GCC_SYSTEM_NOC_BCR] = {0x21000, 0}, + [GCC_PCNOC_BCR] = {0x2102C, 0}, + [GCC_DCD_BCR] = {0x21038, 0}, + [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0}, + [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0}, + [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0}, + [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0}, + [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0}, + [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0}, + [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0}, + [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0}, + [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0}, + [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0}, + [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0}, + [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0}, + [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0}, + [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0}, + [GCC_TCSR_BCR] = {0x22000, 0}, + [GCC_MPM_BCR] = {0x24000, 0}, + [GCC_SPDM_BCR] = {0x25000, 0}, +}; + +static struct msm_clk_data ipq4019_data = { + .resets = gcc_ipq4019_resets, + .num_resets = ARRAY_SIZE(gcc_ipq4019_resets), +}; + +static const struct udevice_id gcc_ipq4019_of_match[] = { + { + .compatible = "qcom,gcc-ipq4019", + .data = (ulong)&ipq4019_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_ipq4019) = { + .name = "gcc_ipq4019", + .id = UCLASS_NOP, + .of_match = gcc_ipq4019_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 5914616fba5d..a661837e4e11 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -1,8 +1,13 @@ -// SPDX-License-Identifier: BSD-3-Clause +// SPDX-License-Identifier: BSD-3-Clause AND GPL-2.0 /* - * Clock drivers for Qualcomm APQ8016, APQ8096 + * Clock and reset drivers for Qualcomm platforms Global Clock + * Controller (GCC). * * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com + * (C) Copyright 2020 Sartura Ltd. (reset driver) + * Author: Robert Marko robert.marko@sartura.hr + * (C) Copyright 2022 Linaro Ltd. (reset driver) + * Author: Sumit Garg sumit.garg@linaro.org * * Based on Little Kernel driver, simplified */ @@ -10,9 +15,13 @@ #include <common.h> #include <clk-uclass.h> #include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> +#include <reset-uclass.h> + #include "clock-qcom.h"
/* CBCR register fields */ @@ -137,12 +146,15 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
static int msm_clk_probe(struct udevice *dev) { + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); struct msm_clk_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) return -EINVAL;
+ priv->data = data; + return 0; }
@@ -161,22 +173,97 @@ static struct clk_ops msm_clk_ops = { .enable = msm_clk_enable, };
-static const struct udevice_id msm_clk_ids[] = { - { .compatible = "qcom,gcc-msm8916" }, - { .compatible = "qcom,gcc-apq8016" }, - { .compatible = "qcom,gcc-msm8996" }, - { .compatible = "qcom,gcc-apq8096" }, - { .compatible = "qcom,gcc-ipq4019" }, - { .compatible = "qcom,gcc-sdm845" }, - { .compatible = "qcom,gcc-qcs404" }, - { } -}; - -U_BOOT_DRIVER(clk_msm) = { - .name = "clk_msm", +U_BOOT_DRIVER(qcom_clk) = { + .name = "qcom_clk", .id = UCLASS_CLK, - .of_match = msm_clk_ids, .ops = &msm_clk_ops, .priv_auto = sizeof(struct msm_clk_priv), .probe = msm_clk_probe, }; + +int qcom_cc_bind(struct udevice *parent) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent); + struct udevice *clkdev, *rstdev; + struct driver *drv; + int ret; + + /* Get a handle to the common clk handler */ + drv = lists_driver_lookup_name("qcom_clk"); + if (!drv) + return -ENOENT; + + /* Register the clock controller */ + ret = device_bind_with_driver_data(parent, drv, "qcom_clk", (ulong)data, + dev_ofnode(parent), &clkdev); + if (ret) + return ret; + + /* Bail out early if resets are not specified for this platform */ + if (!data->resets) + return ret; + + /* Get a handle to the common reset handler */ + drv = lists_driver_lookup_name("qcom_reset"); + if (!drv) + return -ENOENT; + + /* Register the reset controller */ + ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data, + dev_ofnode(parent), &rstdev); + if (ret) + device_unbind(clkdev); + + return ret; +} + +static int qcom_reset_set(struct reset_ctl *rst, bool assert) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(rst->dev); + void __iomem *base = dev_get_priv(rst->dev); + const struct qcom_reset_map *map; + u32 value; + + map = &data->resets[rst->id]; + + value = readl(base + map->reg); + + if (assert) + value |= BIT(map->bit); + else + value &= ~BIT(map->bit); + + writel(value, base + map->reg); + + return 0; +} + +static int qcom_reset_assert(struct reset_ctl *rst) +{ + return qcom_reset_set(rst, true); +} + +static int qcom_reset_deassert(struct reset_ctl *rst) +{ + return qcom_reset_set(rst, false); +} + +static const struct reset_ops qcom_reset_ops = { + .rst_assert = qcom_reset_assert, + .rst_deassert = qcom_reset_deassert, +}; + +static int qcom_reset_probe(struct udevice *dev) +{ + /* Set our priv pointer to the base address */ + dev_set_priv(dev, (void *)dev_read_addr(dev)); + + return 0; +} + +U_BOOT_DRIVER(qcom_reset) = { + .name = "qcom_reset", + .id = UCLASS_RESET, + .ops = &qcom_reset_ops, + .probe = qcom_reset_probe, +}; diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index c90bbefa5881..a9f895c2422e 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Qualcomm APQ8016, APQ8096, SDM845 - * * (C) Copyright 2017 Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org */ -#ifndef _CLOCK_SNAPDRAGON_H -#define _CLOCK_SNAPDRAGON_H +#ifndef _CLOCK_QCOM_H +#define _CLOCK_QCOM_H
#define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) @@ -32,10 +30,22 @@ struct bcr_regs { uintptr_t D; };
-struct msm_clk_priv { - phys_addr_t base; +struct qcom_reset_map { + unsigned int reg; + u8 bit; };
+struct msm_clk_data { + const struct qcom_reset_map *resets; + unsigned long num_resets; +}; + +struct msm_clk_priv { + phys_addr_t base; + struct msm_clk_data *data; +}; + +int qcom_cc_bind(struct udevice *parent); void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 80218af73ef6..10ac3609be42 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -11,9 +11,10 @@ #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-qcs404.h> + #include "clock-qcom.h"
-#include <dt-bindings/clock/qcom,gcc-qcs404.h>
/* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(31) @@ -235,3 +236,50 @@ int msm_enable(struct clk *clk)
return 0; } + +static const struct qcom_reset_map qcs404_gcc_resets[] = { + [GCC_GENI_IR_BCR] = { 0x0F000 }, + [GCC_CDSP_RESTART] = { 0x18000 }, + [GCC_USB_HS_BCR] = { 0x41000 }, + [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 }, + [GCC_QUSB2_PHY_BCR] = { 0x4103c }, + [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 }, + [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 }, + [GCC_USB3_PHY_BCR] = { 0x39004 }, + [GCC_USB_30_BCR] = { 0x39000 }, + [GCC_USB3PHY_PHY_BCR] = { 0x39008 }, + [GCC_PCIE_0_BCR] = { 0x3e000 }, + [GCC_PCIE_0_PHY_BCR] = { 0x3e004 }, + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 }, + [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c }, + [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6}, + [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 }, + [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 }, + [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 }, + [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 }, + [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, + [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, + [GCC_EMAC_BCR] = { 0x4e000 }, + [GCC_WDSP_RESTART] = {0x19000}, +}; + +static const struct msm_clk_data qcs404_gcc_data = { + .resets = qcs404_gcc_resets, + .num_resets = ARRAY_SIZE(qcs404_gcc_resets), +}; + +static const struct udevice_id gcc_qcs404_of_match[] = { + { + .compatible = "qcom,gcc-qcs404", + .data = (ulong)&qcs404_gcc_data + }, + { } +}; + +U_BOOT_DRIVER(gcc_qcs404) = { + .name = "gcc_qcs404", + .id = UCLASS_NOP, + .of_match = gcc_qcs404_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index 95a057b82986..a7a43f69b9b3 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -15,6 +15,7 @@ #include <asm/io.h> #include <linux/bitops.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include "clock-qcom.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } @@ -96,3 +97,44 @@ int msm_enable(struct clk *clk) { return 0; } + +static const struct qcom_reset_map sdm845_gcc_resets[] = { + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_UFS_CARD_BCR] = { 0x75000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB30_PRIM_BCR] = { 0xf000 }, + [GCC_USB30_SEC_BCR] = { 0x10000 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, + [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, + [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, +}; + +static const struct msm_clk_data qcs404_gcc_data = { + .resets = sdm845_gcc_resets, + .num_resets = ARRAY_SIZE(sdm845_gcc_resets), +}; + +static const struct udevice_id gcc_sdm845_of_match[] = { + { + .compatible = "qcom,gcc-sdm845", + .data = (ulong)&qcs404_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_sdm845) = { + .name = "gcc_sdm845", + .id = UCLASS_NOP, + .of_match = gcc_sdm845_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 73bbd3069258..88e04d93f2a0 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -156,13 +156,6 @@ config RESET_IMX7 help Support for reset controller on i.MX7/8 SoCs.
-config RESET_QCOM - bool "Reset driver for Qualcomm SoCs" - depends on DM_RESET && (ARCH_SNAPDRAGON || ARCH_IPQ40XX) - default y - help - Support for reset controller on Qualcomm SoCs. - config RESET_SIFIVE bool "Reset Driver for SiFive SoC's" depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED) diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index e2239a250a3a..7b0066f80188 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -24,7 +24,6 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o -obj-$(CONFIG_RESET_QCOM) += reset-qcom.o obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c deleted file mode 100644 index 94315e76d545..000000000000 --- a/drivers/reset/reset-qcom.c +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2020 Sartura Ltd. - * Copyright (c) 2022 Linaro Ltd. - * - * Author: Robert Marko robert.marko@sartura.hr - * Sumit Garg sumit.garg@linaro.org - * - * Based on Linux driver - */ - -#include <asm/io.h> -#include <common.h> -#include <dm.h> -#include <reset-uclass.h> -#include <linux/bitops.h> -#include <malloc.h> - -struct qcom_reset_priv { - phys_addr_t base; -}; - -struct qcom_reset_map { - unsigned int reg; - u8 bit; -}; - -#ifdef CONFIG_ARCH_IPQ40XX -#include <dt-bindings/reset/qcom,ipq4019-reset.h> -static const struct qcom_reset_map gcc_qcom_resets[] = { - [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 }, - [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 }, - [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 }, - [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 }, - [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 }, - [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 }, - [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 }, - [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 }, - [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 }, - [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 }, - [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 }, - [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 }, - [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 }, - [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 }, - [USB3_HSPHY_S_ARES] = { 0x1e038, 2 }, - [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 }, - [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 }, - [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 }, - [PCIE_AHB_ARES] = { 0x1d010, 10 }, - [PCIE_PWR_ARES] = { 0x1d010, 9 }, - [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 }, - [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 }, - [PCIE_PHY_ARES] = { 0x1d010, 6 }, - [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 }, - [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 }, - [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 }, - [PCIE_PIPE_ARES] = { 0x1d010, 2 }, - [PCIE_AXI_S_ARES] = { 0x1d010, 1 }, - [PCIE_AXI_M_ARES] = { 0x1d010, 0 }, - [ESS_RESET] = { 0x12008, 0}, - [GCC_BLSP1_BCR] = {0x01000, 0}, - [GCC_BLSP1_QUP1_BCR] = {0x02000, 0}, - [GCC_BLSP1_UART1_BCR] = {0x02038, 0}, - [GCC_BLSP1_QUP2_BCR] = {0x03008, 0}, - [GCC_BLSP1_UART2_BCR] = {0x03028, 0}, - [GCC_BIMC_BCR] = {0x04000, 0}, - [GCC_TLMM_BCR] = {0x05000, 0}, - [GCC_IMEM_BCR] = {0x0E000, 0}, - [GCC_ESS_BCR] = {0x12008, 0}, - [GCC_PRNG_BCR] = {0x13000, 0}, - [GCC_BOOT_ROM_BCR] = {0x13008, 0}, - [GCC_CRYPTO_BCR] = {0x16000, 0}, - [GCC_SDCC1_BCR] = {0x18000, 0}, - [GCC_SEC_CTRL_BCR] = {0x1A000, 0}, - [GCC_AUDIO_BCR] = {0x1B008, 0}, - [GCC_QPIC_BCR] = {0x1C000, 0}, - [GCC_PCIE_BCR] = {0x1D000, 0}, - [GCC_USB2_BCR] = {0x1E008, 0}, - [GCC_USB2_PHY_BCR] = {0x1E018, 0}, - [GCC_USB3_BCR] = {0x1E024, 0}, - [GCC_USB3_PHY_BCR] = {0x1E034, 0}, - [GCC_SYSTEM_NOC_BCR] = {0x21000, 0}, - [GCC_PCNOC_BCR] = {0x2102C, 0}, - [GCC_DCD_BCR] = {0x21038, 0}, - [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0}, - [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0}, - [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0}, - [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0}, - [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0}, - [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0}, - [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0}, - [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0}, - [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0}, - [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0}, - [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0}, - [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0}, - [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0}, - [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0}, - [GCC_TCSR_BCR] = {0x22000, 0}, - [GCC_MPM_BCR] = {0x24000, 0}, - [GCC_SPDM_BCR] = {0x25000, 0}, -}; -#endif - -#ifdef CONFIG_TARGET_QCS404EVB -#include <dt-bindings/clock/qcom,gcc-qcs404.h> -static const struct qcom_reset_map gcc_qcom_resets[] = { - [GCC_GENI_IR_BCR] = { 0x0F000 }, - [GCC_CDSP_RESTART] = { 0x18000 }, - [GCC_USB_HS_BCR] = { 0x41000 }, - [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 }, - [GCC_QUSB2_PHY_BCR] = { 0x4103c }, - [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 }, - [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 }, - [GCC_USB3_PHY_BCR] = { 0x39004 }, - [GCC_USB_30_BCR] = { 0x39000 }, - [GCC_USB3PHY_PHY_BCR] = { 0x39008 }, - [GCC_PCIE_0_BCR] = { 0x3e000 }, - [GCC_PCIE_0_PHY_BCR] = { 0x3e004 }, - [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 }, - [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c }, - [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6}, - [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 }, - [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 }, - [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 }, - [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 }, - [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, - [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, - [GCC_EMAC_BCR] = { 0x4e000 }, - [GCC_WDSP_RESTART] = {0x19000}, -}; -#endif - -static int qcom_reset_assert(struct reset_ctl *rst) -{ - struct qcom_reset_priv *priv = dev_get_priv(rst->dev); - const struct qcom_reset_map *reset_map = gcc_qcom_resets; - const struct qcom_reset_map *map; - u32 value; - - map = &reset_map[rst->id]; - - value = readl(priv->base + map->reg); - value |= BIT(map->bit); - writel(value, priv->base + map->reg); - - return 0; -} - -static int qcom_reset_deassert(struct reset_ctl *rst) -{ - struct qcom_reset_priv *priv = dev_get_priv(rst->dev); - const struct qcom_reset_map *reset_map = gcc_qcom_resets; - const struct qcom_reset_map *map; - u32 value; - - map = &reset_map[rst->id]; - - value = readl(priv->base + map->reg); - value &= ~BIT(map->bit); - writel(value, priv->base + map->reg); - - return 0; -} - -static const struct reset_ops qcom_reset_ops = { - .rst_assert = qcom_reset_assert, - .rst_deassert = qcom_reset_deassert, -}; - -static const struct udevice_id qcom_reset_ids[] = { - { .compatible = "qcom,gcc-reset-ipq4019" }, - { .compatible = "qcom,gcc-reset-qcs404" }, - { } -}; - -static int qcom_reset_probe(struct udevice *dev) -{ - struct qcom_reset_priv *priv = dev_get_priv(dev); - - priv->base = dev_read_addr(dev); - if (priv->base == FDT_ADDR_T_NONE) - return -EINVAL; - - return 0; -} - -U_BOOT_DRIVER(qcom_reset) = { - .name = "qcom_reset", - .id = UCLASS_RESET, - .of_match = qcom_reset_ids, - .ops = &qcom_reset_ops, - .probe = qcom_reset_probe, - .priv_auto = sizeof(struct qcom_reset_priv), -}; diff --git a/include/dt-bindings/clock/qcom,ipq4019-gcc.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h similarity index 58% rename from include/dt-bindings/clock/qcom,ipq4019-gcc.h rename to include/dt-bindings/clock/qcom,gcc-ipq4019.h index 7130e222e41c..7e8a7be6dcda 100644 --- a/include/dt-bindings/clock/qcom,ipq4019-gcc.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h @@ -93,4 +93,77 @@ #define GCC_APSS_CPU_PLLDIV_CLK 74 #define GCC_PCNOC_AHB_CLK_SRC 75
+#define WIFI0_CPU_INIT_RESET 0 +#define WIFI0_RADIO_SRIF_RESET 1 +#define WIFI0_RADIO_WARM_RESET 2 +#define WIFI0_RADIO_COLD_RESET 3 +#define WIFI0_CORE_WARM_RESET 4 +#define WIFI0_CORE_COLD_RESET 5 +#define WIFI1_CPU_INIT_RESET 6 +#define WIFI1_RADIO_SRIF_RESET 7 +#define WIFI1_RADIO_WARM_RESET 8 +#define WIFI1_RADIO_COLD_RESET 9 +#define WIFI1_CORE_WARM_RESET 10 +#define WIFI1_CORE_COLD_RESET 11 +#define USB3_UNIPHY_PHY_ARES 12 +#define USB3_HSPHY_POR_ARES 13 +#define USB3_HSPHY_S_ARES 14 +#define USB2_HSPHY_POR_ARES 15 +#define USB2_HSPHY_S_ARES 16 +#define PCIE_PHY_AHB_ARES 17 +#define PCIE_AHB_ARES 18 +#define PCIE_PWR_ARES 19 +#define PCIE_PIPE_STICKY_ARES 20 +#define PCIE_AXI_M_STICKY_ARES 21 +#define PCIE_PHY_ARES 22 +#define PCIE_PARF_XPU_ARES 23 +#define PCIE_AXI_S_XPU_ARES 24 +#define PCIE_AXI_M_VMIDMT_ARES 25 +#define PCIE_PIPE_ARES 26 +#define PCIE_AXI_S_ARES 27 +#define PCIE_AXI_M_ARES 28 +#define ESS_RESET 29 +#define GCC_BLSP1_BCR 30 +#define GCC_BLSP1_QUP1_BCR 31 +#define GCC_BLSP1_UART1_BCR 32 +#define GCC_BLSP1_QUP2_BCR 33 +#define GCC_BLSP1_UART2_BCR 34 +#define GCC_BIMC_BCR 35 +#define GCC_TLMM_BCR 36 +#define GCC_IMEM_BCR 37 +#define GCC_ESS_BCR 38 +#define GCC_PRNG_BCR 39 +#define GCC_BOOT_ROM_BCR 40 +#define GCC_CRYPTO_BCR 41 +#define GCC_SDCC1_BCR 42 +#define GCC_SEC_CTRL_BCR 43 +#define GCC_AUDIO_BCR 44 +#define GCC_QPIC_BCR 45 +#define GCC_PCIE_BCR 46 +#define GCC_USB2_BCR 47 +#define GCC_USB2_PHY_BCR 48 +#define GCC_USB3_BCR 49 +#define GCC_USB3_PHY_BCR 50 +#define GCC_SYSTEM_NOC_BCR 51 +#define GCC_PCNOC_BCR 52 +#define GCC_DCD_BCR 53 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 +#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 +#define GCC_TCSR_BCR 68 +#define GCC_QDSS_BCR 69 +#define GCC_MPM_BCR 70 +#define GCC_SPDM_BCR 71 + #endif diff --git a/include/dt-bindings/reset/qcom,ipq4019-reset.h b/include/dt-bindings/reset/qcom,ipq4019-reset.h deleted file mode 100644 index ed047d7402df..000000000000 --- a/include/dt-bindings/reset/qcom,ipq4019-reset.h +++ /dev/null @@ -1,92 +0,0 @@ -/* Copyright (c) 2015 The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -#ifndef __QCOM_RESET_IPQ4019_H__ -#define __QCOM_RESET_IPQ4019_H__ - -#define WIFI0_CPU_INIT_RESET 0 -#define WIFI0_RADIO_SRIF_RESET 1 -#define WIFI0_RADIO_WARM_RESET 2 -#define WIFI0_RADIO_COLD_RESET 3 -#define WIFI0_CORE_WARM_RESET 4 -#define WIFI0_CORE_COLD_RESET 5 -#define WIFI1_CPU_INIT_RESET 6 -#define WIFI1_RADIO_SRIF_RESET 7 -#define WIFI1_RADIO_WARM_RESET 8 -#define WIFI1_RADIO_COLD_RESET 9 -#define WIFI1_CORE_WARM_RESET 10 -#define WIFI1_CORE_COLD_RESET 11 -#define USB3_UNIPHY_PHY_ARES 12 -#define USB3_HSPHY_POR_ARES 13 -#define USB3_HSPHY_S_ARES 14 -#define USB2_HSPHY_POR_ARES 15 -#define USB2_HSPHY_S_ARES 16 -#define PCIE_PHY_AHB_ARES 17 -#define PCIE_AHB_ARES 18 -#define PCIE_PWR_ARES 19 -#define PCIE_PIPE_STICKY_ARES 20 -#define PCIE_AXI_M_STICKY_ARES 21 -#define PCIE_PHY_ARES 22 -#define PCIE_PARF_XPU_ARES 23 -#define PCIE_AXI_S_XPU_ARES 24 -#define PCIE_AXI_M_VMIDMT_ARES 25 -#define PCIE_PIPE_ARES 26 -#define PCIE_AXI_S_ARES 27 -#define PCIE_AXI_M_ARES 28 -#define ESS_RESET 29 -#define GCC_BLSP1_BCR 30 -#define GCC_BLSP1_QUP1_BCR 31 -#define GCC_BLSP1_UART1_BCR 32 -#define GCC_BLSP1_QUP2_BCR 33 -#define GCC_BLSP1_UART2_BCR 34 -#define GCC_BIMC_BCR 35 -#define GCC_TLMM_BCR 36 -#define GCC_IMEM_BCR 37 -#define GCC_ESS_BCR 38 -#define GCC_PRNG_BCR 39 -#define GCC_BOOT_ROM_BCR 40 -#define GCC_CRYPTO_BCR 41 -#define GCC_SDCC1_BCR 42 -#define GCC_SEC_CTRL_BCR 43 -#define GCC_AUDIO_BCR 44 -#define GCC_QPIC_BCR 45 -#define GCC_PCIE_BCR 46 -#define GCC_USB2_BCR 47 -#define GCC_USB2_PHY_BCR 48 -#define GCC_USB3_BCR 49 -#define GCC_USB3_PHY_BCR 50 -#define GCC_SYSTEM_NOC_BCR 51 -#define GCC_PCNOC_BCR 52 -#define GCC_DCD_BCR 53 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 -#define GCC_TCSR_BCR 68 -#define GCC_QDSS_BCR 69 -#define GCC_MPM_BCR 70 -#define GCC_SPDM_BCR 71 - -#endif
Many gate clocks can be enabled with a single register write, add support for defining these simple gate clocks and add the ones found on SDM845.
While we're here, inline clk_init_uart() into msm_set_rate().
Reviewed-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/clk/qcom/clock-qcom.h | 26 ++++++++++++ drivers/clk/qcom/clock-sdm845.c | 87 +++++++++++++++++++++++++++++++++++------ 2 files changed, 101 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index a9f895c2422e..6d399db987b6 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -5,6 +5,8 @@ #ifndef _CLOCK_QCOM_H #define _CLOCK_QCOM_H
+#include <asm/io.h> + #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) @@ -30,6 +32,18 @@ struct bcr_regs { uintptr_t D; };
+struct gate_clk { + uintptr_t reg; + u32 en_val; + const char *name; +}; + +#ifdef DEBUG +#define GATE_CLK(clk, reg, val) [clk] = { reg, val, #clk } +#else +#define GATE_CLK(clk, reg, val) [clk] = { reg, val, NULL } +#endif + struct qcom_reset_map { unsigned int reg; u8 bit; @@ -38,6 +52,8 @@ struct qcom_reset_map { struct msm_clk_data { const struct qcom_reset_map *resets; unsigned long num_resets; + const struct gate_clk *clks; + unsigned long num_clks; };
struct msm_clk_priv { @@ -55,4 +71,14 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, int source);
+static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) +{ + u32 val; + if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) + return; + + val = readl(priv->base + priv->data->clks[id].reg); + writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg); +} + #endif diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index a7a43f69b9b3..57124e2a661a 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -11,6 +11,7 @@ #include <common.h> #include <clk-uclass.h> #include <dm.h> +#include <linux/delay.h> #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> @@ -71,30 +72,90 @@ const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) return f - 1; }
-static int clk_init_uart(struct msm_clk_priv *priv, uint rate) -{ - const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); - - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, - freq->pre_div, freq->m, freq->n, freq->src); - - return 0; -} - ulong msm_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq;
switch (clk->id) { - case GCC_QUPV3_WRAP1_S1_CLK: /*UART2*/ - return clk_init_uart(priv, rate); + case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */ + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, &uart2_regs, + freq->pre_div, freq->m, freq->n, freq->src); + + return freq->freq; default: return 0; } }
+static const struct gate_clk sdm845_clks[] = { + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400), + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800), + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000), + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, 0x00002000), + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x5200c, 0x00004000), + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x5200c, 0x00008000), + GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x5200c, 0x00010000), + GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x5200c, 0x00020000), + GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x5200c, 0x00400000), + GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x5200c, 0x00800000), + GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x5200c, 0x02000000), + GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, 0x04000000), + GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, 0x08000000), + GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK, 0x5200c, 0x10000000), + GATE_CLK(GCC_QUPV3_WRAP1_S7_CLK, 0x5200c, 0x20000000), + GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x5200c, 0x00000040), + GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x5200c, 0x00000080), + GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x5200c, 0x00100000), + GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x5200c, 0x00200000), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, 0x00000001), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, 0x00000001), + GATE_CLK(GCC_SDCC4_AHB_CLK, 0x16008, 0x00000001), + GATE_CLK(GCC_SDCC4_APPS_CLK, 0x16004, 0x00000001), + GATE_CLK(GCC_UFS_CARD_AHB_CLK, 0x75010, 0x00000001), + GATE_CLK(GCC_UFS_CARD_AXI_CLK, 0x7500c, 0x00000001), + GATE_CLK(GCC_UFS_CARD_CLKREF_CLK, 0x8c004, 0x00000001), + GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK, 0x75058, 0x00000001), + GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK, 0x7508c, 0x00000001), + GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK, 0x75018, 0x00000001), + GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK, 0x750a8, 0x00000001), + GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK, 0x75014, 0x00000001), + GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK, 0x75054, 0x00000001), + GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, 0x00000001), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77010, 0x00000001), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x7700c, 0x00000001), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77058, 0x00000001), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7708c, 0x00000001), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77018, 0x00000001), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770a8, 0x00000001), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77014, 0x00000001), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77054, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x0f00c, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x0f014, 0x00000001), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x0f010, 0x00000001), + GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x1000c, 0x00000001), + GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x10014, 0x00000001), + GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x10010, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c008, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x0f04c, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x0f050, 0x00000001), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x0f054, 0x00000001), + GATE_CLK(GCC_USB3_SEC_CLKREF_CLK, 0x8c028, 0x00000001), + GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x1004c, 0x00000001), + GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK, 0x10054, 0x00000001), + GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x10050, 0x00000001), + GATE_CLK(GCC_USB_PHY_CFG_AHB2PHY_CLK, 0x6a004, 0x00000001), +}; + int msm_enable(struct clk *clk) { + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name); + + qcom_gate_clk_en(priv, clk->id); + return 0; }
@@ -121,6 +182,8 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { static const struct msm_clk_data qcs404_gcc_data = { .resets = sdm845_gcc_resets, .num_resets = ARRAY_SIZE(sdm845_gcc_resets), + .clks = sdm845_clks, + .num_clks = ARRAY_SIZE(sdm845_clks), };
static const struct udevice_id gcc_sdm845_of_match[] = {
Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented.
Extend qcom_clk_data to include function pointers for these and convert all platforms to use them.
Previously, clock drivers relied on include/configs/<board.h> to include the board specific sysmap header, however as most of the header contents are clock driver related, import the contents directly into each clock driver and remove the header. The only exception here is the dragonboard820c board file which includes some pinctrl macros, those are also inlined.
Reviewed-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- .../mach-snapdragon/include/mach/sysmap-apq8016.h | 39 ---------- .../mach-snapdragon/include/mach/sysmap-apq8096.h | 37 --------- .../mach-snapdragon/include/mach/sysmap-qcs404.h | 88 ---------------------- .../mach-snapdragon/include/mach/sysmap-sdm845.h | 42 ----------- board/qualcomm/dragonboard820c/dragonboard820c.c | 6 +- drivers/clk/qcom/clock-apq8016.c | 37 +++++++-- drivers/clk/qcom/clock-apq8096.c | 33 ++++++-- drivers/clk/qcom/clock-ipq4019.c | 10 ++- drivers/clk/qcom/clock-qcom.c | 17 +++-- drivers/clk/qcom/clock-qcom.h | 5 ++ drivers/clk/qcom/clock-qcs404.c | 85 ++++++++++++++++++++- drivers/clk/qcom/clock-sdm845.c | 19 ++++- include/configs/dragonboard410c.h | 1 - include/configs/dragonboard820c.h | 1 - include/configs/dragonboard845c.h | 1 - include/configs/qcs404-evb.h | 1 - 16 files changed, 182 insertions(+), 240 deletions(-)
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h deleted file mode 100644 index d9a3b1af986d..000000000000 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Qualcomm APQ8916 sysmap - * - * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com - */ -#ifndef _MACH_SYSMAP_APQ8016_H -#define _MACH_SYSMAP_APQ8016_H - -#define GICD_BASE (0x0b000000) -#define GICC_BASE (0x0b002000) - -/* Clocks: (from CLK_CTL_BASE) */ -#define GPLL0_STATUS (0x2101C) -#define APCS_GPLL_ENA_VOTE (0x45000) -#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) - -#define SDCC_BCR(n) ((n * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) -#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) -#define SDCC_M(n) ((n * 0x1000) + 0x4100C) -#define SDCC_N(n) ((n * 0x1000) + 0x41010) -#define SDCC_D(n) ((n * 0x1000) + 0x41014) -#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) -#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) - -/* BLSP1 AHB clock (root clock for BLSP) */ -#define BLSP1_AHB_CBCR 0x1008 - -/* Uart clock control registers */ -#define BLSP1_UART2_BCR (0x3028) -#define BLSP1_UART2_APPS_CBCR (0x302C) -#define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -#define BLSP1_UART2_APPS_M (0x303C) -#define BLSP1_UART2_APPS_N (0x3040) -#define BLSP1_UART2_APPS_D (0x3044) - -#endif diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h deleted file mode 100644 index 36a902bd9290..000000000000 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Qualcomm APQ8096 sysmap - * - * (C) Copyright 2017 Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org - */ -#ifndef _MACH_SYSMAP_APQ8096_H -#define _MACH_SYSMAP_APQ8096_H - -#define TLMM_BASE_ADDR (0x1010000) - -/* Strength (sdc1) */ -#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) - -/* Clocks: (from CLK_CTL_BASE) */ -#define GPLL0_STATUS (0x0000) -#define APCS_GPLL_ENA_VOTE (0x52000) -#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) - -#define SDCC2_BCR (0x14000) /* block reset */ -#define SDCC2_APPS_CBCR (0x14004) /* branch control */ -#define SDCC2_AHB_CBCR (0x14008) -#define SDCC2_CMD_RCGR (0x14010) -#define SDCC2_CFG_RCGR (0x14014) -#define SDCC2_M (0x14018) -#define SDCC2_N (0x1401C) -#define SDCC2_D (0x14020) - -#define BLSP2_AHB_CBCR (0x25004) -#define BLSP2_UART2_APPS_CBCR (0x29004) -#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) -#define BLSP2_UART2_APPS_CFG_RCGR (0x29010) -#define BLSP2_UART2_APPS_M (0x29014) -#define BLSP2_UART2_APPS_N (0x29018) -#define BLSP2_UART2_APPS_D (0x2901C) - -#endif diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h deleted file mode 100644 index 5768fb13775c..000000000000 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Qualcomm QCS404 sysmap - * - * (C) Copyright 2022 Sumit Garg sumit.garg@linaro.org - */ -#ifndef _MACH_SYSMAP_QCS404_H -#define _MACH_SYSMAP_QCS404_H - -#define GICD_BASE (0x0b000000) -#define GICC_BASE (0x0b002000) - -/* Clocks: (from CLK_CTL_BASE) */ -#define GPLL0_STATUS (0x21000) -#define GPLL1_STATUS (0x20000) -#define APCS_GPLL_ENA_VOTE (0x45000) -#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) - -/* BLSP1 AHB clock (root clock for BLSP) */ -#define BLSP1_AHB_CBCR 0x1008 - -/* Uart clock control registers */ -#define BLSP1_UART2_BCR (0x3028) -#define BLSP1_UART2_APPS_CBCR (0x302C) -#define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -#define BLSP1_UART2_APPS_M (0x303C) -#define BLSP1_UART2_APPS_N (0x3040) -#define BLSP1_UART2_APPS_D (0x3044) - -/* I2C controller clock control registerss */ -#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028) -#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C) -#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030) -#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008) -#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C) -#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010) -#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010) -#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000) -#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004) -#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020) -#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000) -#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004) -#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020) -#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000) -#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004) - -/* SD controller clock control registers */ -#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004) -#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008) -#define SDCC_M(n) (((n) * 0x1000) + 0x4100C) -#define SDCC_N(n) (((n) * 0x1000) + 0x41010) -#define SDCC_D(n) (((n) * 0x1000) + 0x41014) -#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018) -#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C) - -/* USB-3.0 controller clock control registers */ -#define SYS_NOC_USB3_CBCR (0x26014) -#define USB30_BCR (0x39000) -#define USB3PHY_BCR (0x39008) -#define USB30_MASTER_CBCR (0x3900C) -#define USB30_SLEEP_CBCR (0x39010) -#define USB30_MOCK_UTMI_CBCR (0x39014) -#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C) -#define USB30_MOCK_UTMI_CFG_RCGR (0x39020) -#define USB30_MASTER_CMD_RCGR (0x39028) -#define USB30_MASTER_CFG_RCGR (0x3902C) -#define USB30_MASTER_M (0x39030) -#define USB30_MASTER_N (0x39034) -#define USB30_MASTER_D (0x39038) -#define USB2A_PHY_SLEEP_CBCR (0x4102C) -#define USB_HS_PHY_CFG_AHB_CBCR (0x41030) - -/* ETH controller clock control registers */ -#define ETH_PTP_CBCR (0x4e004) -#define ETH_RGMII_CBCR (0x4e008) -#define ETH_SLAVE_AHB_CBCR (0x4e00c) -#define ETH_AXI_CBCR (0x4e010) -#define EMAC_PTP_CMD_RCGR (0x4e014) -#define EMAC_PTP_CFG_RCGR (0x4e018) -#define EMAC_CMD_RCGR (0x4e01c) -#define EMAC_CFG_RCGR (0x4e020) -#define EMAC_M (0x4e024) -#define EMAC_N (0x4e028) -#define EMAC_D (0x4e02c) - -#endif diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h b/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h deleted file mode 100644 index 7165985bcd1e..000000000000 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Qualcomm SDM845 sysmap - * - * (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com - */ -#ifndef _MACH_SYSMAP_SDM845_H -#define _MACH_SYSMAP_SDM845_H - -#define TLMM_BASE_ADDR (0x1010000) - -/* Strength (sdc1) */ -#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) - -/* Clocks: (from CLK_CTL_BASE) */ -#define GPLL0_STATUS (0x0000) -#define APCS_GPLL_ENA_VOTE (0x52000) -#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) - -#define SDCC2_BCR (0x14000) /* block reset */ -#define SDCC2_APPS_CBCR (0x14004) /* branch control */ -#define SDCC2_AHB_CBCR (0x14008) -#define SDCC2_CMD_RCGR (0x1400c) -#define SDCC2_CFG_RCGR (0x14010) -#define SDCC2_M (0x14014) -#define SDCC2_N (0x14018) -#define SDCC2_D (0x1401C) - -#define RCG2_CFG_REG 0x4 -#define M_REG 0x8 -#define N_REG 0xc -#define D_REG 0x10 - -#define SE9_AHB_CBCR (0x25004) -#define SE9_UART_APPS_CBCR (0x29004) -#define SE9_UART_APPS_CMD_RCGR (0x18148) -#define SE9_UART_APPS_CFG_RCGR (0x1814C) -#define SE9_UART_APPS_M (0x18150) -#define SE9_UART_APPS_N (0x18154) -#define SE9_UART_APPS_D (0x18158) - -#endif diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c index f9cc762a25cd..6785bf58e949 100644 --- a/board/qualcomm/dragonboard820c/dragonboard820c.c +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c @@ -7,7 +7,6 @@
#include <cpu_func.h> #include <init.h> -#include <asm/arch/sysmap-apq8096.h> #include <env.h> #include <asm/cache.h> #include <asm/global_data.h> @@ -20,6 +19,11 @@ #include <asm/psci.h> #include <asm/gpio.h>
+#define TLMM_BASE_ADDR (0x1010000) + +/* Strength (sdc1) */ +#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) + DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 3bddbd275906..3f44252c453e 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -16,6 +16,32 @@
#include "clock-qcom.h"
+/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x2101C) +#define APCS_GPLL_ENA_VOTE (0x45000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) + +#define SDCC_BCR(n) ((n * 0x1000) + 0x41000) +#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) +#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) +#define SDCC_M(n) ((n * 0x1000) + 0x4100C) +#define SDCC_N(n) ((n * 0x1000) + 0x41010) +#define SDCC_D(n) ((n * 0x1000) + 0x41014) +#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) +#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) + +/* BLSP1 AHB clock (root clock for BLSP) */ +#define BLSP1_AHB_CBCR 0x1008 + +/* Uart clock control registers */ +#define BLSP1_UART2_BCR (0x3028) +#define BLSP1_UART2_APPS_CBCR (0x302C) +#define BLSP1_UART2_APPS_CMD_RCGR (0x3034) +#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) +#define BLSP1_UART2_APPS_M (0x303C) +#define BLSP1_UART2_APPS_N (0x3040) +#define BLSP1_UART2_APPS_D (0x3044) + /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17)
@@ -94,7 +120,7 @@ static int clk_init_uart(struct msm_clk_priv *priv) return 0; }
-ulong msm_set_rate(struct clk *clk, ulong rate) +static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -113,15 +139,14 @@ ulong msm_set_rate(struct clk *clk, ulong rate) } }
-int msm_enable(struct clk *clk) -{ - return 0; -} +static struct msm_clk_data apq8016_clk_data = { + .set_rate = apq8016_clk_set_rate, +};
static const struct udevice_id gcc_apq8016_of_match[] = { { .compatible = "qcom,gcc-apq8016", - /* TODO: add reset map */ + .data = (ulong)&apq8016_clk_data, }, { } }; diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index 64b8cdf4c54b..75633a7c2af8 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -16,6 +16,28 @@
#include "clock-qcom.h"
+/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x0000) +#define APCS_GPLL_ENA_VOTE (0x52000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) + +#define SDCC2_BCR (0x14000) /* block reset */ +#define SDCC2_APPS_CBCR (0x14004) /* branch control */ +#define SDCC2_AHB_CBCR (0x14008) +#define SDCC2_CMD_RCGR (0x14010) +#define SDCC2_CFG_RCGR (0x14014) +#define SDCC2_M (0x14018) +#define SDCC2_N (0x1401C) +#define SDCC2_D (0x14020) + +#define BLSP2_AHB_CBCR (0x25004) +#define BLSP2_UART2_APPS_CBCR (0x29004) +#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) +#define BLSP2_UART2_APPS_CFG_RCGR (0x29010) +#define BLSP2_UART2_APPS_M (0x29014) +#define BLSP2_UART2_APPS_N (0x29018) +#define BLSP2_UART2_APPS_D (0x2901C) + /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(30) #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) @@ -80,7 +102,7 @@ static int clk_init_uart(struct msm_clk_priv *priv) return 0; }
-ulong msm_set_rate(struct clk *clk, ulong rate) +static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -95,15 +117,14 @@ ulong msm_set_rate(struct clk *clk, ulong rate) } }
-int msm_enable(struct clk *clk) -{ - return 0; -} +static struct msm_clk_data apq8096_clk_data = { + .set_rate = apq8096_clk_set_rate, +};
static const struct udevice_id gcc_apq8096_of_match[] = { { .compatible = "qcom,gcc-apq8096", - /* TODO: add reset map */ + .data = (ulong)&apq8096_clk_data, }, { } }; diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index db869f874219..d693776d339d 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -16,7 +16,7 @@
#include "clock-qcom.h"
-ulong msm_set_rate(struct clk *clk, ulong rate) +static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate) { switch (clk->id) { case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ @@ -27,7 +27,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate) } }
-int msm_enable(struct clk *clk) +static int ipq4019_clk_enable(struct clk *clk) { switch (clk->id) { case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/ @@ -123,7 +123,9 @@ static const struct qcom_reset_map gcc_ipq4019_resets[] = { [GCC_SPDM_BCR] = {0x25000, 0}, };
-static struct msm_clk_data ipq4019_data = { +static struct msm_clk_data ipq4019_clk_data = { + .enable = ipq4019_clk_enable, + .set_rate = ipq4019_clk_set_rate, .resets = gcc_ipq4019_resets, .num_resets = ARRAY_SIZE(gcc_ipq4019_resets), }; @@ -131,7 +133,7 @@ static struct msm_clk_data ipq4019_data = { static const struct udevice_id gcc_ipq4019_of_match[] = { { .compatible = "qcom,gcc-ipq4019", - .data = (ulong)&ipq4019_data, + .data = (ulong)&ipq4019_clk_data, }, { } }; diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index a661837e4e11..77bcaacd1583 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -28,9 +28,6 @@ #define CBCR_BRANCH_ENABLE_BIT BIT(0) #define CBCR_BRANCH_OFF_BIT BIT(31)
-extern ulong msm_set_rate(struct clk *clk, ulong rate); -extern int msm_enable(struct clk *clk); - /* Enable clock controlled by CBC soft macro */ void clk_enable_cbc(phys_addr_t cbcr) { @@ -160,12 +157,22 @@ static int msm_clk_probe(struct udevice *dev)
static ulong msm_clk_set_rate(struct clk *clk, ulong rate) { - return msm_set_rate(clk, rate); + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev); + + if (data->set_rate) + return data->set_rate(clk, rate); + + return 0; }
static int msm_clk_enable(struct clk *clk) { - return msm_enable(clk); + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev); + + if (data->enable) + return data->enable(clk); + + return 0; }
static struct clk_ops msm_clk_ops = { diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 6d399db987b6..86f9ff6eb2f6 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -49,11 +49,16 @@ struct qcom_reset_map { u8 bit; };
+struct clk; + struct msm_clk_data { const struct qcom_reset_map *resets; unsigned long num_resets; const struct gate_clk *clks; unsigned long num_clks; + + int (*enable)(struct clk *clk); + unsigned long (*set_rate)(struct clk *clk, unsigned long rate); };
struct msm_clk_priv { diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 10ac3609be42..9ad580b50fc8 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -15,6 +15,81 @@
#include "clock-qcom.h"
+/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x21000) +#define GPLL1_STATUS (0x20000) +#define APCS_GPLL_ENA_VOTE (0x45000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) + +/* BLSP1 AHB clock (root clock for BLSP) */ +#define BLSP1_AHB_CBCR 0x1008 + +/* Uart clock control registers */ +#define BLSP1_UART2_BCR (0x3028) +#define BLSP1_UART2_APPS_CBCR (0x302C) +#define BLSP1_UART2_APPS_CMD_RCGR (0x3034) +#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) +#define BLSP1_UART2_APPS_M (0x303C) +#define BLSP1_UART2_APPS_N (0x3040) +#define BLSP1_UART2_APPS_D (0x3044) + +/* I2C controller clock control registerss */ +#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028) +#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C) +#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030) +#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008) +#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C) +#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010) +#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010) +#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000) +#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004) +#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020) +#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000) +#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004) +#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020) +#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000) +#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004) + +/* SD controller clock control registers */ +#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000) +#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004) +#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008) +#define SDCC_M(n) (((n) * 0x1000) + 0x4100C) +#define SDCC_N(n) (((n) * 0x1000) + 0x41010) +#define SDCC_D(n) (((n) * 0x1000) + 0x41014) +#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018) +#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C) + +/* USB-3.0 controller clock control registers */ +#define SYS_NOC_USB3_CBCR (0x26014) +#define USB30_BCR (0x39000) +#define USB3PHY_BCR (0x39008) +#define USB30_MASTER_CBCR (0x3900C) +#define USB30_SLEEP_CBCR (0x39010) +#define USB30_MOCK_UTMI_CBCR (0x39014) +#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C) +#define USB30_MOCK_UTMI_CFG_RCGR (0x39020) +#define USB30_MASTER_CMD_RCGR (0x39028) +#define USB30_MASTER_CFG_RCGR (0x3902C) +#define USB30_MASTER_M (0x39030) +#define USB30_MASTER_N (0x39034) +#define USB30_MASTER_D (0x39038) +#define USB2A_PHY_SLEEP_CBCR (0x4102C) +#define USB_HS_PHY_CFG_AHB_CBCR (0x41030) + +/* ETH controller clock control registers */ +#define ETH_PTP_CBCR (0x4e004) +#define ETH_RGMII_CBCR (0x4e008) +#define ETH_SLAVE_AHB_CBCR (0x4e00c) +#define ETH_AXI_CBCR (0x4e010) +#define EMAC_PTP_CMD_RCGR (0x4e014) +#define EMAC_PTP_CFG_RCGR (0x4e018) +#define EMAC_CMD_RCGR (0x4e01c) +#define EMAC_CFG_RCGR (0x4e020) +#define EMAC_M (0x4e024) +#define EMAC_N (0x4e028) +#define EMAC_D (0x4e02c) +
/* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(31) @@ -112,7 +187,7 @@ static const struct bcr_regs blsp1_qup4_i2c_apps_regs = { /* mnd_width = 0 */ };
-ulong msm_set_rate(struct clk *clk, ulong rate) +static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -157,7 +232,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; }
-int msm_enable(struct clk *clk) +static int qcs404_clk_enable(struct clk *clk) { struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -263,15 +338,17 @@ static const struct qcom_reset_map qcs404_gcc_resets[] = { [GCC_WDSP_RESTART] = {0x19000}, };
-static const struct msm_clk_data qcs404_gcc_data = { +static const struct msm_clk_data qcs404_clk_gcc_data = { .resets = qcs404_gcc_resets, .num_resets = ARRAY_SIZE(qcs404_gcc_resets), + .enable = qcs404_clk_enable, + .set_rate = qcs404_clk_set_rate, };
static const struct udevice_id gcc_qcs404_of_match[] = { { .compatible = "qcom,gcc-qcs404", - .data = (ulong)&qcs404_gcc_data + .data = (ulong)&qcs404_clk_gcc_data }, { } }; diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index 57124e2a661a..fc9a783f7354 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -19,6 +19,14 @@
#include "clock-qcom.h"
+#define SE9_AHB_CBCR 0x25004 +#define SE9_UART_APPS_CBCR 0x29004 +#define SE9_UART_APPS_CMD_RCGR 0x18148 +#define SE9_UART_APPS_CFG_RCGR 0x1814C +#define SE9_UART_APPS_M 0x18150 +#define SE9_UART_APPS_N 0x18154 +#define SE9_UART_APPS_D 0x18158 + #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
struct freq_tbl { @@ -72,7 +80,7 @@ const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) return f - 1; }
-ulong msm_set_rate(struct clk *clk, ulong rate) +static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); const struct freq_tbl *freq; @@ -148,7 +156,7 @@ static const struct gate_clk sdm845_clks[] = { GATE_CLK(GCC_USB_PHY_CFG_AHB2PHY_CLK, 0x6a004, 0x00000001), };
-int msm_enable(struct clk *clk) +static int sdm845_clk_enable(struct clk *clk) { struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -179,17 +187,20 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, };
-static const struct msm_clk_data qcs404_gcc_data = { +static struct msm_clk_data sdm845_clk_data = { .resets = sdm845_gcc_resets, .num_resets = ARRAY_SIZE(sdm845_gcc_resets), .clks = sdm845_clks, .num_clks = ARRAY_SIZE(sdm845_clks), + + .enable = sdm845_clk_enable, + .set_rate = sdm845_clk_set_rate, };
static const struct udevice_id gcc_sdm845_of_match[] = { { .compatible = "qcom,gcc-sdm845", - .data = (ulong)&qcs404_gcc_data, + .data = (ulong)&sdm845_clk_data, }, { } }; diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 73aec348458a..00102cd5c4f5 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -9,7 +9,6 @@ #define __CONFIGS_DRAGONBOARD410C_H
#include <linux/sizes.h> -#include <asm/arch/sysmap-apq8016.h>
/* Build new ELF image from u-boot.bin (U-Boot + appended DTB) */
diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 499708371113..c6d9182ccc9d 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -9,7 +9,6 @@ #define __CONFIGS_DRAGONBOARD820C_H
#include <linux/sizes.h> -#include <asm/arch/sysmap-apq8096.h>
/* Physical Memory Map */
diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h index c1e590fae2a5..14a8a2ca049e 100644 --- a/include/configs/dragonboard845c.h +++ b/include/configs/dragonboard845c.h @@ -9,7 +9,6 @@ #define __CONFIGS_SDM845_H
#include <linux/sizes.h> -#include <asm/arch/sysmap-sdm845.h>
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h index 8ea59aa21ca6..9501d43665e9 100644 --- a/include/configs/qcs404-evb.h +++ b/include/configs/qcs404-evb.h @@ -9,7 +9,6 @@ #define __CONFIGS_QCS404EVB_H
#include <linux/sizes.h> -#include <asm/arch/sysmap-qcs404.h>
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org Reviewed-by: Sumit Garg sumit.garg@linaro.org --- drivers/clk/qcom/clock-apq8016.c | 4 ++-- drivers/clk/qcom/clock-apq8096.c | 4 ++-- drivers/clk/qcom/clock-qcom.c | 11 +++++++---- drivers/clk/qcom/clock-qcom.h | 2 +- drivers/clk/qcom/clock-qcs404.c | 18 +++++++++--------- drivers/clk/qcom/clock-sdm845.c | 3 +-- 6 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 3f44252c453e..630619c83454 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -86,7 +86,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot)); /* 800Mhz/div, gpll0 */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0, - CFG_CLK_SRC_GPLL0); + CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
@@ -109,7 +109,7 @@ static int clk_init_uart(struct msm_clk_priv *priv)
/* 7372800 uart block clock @ GPLL0 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625, - CFG_CLK_SRC_GPLL0); + CFG_CLK_SRC_GPLL0, 8);
/* Vote for gpll0 clock */ clk_enable_gpll0(priv->base, &gpll0_vote_clk); diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index 75633a7c2af8..095c1b431245 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -69,7 +69,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, - CFG_CLK_SRC_GPLL0); + CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
@@ -91,7 +91,7 @@ static int clk_init_uart(struct msm_clk_priv *priv)
/* 7372800 uart block clock @ GPLL0 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625, - CFG_CLK_SRC_GPLL0); + CFG_CLK_SRC_GPLL0, 8);
/* Vote for gpll0 clock */ clk_enable_gpll0(priv->base, &gpll0_vote_clk); diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 77bcaacd1583..fc478554f982 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -83,7 +83,7 @@ void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
/* root set rate for clocks with half integer and MND divider */ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, - int div, int m, int n, int source) + int div, int m, int n, int source, u8 mnd_width) { u32 cfg; /* M value for MND divider. */ @@ -92,11 +92,14 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, u32 n_val = ~((n) - (m)) * !!(n); /* NOT 2D value for MND divider. */ u32 d_val = ~(n); + u32 mask = BIT(mnd_width) - 1; + + debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask);
/* Program MND values */ - writel(m_val, base + regs->M); - writel(n_val, base + regs->N); - writel(d_val, base + regs->D); + writel(m_val & mask, base + regs->M); + writel(n_val & mask, base + regs->N); + writel(d_val & mask, base + regs->D);
/* setup src select and divider */ cfg = readl(base + regs->cfg_rcgr); diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 86f9ff6eb2f6..24a32cb9666d 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -72,7 +72,7 @@ void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, - int div, int m, int n, int source); + int div, int m, int n, int source, u8 mnd_width); void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, int source);
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 9ad580b50fc8..921abf1f699b 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -195,7 +195,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_BLSP1_UART2_APPS_CLK: /* UART: 115200 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125, - CFG_CLK_SRC_CXO); + CFG_CLK_SRC_CXO, 8); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); break; case GCC_BLSP1_AHB_CLK: @@ -204,7 +204,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0, - CFG_CLK_SRC_GPLL0); + CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); break; @@ -214,16 +214,16 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_ETH_RGMII_CLK: if (rate == 250000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0, - CFG_CLK_SRC_GPLL1); + CFG_CLK_SRC_GPLL1, 8); else if (rate == 125000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0, - CFG_CLK_SRC_GPLL1); + CFG_CLK_SRC_GPLL1, 8); else if (rate == 50000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0, - CFG_CLK_SRC_GPLL1); + CFG_CLK_SRC_GPLL1, 8); else if (rate == 5000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50, - CFG_CLK_SRC_GPLL1); + CFG_CLK_SRC_GPLL1, 8); break; default: return 0; @@ -240,7 +240,7 @@ static int qcs404_clk_enable(struct clk *clk) case GCC_USB30_MASTER_CLK: clk_enable_cbc(priv->base + USB30_MASTER_CBCR); clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0, - CFG_CLK_SRC_GPLL0); + CFG_CLK_SRC_GPLL0, 8); break; case GCC_SYS_NOC_USB3_CLK: clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR); @@ -262,14 +262,14 @@ static int qcs404_clk_enable(struct clk *clk) clk_enable_cbc(priv->base + ETH_PTP_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0, - CFG_CLK_SRC_GPLL1); + CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_RGMII_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_RGMII_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0, - CFG_CLK_SRC_GPLL1); + CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_SLAVE_AHB_CLK: clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR); diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index fc9a783f7354..6af1f38302d2 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -89,8 +89,7 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); clk_rcg_set_rate_mnd(priv->base, &uart2_regs, - freq->pre_div, freq->m, freq->n, freq->src); - + freq->pre_div, freq->m, freq->n, freq->src, 16); return freq->freq; default: return 0;
On Fri, 3 Nov 2023 at 21:09, Caleb Connolly caleb.connolly@linaro.org wrote:
This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers.
This commit broke qcs404 platform which is fixed by following add-on change:
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 429ff35e1d..f5b3528039 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -195,7 +195,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_BLSP1_UART2_APPS_CLK: /* UART: 115200 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125, - CFG_CLK_SRC_CXO, 8); + CFG_CLK_SRC_CXO, 16); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); break; case GCC_BLSP1_AHB_CLK:
This is needed as per Linux qcs404 clock driver too. I would suggest you double check if you have imported correct values from corresponding Linux clock drivers for other platforms too.
BTW, after this fix feel free to add:
Tested-by: Sumit Garg sumit.garg@linaro.org (QCS404)
-Sumit
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org Reviewed-by: Sumit Garg sumit.garg@linaro.org
drivers/clk/qcom/clock-apq8016.c | 4 ++-- drivers/clk/qcom/clock-apq8096.c | 4 ++-- drivers/clk/qcom/clock-qcom.c | 11 +++++++---- drivers/clk/qcom/clock-qcom.h | 2 +- drivers/clk/qcom/clock-qcs404.c | 18 +++++++++--------- drivers/clk/qcom/clock-sdm845.c | 3 +-- 6 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 3f44252c453e..630619c83454 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -86,7 +86,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot)); /* 800Mhz/div, gpll0 */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));@@ -109,7 +109,7 @@ static int clk_init_uart(struct msm_clk_priv *priv)
/* 7372800 uart block clock @ GPLL0 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); /* Vote for gpll0 clock */ clk_enable_gpll0(priv->base, &gpll0_vote_clk);diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index 75633a7c2af8..095c1b431245 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -69,7 +69,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);@@ -91,7 +91,7 @@ static int clk_init_uart(struct msm_clk_priv *priv)
/* 7372800 uart block clock @ GPLL0 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); /* Vote for gpll0 clock */ clk_enable_gpll0(priv->base, &gpll0_vote_clk);diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 77bcaacd1583..fc478554f982 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -83,7 +83,7 @@ void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
/* root set rate for clocks with half integer and MND divider */ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
int div, int m, int n, int source)
int div, int m, int n, int source, u8 mnd_width){ u32 cfg; /* M value for MND divider. */ @@ -92,11 +92,14 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, u32 n_val = ~((n) - (m)) * !!(n); /* NOT 2D value for MND divider. */ u32 d_val = ~(n);
u32 mask = BIT(mnd_width) - 1;debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask); /* Program MND values */
writel(m_val, base + regs->M);writel(n_val, base + regs->N);writel(d_val, base + regs->D);
writel(m_val & mask, base + regs->M);writel(n_val & mask, base + regs->N);writel(d_val & mask, base + regs->D); /* setup src select and divider */ cfg = readl(base + regs->cfg_rcgr);diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 86f9ff6eb2f6..24a32cb9666d 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -72,7 +72,7 @@ void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
int div, int m, int n, int source);
int div, int m, int n, int source, u8 mnd_width);void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, int source);
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 9ad580b50fc8..921abf1f699b 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -195,7 +195,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_BLSP1_UART2_APPS_CLK: /* UART: 115200 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
CFG_CLK_SRC_CXO);
CFG_CLK_SRC_CXO, 8); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); break; case GCC_BLSP1_AHB_CLK:@@ -204,7 +204,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); break;@@ -214,16 +214,16 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_ETH_RGMII_CLK: if (rate == 250000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); else if (rate == 125000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); else if (rate == 50000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); else if (rate == 5000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); break; default: return 0;@@ -240,7 +240,7 @@ static int qcs404_clk_enable(struct clk *clk) case GCC_USB30_MASTER_CLK: clk_enable_cbc(priv->base + USB30_MASTER_CBCR); clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); break; case GCC_SYS_NOC_USB3_CLK: clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);@@ -262,14 +262,14 @@ static int qcs404_clk_enable(struct clk *clk) clk_enable_cbc(priv->base + ETH_PTP_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_RGMII_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_RGMII_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_SLAVE_AHB_CLK: clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR);diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index fc9a783f7354..6af1f38302d2 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -89,8 +89,7 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
freq->pre_div, freq->m, freq->n, freq->src);
freq->pre_div, freq->m, freq->n, freq->src, 16); return freq->freq; default: return 0;-- 2.42.0
On 06/11/2023 07:06, Sumit Garg wrote:
On Fri, 3 Nov 2023 at 21:09, Caleb Connolly caleb.connolly@linaro.org wrote:
This property is needed on some platforms to ensure that only the relevant bits are set in the M/N/D registers.
This commit broke qcs404 platform which is fixed by following add-on change:
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 429ff35e1d..f5b3528039 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -195,7 +195,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_BLSP1_UART2_APPS_CLK: /* UART: 115200 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
CFG_CLK_SRC_CXO, 8);
CFG_CLK_SRC_CXO, 16); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); break; case GCC_BLSP1_AHB_CLK:This is needed as per Linux qcs404 clock driver too. I would suggest you double check if you have imported correct values from corresponding Linux clock drivers for other platforms too.
Ah, you're right - I think all platforms use 16 bits for the UART RCG, Thanks a lot for testing this.
BTW, after this fix feel free to add:
Tested-by: Sumit Garg sumit.garg@linaro.org (QCS404)
-Sumit
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org Reviewed-by: Sumit Garg sumit.garg@linaro.org
drivers/clk/qcom/clock-apq8016.c | 4 ++-- drivers/clk/qcom/clock-apq8096.c | 4 ++-- drivers/clk/qcom/clock-qcom.c | 11 +++++++---- drivers/clk/qcom/clock-qcom.h | 2 +- drivers/clk/qcom/clock-qcs404.c | 18 +++++++++--------- drivers/clk/qcom/clock-sdm845.c | 3 +-- 6 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 3f44252c453e..630619c83454 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -86,7 +86,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot)); /* 800Mhz/div, gpll0 */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));@@ -109,7 +109,7 @@ static int clk_init_uart(struct msm_clk_priv *priv)
/* 7372800 uart block clock @ GPLL0 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); /* Vote for gpll0 clock */ clk_enable_gpll0(priv->base, &gpll0_vote_clk);diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index 75633a7c2af8..095c1b431245 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -69,7 +69,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);@@ -91,7 +91,7 @@ static int clk_init_uart(struct msm_clk_priv *priv)
/* 7372800 uart block clock @ GPLL0 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); /* Vote for gpll0 clock */ clk_enable_gpll0(priv->base, &gpll0_vote_clk);diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 77bcaacd1583..fc478554f982 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -83,7 +83,7 @@ void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
/* root set rate for clocks with half integer and MND divider */ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
int div, int m, int n, int source)
int div, int m, int n, int source, u8 mnd_width){ u32 cfg; /* M value for MND divider. */ @@ -92,11 +92,14 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, u32 n_val = ~((n) - (m)) * !!(n); /* NOT 2D value for MND divider. */ u32 d_val = ~(n);
u32 mask = BIT(mnd_width) - 1;debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask); /* Program MND values */
writel(m_val, base + regs->M);writel(n_val, base + regs->N);writel(d_val, base + regs->D);
writel(m_val & mask, base + regs->M);writel(n_val & mask, base + regs->N);writel(d_val & mask, base + regs->D); /* setup src select and divider */ cfg = readl(base + regs->cfg_rcgr);diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 86f9ff6eb2f6..24a32cb9666d 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -72,7 +72,7 @@ void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
int div, int m, int n, int source);
int div, int m, int n, int source, u8 mnd_width);void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, int source);
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 9ad580b50fc8..921abf1f699b 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -195,7 +195,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_BLSP1_UART2_APPS_CLK: /* UART: 115200 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
CFG_CLK_SRC_CXO);
CFG_CLK_SRC_CXO, 8); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); break; case GCC_BLSP1_AHB_CLK:@@ -204,7 +204,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); break;@@ -214,16 +214,16 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) case GCC_ETH_RGMII_CLK: if (rate == 250000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); else if (rate == 125000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); else if (rate == 50000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); else if (rate == 5000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); break; default: return 0;@@ -240,7 +240,7 @@ static int qcs404_clk_enable(struct clk *clk) case GCC_USB30_MASTER_CLK: clk_enable_cbc(priv->base + USB30_MASTER_CBCR); clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
CFG_CLK_SRC_GPLL0);
CFG_CLK_SRC_GPLL0, 8); break; case GCC_SYS_NOC_USB3_CLK: clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);@@ -262,14 +262,14 @@ static int qcs404_clk_enable(struct clk *clk) clk_enable_cbc(priv->base + ETH_PTP_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_RGMII_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_RGMII_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
CFG_CLK_SRC_GPLL1);
CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_SLAVE_AHB_CLK: clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR);diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index fc9a783f7354..6af1f38302d2 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -89,8 +89,7 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
freq->pre_div, freq->m, freq->n, freq->src);
freq->pre_div, freq->m, freq->n, freq->src, 16); return freq->freq; default: return 0;-- 2.42.0
The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro.
However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors.
Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- drivers/clk/qcom/clock-apq8016.c | 2 +- drivers/clk/qcom/clock-apq8096.c | 2 +- drivers/clk/qcom/clock-qcom.c | 64 +++++++++++++++++++++++++++++----------- drivers/clk/qcom/clock-qcom.h | 11 +++++++ drivers/clk/qcom/clock-qcs404.c | 16 +++++----- drivers/clk/qcom/clock-sdm845.c | 26 ---------------- 6 files changed, 67 insertions(+), 54 deletions(-)
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 630619c83454..eb812934cbae 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -78,7 +78,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = { /* SDHCI */ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) { - int div = 8; /* 100MHz default */ + int div = 15; /* 100MHz default */
if (rate == 200000000) div = 4; diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index 095c1b431245..55f16c14e046 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -65,7 +65,7 @@ static struct vote_clk gcc_blsp2_ahb_clk = {
static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) { - int div = 3; + int div = 5;
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index fc478554f982..7c683e519226 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -19,6 +19,8 @@ #include <dm/lists.h> #include <errno.h> #include <asm/io.h> +#include <linux/bug.h> +#include <linux/delay.h> #include <linux/bitops.h> #include <reset-uclass.h>
@@ -68,30 +70,42 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) /* Update clock command via CMD_RCGR */ void clk_bcr_update(phys_addr_t apps_cmd_rcgr) { + u32 count; setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE);
/* Wait for frequency to be updated. */ - while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE) - ; + for (count = 0; count < 50000; count++) { + if (!(readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE)) + break; + udelay(1); + } + WARN(count == 50000, "WARNING: RCG @ %#llx [%#010x] stuck at off\n", + apps_cmd_rcgr, readl(apps_cmd_rcgr)); }
-#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */ +#define CFG_SRC_DIV_MASK 0b11111 +#define CFG_SRC_SEL_SHIFT 8 +#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT) +#define CFG_MODE_SHIFT 12 +#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) +#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) +#define CFG_HW_CLK_CTRL_MASK BIT(20)
-#define CFG_MASK 0x3FFF - -#define CFG_DIVIDER_MASK 0x1F - -/* root set rate for clocks with half integer and MND divider */ +/* + * root set rate for clocks with half integer and MND divider + * div should be pre-calculated ((div * 2) - 1) + */ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, int div, int m, int n, int source, u8 mnd_width) { u32 cfg; /* M value for MND divider. */ u32 m_val = m; + u32 n_minus_m = n - m; /* NOT(N-M) value for MND divider. */ - u32 n_val = ~((n) - (m)) * !!(n); + u32 n_val = ~n_minus_m * !!(n); /* NOT 2D value for MND divider. */ - u32 d_val = ~(n); + u32 d_val = ~(clamp_t(u32, n, m, n_minus_m)); u32 mask = BIT(mnd_width) - 1;
debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask); @@ -103,15 +117,13 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
/* setup src select and divider */ cfg = readl(base + regs->cfg_rcgr); - cfg &= ~CFG_MASK; - cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ + cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); + cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */
- /* Set the divider; HW permits fraction dividers (+0.5), but - for simplicity, we will support integers only */ if (div) - cfg |= (2 * div - 1) & CFG_DIVIDER_MASK; + cfg |= div & CFG_SRC_DIV_MASK;
- if (n_val) + if (n && n != m) cfg |= CFG_MODE_DUAL_EDGE;
writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ @@ -128,7 +140,7 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
/* setup src select and divider */ cfg = readl(base + regs->cfg_rcgr); - cfg &= ~CFG_MASK; + cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
/* @@ -136,7 +148,7 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, * for simplicity, we will support integers only */ if (div) - cfg |= (2 * div - 1) & CFG_DIVIDER_MASK; + cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK;
writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
@@ -144,6 +156,22 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, clk_bcr_update(base + regs->cmd_rcgr); }
+const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) +{ + if (!f) + return NULL; + + if (!f->freq) + return f; + + for (; f->freq; f++) + if (rate <= f->freq) + return f; + + /* Default to our fastest rate */ + return f - 1; +} + static int msm_clk_probe(struct udevice *dev) { struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 24a32cb9666d..01088c19015a 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -32,6 +32,16 @@ struct bcr_regs { uintptr_t D; };
+struct freq_tbl { + uint freq; + uint src; + u8 pre_div; + u16 m; + u16 n; +}; + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + struct gate_clk { uintptr_t reg; u32 en_val; @@ -71,6 +81,7 @@ void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); +const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, int div, int m, int n, int source, u8 mnd_width); void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 921abf1f699b..429ff35e1d1a 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -203,7 +203,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) break; case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */ - clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0, + clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); @@ -213,16 +213,16 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) break; case GCC_ETH_RGMII_CLK: if (rate == 250000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0, + clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 125000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0, + clk_rcg_set_rate_mnd(priv->base, &emac_regs, 7, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 50000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0, + clk_rcg_set_rate_mnd(priv->base, &emac_regs, 19, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 5000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50, + clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); break; default: @@ -239,7 +239,7 @@ static int qcs404_clk_enable(struct clk *clk) switch (clk->id) { case GCC_USB30_MASTER_CLK: clk_enable_cbc(priv->base + USB30_MASTER_CBCR); - clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0, + clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); break; case GCC_SYS_NOC_USB3_CLK: @@ -261,14 +261,14 @@ static int qcs404_clk_enable(struct clk *clk) /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_PTP_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); - clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0, + clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_RGMII_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_RGMII_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0, + clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_SLAVE_AHB_CLK: diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index 6af1f38302d2..36ffee79d966 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -27,16 +27,6 @@ #define SE9_UART_APPS_N 0x18154 #define SE9_UART_APPS_D 0x18158
-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - -struct freq_tbl { - uint freq; - uint src; - u8 pre_div; - u16 m; - u16 n; -}; - static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), @@ -64,22 +54,6 @@ static const struct bcr_regs uart2_regs = { .D = SE9_UART_APPS_D, };
-const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) -{ - if (!f) - return NULL; - - if (!f->freq) - return f; - - for (; f->freq; f++) - if (rate <= f->freq) - return f; - - /* Default to our fastest rate */ - return f - 1; -} - static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev);
On Fri, 3 Nov 2023 at 21:11, Caleb Connolly caleb.connolly@linaro.org wrote:
The RCG divider field takes a value of (2*h - 1) where h is the divisor. This allows fractional dividers to be supported by calculating them at compile time using a macro.
However, the clk_rcg_set_rate_mnd() function was also performing the calculation. Clean this all up and consistently use the F() macro to calculate these at compile time and properly support fractional divisors.
Additionally, improve clk_bcr_update() to timeout with a warning rather than hanging the board, and make the freq_tbl struct and helpers common so that they can be reused by future platforms.
Signed-off-by: Caleb Connolly caleb.connolly@linaro.org
drivers/clk/qcom/clock-apq8016.c | 2 +- drivers/clk/qcom/clock-apq8096.c | 2 +- drivers/clk/qcom/clock-qcom.c | 64 +++++++++++++++++++++++++++++----------- drivers/clk/qcom/clock-qcom.h | 11 +++++++ drivers/clk/qcom/clock-qcs404.c | 16 +++++----- drivers/clk/qcom/clock-sdm845.c | 26 ---------------- 6 files changed, 67 insertions(+), 54 deletions(-)
Reviewed-by: Sumit Garg sumit.garg@linaro.org
-Sumit
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 630619c83454..eb812934cbae 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -78,7 +78,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = { /* SDHCI */ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) {
int div = 8; /* 100MHz default */
int div = 15; /* 100MHz default */ if (rate == 200000000) div = 4;diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index 095c1b431245..55f16c14e046 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -65,7 +65,7 @@ static struct vote_clk gcc_blsp2_ahb_clk = {
static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) {
int div = 3;
int div = 5; clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index fc478554f982..7c683e519226 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -19,6 +19,8 @@ #include <dm/lists.h> #include <errno.h> #include <asm/io.h> +#include <linux/bug.h> +#include <linux/delay.h> #include <linux/bitops.h> #include <reset-uclass.h>
@@ -68,30 +70,42 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) /* Update clock command via CMD_RCGR */ void clk_bcr_update(phys_addr_t apps_cmd_rcgr) {
u32 count; setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE); /* Wait for frequency to be updated. */
while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE);
for (count = 0; count < 50000; count++) {if (!(readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE))break;udelay(1);}WARN(count == 50000, "WARNING: RCG @ %#llx [%#010x] stuck at off\n",apps_cmd_rcgr, readl(apps_cmd_rcgr));}
-#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */ +#define CFG_SRC_DIV_MASK 0b11111 +#define CFG_SRC_SEL_SHIFT 8 +#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT) +#define CFG_MODE_SHIFT 12 +#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) +#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) +#define CFG_HW_CLK_CTRL_MASK BIT(20)
-#define CFG_MASK 0x3FFF
-#define CFG_DIVIDER_MASK 0x1F
-/* root set rate for clocks with half integer and MND divider */ +/*
- root set rate for clocks with half integer and MND divider
- div should be pre-calculated ((div * 2) - 1)
- */
void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, int div, int m, int n, int source, u8 mnd_width) { u32 cfg; /* M value for MND divider. */ u32 m_val = m;
u32 n_minus_m = n - m; /* NOT(N-M) value for MND divider. */
u32 n_val = ~((n) - (m)) * !!(n);
u32 n_val = ~n_minus_m * !!(n); /* NOT 2D value for MND divider. */
u32 d_val = ~(n);
u32 d_val = ~(clamp_t(u32, n, m, n_minus_m)); u32 mask = BIT(mnd_width) - 1; debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask);@@ -103,15 +117,13 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
/* setup src select and divider */ cfg = readl(base + regs->cfg_rcgr);
cfg &= ~CFG_MASK;cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK);cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */
/* Set the divider; HW permits fraction dividers (+0.5), butfor simplicity, we will support integers only */ if (div)cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
cfg |= div & CFG_SRC_DIV_MASK;
if (n_val)
if (n && n != m) cfg |= CFG_MODE_DUAL_EDGE; writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */@@ -128,7 +140,7 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
/* setup src select and divider */ cfg = readl(base + regs->cfg_rcgr);
cfg &= ~CFG_MASK;
cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ /*@@ -136,7 +148,7 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, * for simplicity, we will support integers only */ if (div)
cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK; writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */@@ -144,6 +156,22 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, clk_bcr_update(base + regs->cmd_rcgr); }
+const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) +{
if (!f)return NULL;if (!f->freq)return f;for (; f->freq; f++)if (rate <= f->freq)return f;/* Default to our fastest rate */return f - 1;+}
static int msm_clk_probe(struct udevice *dev) { struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 24a32cb9666d..01088c19015a 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -32,6 +32,16 @@ struct bcr_regs { uintptr_t D; };
+struct freq_tbl {
uint freq;uint src;u8 pre_div;u16 m;u16 n;+};
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
struct gate_clk { uintptr_t reg; u32 en_val; @@ -71,6 +81,7 @@ void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); +const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, int div, int m, int n, int source, u8 mnd_width); void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 921abf1f699b..429ff35e1d1a 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -203,7 +203,7 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) break; case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));@@ -213,16 +213,16 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) break; case GCC_ETH_RGMII_CLK: if (rate == 250000000)
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 125000000)
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0,
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 7, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 50000000)
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0,
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 19, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 5000000)
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50,
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); break; default:@@ -239,7 +239,7 @@ static int qcs404_clk_enable(struct clk *clk) switch (clk->id) { case GCC_USB30_MASTER_CLK: clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); break; case GCC_SYS_NOC_USB3_CLK:@@ -261,14 +261,14 @@ static int qcs404_clk_enable(struct clk *clk) /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_PTP_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk);
clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0,
clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_RGMII_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_RGMII_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk);
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_SLAVE_AHB_CLK:diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index 6af1f38302d2..36ffee79d966 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -27,16 +27,6 @@ #define SE9_UART_APPS_N 0x18154 #define SE9_UART_APPS_D 0x18158
-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-struct freq_tbl {
uint freq;uint src;u8 pre_div;u16 m;u16 n;-};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), @@ -64,22 +54,6 @@ static const struct bcr_regs uart2_regs = { .D = SE9_UART_APPS_D, };
-const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) -{
if (!f)return NULL;if (!f->freq)return f;for (; f->freq; f++)if (rate <= f->freq)return f;/* Default to our fastest rate */return f - 1;-}
static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev);
-- 2.42.0
participants (2)
-
Caleb Connolly -
Sumit Garg