[PATCH v2 0/2] board: phytec_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1

PCL-070 supports 2GHz RAM-timings from pcb_rev 1 and newer. PCM-070 supports 2GHz RAM-timings only from pcb_rev 3 and newer.
Signed-off-by: Benjamin Hahn B.Hahn@phytec.de --- Changes in v2: - Fix mistakes that prevented building - Link to v1: https://lore.kernel.org/r/20240304-pcl-070-patches-v1-0-6aa6c89e3b81@phytec....
--- Benjamin Hahn (2): board: phytec: common: phytec_som_detection: Add phytec_get_som_type board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1
board/phytec/common/phytec_som_detection.c | 10 ++++++++++ board/phytec/common/phytec_som_detection.h | 8 ++++++++ board/phytec/phycore_imx8mp/spl.c | 6 ++++-- 3 files changed, 22 insertions(+), 2 deletions(-) --- base-commit: eac52e4be4e234d563d6911737ee7ccdc0ada1f1 change-id: 20240304-pcl-070-patches-d31b989cf5b3
Best regards,

Add a function that gets the som_type from the EEPROM. Add an enum for the som_type.
Signed-off-by: Benjamin Hahn B.Hahn@phytec.de --- board/phytec/common/phytec_som_detection.c | 10 ++++++++++ board/phytec/common/phytec_som_detection.h | 8 ++++++++ 2 files changed, 18 insertions(+)
diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index c73bf9721b2f..f9607b018dea 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -203,6 +203,16 @@ u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) return api2->pcb_rev; }
+u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data) +{ + if (!data) + data = &eeprom_data; + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + return data->data.data_api2.som_type; +} + #else
inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index 11009240875c..c0f0c57a6123 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -19,6 +19,13 @@ enum { PHYTEC_API_REV2, };
+enum phytec_som_type_str { + PCM = 0, + PCL, + KSM, + KSP, +}; + static const char * const phytec_som_type_str[] = { "PCM", "PCL", @@ -67,5 +74,6 @@ void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data);
char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data);
#endif /* _PHYTEC_SOM_DETECTION_H */

On Mon, Mar 4, 2024 at 1:04 PM Benjamin Hahn B.Hahn@phytec.de wrote:
+enum phytec_som_type_str {
PCM = 0,
PCL,
KSM,
KSP,
+};
To avoid potential name clashes in the future, I suggest adding a prefix like:
SOM_TYPE_PCM = 0, SOM_TYPE_PCL, ...
static const char * const phytec_som_type_str[] = { "PCM", "PCL", @@ -67,5 +74,6 @@ void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data);
char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data);
#endif /* _PHYTEC_SOM_DETECTION_H */
-- 2.34.1

We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from pcb rev 3 or newer.
Signed-off-by: Benjamin Hahn B.Hahn@phytec.de --- board/phytec/phycore_imx8mp/spl.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index d38f6368fe36..15a8c75e9982 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -46,8 +46,10 @@ void spl_dram_init(void) if (!ret) phytec_print_som_info(NULL);
- ret = phytec_get_rev(NULL); - if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) { + u8 rev = phytec_get_rev(NULL); + u8 somtyp = phytec_get_som_type(NULL); + + if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtyp == PCL && rev >= 1))) { dram_timing.ddrc_cfg[3].val = 0x1323; dram_timing.ddrc_cfg[4].val = 0x1e84800; dram_timing.ddrc_cfg[5].val = 0x7a0118;

On Mon, Mar 4, 2024 at 1:04 PM Benjamin Hahn B.Hahn@phytec.de wrote:
ret = phytec_get_rev(NULL);
if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) {
u8 rev = phytec_get_rev(NULL);
u8 somtyp = phytec_get_som_type(NULL);
Nitpick: Better to spell out 'somtype' or 'som_type' to make it clearer.
"typ" usually means 'typical'.
participants (2)
-
Benjamin Hahn
-
Fabio Estevam