From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

The register CLKCNCSR controls the frequency of all cores in the same cluster.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 453a93d..d57f4da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/soc.h> #include <fsl_ifc.h> +#include "cpu.h"

DECLARE_GLOBAL_DATA_PTR;

@@ -44,7 +45,7 @@ void get_sys_info(struct sys_info *sys_info) [5] = 2, /* CC2 PPL / 2 */ };

- uint i; + uint i, cluster; uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; @@ -71,8 +72,9 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; }

- for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) { - u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + cluster = fsl_qoriq_core_to_cluster(cpu); + u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) & 0xf; u32 cplx_pll = core_cplx_pll[c_pll_sel];