some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL.

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: None Changes in v2: - add udelay function Changes in v3: - fix some coding style Changes in v4: None Changes in v5: None Changes in v6: - Adviced by Ben Chan: - use uint64_t as usec_to_tick() return type

arch/arm/include/asm/arch-rockchip/timer.h | 22 ++++++++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/board-spl.c | 21 ++----------- arch/arm/mach-rockchip/rk_timer.c | 48 ++++++++++++++++++++++++++++++ include/configs/rk3288_common.h | 3 +- 5 files changed, 75 insertions(+), 20 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/mach-rockchip/rk_timer.c

diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h new file mode 100644 index 0000000..1d044bb --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/timer.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_TIMER_H +#define __ASM_ARCH_TIMER_H + +struct rk_timer { + unsigned int timer_load_count0; + unsigned int timer_load_count1; + unsigned int timer_curr_value0; + unsigned int timer_curr_value1; + unsigned int timer_ctrl_reg; + unsigned int timer_int_status; +}; + +void rockchip_timer_init(void); +void rockchip_udelay(unsigned int usec); + +#endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 5a4e383..abe03a8 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -10,4 +10,5 @@ else obj-y += board.o endif obj-y += common.o +obj-y += rk_timer.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ diff --git a/arch/arm/mach-rockchip/board-spl.c b/arch/arm/mach-rockchip/board-spl.c index 28c3949..0426adf 100644 --- a/arch/arm/mach-rockchip/board-spl.c +++ b/arch/arm/mach-rockchip/board-spl.c @@ -18,6 +18,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/sdram.h> +#include <asm/arch/timer.h> #include <dm/pinctrl.h> #include <dm/root.h> #include <dm/test.h> @@ -110,24 +111,6 @@ static void configure_l2ctlr(void) write_l2ctlr(l2ctlr); }

-struct rk3288_timer { - u32 timer_load_count0; - u32 timer_load_count1; - u32 timer_curr_value0; - u32 timer_curr_value1; - u32 timer_ctrl_reg; - u32 timer_int_status; -}; - -void init_timer(void) -{ - struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE; - - writel(0xffffffff, &timer7_ptr->timer_load_count0); - writel(0xffffffff, &timer7_ptr->timer_load_count1); - writel(1, &timer7_ptr->timer_ctrl_reg); -} - static int configure_emmc(struct udevice *pinctrl) { struct gpio_desc desc; @@ -197,7 +180,7 @@ void board_init_f(ulong dummy) hang(); }

- init_timer(); + rockchip_timer_init(); configure_l2ctlr();

ret = uclass_get_device(UCLASS_CLK, 0, &dev); diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c new file mode 100644 index 0000000..ae5123d --- /dev/null +++ b/arch/arm/mach-rockchip/rk_timer.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/timer.h> +#include <asm/io.h> +#include <common.h> +#include <linux/types.h> + +struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE; + +static uint64_t rockchip_get_ticks(void) +{ + uint64_t timebase_h, timebase_l; + + timebase_l = readl(&timer_ptr->timer_curr_value0); + timebase_h = readl(&timer_ptr->timer_curr_value1); + + return timebase_h << 32 | timebase_l; +} + +static uint64_t usec_to_tick(unsigned int usec) +{ + uint64_t tick = usec; + tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000); + return tick; +} + +void rockchip_udelay(unsigned int usec) +{ + uint64_t tmp; + + /* get timestamp */ + tmp = rockchip_get_ticks() + usec_to_tick(usec); + + /* loop till event */ + while (rockchip_get_ticks() < tmp+1) + ; +} + +void rockchip_timer_init(void) +{ + writel(0xffffffff, &timer_ptr->timer_load_count0); + writel(0xffffffff, &timer_ptr->timer_load_count1); + writel(1, &timer_ptr->timer_ctrl_reg); +} diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 36408b9..cdea6cb 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -23,7 +23,8 @@ #define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_COUNTER (TIMER7_BASE + 8) +#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)

#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LIBCOMMON_SUPPORT

since different rockchip SOC have different size of SRAM, So the size SYS_MALLOC_F_LEN may different, so move this config to rk3288 own Kconfig

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: None Changes in v2: None Changes in v3: None Changes in v4: None Changes in v5: None Changes in v6: None

arch/arm/mach-rockchip/Kconfig | 3 --- arch/arm/mach-rockchip/rk3288/Kconfig | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ab50f4e..da665ef 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -12,9 +12,6 @@ config ROCKCHIP_RK3288 config SYS_MALLOC_F default y

-config SYS_MALLOC_F_LEN - default 0x800 - config SPL_DM default y

diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 4d0f1b5..d0a7276 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -19,6 +19,9 @@ config TARGET_CHROMEBOOK_JERRY config SYS_SOC default "rockchip"

+config SYS_MALLOC_F_LEN + default 0x0800 + source "board/google/chromebook_jerry/Kconfig"

source "board/firefly/firefly-rk3288/Kconfig"

since different rockchip soc need different spl file, so rename board-spl.c.

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: None Changes in v2: None Changes in v3: None Changes in v4: None Changes in v5: None Changes in v6: None

arch/arm/mach-rockchip/Makefile | 2 +- arch/arm/mach-rockchip/board-spl.c | 277 ------------------------------ arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++++++++++++++++++++++++ 3 files changed, 278 insertions(+), 278 deletions(-) delete mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index abe03a8..7088711 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -5,7 +5,7 @@ #

ifdef CONFIG_SPL_BUILD -obj-y += board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o else obj-y += board.o endif diff --git a/arch/arm/mach-rockchip/board-spl.c b/arch/arm/mach-rockchip/board-spl.c deleted file mode 100644 index 0426adf..0000000 --- a/arch/arm/mach-rockchip/board-spl.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <fdtdec.h> -#include <led.h> -#include <malloc.h> -#include <ram.h> -#include <spl.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/sdram.h> -#include <asm/arch/timer.h> -#include <dm/pinctrl.h> -#include <dm/root.h> -#include <dm/test.h> -#include <dm/util.h> -#include <power/regulator.h> - -DECLARE_GLOBAL_DATA_PTR; - -u32 spl_boot_device(void) -{ - const void *blob = gd->fdt_blob; - struct udevice *dev; - const char *bootdev; - int node; - int ret; - - bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); - debug("Boot device %s\n", bootdev); - if (!bootdev) - goto fallback; - - node = fdt_path_offset(blob, bootdev); - if (node < 0) { - debug("node=%d\n", node); - goto fallback; - } - ret = device_get_global_by_of_offset(node, &dev); - if (ret) { - debug("device at node %s/%d not found: %d\n", bootdev, node, - ret); - goto fallback; - } - debug("Found device %s\n", dev->name); - switch (device_get_uclass_id(dev)) { - case UCLASS_SPI_FLASH: - return BOOT_DEVICE_SPI; - case UCLASS_MMC: - return BOOT_DEVICE_MMC1; - default: - debug("Booting from device uclass '%s' not supported\n", - dev_get_uclass_name(dev)); - } - -fallback: - return BOOT_DEVICE_MMC1; -} - -u32 spl_boot_mode(void) -{ - return MMCSD_MODE_RAW; -} - -/* read L2 control register (L2CTLR) */ -static inline uint32_t read_l2ctlr(void) -{ - uint32_t val = 0; - - asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); - - return val; -} - -/* write L2 control register (L2CTLR) */ -static inline void write_l2ctlr(uint32_t val) -{ - /* - * Note: L2CTLR can only be written when the L2 memory system - * is idle, ie before the MMU is enabled. - */ - asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); - isb(); -} - -static void configure_l2ctlr(void) -{ - uint32_t l2ctlr; - - l2ctlr = read_l2ctlr(); - l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ - - /* - * Data RAM write latency: 2 cycles - * Data RAM read latency: 2 cycles - * Data RAM setup latency: 1 cycle - * Tag RAM write latency: 1 cycle - * Tag RAM read latency: 1 cycle - * Tag RAM setup latency: 1 cycle - */ - l2ctlr |= (1 << 3 | 1 << 0); - write_l2ctlr(l2ctlr); -} - -static int configure_emmc(struct udevice *pinctrl) -{ - struct gpio_desc desc; - int ret; - - pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC); - - /* - * TODO(sjg@chromium.org): Pick this up from device tree or perhaps - * use the EMMC_PWREN setting. - */ - ret = dm_gpio_lookup_name("D9", &desc); - if (ret) { - debug("gpio ret=%d\n", ret); - return ret; - } - ret = dm_gpio_request(&desc, "emmc_pwren"); - if (ret) { - debug("gpio_request ret=%d\n", ret); - return ret; - } - ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); - if (ret) { - debug("gpio dir ret=%d\n", ret); - return ret; - } - ret = dm_gpio_set_value(&desc, 1); - if (ret) { - debug("gpio value ret=%d\n", ret); - return ret; - } - - return 0; -} - -void board_init_f(ulong dummy) -{ - struct udevice *pinctrl; - struct udevice *dev; - int ret; - - /* Example code showing how to enable the debug UART on RK3288 */ -#ifdef EARLY_UART -#include <asm/arch/grf_rk3288.h> - /* Enable early UART on the RK3288 */ -#define GRF_BASE 0xff770000 - struct rk3288_grf * const grf = (void *)GRF_BASE; - - rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | - GPIO7C6_MASK << GPIO7C6_SHIFT, - GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | - GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); -#endif - - ret = spl_init(); - if (ret) { - debug("spl_init() failed: %d\n", ret); - hang(); - } - - rockchip_timer_init(); - configure_l2ctlr(); - - ret = uclass_get_device(UCLASS_CLK, 0, &dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("Pinctrl init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } - - /* - * Now that DRAM is initialized setup base pointer for simple malloc - * into RAM. - */ - gd->malloc_base = CONFIG_SPL_STACK_R_ADDR; - gd->malloc_ptr = 0; -} - -static int setup_led(void) -{ -#ifdef CONFIG_SPL_LED - struct udevice *dev; - char *led_name; - int ret; - - led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); - if (!led_name) - return 0; - ret = led_get_by_label(led_name, &dev); - if (ret) { - debug("%s: get=%d\n", __func__, ret); - return ret; - } - ret = led_set_on(dev, 1); - if (ret) - return ret; -#endif - - return 0; -} - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = setup_led(); - - if (ret) { - debug("LED ret=%d\n", ret); - hang(); - } - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } - ret = configure_emmc(pinctrl); - if (ret) { - debug("%s: Failed to set up eMMC\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); - return; -err: - printf("spl_board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); -} diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c new file mode 100644 index 0000000..0426adf --- /dev/null +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -0,0 +1,277 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <fdtdec.h> +#include <led.h> +#include <malloc.h> +#include <ram.h> +#include <spl.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <asm/arch/sdram.h> +#include <asm/arch/timer.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <dm/test.h> +#include <dm/util.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + const void *blob = gd->fdt_blob; + struct udevice *dev; + const char *bootdev; + int node; + int ret; + + bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); + debug("Boot device %s\n", bootdev); + if (!bootdev) + goto fallback; + + node = fdt_path_offset(blob, bootdev); + if (node < 0) { + debug("node=%d\n", node); + goto fallback; + } + ret = device_get_global_by_of_offset(node, &dev); + if (ret) { + debug("device at node %s/%d not found: %d\n", bootdev, node, + ret); + goto fallback; + } + debug("Found device %s\n", dev->name); + switch (device_get_uclass_id(dev)) { + case UCLASS_SPI_FLASH: + return BOOT_DEVICE_SPI; + case UCLASS_MMC: + return BOOT_DEVICE_MMC1; + default: + debug("Booting from device uclass '%s' not supported\n", + dev_get_uclass_name(dev)); + } + +fallback: + return BOOT_DEVICE_MMC1; +} + +u32 spl_boot_mode(void) +{ + return MMCSD_MODE_RAW; +} + +/* read L2 control register (L2CTLR) */ +static inline uint32_t read_l2ctlr(void) +{ + uint32_t val = 0; + + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + + return val; +} + +/* write L2 control register (L2CTLR) */ +static inline void write_l2ctlr(uint32_t val) +{ + /* + * Note: L2CTLR can only be written when the L2 memory system + * is idle, ie before the MMU is enabled. + */ + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); + isb(); +} + +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} + +static int configure_emmc(struct udevice *pinctrl) +{ + struct gpio_desc desc; + int ret; + + pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC); + + /* + * TODO(sjg@chromium.org): Pick this up from device tree or perhaps + * use the EMMC_PWREN setting. + */ + ret = dm_gpio_lookup_name("D9", &desc); + if (ret) { + debug("gpio ret=%d\n", ret); + return ret; + } + ret = dm_gpio_request(&desc, "emmc_pwren"); + if (ret) { + debug("gpio_request ret=%d\n", ret); + return ret; + } + ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + if (ret) { + debug("gpio dir ret=%d\n", ret); + return ret; + } + ret = dm_gpio_set_value(&desc, 1); + if (ret) { + debug("gpio value ret=%d\n", ret); + return ret; + } + + return 0; +} + +void board_init_f(ulong dummy) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + + /* Example code showing how to enable the debug UART on RK3288 */ +#ifdef EARLY_UART +#include <asm/arch/grf_rk3288.h> + /* Enable early UART on the RK3288 */ +#define GRF_BASE 0xff770000 + struct rk3288_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | + GPIO7C6_MASK << GPIO7C6_SHIFT, + GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | + GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); +#endif + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + rockchip_timer_init(); + configure_l2ctlr(); + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return; + } + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("Pinctrl init failed: %d\n", ret); + return; + } + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } + + /* + * Now that DRAM is initialized setup base pointer for simple malloc + * into RAM. + */ + gd->malloc_base = CONFIG_SPL_STACK_R_ADDR; + gd->malloc_ptr = 0; +} + +static int setup_led(void) +{ +#ifdef CONFIG_SPL_LED + struct udevice *dev; + char *led_name; + int ret; + + led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); + if (!led_name) + return 0; + ret = led_get_by_label(led_name, &dev); + if (ret) { + debug("%s: get=%d\n", __func__, ret); + return ret; + } + ret = led_set_on(dev, 1); + if (ret) + return ret; +#endif + + return 0; +} + +void spl_board_init(void) +{ + struct udevice *pinctrl; + int ret; + + ret = setup_led(); + + if (ret) { + debug("LED ret=%d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); + if (ret) { + debug("%s: Failed to set up SD card\n", __func__); + goto err; + } + ret = configure_emmc(pinctrl); + if (ret) { + debug("%s: Failed to set up eMMC\n", __func__); + goto err; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + goto err; + } + + preloader_console_init(); + return; +err: + printf("spl_board_init: Error %d\n", ret); + + /* No way to report error here */ + hang(); +}

some rockchips soc will not use uclass in SPL stage, so define config to decide whether to build common.c

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: None Changes in v2: None Changes in v3: None Changes in v4: None Changes in v5: None Changes in v6: None

arch/arm/mach-rockchip/Makefile | 2 +- include/configs/rk3288_common.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 7088711..902235b 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -9,6 +9,6 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o else obj-y += board.o endif -obj-y += common.o obj-y += rk_timer.o +obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index cdea6cb..5ba084d 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -44,6 +44,9 @@ #define CONFIG_SPL_STACK 0xff718000 #define CONFIG_SPL_TEXT_BASE 0xff704004

+#define CONFIG_ROCKCHIP_COMMON +#define CONFIG_SPL_ROCKCHIP_COMMON + /* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC

Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can remove from SPL stage.

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: None Changes in v2: None Changes in v3: - fix compile error Changes in v4: None Changes in v5: None Changes in v6: None

configs/chromebook_jerry_defconfig | 2 ++ configs/firefly-rk3288_defconfig | 2 ++ configs/sandbox_defconfig | 2 ++ drivers/core/Kconfig | 19 +++++++++++++++++++ drivers/core/Makefile | 4 ++-- 5 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 3ded392..eca8409 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -12,11 +12,13 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SPL_SYSCON=y CONFIG_LED=y CONFIG_SPL_LED=y CONFIG_LED_GPIO=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index edb2db2..ec7ab8e 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -12,11 +12,13 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SPL_SYSCON=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_RESET=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 94c8e68..8919db5 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -17,7 +17,9 @@ CONFIG_CMD_TPM_TEST=y CONFIG_OF_CONTROL=y CONFIG_OF_HOSTFILE=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_DEVRES=y CONFIG_CLK=y CONFIG_SANDBOX_GPIO=y diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 15681df..ac68172 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -72,6 +72,16 @@ config REGMAP support any bus type (I2C, SPI) but so far this only supports direct memory access.

+config SPL_REGMAP + bool "Support register maps in SPL" + depends on DM + help + Hardware peripherals tend to have one or more sets of registers + which can be accessed to control the hardware. A register map + models this with a simple read/write interface. It can in principle + support any bus type (I2C, SPI) but so far this only supports + direct memory access. + config SYSCON bool "Support system controllers" depends on REGMAP @@ -81,6 +91,15 @@ config SYSCON by this uclass, including accessing registers via regmap and assigning a unique number to each.

+config SPL_SYSCON + bool "Support system controllers in SPL" + depends on REGMAP + help + Many SoCs have a number of system controllers which are dealt with + as a group by a single driver. Some common functionality is provided + by this uclass, including accessing registers via regmap and + assigning a unique number to each. + config DEVRES bool "Managed device resources" depends on DM diff --git a/drivers/core/Makefile b/drivers/core/Makefile index f19f67d..07adb61 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -9,5 +9,5 @@ obj-$(CONFIG_DEVRES) += devres.o obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o obj-$(CONFIG_DM) += dump.o -obj-$(CONFIG_REGMAP) += regmap.o -obj-$(CONFIG_SYSCON) += syscon-uclass.o +obj-$(CONFIG_$(SPL_)REGMAP) += regmap.o +obj-$(CONFIG_$(SPL_)SYSCON) += syscon-uclass.o

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: None Changes in v2: - modify code suggest by Simon Changes in v3: None Changes in v4: None Changes in v5: None Changes in v6: None

drivers/serial/serial_rockchip.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index 0e7bbfc..21836bb 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -12,6 +12,7 @@

static const struct udevice_id rockchip_serial_ids[] = { { .compatible = "rockchip,rk3288-uart" }, + { .compatible = "rockchip,rk3036-uart" }, { } };

Since rk3036 device tree file still in reviewing, bring it from https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in uboot

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: - clean copyright announcement Changes in v2: None Changes in v3: None Changes in v4: None Changes in v5: None Changes in v6: None

arch/arm/dts/rk3036.dtsi | 427 +++++++++++++++++++++++++++++++++ include/dt-bindings/clock/rk3036-cru.h | 186 ++++++++++++++ 2 files changed, 613 insertions(+) create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi new file mode 100644 index 0000000..0daae1e --- /dev/null +++ b/arch/arm/dts/rk3036.dtsi @@ -0,0 +1,427 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3036-cru.h> +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3036"; + + interrupt-parent = <&gic>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + i2c1 = &i2c1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + mmc0 = &emmc; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3036-smp"; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + resets = <&cru SRST_CORE0>; + }; + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + arm,pl330-broken-no-flushp; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + uart0: serial@20060000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + }; + + uart1: serial@20064000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20064000 0x100>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + }; + + uart2: serial@20068000 { + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; + reg = <0x20068000 0x100>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + }; + + pwm0: pwm@20050000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050000 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@20050010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050010 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + sram: sram@10080000 { + compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; + reg = <0x10080000 0x2000>; + }; + + gic: interrupt-controller@10139000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x10139000 0x1000>, + <0x1013a000 0x1000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts = <GIC_PPI 9 0xf04>; + }; + + grf: syscon@20008000 { + compatible = "rockchip,rk3036-grf", "syscon"; + reg = <0x20008000 0x1000>; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; + status = "disabled"; + }; + + usb_host: usb@101c0000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x101c0000 0x40000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG1>; + clock-names = "otg"; + dr_mode = "host"; + status = "disabled"; + }; + + emmc: dwmmc@1021c000 { + compatible = "rockchip,rk3288-dw-mshc"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + dmas = <&pdma 12>; + dma-names = "rx-tx"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x1021c000 0x4000>; + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + disable-wp; + non-removable; + num-slots = <1>; + default-sample-phase = <158>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3036-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@2007c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2007c000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, + <1 25 RK_FUNC_2 &pcfg_pull_none>, + <1 26 RK_FUNC_2 &pcfg_pull_none>, + <1 27 RK_FUNC_2 &pcfg_pull_none>; + /* + <1 28 RK_FUNC_2 &pcfg_pull_up>, + <1 29 RK_FUNC_2 &pcfg_pull_up>, + <1 30 RK_FUNC_2 &pcfg_pull_up>, + <1 31 RK_FUNC_2 &pcfg_pull_up>; + */ + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, + <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, + <2 23 RK_FUNC_1 &pcfg_pull_none>; + }; + /* no rts / cts for uart1 */ + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + <1 19 RK_FUNC_2 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 1 2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <0 27 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, + <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; + + i2c1: i2c@20056000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x20056000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; +}; diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h new file mode 100644 index 0000000..87acf4a --- /dev/null +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner heiko@sntech.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_SFC 160 + +#define DCLK_LCDC 190 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif

Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: - clean copyright announcement Changes in v2: - move some macro to cru_rk3036.h Changes in v3: None Changes in v4: None Changes in v5: None Changes in v6: None

arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 ++++++++++ drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++++++++++++++ 3 files changed, 583 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 drivers/clk/clk_rk3036.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h new file mode 100644 index 0000000..7ecc8ee --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3036_H +#define _ASM_ARCH_CRU_RK3036_H + +#include <common.h> + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define CPU_ACLK_HZ 150000000 +#define CPU_HCLK_HZ 300000000 +#define CPU_PCLK_HZ 300000000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +struct rk3036_cru { + struct rk3036_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + } pll[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[11]; + unsigned int reserved; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int reserved1[2]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved2[2]; + unsigned int cru_glb_cnt_th; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved3; + unsigned int cru_rst_st; + unsigned int reserved4[0x23]; + unsigned int cru_pll_mask_con; +}; +check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_POSTDIV1_MASK = 7, + PLL_POSTDIV1_SHIFT = 12, + PLL_FBDIV_MASK = 0xfff, + PLL_FBDIV_SHIFT = 0, + + /* PLLCON1 */ + PLL_DSMPD_MASK = 1, + PLL_DSMPD_SHIFT = 12, + PLL_LOCK_STATUS_MASK = 1, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_POSTDIV2_MASK = 7, + PLL_POSTDIV2_SHIFT = 6, + PLL_REFDIV_MASK = 0x3f, + PLL_REFDIV_SHIFT = 0, + PLL_RST_SHIFT = 14, + + /* CRU_MODE */ + GPLL_MODE_MASK = 3, + GPLL_MODE_SHIFT = 12, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + GPLL_MODE_DEEP, + DPLL_MODE_MASK = 1, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_MASK = 1, + APLL_MODE_SHIFT = 0, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + CPU_CLK_PLL_SEL_MASK = 3, + CPU_CLK_PLL_SEL_SHIFT = 14, + CPU_CLK_PLL_SEL_APLL = 0, + CPU_CLK_PLL_SEL_DPLL, + CPU_CLK_PLL_SEL_GPLL, + ACLK_CPU_DIV_MASK = 0x1f, + ACLK_CPU_DIV_SHIFT = 8, + CORE_CLK_PLL_SEL_MASK = 1, + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_DIV_CON_MASK = 0x1f, + CORE_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL1_CON */ + CPU_PCLK_DIV_MASK = 7, + CPU_PCLK_DIV_SHIFT = 12, + CPU_HCLK_DIV_MASK = 3, + CPU_HCLK_DIV_SHIFT = 8, + CORE_ACLK_DIV_MASK = 7, + CORE_ACLK_DIV_SHIFT = 4, + CORE_PERI_DIV_MASK = 0xf, + CORE_PERI_DIV_SHIFT = 0, + + /* CRU_CLKSEL10_CON */ + PERI_PLL_SEL_MASK = 3, + PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_APLL = 0, + PERI_PLL_DPLL, + PERI_PLL_GPLL, + PERI_PCLK_DIV_MASK = 3, + PERI_PCLK_DIV_SHIFT = 12, + PERI_HCLK_DIV_MASK = 3, + PERI_HCLK_DIV_SHIFT = 8, + PERI_ACLK_DIV_MASK = 0x1f, + PERI_ACLK_DIV_SHIFT = 0, + + /* CRU_CLKSEL11_CON */ + SDIO_DIV_MASK = 0x7f, + SDIO_DIV_SHIFT = 8, + MMC0_DIV_MASK = 0x7f, + MMC0_DIV_SHIFT = 0, + + /* CRU_CLKSEL12_CON */ + EMMC_PLL_MASK = 3, + EMMC_PLL_SHIFT = 12, + EMMC_SEL_APLL = 0, + EMMC_SEL_DPLL, + EMMC_SEL_GPLL, + EMMC_SEL_24M, + SDIO_PLL_MASK = 3, + SDIO_PLL_SHIFT = 10, + SDIO_SEL_APLL = 0, + SDIO_SEL_DPLL, + SDIO_SEL_GPLL, + SDIO_SEL_24M, + MMC0_PLL_MASK = 3, + MMC0_PLL_SHIFT = 8, + MMC0_SEL_APLL = 0, + MMC0_SEL_DPLL, + MMC0_SEL_GPLL, + MMC0_SEL_24M, + EMMC_DIV_MASK = 0x7f, + EMMC_DIV_SHIFT = 0, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 008ec10..4a6a4a8 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -6,5 +6,6 @@ #

obj-$(CONFIG_CLK) += clk-uclass.o +obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c new file mode 100644 index 0000000..6c802b6 --- /dev/null +++ b/drivers/clk/clk_rk3036.c @@ -0,0 +1,414 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <dm/lists.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3036_clk_plat { + enum rk_clk_id clk_id; +}; + +struct rk3036_clk_priv { + struct rk3036_cru *cru; + ulong rate; +}; + +enum { + VCO_MAX_HZ = 2400U * 1000000, + VCO_MIN_HZ = 600 * 1000000, + OUTPUT_MAX_HZ = 2400U * 1000000, + OUTPUT_MIN_HZ = 24 * 1000000, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ + _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ + OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ + #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* use interge mode*/ +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); + +static inline unsigned int log2(unsigned int value) +{ + return fls(value) - 1; +} + +static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +{ + int pll_id = rk_pll_id(clk_id); + struct rk3036_pll *pll = &cru->pll[pll_id]; + + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; + uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; + + debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ + vco=%u Hz, output=%u Hz\n", + pll, div->fbdiv, div->refdiv, div->postdiv1, + div->postdiv2, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); + + /* use interger mode */ + rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + + rk_clrsetreg(&pll->con0, + PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | + PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, + (div->postdiv2 << PLL_POSTDIV2_SHIFT | + div->refdiv << PLL_REFDIV_SHIFT)); + + /* waiting for pll lock */ + while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) + udelay(1); + + return 0; +} + +static void rkclk_init(struct rk3036_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | + APLL_MODE_SLOW << APLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + + /* + * select apll as core clock pll source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + * core hz : apll = 1:1 + */ + aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; + assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); + + pclk_div = APLL_HZ / CORE_PERI_HZ - 1; + assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CORE_CLK_PLL_SEL_MASK << CORE_CLK_PLL_SEL_SHIFT | + CORE_DIV_CON_MASK << CORE_DIV_CON_SHIFT, + CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | + 0 << CORE_DIV_CON_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT | + CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT, + aclk_div << CORE_ACLK_DIV_SHIFT | + pclk_div << CORE_PERI_DIV_SHIFT); + + /* + * select apll as cpu clock pll source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = APLL_HZ / CPU_ACLK_HZ - 1; + assert((aclk_div + 1) * CPU_ACLK_HZ == APLL_HZ && aclk_div < 0x1f); + + pclk_div = APLL_HZ / CPU_PCLK_HZ - 1; + assert((pclk_div + 1) * CPU_PCLK_HZ == APLL_HZ && pclk_div < 0x7); + + hclk_div = APLL_HZ / CPU_HCLK_HZ - 1; + assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CPU_CLK_PLL_SEL_MASK << CPU_CLK_PLL_SEL_SHIFT | + ACLK_CPU_DIV_MASK << ACLK_CPU_DIV_SHIFT, + CPU_CLK_PLL_SEL_APLL << CPU_CLK_PLL_SEL_SHIFT | + aclk_div << ACLK_CPU_DIV_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT | + CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT, + pclk_div << CPU_PCLK_DIV_SHIFT | + hclk_div << CPU_HCLK_DIV_SHIFT); + + /* + * select gpll as peri clock pll source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (pclk_div < 0x4)); + + pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && pclk_div < 0x8); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PLL_SEL_MASK << PERI_PLL_SEL_SHIFT | + PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | + PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | + PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_NORM << GPLL_MODE_SHIFT | + APLL_MODE_NORM << APLL_MODE_SHIFT); +} + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t refdiv, fbdiv, postdiv1, postdiv2; + uint32_t con; + int pll_id = rk_pll_id(clk_id); + struct rk3036_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, + GPLL_MODE_SHIFT, 0xff + }; + static u8 clk_mask[CLK_COUNT] = { + 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, + GPLL_MODE_MASK, 0xff + }; + uint shift; + uint mask; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + mask = clk_mask[clk_id]; + + switch ((con >> shift) & mask) { + case GPLL_MODE_SLOW: + return OSC_HZ; + case GPLL_MODE_NORM: + + /* normal mode */ + con = readl(&pll->con0); + postdiv1 = (con >> PLL_POSTDIV1_SHIFT) & PLL_POSTDIV1_MASK; + fbdiv = (con >> PLL_FBDIV_SHIFT) & PLL_FBDIV_MASK; + con = readl(&pll->con1); + postdiv2 = (con >> PLL_POSTDIV2_SHIFT) & PLL_POSTDIV2_MASK; + refdiv = (con >> PLL_REFDIV_SHIFT) & PLL_REFDIV_MASK; + return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; + case GPLL_MODE_DEEP: + default: + return 32768; + } +} + +static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, + enum periph_id periph) +{ + uint src_rate; + uint div, mux; + u32 con; + + switch (periph) { + case PERIPH_ID_EMMC: + con = readl(&cru->cru_clksel_con[12]); + mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; + div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + break; + case PERIPH_ID_SDCARD: + con = readl(&cru->cru_clksel_con[12]); + mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; + div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + break; + default: + return -EINVAL; + } + + src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; + return DIV_TO_RATE(src_rate, div); +} + +static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, + enum periph_id periph, uint freq) +{ + int src_clk_div; + int mux; + + debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); + + /* mmc clock auto divide 2 in internal */ + src_clk_div = (clk_general_rate / 2 + freq - 1) / freq; + + if (src_clk_div > 0x7f) { + src_clk_div = (OSC_HZ / 2 + freq - 1) / freq; + mux = EMMC_SEL_24M; + } else { + mux = EMMC_SEL_GPLL; + } + + switch (periph) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_PLL_MASK << EMMC_PLL_SHIFT | + EMMC_DIV_MASK << EMMC_DIV_SHIFT, + mux << EMMC_PLL_SHIFT | + (src_clk_div - 1) << EMMC_DIV_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_PLL_MASK << MMC0_PLL_SHIFT | + MMC0_DIV_MASK << MMC0_DIV_SHIFT, + mux << MMC0_PLL_SHIFT | + (src_clk_div - 1) << MMC0_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_mmc_get_clk(cru, clk_general_rate, periph); +} + +static ulong rk3036_clk_get_rate(struct udevice *dev) +{ + struct rk3036_clk_plat *plat = dev_get_platdata(dev); + struct rk3036_clk_priv *priv = dev_get_priv(dev); + + debug("%s\n", dev->name); + return rkclk_pll_get_rate(priv->cru, plat->clk_id); +} + +static ulong rk3036_clk_set_rate(struct udevice *dev, ulong rate) +{ + debug("%s\n", dev->name); + + return 0; +} + +ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate) +{ + struct rk3036_clk_priv *priv = dev_get_priv(dev); + ulong new_rate; + + switch (periph) { + case PERIPH_ID_EMMC: + new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev), + periph, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static struct clk_ops rk3036_clk_ops = { + .get_rate = rk3036_clk_get_rate, + .set_rate = rk3036_clk_set_rate, + .set_periph_rate = rk3036_set_periph_rate, +}; + +static int rk3036_clk_probe(struct udevice *dev) +{ + struct rk3036_clk_plat *plat = dev_get_platdata(dev); + struct rk3036_clk_priv *priv = dev_get_priv(dev); + + if (plat->clk_id != CLK_OSC) { + struct rk3036_clk_priv *parent_priv = dev_get_priv(dev->parent); + + priv->cru = parent_priv->cru; + return 0; + } + priv->cru = (struct rk3036_cru *)dev_get_addr(dev); + rkclk_init(priv->cru); + + return 0; +} + +static const char *const clk_name[] = { + "osc", + "apll", + "dpll", + "cpll", + "gpll", + "mpll", +}; + +static int rk3036_clk_bind(struct udevice *dev) +{ + struct rk3036_clk_plat *plat = dev_get_platdata(dev); + int pll, ret; + + /* We only need to set up the root clock */ + if (dev->of_offset == -1) { + plat->clk_id = CLK_OSC; + return 0; + } + + /* Create devices for P main clocks */ + for (pll = 1; pll < CLK_COUNT; pll++) { + struct udevice *child; + struct rk3036_clk_plat *cplat; + + debug("%s %s\n", __func__, clk_name[pll]); + ret = device_bind_driver(dev, "clk_rk3036", clk_name[pll], + &child); + if (ret) + return ret; + + cplat = dev_get_platdata(child); + cplat->clk_id = pll; + } + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev); + if (ret) + debug("Warning: No RK3036 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rk3036_clk_ids[] = { + { .compatible = "rockchip,rk3036-cru" }, + { } +}; + +U_BOOT_DRIVER(clk_rk3036) = { + .name = "clk_rk3036", + .id = UCLASS_CLK, + .of_match = rk3036_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv), + .platdata_auto_alloc_size = sizeof(struct rk3036_clk_plat), + .ops = &rk3036_clk_ops, + .bind = rk3036_clk_bind, + .probe = rk3036_clk_probe, +};

GRF is the gereral register file. Add header files with register definitions.

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: - clean copyright announcement Changes in v2: - move some macro to grf_rk3036.h Changes in v3: None Changes in v4: None Changes in v5: None Changes in v6: None

arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 ++++++++++++++++++++++++ 1 file changed, 493 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h new file mode 100644 index 0000000..72d133c --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -0,0 +1,493 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK3036_H +#define _ASM_ARCH_GRF_RK3036_H + +#include <common.h> + +struct rk3036_grf { + unsigned int reserved[0x2a]; + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + + unsigned int reserved2[0x0a]; + unsigned int gpiods; + unsigned int reserved3[0x05]; + unsigned int gpio0l_pull; + unsigned int gpio0h_pull; + unsigned int gpio1l_pull; + unsigned int gpio1h_pull; + unsigned int gpio2l_pull; + unsigned int gpio2h_pull; + unsigned int reserved4[4]; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_status0; + unsigned int reserved5; + unsigned int soc_con3; + unsigned int reserved6; + unsigned int dmac_con0; + unsigned int dmac_con1; + unsigned int dmac_con2; + unsigned int reserved7[5]; + unsigned int uoc0_con5; + unsigned int reserved8[4]; + unsigned int uoc1_con4; + unsigned int uoc1_con5; + unsigned int reserved9; + unsigned int ddrc_stat; + unsigned int uoc_con6; + unsigned int soc_status1; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int cpu_con2; + unsigned int cpu_con3; + unsigned int reserved10; + unsigned int reserved11; + unsigned int cpu_status0; + unsigned int cpu_status1; + unsigned int os_reg[8]; + unsigned int reserved12[6]; + unsigned int dll_con[4]; + unsigned int dll_status[4]; + unsigned int dfi_wrnum; + unsigned int dfi_rdnum; + unsigned int dfi_actnum; + unsigned int dfi_timerval; + unsigned int nfi_fifo[4]; + unsigned int reserved13[0x10]; + unsigned int usbphy0_con[8]; + unsigned int usbphy1_con[8]; + unsigned int reserved14[0x10]; + unsigned int chip_tag; + unsigned int sdmmc_det_cnt; +}; +check_member(rk3036_grf, sdmmc_det_cnt, 0x304); + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 1, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 1, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 3, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + GPIO0A1_PWM2, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 3, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, + GPIO0A0_PWM1, + +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3, + GPIO0B6_GPIO = 0, + GPIO0B6_MMC1_D3, + GPIO0B6_I2S1_SCLK, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3, + GPIO0B5_GPIO = 0, + GPIO0B5_MMC1_D2, + GPIO0B5_I2S1_SDI, + + GPIO0B4_SHIFT = 8, + GPIO0B4_MASK = 3, + GPIO0B4_GPIO = 0, + GPIO0B4_MMC1_D1, + GPIO0B4_I2S1_LRCKTX, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3, + GPIO0B3_GPIO = 0, + GPIO0B3_MMC1_D0, + GPIO0B3_I2S1_LRCKRX, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3, + GPIO0B1_GPIO = 0, + GPIO0B1_MMC1_CLKOUT, + GPIO0B1_I2S1_MCLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_MMC1_CMD, + GPIO0B0_I2S1_SDO, +}; + +/* GRF_GPIO0C_IOMUX */ +enum { + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 1, + GPIO0C4_GPIO = 0, + GPIO0C4_DRIVE_VBUS, + + GPIO0C3_SHIFT = 6, + GPIO0C3_MASK = 1, + GPIO0C3_GPIO = 0, + GPIO0C3_UART0_CTSN, + + GPIO0C2_SHIFT = 4, + GPIO0C2_MASK = 1, + GPIO0C2_GPIO = 0, + GPIO0C2_UART0_RTSN, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 1, + GPIO0C1_GPIO = 0, + GPIO0C1_UART0_SIN, + + + GPIO0C0_SHIFT = 0, + GPIO0C0_MASK = 1, + GPIO0C0_GPIO = 0, + GPIO0C0_UART0_SOUT, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 1, + GPIO0D4_GPIO = 0, + GPIO0D4_SPDIF, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 1, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM3, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 1, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 1, + GPIO1A5_GPIO = 0, + GPIO1A5_I2S_SDI, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 1, + GPIO1A4_GPIO = 0, + GPIO1A4_I2S_SD0, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1, + GPIO1A3_GPIO = 0, + GPIO1A3_I2S_LRCKTX, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 6, + GPIO1A2_GPIO = 0, + GPIO1A2_I2S_LRCKRX, + GPIO1A2_I2S_PWM1_0, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 1, + GPIO1A1_GPIO = 0, + GPIO1A1_I2S_SCLK, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 1, + GPIO1A0_GPIO = 0, + GPIO1A0_I2S_MCLK, + +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 1, + GPIO1B7_GPIO = 0, + GPIO1B7_MMC0_CMD, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 1, + GPIO1B3_GPIO = 0, + GPIO1B3_HDMI_HPD, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 1, + GPIO1B2_GPIO = 0, + GPIO1B2_HDMI_SCL, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 1, + GPIO1B1_GPIO = 0, + GPIO1B1_HDMI_SDA, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 1, + GPIO1B0_GPIO = 0, + GPIO1B0_HDMI_CEC, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3, + GPIO1C5_GPIO = 0, + GPIO1C5_MMC0_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3, + GPIO1C4_GPIO = 0, + GPIO1C4_MMC0_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3, + GPIO1C3_GPIO = 0, + GPIO1C3_MMC0_D1, + GPIO1C3_UART2_SOUT, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3, + GPIO1C2_GPIO = 0, + GPIO1C2_MMC0_D0, + GPIO1C2_UART2_SIN, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 1, + GPIO1C1_GPIO = 0, + GPIO1C1_MMC0_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 1, + GPIO1C0_GPIO = 0, + GPIO1C0_MMC0_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + GPIO1D7_SPI_CSN1, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + GPIO1D6_SPI_CSN0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + GPIO1D5_SPI_TXD, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + GPIO1D4_SPI_RXD, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + GPIO1D3_SFC_SIO3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + GPIO1D2_SFC_SIO2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + GPIO1D1_SFC_SIO1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, + GPIO1D0_SFC_SIO0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 1, + GPIO2A7_GPIO = 0, + GPIO2A7_TESTCLK_OUT, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 1, + GPIO2A6_GPIO = 0, + GPIO2A6_NAND_CS0, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + GPIO2A3_SFC_CLK, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SFC_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SFC_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_EMMC_CLKOUT, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI_CLK, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 1, + GPIO2B7_GPIO = 0, + GPIO2B7_MAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3, + GPIO2B6_GPIO = 0, + GPIO2B6_MAC_CLKOUT, + GPIO2B6_MAC_CLKIN, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 1, + GPIO2B5_GPIO = 0, + GPIO2B5_MAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 1, + GPIO2B4_GPIO = 0, + GPIO2B4_MAC_MDIO, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 1, + GPIO2B2_GPIO = 0, + GPIO2B2_MAC_CRS, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C7_SHIFT = 14, + GPIO2C7_MASK = 3, + GPIO2C7_GPIO = 0, + GPIO2C7_UART1_SOUT, + GPIO2C7_TESTCLK_OUT1, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 1, + GPIO2C6_GPIO = 0, + GPIO2C6_UART1_SIN, + + GPIO2C5_SHIFT = 10, + GPIO2C5_MASK = 1, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL, + + GPIO2C4_SHIFT = 8, + GPIO2C4_MASK = 1, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA, + + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 1, + GPIO2C3_GPIO = 0, + GPIO2C3_MAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 1, + GPIO2C2_GPIO = 0, + GPIO2C2_MAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 1, + GPIO2C1_GPIO = 0, + GPIO2C1_MAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 1, + GPIO2C0_GPIO = 0, + GPIO2C0_MAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 1, + GPIO2D6_GPIO = 0, + GPIO2D6_I2S_SDO1, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 1, + GPIO2D5_GPIO = 0, + GPIO2D5_I2S_SDO2, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 1, + GPIO2D4_GPIO = 0, + GPIO2D4_I2S_SDO3, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 1, + GPIO2D1_GPIO = 0, + GPIO2D1_MAC_MDC, +}; +#endif

We can reset the Soc using some CRU (clock/reset unit) register. Add support for this.

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- --- Changes in v1: - clean copyright announcement Changes in v2: - only build reset_rk3036.c in NON-SPL stage Changes in v3: None Changes in v4: None Changes in v5: None Changes in v6: None

arch/arm/mach-rockchip/rk3036/Makefile | 10 +++++++ arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c

diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile new file mode 100644 index 0000000..a483347 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2015 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y += reset_rk3036.o +endif + diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c new file mode 100644 index 0000000..fefb568 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <reset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3036.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rk3036_reset_request(struct udevice *dev, enum reset_t type) +{ + struct rk3036_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case RESET_WARM: + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case RESET_COLD: + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct reset_ops rk3036_reset = { + .request = rk3036_reset_request, +}; + +U_BOOT_DRIVER(reset_rk3036) = { + .name = "rk3036_reset", + .id = UCLASS_RESET, + .ops = &rk3036_reset, +};

Add a driver that provides access to system controllers

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: - clean copyright announcement Changes in v2: - only build syscon_rk3036.c on NON-SPL stage Changes in v3: None Changes in v4: None Changes in v5: None

arch/arm/mach-rockchip/rk3036/Makefile | 2 +- arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c

diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index a483347..5d14b95 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -6,5 +6,5 @@

ifndef CONFIG_SPL_BUILD obj-y += reset_rk3036.o +obj-y += syscon_rk3036.o endif - diff --git a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c new file mode 100644 index 0000000..965afde --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3036_syscon_ids[] = { + { .compatible = "rockchip,rk3036-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3036) = { + .name = "rk3036_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3036_syscon_ids, +};

Add a driver which support pin multiplexing setup for rk3036

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: - clean copyright announcement Changes in v2: None Changes in v3: - fix some coding style error Changes in v4: None Changes in v5: None Changes in v6: - remove duplicate ROCKCHIP_PINCTRL in Kconfig

drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++++++++++++++++++++++++ 3 files changed, 286 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 3b6e3b7..57e6142 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -114,6 +114,15 @@ config ROCKCHIP_PINCTRL definitions and pin control functions for each available multiplex function.

+config ROCKCHIP_3036_PINCTRL + bool "Rockchip rk3036 pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is + controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config PINCTRL_SANDBOX bool "Sandbox pinctrl driver" depends on SANDBOX diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 251bace..6fa7d00 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -6,3 +6,4 @@ #

obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o +obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c new file mode 100644 index 0000000..581b096 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c @@ -0,0 +1,276 @@ +/* + * Pinctrl driver for Rockchip 3036 SoCs + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3036_pinctrl_priv { + struct rk3036_grf *grf; +}; + +static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id) +{ + switch (pwm_id) { + case PERIPH_ID_PWM0: + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK << GPIO0D2_SHIFT, + GPIO0D2_PWM0 << GPIO0D2_SHIFT); + break; + case PERIPH_ID_PWM1: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK << GPIO0A0_SHIFT, + GPIO0A0_PWM1 << GPIO0A0_SHIFT); + break; + case PERIPH_ID_PWM2: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK << GPIO0A1_SHIFT, + GPIO0A1_PWM2 << GPIO0A1_SHIFT); + break; + case PERIPH_ID_PWM3: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK << GPIO0D3_SHIFT, + GPIO0D3_PWM3 << GPIO0D3_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A1_MASK << GPIO0A1_SHIFT | + GPIO0A0_MASK << GPIO0A0_SHIFT, + GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | + GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); + + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A3_MASK << GPIO0A3_SHIFT | + GPIO0A2_MASK << GPIO0A2_SHIFT, + GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | + GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C5_MASK << GPIO2C5_SHIFT | + GPIO2C4_MASK << GPIO2C4_SHIFT, + GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | + GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); + + break; + } +} + +static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs) +{ + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D6_MASK << GPIO1D6_SHIFT, + GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D7_MASK << GPIO1D7_SHIFT, + GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT); + break; + } + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D5_MASK << GPIO1D5_SHIFT | + GPIO1D4_MASK << GPIO1D4_SHIFT, + GPIO1D5_SPI_TXD << GPIO1D5_SHIFT | + GPIO1D4_SPI_RXD << GPIO1D4_SHIFT); + + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A0_MASK << GPIO2A0_SHIFT, + GPIO2A0_SPI_CLK << GPIO2A0_SHIFT); +} + +static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART0: + rk_clrsetreg(&grf->gpio0c_iomux, + GPIO0C3_MASK << GPIO0C3_SHIFT | + GPIO0C2_MASK << GPIO0C2_SHIFT | + GPIO0C1_MASK << GPIO0C1_SHIFT | + GPIO0C0_MASK << GPIO0C0_SHIFT, + GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT | + GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT | + GPIO0C1_UART0_SIN << GPIO0C1_SHIFT | + GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT); + break; + case PERIPH_ID_UART1: + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C7_MASK << GPIO2C7_SHIFT | + GPIO2C6_MASK << GPIO2C6_SHIFT, + GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT | + GPIO2C6_UART1_SIN << GPIO2C6_SHIFT); + break; + case PERIPH_ID_UART2: + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C3_MASK << GPIO1C3_SHIFT | + GPIO1C2_MASK << GPIO1C2_SHIFT, + GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | + GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); + break; + } +} + +static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, + GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT | + GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT | + GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT | + GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT | + GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT | + GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT | + GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | + GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A4_MASK << GPIO2A4_SHIFT | + GPIO2A1_MASK << GPIO2A1_SHIFT, + GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT | + GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio1c_iomux, 0xffff, + GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT | + GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT | + GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT | + GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT | + GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT | + GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT); + break; + } +} + +static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + pinctrl_rk3036_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + pinctrl_rk3036_i2c_config(priv->grf, func); + break; + case PERIPH_ID_SPI0: + pinctrl_rk3036_spi_config(priv->grf, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + pinctrl_rk3036_uart_config(priv->grf, func); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk3036_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3036_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 14: + return PERIPH_ID_SDCARD; + case 16: + return PERIPH_ID_EMMC; + case 20: + return PERIPH_ID_UART0; + case 21: + return PERIPH_ID_UART1; + case 22: + return PERIPH_ID_UART2; + case 23: + return PERIPH_ID_SPI0; + case 24: + return PERIPH_ID_I2C0; + case 25: + return PERIPH_ID_I2C1; + case 26: + return PERIPH_ID_I2C2; + case 30: + return PERIPH_ID_PWM0; + } + return -ENOENT; +} + +static int rk3036_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3036_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return rk3036_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk3036_pinctrl_ops = { + .set_state_simple = rk3036_pinctrl_set_state_simple, + .request = rk3036_pinctrl_request, + .get_periph_id = rk3036_pinctrl_get_periph_id, +}; + +static int rk3036_pinctrl_probe(struct udevice *dev) +{ + struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + return 0; +} + +static const struct udevice_id rk3036_pinctrl_ids[] = { + { .compatible = "rockchip,rk3036-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3036) = { + .name = "pinctrl_rk3036", + .id = UCLASS_PINCTRL, + .of_match = rk3036_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv), + .ops = &rk3036_pinctrl_ops, + .probe = rk3036_pinctrl_probe, +};

the data transfer seem to long in the dwmci_send_cmd function, so move this block as a separate funciton.

Signed-off-by: Lin Huang hl@rock-chips.com ---

drivers/mmc/dw_mmc.c | 65 ++++++++++++++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 28 deletions(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4375abc..bee8fab 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -94,6 +94,42 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); }

+static int dwmci_data_transfer(struct dwmci_host *host) +{ + int ret = 0; + unsigned int timeout = 240000; + u32 mask; + ulong start = get_timer(0); + + for (;;) { + mask = dwmci_readl(host, DWMCI_RINTSTS); + /* Error during data transfer. */ + if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { + debug("%s: DATA ERROR!\n", __func__); + ret = -EINVAL; + break; + } + + /* Data arrived correctly. */ + if (mask & DWMCI_INTMSK_DTO) { + ret = 0; + break; + } + + /* Check for timeout. */ + if (get_timer(start) > timeout) { + debug("%s: Timeout waiting for data!\n", + __func__); + ret = TIMEOUT; + break; + } + } + + dwmci_writel(host, DWMCI_RINTSTS, mask); + + return ret; +} + static int dwmci_set_transfer_mode(struct dwmci_host *host, struct mmc_data *data) { @@ -213,38 +249,11 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, }

if (data) { - start = get_timer(0); - timeout = 240000; - for (;;) { - mask = dwmci_readl(host, DWMCI_RINTSTS); - /* Error during data transfer. */ - if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { - debug("%s: DATA ERROR!\n", __func__); - ret = -EINVAL; - break; - } - - /* Data arrived correctly. */ - if (mask & DWMCI_INTMSK_DTO) { - ret = 0; - break; - } - - /* Check for timeout. */ - if (get_timer(start) > timeout) { - debug("%s: Timeout waiting for data!\n", - __func__); - ret = TIMEOUT; - break; - } - } - - dwmci_writel(host, DWMCI_RINTSTS, mask); + ret = dwmci_data_transfer(host);

ctrl = dwmci_readl(host, DWMCI_CTRL); ctrl &= ~(DWMCI_DMA_EN); dwmci_writel(host, DWMCI_CTRL, ctrl); - bounce_buffer_stop(&bbstate); }

some soc(rk3036 etc) use dw_mmc but do not have internal dma, so we implement fifo mode to read and write data.

Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: None Changes in v2: None Changes in v3: None Changes in v4: None Changes in v5: None Changes in v6: - move data fifo mode to dwmci_data_transfer() function

drivers/mmc/dw_mmc.c | 85 +++++++++++++++++++++++++++++++++++++++++----------- include/dwmmc.h | 5 ++++ 2 files changed, 72 insertions(+), 18 deletions(-)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index bee8fab..909e3ca 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -94,12 +94,21 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); }

-static int dwmci_data_transfer(struct dwmci_host *host) +static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) { int ret = 0; - unsigned int timeout = 240000; - u32 mask; + u32 timeout = 240000; + u32 mask, size, i, len = 0; + u32 *buf = NULL; ulong start = get_timer(0); + u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> + RX_WMARK_SHIFT) + 1) * 2; + + size = data->blocksize * data->blocks / 4; + if (data->flags == MMC_DATA_READ) + buf = (unsigned int *)data->dest; + else + buf = (unsigned int *)data->src;

for (;;) { mask = dwmci_readl(host, DWMCI_RINTSTS); @@ -110,6 +119,36 @@ static int dwmci_data_transfer(struct dwmci_host *host) break; }

+ if (host->fifo_mode && size) { + if (data->flags == MMC_DATA_READ) { + if ((dwmci_readl(host, DWMCI_RINTSTS) && + DWMCI_INTMSK_RXDR)) { + len = dwmci_readl(host, DWMCI_STATUS); + len = (len >> DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK; + for (i = 0; i < len; i++) + *buf++ = + dwmci_readl(host, DWMCI_DATA); + dwmci_writel(host, DWMCI_RINTSTS, + DWMCI_INTMSK_RXDR); + } + } else { + if ((dwmci_readl(host, DWMCI_RINTSTS) && + DWMCI_INTMSK_TXDR)) { + len = dwmci_readl(host, DWMCI_STATUS); + len = fifo_depth - ((len >> + DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK); + for (i = 0; i < len; i++) + dwmci_writel(host, DWMCI_DATA, + *buf++); + dwmci_writel(host, DWMCI_RINTSTS, + DWMCI_INTMSK_TXDR); + } + } + size = size > len ? (size - len) : 0; + } + /* Data arrived correctly. */ if (mask & DWMCI_INTMSK_DTO) { ret = 0; @@ -165,17 +204,24 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

if (data) { - if (data->flags == MMC_DATA_READ) { - bounce_buffer_start(&bbstate, (void*)data->dest, - data->blocksize * - data->blocks, GEN_BB_WRITE); + if (host->fifo_mode) { + dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); + dwmci_writel(host, DWMCI_BYTCNT, + data->blocksize * data->blocks); + dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); } else { - bounce_buffer_start(&bbstate, (void*)data->src, - data->blocksize * - data->blocks, GEN_BB_READ); + if (data->flags == MMC_DATA_READ) { + bounce_buffer_start(&bbstate, (void*)data->dest, + data->blocksize * + data->blocks, GEN_BB_WRITE); + } else { + bounce_buffer_start(&bbstate, (void*)data->src, + data->blocksize * + data->blocks, GEN_BB_READ); + } + dwmci_prepare_data(host, data, cur_idmac, + bbstate.bounce_buffer); } - dwmci_prepare_data(host, data, cur_idmac, - bbstate.bounce_buffer); }

dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); @@ -249,12 +295,15 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, }

if (data) { - ret = dwmci_data_transfer(host); - - ctrl = dwmci_readl(host, DWMCI_CTRL); - ctrl &= ~(DWMCI_DMA_EN); - dwmci_writel(host, DWMCI_CTRL, ctrl); - bounce_buffer_stop(&bbstate); + ret = dwmci_data_transfer(host, data); + + /* only dma mode need it */ + if (!host->fifo_mode) { + ctrl = dwmci_readl(host, DWMCI_CTRL); + ctrl &= ~(DWMCI_DMA_EN); + dwmci_writel(host, DWMCI_CTRL, ctrl); + bounce_buffer_stop(&bbstate); + } }

udelay(100); diff --git a/include/dwmmc.h b/include/dwmmc.h index 25cf42c..05b0817 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -105,6 +105,8 @@

/* Status Register */ #define DWMCI_BUSY (1 << 9) +#define DWMCI_FIFO_MASK 0x1ff +#define DWMCI_FIFO_SHIFT 17

/* FIFOTH Register */ #define MSIZE(x) ((x) << 28) @@ -180,6 +182,9 @@ struct dwmci_host { unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);

struct mmc_config cfg; + + /* use fifo mode to read and write data */ + bool fifo_mode; };

struct dwmci_idmac {

emmc and sdcard have different register address, use non-removeable property to disginuish them.

Signed-off-by: Lin Huang hl@rock-chips.com --- drivers/mmc/rockchip_dw_mmc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index f11c8e0..8502dfc 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -50,8 +50,10 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; host->priv = dev;

- /* TODO(sjg@chromium.org): Remove the need for this hack */ - host->dev_index = (ulong)host->ioaddr == 0xff0f0000 ? 0 : 1; + /* use non-removeable as sdcard and emmc as judgement */ + if (fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "non-removable") + == -FDT_ERR_NOTFOUND) + host->dev_index = 1;

return 0; }

rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver.

Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: None Changes in v2: None Changes in v3: None Changes in v4: None Changes in v5: None Changes in v6: - Advices by Simon: - use int instead of u32 for fifo_depth - use fdtdec_get_bool() to get "fifo-mode" property

arch/arm/dts/rk3036.dtsi | 1 + drivers/mmc/rockchip_dw_mmc.c | 21 +++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi index 0daae1e..ecf5416 100644 --- a/arch/arm/dts/rk3036.dtsi +++ b/arch/arm/dts/rk3036.dtsi @@ -257,6 +257,7 @@ cap-mmc-highspeed; mmc-ddr-1_8v; disable-wp; + fifo-mode; non-removable; num-slots = <1>; default-sample-phase = <158>; diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 8502dfc..4c523c0 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -65,6 +65,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev) struct dwmci_host *host = &priv->host; u32 minmax[2]; int ret; + int fifo_depth;

priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (IS_ERR(priv->grf)) @@ -73,10 +74,22 @@ static int rockchip_dwmmc_probe(struct udevice *dev) if (ret) return ret;

- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, - "clock-freq-min-max", minmax, 2); - if (!ret) - ret = add_dwmci(host, minmax[1], minmax[0]); + if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "clock-freq-min-max", minmax, 2)) + return -EINVAL; + + fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "fifo-depth", 0); + if (fifo_depth < 0) + return -EINVAL; + + host->fifoth_val = MSIZE(0x2) | + RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); + + if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode")) + host->fifo_mode = true; + + ret = add_dwmci(host, minmax[1], minmax[0]); if (ret) return ret;

add early uart driver so we can print debug message in SPL stage

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: None Changes in v2: None Changes in v3: - pass uart base address to rk_uart_init() function Changes in v4: None Changes in v5: None Changes in v6: - Adviced by Simon: - add some comment

arch/arm/include/asm/arch-rockchip/uart.h | 44 +++++++++++++++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk_early_print.c | 63 +++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h create mode 100644 arch/arm/mach-rockchip/rk_early_print.c

diff --git a/arch/arm/include/asm/arch-rockchip/uart.h b/arch/arm/include/asm/arch-rockchip/uart.h new file mode 100644 index 0000000..ea86ce6 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/uart.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_UART_H +#define __ASM_ARCH_UART_H +struct rk_uart { + unsigned int rbr; /* Receive buffer register. */ + unsigned int ier; /* Interrupt enable register. */ + unsigned int fcr; /* FIFO control register. */ + unsigned int lcr; /* Line control register. */ + unsigned int mcr; /* Modem control register. */ + unsigned int lsr; /* Line status register. */ + unsigned int msr; /* Modem status register. */ + unsigned int scr; + unsigned int reserved1[(0x30 - 0x20) / 4]; + unsigned int srbr[(0x70 - 0x30) / 4]; + unsigned int far; + unsigned int tfr; + unsigned int rfw; + unsigned int usr; + unsigned int tfl; + unsigned int rfl; + unsigned int srr; + unsigned int srts; + unsigned int sbcr; + unsigned int sdmam; + unsigned int sfe; + unsigned int srt; + unsigned int stet; + unsigned int htx; + unsigned int dmasa; + unsigned int reserver2[(0xf4 - 0xac) / 4]; + unsigned int cpr; + unsigned int ucv; + unsigned int ctr; +}; + +void rk_uart_init(void *base); +void print_hex(unsigned int n); +void print(char *s); +#endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 902235b..a29675d 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -10,5 +10,6 @@ else obj-y += board.o endif obj-y += rk_timer.o +obj-y += rk_early_print.o obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ diff --git a/arch/arm/mach-rockchip/rk_early_print.c b/arch/arm/mach-rockchip/rk_early_print.c new file mode 100644 index 0000000..a1c14b0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk_early_print.c @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch/uart.h> +#include <common.h> + +static struct rk_uart *uart_ptr; + +static void uart_wrtie_byte(char byte) +{ + writel(byte, &uart_ptr->rbr); + while (!(readl(&uart_ptr->lsr) & 0x40)) + ; +} + +void print(char *s) +{ + while (*s) { + if (*s == '\n') + uart_wrtie_byte('\r'); + uart_wrtie_byte(*s); + s++; + } +} + +void print_hex(unsigned int n) +{ + int i; + int temp; + + uart_wrtie_byte('0'); + uart_wrtie_byte('x'); + + for (i = 8; i > 0; i--) { + temp = (n >> (i - 1) * 4) & 0x0f; + if (temp < 10) + uart_wrtie_byte((char)(temp + '0')); + else + uart_wrtie_byte((char)(temp - 10 + 'a')); + } + uart_wrtie_byte('\n'); + uart_wrtie_byte('\r'); +} + +/* + * TODO: since rk3036 only 4K sram to use in SPL, for saving space, + * we implement uart driver this way, we should convert this to use + * ns16550 driver in future, which support DEBUG_UART in the standard way + */ +void rk_uart_init(void *base) +{ + uart_ptr = (struct rk_uart *)base; + writel(0x83, &uart_ptr->lcr); + writel(0x0d, &uart_ptr->rbr); + writel(0x03, &uart_ptr->lcr); + + /* fifo enable, sfe is shadow register of FCR[0] */ + writel(0x01, &uart_ptr->sfe); +}

add rk3036 sdram driver so we can set up sdram in SPL

Signed-off-by: Lin Huang hl@rock-chips.com --- Changes in v1: None Changes in v2: None Changes in v3: - fix some code style error Changes in v4: - modify code advice by Simon Glass Changes in v5: - Advice by Simon: - move some global variables to local variables - delete __weak get_ddr_config() function Changes in v6: - Adviced by Simon: - pass pointer to the function call - fix some nits

arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/mach-rockchip/rk3036/Makefile | 2 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 764 ++++++++++++++++++++++ 3 files changed, 1107 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3036.h create mode 100644 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h new file mode 100644 index 0000000..4ce2ba5 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h @@ -0,0 +1,341 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SDRAM_RK3036_H +#define _ASM_ARCH_SDRAM_RK3036_H + +#include <common.h> + +struct rk3036_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 reserved5[47]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[2]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[2]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[3]; + u32 dfilpcfg0; + u32 reserved13[3]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[46]; + u32 ipvr; + u32 iptr; +}; +check_member(rk3036_ddr_pctl, iptr, 0x03fc); + +struct rk3036_ddr_phy { + u32 ddrphy_reg1; + u32 ddrphy_reg3; + u32 ddrphy_reg2; + u32 reserve[11]; + u32 ddrphy_reg4a; + u32 ddrphy_reg4b; + u32 reserve1[5]; + u32 ddrphy_reg16; + u32 reserve2; + u32 ddrphy_reg18; + u32 ddrphy_reg19; + u32 reserve3; + u32 ddrphy_reg21; + u32 reserve4; + u32 ddrphy_reg22; + u32 reserve5[3]; + u32 ddrphy_reg25; + u32 ddrphy_reg26; + u32 ddrphy_reg27; + u32 ddrphy_reg28; + u32 reserve6[17]; + u32 ddrphy_reg6; + u32 ddrphy_reg7; + u32 reserve7; + u32 ddrphy_reg8; + u32 ddrphy_reg0e4; + u32 reserve8[11]; + u32 ddrphy_reg9; + u32 ddrphy_reg10; + u32 reserve9; + u32 ddrphy_reg11; + u32 ddrphy_reg124; + u32 reserve10[38]; + u32 ddrphy_reg29; + u32 reserve11[40]; + u32 ddrphy_reg264; + u32 reserve12[18]; + u32 ddrphy_reg2a; + u32 reserve13[4]; + u32 ddrphy_reg30; + u32 ddrphy_reg31; + u32 ddrphy_reg32; + u32 ddrphy_reg33; + u32 ddrphy_reg34; + u32 ddrphy_reg35; + u32 ddrphy_reg36; + u32 ddrphy_reg37; + u32 ddrphy_reg38; + u32 ddrphy_reg39; + u32 ddrphy_reg40; + u32 ddrphy_reg41; + u32 ddrphy_reg42; + u32 ddrphy_reg43; + u32 ddrphy_reg44; + u32 ddrphy_reg45; + u32 ddrphy_reg46; + u32 ddrphy_reg47; + u32 ddrphy_reg48; + u32 ddrphy_reg49; + u32 ddrphy_reg50; + u32 ddrphy_reg51; + u32 ddrphy_reg52; + u32 ddrphy_reg53; + u32 reserve14; + u32 ddrphy_reg54; + u32 ddrphy_reg55; + u32 ddrphy_reg56; + u32 ddrphy_reg57; + u32 ddrphy_reg58; + u32 ddrphy_reg59; + u32 ddrphy_reg5a; + u32 ddrphy_reg5b; + u32 ddrphy_reg5c; + u32 ddrphy_reg5d; + u32 ddrphy_reg5e; + u32 reserve15[28]; + u32 ddrphy_reg5f; + u32 reserve16[6]; + u32 ddrphy_reg60; + u32 ddrphy_reg61; + u32 ddrphy_reg62; +}; +check_member(rk3036_ddr_phy, ddrphy_reg62, 0x03e8); + +struct rk3036_pctl_timing { + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; +}; + +struct rk3036_phy_timing { + u32 mr[4]; + u32 bl; + u32 cl_al; +}; + +typedef union { + u32 noc_timing; + struct { + u32 acttoact:6; + u32 rdtomiss:6; + u32 wrtomiss:6; + u32 burstlen:3; + u32 rdtowr:5; + u32 wrtord:5; + u32 bwratio:1; + }; +} rk3036_noc_timing; + +struct rk3036_ddr_timing { + u32 freq; + struct rk3036_pctl_timing pctl_timing; + struct rk3036_phy_timing phy_timing; + rk3036_noc_timing noc_timing; +}; + +struct rk3036_service_sys { + u32 id_coreid; + u32 id_revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; +}; + +struct rk3036_ddr_config { + /* + * 000: lpddr + * 001: ddr + * 010: ddr2 + * 011: ddr3 + * 100: lpddr2-s2 + * 101: lpddr2-s4 + * 110: lpddr3 + */ + u32 ddr_type; + u32 rank; + u32 cs0_row; + u32 cs1_row; + + /* 2: 4bank, 3: 8bank */ + u32 bank; + u32 col; + + /* bw(0: 8bit, 1: 16bit, 2: 32bit) */ + u32 bw; +}; + +/* rk3036 sdram initial */ +void sdram_init(void); + +/* get ddr die config, implement in specific board */ +void get_ddr_config(struct rk3036_ddr_config *config); + +/* get ddr size on board */ +size_t sdram_size(void); +#endif diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 5d14b95..6095777 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -8,3 +8,5 @@ ifndef CONFIG_SPL_BUILD obj-y += reset_rk3036.o obj-y += syscon_rk3036.o endif + +obj-y += sdram_rk3036.o diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c new file mode 100644 index 0000000..7a05e31 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -0,0 +1,764 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <asm/types.h> +#include <asm/arch/cru_rk3036.h> +#include <asm/arch/grf_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sdram_rk3036.h> +#include <asm/arch/timer.h> +#include <asm/arch/uart.h> + +/* + * we can not fit the code to access the device tree in SPL + * (due to 4K SRAM size limits), so these are hard-coded + */ +#define CRU_BASE 0x20000000 +#define GRF_BASE 0x20008000 +#define DDR_PHY_BASE 0x2000a000 +#define DDR_PCTL_BASE 0x20004000 +#define CPU_AXI_BUS_BASE 0x10128000 + +struct rk3036_sdram_priv { + struct rk3036_cru *cru; + struct rk3036_grf *grf; + struct rk3036_ddr_phy *phy; + struct rk3036_ddr_pctl *pctl; + struct rk3036_service_sys *axi_bus; + + /* ddr die config */ + struct rk3036_ddr_config ddr_config; +}; + +/* use integer mode, 396MHz dpll setting + * refdiv, fbdiv, postdiv1, postdiv2 + */ +const struct pll_div dpll_init_cfg = {1, 66, 4, 1}; + +/* 396Mhz ddr timing */ +const struct rk3036_ddr_timing ddr_timing = {0x18c, + {0x18c, 0xc8, 0x1f4, 0x27, 0x4e, + 0x4, 0x8b, 0x06, 0x03, 0x0, 0x06, 0x05, 0x0f, 0x15, 0x06, 0x04, 0x04, + 0x06, 0x04, 0x200, 0x03, 0x0a, 0x40, 0x2710, 0x01, 0x05, 0x05, 0x03, + 0x0c, 0x28, 0x100, 0x0, 0x04, 0x0}, + {{0x420, 0x42, 0x0, 0x0}, 0x01, 0x60}, + {0x24717315} }; + +/* + * [7:6] bank(n:n bit bank) + * [5:4] row(13+n) + * [3] cs(0:1 cs, 1:2 cs) + * [2:1] bank(n:n bit bank) + * [0] col(10+n) + */ +const char ddr_cfg_2_rbc[] = { + ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 1), + ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 0), + ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 0), + ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 0), + ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 1), + ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 1), + ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 1), + ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 0), + ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 1), + ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 0), + ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 1), + ((1 << 6) | (2 << 4) | (0 << 3) | (2 << 1) | 0), + ((3 << 6) | (2 << 4) | (0 << 3) | (0 << 1) | 1), + ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 0), +}; + +/* DDRPHY REG */ +enum { + /* DDRPHY_REG1 */ + SOFT_RESET_MASK = 3, + SOFT_RESET_SHIFT = 2, + + /* DDRPHY_REG2 */ + MEMORY_SELECT_DDR3 = 0 << 6, + DQS_SQU_CAL_NORMAL_MODE = 0 << 1, + DQS_SQU_CAL_START = 1 << 0, + DQS_SQU_NO_CAL = 0 << 0, + + /* DDRPHY_REG2A */ + CMD_DLL_BYPASS = 1 << 4, + CMD_DLL_BYPASS_DISABLE = 0 << 4, + HIGH_8BIT_DLL_BYPASS = 1 << 3, + HIGH_8BIT_DLL_BYPASS_DISABLE = 0 << 3, + LOW_8BIT_DLL_BYPASS = 1 << 2, + LOW_8BIT_DLL_BYPASS_DISABLE = 0 << 2, + + /* DDRPHY_REG19 */ + CMD_FEEDBACK_ENABLE = 1 << 5, + CMD_SLAVE_DLL_INVERSE_MODE = 1 << 4, + CMD_SLAVE_DLL_NO_INVERSE_MODE = 0 << 4, + CMD_SLAVE_DLL_ENALBE = 1 << 3, + CMD_TX_SLAVE_DLL_DELAY_MASK = 7, + CMD_TX_SLAVE_DLL_DELAY_SHIFT = 0, + + /* DDRPHY_REG6 */ + LEFT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4, + LEFT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4, + LEFT_CHN_TX_DQ_DLL_ENABLE = 1 << 3, + LEFT_CHN_TX_DQ_DLL_DELAY_MASK = 7, + LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0, + + /* DDRPHY_REG8 */ + LEFT_CHN_RX_DQS_DELAY_TAP_MASK = 3, + LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0, + + /* DDRPHY_REG9 */ + RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4, + RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4, + RIGHT_CHN_TX_DQ_DLL_ENABLE = 1 << 3, + RIGHT_CHN_TX_DQ_DLL_DELAY_MASK = 7, + RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0, + + /* DDRPHY_REG11 */ + RIGHT_CHN_RX_DQS_DELAY_TAP_MASK = 3, + RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0, + + /* DDRPHY_REG62 */ + CAL_DONE_MASK = 3, + HIGH_8BIT_CAL_DONE = 1 << 1, + LOW_8BIT_CAL_DONE = 1 << 0, +}; + +/* PTCL */ +enum { + /* PCTL_DFISTCFG0 */ + DFI_INIT_START = 1 << 0, + DFI_DATA_BYTE_DISABLE_EN = 1 << 2, + + /* PCTL_DFISTCFG1 */ + DFI_DRAM_CLK_SR_EN = 1 << 0, + DFI_DRAM_CLK_DPD_EN = 1 << 1, + + /* PCTL_DFISTCFG2 */ + DFI_PARITY_INTR_EN = 1 << 0, + DFI_PARITY_EN = 1 << 1, + + /* PCTL_DFILPCFG0 */ + TLP_RESP_TIME_SHIFT = 16, + LP_SR_EN = 1 << 8, + LP_PD_EN = 1 << 0, + + /* PCTL_DFIODTCFG */ + RANK0_ODT_WRITE_SEL = 1 << 3, + RANK1_ODT_WRITE_SEL = 1 << 11, + + /* PCTL_DFIODTCFG1 */ + ODT_LEN_BL8_W_SHIFT = 16, + + /* PCTL_MCFG */ + TFAW_CFG_MASK = 3, + TFAW_CFG_SHIFT = 18, + PD_EXIT_SLOW_MODE = 0 << 17, + PD_ACTIVE_POWER_DOWN = 1 << 16, + PD_IDLE_MASK = 0xff, + PD_IDLE_SHIFT = 8, + MEM_BL4 = 0 << 0, + MEM_BL8 = 1 << 0, + + /* PCTL_MCFG1 */ + HW_EXIT_IDLE_EN_MASK = 1, + HW_EXIT_IDLE_EN_SHIFT = 31, + SR_IDLE_MASK = 0x1ff, + SR_IDLE_SHIFT = 0, + + /* PCTL_SCFG */ + HW_LOW_POWER_EN = 1 << 0, + + /* PCTL_POWCTL */ + POWER_UP_START = 1 << 0, + + /* PCTL_POWSTAT */ + POWER_UP_DONE = 1 << 0, + + /* PCTL_MCMD */ + START_CMD = 1 << 31, + BANK_ADDR_MASK = 7, + BANK_ADDR_SHIFT = 17, + CMD_ADDR_MASK = 0x1fff, + CMD_ADDR_SHIFT = 4, + DESELECT_CMD = 0, + PREA_CMD, + REF_CMD, + MRS_CMD, + ZQCS_CMD, + ZQCL_CMD, + RSTL_CMD, + MRR_CMD = 8, + + /* PCTL_STAT */ + INIT_MEM = 0, + CONFIG, + CONFIG_REQ, + ACCESS, + ACCESS_REQ, + LOW_POWER, + LOW_POWER_ENTRY_REQ, + LOW_POWER_EXIT_REQ, + PCTL_STAT_MASK = 7, + + /* PCTL_SCTL */ + INIT_STATE = 0, + CFG_STATE = 1, + GO_STATE = 2, + SLEEP_STATE = 3, + WAKEUP_STATE = 4, +}; + +/* GRF_SOC_CON2 */ +#define MSCH4_MAINDDR3 (1 << 7) +#define PHY_DRV_ODT_SET(n) ((n << 4) | n) +#define DDR3_DLL_RESET (1 << 8) + +/* CK pull up/down driver strength control */ +enum { + PHY_RON_DISABLE = 0, + PHY_RON_309OHM = 1, + PHY_RON_155OHM, + PHY_RON_103OHM = 3, + PHY_RON_63OHM = 5, + PHY_RON_45OHM = 7, + PHY_RON_77OHM, + PHY_RON_62OHM, + PHY_RON_52OHM, + PHY_RON_44OHM, + PHY_RON_39OHM, + PHY_RON_34OHM, + PHY_RON_31OHM, + PHY_RON_28OHM, +}; + +/* DQ pull up/down control */ +enum { + PHY_RTT_DISABLE = 0, + PHY_RTT_861OHM = 1, + PHY_RTT_431OHM, + PHY_RTT_287OHM, + PHY_RTT_216OHM, + PHY_RTT_172OHM, + PHY_RTT_145OHM, + PHY_RTT_124OHM, + PHY_RTT_215OHM, + PHY_RTT_144OHM = 0xa, + PHY_RTT_123OHM, + PHY_RTT_108OHM, + PHY_RTT_96OHM, + PHY_RTT_86OHM, + PHY_RTT_78OHM, +}; + +/* DQS squelch DLL delay */ +enum { + DQS_DLL_NO_DELAY = 0, + DQS_DLL_22P5_DELAY, + DQS_DLL_45_DELAY, + DQS_DLL_67P5_DELAY, + DQS_DLL_90_DELAY, + DQS_DLL_112P5_DELAY, + DQS_DLL_135_DELAY, + DQS_DLL_157P5_DELAY, +}; + +/* GRF_OS_REG1 */ +enum { + /* + * 000: lpddr + * 001: ddr + * 010: ddr2 + * 011: ddr3 + * 100: lpddr2-s2 + * 101: lpddr2-s4 + * 110: lpddr3 + */ + DDR_TYPE_MASK = 7, + DDR_TYPE_SHIFT = 13, + + /* 0: 1 chn, 1: 2 chn */ + DDR_CHN_CNT_SHIFT = 12, + + /* 0: 1 rank, 1: 2 rank */ + DDR_RANK_CNT_MASK = 1, + DDR_RANK_CNT_SHIFT = 11, + + /* + * 00: 9col + * 01: 10col + * 10: 11col + * 11: 12col + */ + DDR_COL_MASK = 3, + DDR_COL_SHIFT = 9, + + /* 0: 8 bank, 1: 4 bank*/ + DDR_BANK_MASK = 1, + DDR_BANK_SHIFT = 8, + + /* + * 00: 13 row + * 01: 14 row + * 10: 15 row + * 11: 16 row + */ + DDR_CS0_ROW_MASK = 3, + DDR_CS0_ROW_SHIFT = 6, + DDR_CS1_ROW_MASK = 3, + DDR_CS1_ROW_SHIFT = 4, + + /* + * 00: 32 bit + * 01: 16 bit + * 10: 8 bit + * rk3036 only support 16bit + */ + DDR_BW_MASK = 3, + DDR_BW_SHIFT = 2, + DDR_DIE_BW_MASK = 3, + DDR_DIE_BW_SHIFT = 0, +}; + +static void rkdclk_init(struct rk3036_sdram_priv *priv) +{ + struct rk3036_pll *pll = &priv->cru->pll[1]; + + /* pll enter slow-mode */ + rk_clrsetreg(&priv->cru->cru_mode_con, + DPLL_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW << DPLL_MODE_SHIFT); + + /* use integer mode */ + rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + + rk_clrsetreg(&pll->con0, + PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | + dpll_init_cfg.fbdiv); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | + PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, + (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | + dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); + + /* waiting for pll lock */ + while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) + rockchip_udelay(1); + + /* PLL enter normal-mode */ + rk_clrsetreg(&priv->cru->cru_mode_con, + DPLL_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_NORM << DPLL_MODE_SHIFT); +} + +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +void phy_pctrl_reset(struct rk3036_sdram_priv *priv) +{ + struct rk3036_ddr_phy *ddr_phy = priv->phy; + + rk_clrsetreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | + 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | + 1 << DDRPHY_SRST_SHIFT, + 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | + 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); + + rockchip_udelay(10); + + rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | + 1 << DDRPHY_SRST_SHIFT); + rockchip_udelay(10); + + rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | + 1 << DDRCTRL_SRST_SHIFT); + rockchip_udelay(10); + + clrsetbits_le32(&ddr_phy->ddrphy_reg1, + SOFT_RESET_MASK << SOFT_RESET_SHIFT, + 0 << SOFT_RESET_SHIFT); + rockchip_udelay(10); + clrsetbits_le32(&ddr_phy->ddrphy_reg1, + SOFT_RESET_MASK << SOFT_RESET_SHIFT, + 3 << SOFT_RESET_SHIFT); + + rockchip_udelay(1); +} + +void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq) +{ + struct rk3036_ddr_phy *ddr_phy = priv->phy; + + if (freq < ddr_timing.freq) { + writel(CMD_DLL_BYPASS | HIGH_8BIT_DLL_BYPASS | + LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a); + + writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_90 | + LEFT_CHN_TX_DQ_DLL_ENABLE | + (0 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) << + LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6); + + writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 | + RIGHT_CHN_TX_DQ_DLL_ENABLE | + (0 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) << + RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT, + &ddr_phy->ddrphy_reg9); + } else { + writel(CMD_DLL_BYPASS_DISABLE | HIGH_8BIT_DLL_BYPASS_DISABLE | + LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a); + + writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_0 | + LEFT_CHN_TX_DQ_DLL_ENABLE | + (4 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) << + LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, + &ddr_phy->ddrphy_reg6); + + writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 | + RIGHT_CHN_TX_DQ_DLL_ENABLE | + (4 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) << + RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT, + &ddr_phy->ddrphy_reg9); + } + + writel(CMD_SLAVE_DLL_NO_INVERSE_MODE | CMD_SLAVE_DLL_ENALBE | + (0 & CMD_TX_SLAVE_DLL_DELAY_MASK) << + CMD_TX_SLAVE_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg19); + + /* 45 degree delay */ + writel((DQS_DLL_45_DELAY & LEFT_CHN_RX_DQS_DELAY_TAP_MASK) << + LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg8); + writel((DQS_DLL_45_DELAY & RIGHT_CHN_RX_DQS_DELAY_TAP_MASK) << + RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg11); +} + +static void send_command(struct rk3036_ddr_pctl *pctl, + u32 rank, u32 cmd, u32 arg) +{ + writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); + rockchip_udelay(1); + while (readl(&pctl->mcmd) & START_CMD) + ; +} + +static void memory_init(struct rk3036_sdram_priv *priv) +{ + struct rk3036_ddr_pctl *pctl = priv->pctl; + + send_command(pctl, 3, DESELECT_CMD, 0); + rockchip_udelay(1); + send_command(pctl, 3, PREA_CMD, 0); + send_command(pctl, 3, MRS_CMD, + (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT); + + send_command(pctl, 3, MRS_CMD, + (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT); + + send_command(pctl, 3, MRS_CMD, + (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT); + + send_command(pctl, 3, MRS_CMD, + (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | + (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << + CMD_ADDR_SHIFT | DDR3_DLL_RESET); + + send_command(pctl, 3, ZQCL_CMD, 0); +} + +static void data_training(struct rk3036_sdram_priv *priv) +{ + struct rk3036_ddr_phy *ddr_phy = priv->phy; + struct rk3036_ddr_pctl *pctl = priv->pctl; + u32 value; + + /* disable auto refresh */ + value = readl(&pctl->trefi), + writel(0, &pctl->trefi); + + clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, + DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START); + + rockchip_udelay(1); + while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) != + (HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) { + ; + } + + clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, + DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_NO_CAL); + + /* + * since data training will take about 20us, so send some auto + * refresh(about 7.8us) to complement the lost time + */ + send_command(pctl, 3, REF_CMD, 0); + send_command(pctl, 3, REF_CMD, 0); + send_command(pctl, 3, REF_CMD, 0); + + writel(value, &pctl->trefi); +} + +static void move_to_config_state(struct rk3036_sdram_priv *priv) +{ + unsigned int state; + struct rk3036_ddr_pctl *pctl = priv->pctl; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MASK; + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) + != ACCESS) + ; + /* + * If at low power state, need wakeup first, and then + * enter the config, so fallthrough + */ + case ACCESS: + /* fallthrough */ + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) + ; + break; + case CONFIG: + return; + default: + break; + } + } +} + +static void move_to_access_state(struct rk3036_sdram_priv *priv) +{ + unsigned int state; + struct rk3036_ddr_pctl *pctl = priv->pctl; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MASK; + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) + ; + break; + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) + ; + /* fallthrough */ + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) + ; + break; + case ACCESS: + return; + default: + break; + } + } +} + +static void pctl_cfg(struct rk3036_sdram_priv *priv) +{ + struct rk3036_ddr_pctl *pctl = priv->pctl; + u32 burst_len; + u32 reg; + + writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, + &pctl->dfilpcfg0); + + writel(1, &pctl->dfitphyupdtype0); + writel(0x0d, &pctl->dfitphyrdlat); + + /* cs0 and cs1 write odt enable */ + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), + &pctl->dfiodtcfg); + + /* odt write length */ + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); + + /* phyupd and ctrlupd disabled */ + writel(0, &pctl->dfiupdcfg); + + if ((ddr_timing.noc_timing.burstlen << 1) == 4) + burst_len = MEM_BL4; + else + burst_len = MEM_BL8; + + copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, + sizeof(struct rk3036_pctl_timing)); + reg = readl(&pctl->tcl); + writel(reg - 3, &pctl->dfitrddataen); + reg = readl(&pctl->tcwl); + writel(reg - 1, &pctl->dfitphywrlat); + + writel(burst_len | (1 & TFAW_CFG_MASK) << TFAW_CFG_SHIFT | + PD_EXIT_SLOW_MODE | PD_ACTIVE_POWER_DOWN | + (0 & PD_IDLE_MASK) << PD_IDLE_SHIFT, + &pctl->mcfg); + + writel(RK_SETBITS(MSCH4_MAINDDR3), &priv->grf->soc_con2); + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); +} + +static void phy_cfg(struct rk3036_sdram_priv *priv) +{ + struct rk3036_ddr_phy *ddr_phy = priv->phy; + struct rk3036_service_sys *axi_bus = priv->axi_bus; + + writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); + writel(0x3f, &axi_bus->readlatency); + + writel(MEMORY_SELECT_DDR3 | DQS_SQU_CAL_NORMAL_MODE, + &ddr_phy->ddrphy_reg2); + + clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl); + writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); + writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg16); + writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg22); + writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg25); + writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg26); + writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg27); + writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg28); +} + +void dram_cfg_rbc(struct rk3036_sdram_priv *priv) +{ + char noc_config; + int i = 0; + struct rk3036_ddr_config config = priv->ddr_config; + struct rk3036_service_sys *axi_bus = priv->axi_bus; + + move_to_config_state(priv); + + /* 2bit in BIT1, 2 */ + if (config.rank == 2) { + noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | + 1 << 3 | (config.col - 10); + if (noc_config == ddr_cfg_2_rbc[9]) { + i = 9; + goto finish; + } else if (noc_config == ddr_cfg_2_rbc[10]) { + i = 10; + goto finish; + } + } + + noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | + (config.col - 10); + + for (i = 0; i < sizeof(ddr_cfg_2_rbc); i++) { + if (noc_config == ddr_cfg_2_rbc[i]) + goto finish; + } + + /* bank: 1 bit in BIT6,7, 1bit in BIT1, 2 */ + noc_config = 1 << 6 | (config.cs0_row - 13) << 4 | + 2 << 1 | (config.col - 10); + if (noc_config == ddr_cfg_2_rbc[11]) { + i = 11; + goto finish; + } + + /* bank: 2bit in BIT6,7 */ + noc_config = (config.bank << 6) | (config.cs0_row - 13) << 4 | + (config.col - 10); + + if (noc_config == ddr_cfg_2_rbc[0]) + i = 0; + else if (noc_config == ddr_cfg_2_rbc[12]) + i = 12; + else if (noc_config == ddr_cfg_2_rbc[13]) + i = 13; +finish: + writel(i, &axi_bus->ddrconf); + move_to_access_state(priv); +} + +static void sdram_all_config(struct rk3036_sdram_priv *priv) +{ + u32 os_reg = 0; + struct rk3036_ddr_config config = priv->ddr_config; + + os_reg = config.ddr_type << DDR_TYPE_SHIFT | + 0 << DDR_CHN_CNT_SHIFT | + (config.rank - 1) << DDR_RANK_CNT_SHIFT | + (config.col - 1) << DDR_COL_SHIFT | + (config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT | + (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT | + (config.cs1_row - 13) << DDR_CS1_ROW_SHIFT | + 1 << DDR_BW_SHIFT | config.bw << DDR_DIE_BW_SHIFT; + writel(os_reg, &priv->grf->os_reg[1]); +} + +size_t sdram_size(void) +{ + u32 size, os_reg, cs0_row, cs1_row, col, bank, rank; + struct rk3036_grf *grf = (void *)GRF_BASE; + + os_reg = readl(&grf->os_reg[1]); + + cs0_row = 13 + ((os_reg >> DDR_CS0_ROW_SHIFT) & DDR_CS0_ROW_MASK); + cs1_row = 13 + ((os_reg >> DDR_CS1_ROW_SHIFT) & DDR_CS1_ROW_MASK); + col = 9 + ((os_reg >> DDR_COL_SHIFT) & DDR_COL_MASK); + bank = 3 - ((os_reg >> DDR_BANK_SHIFT) & DDR_BANK_MASK); + rank = 1 + ((os_reg >> DDR_RANK_CNT_SHIFT) & DDR_RANK_CNT_MASK); + + /* row + col + bank + bw(rk3036 only support 16bit, so fix in 1) */ + size = 1 << (cs0_row + col + bank + 1); + + if (rank > 1) + size += size >> (cs0_row - cs1_row); + + return size; +} + +void sdram_init(void) +{ + struct rk3036_sdram_priv sdram_priv; + + sdram_priv.cru = (void *)CRU_BASE; + sdram_priv.grf = (void *)GRF_BASE; + sdram_priv.phy = (void *)DDR_PHY_BASE; + sdram_priv.pctl = (void *)DDR_PCTL_BASE; + sdram_priv.axi_bus = (void *)CPU_AXI_BUS_BASE; + + get_ddr_config(&sdram_priv.ddr_config); + sdram_all_config(&sdram_priv); + rkdclk_init(&sdram_priv); + phy_pctrl_reset(&sdram_priv); + phy_dll_bypass_set(&sdram_priv, ddr_timing.freq); + pctl_cfg(&sdram_priv); + phy_cfg(&sdram_priv); + writel(POWER_UP_START, &sdram_priv.pctl->powctl); + while (!(readl(&sdram_priv.pctl->powstat) & POWER_UP_DONE)) + ; + memory_init(&sdram_priv); + move_to_config_state(&sdram_priv); + data_training(&sdram_priv); + move_to_access_state(&sdram_priv); + dram_cfg_rbc(&sdram_priv); +}

rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart.

Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: - clean copyright announcement Changes in v2: - support SPL Changes in v3: - delete DEBUG_UART config - modify ENV_MEM_LAYOUT_SETTINGS config Changes in v4: - delete some unuse config advice by Sjoerd Simons Changes in v5: - use CONFIG_DWMMC Changes in v6: - Adviced by Simon: - fix some nits

arch/arm/mach-rockchip/Kconfig | 10 ++- arch/arm/mach-rockchip/Makefile | 4 +- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 +++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 17 ++++ arch/arm/mach-rockchip/rk3036/Makefile | 1 + arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 ++++++++ include/configs/rk3036_common.h | 103 ++++++++++++++++++++++++ 8 files changed, 221 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 include/configs/rk3036_common.h

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index da665ef..6b608db 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -9,6 +9,14 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.

+config ROCKCHIP_RK3036 + bool "Support Rockchip RK3036" + help + The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config SYS_MALLOC_F default y

@@ -34,5 +42,5 @@ config ROCKCHIP_SERIAL default y

source "arch/arm/mach-rockchip/rk3288/Kconfig" - +source "arch/arm/mach-rockchip/rk3036/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index a29675d..b703c3c 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -6,10 +6,12 @@

ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o else -obj-y += board.o +obj-$(CONFIG_ROCKCHIP_RK3288) += board.o endif obj-y += rk_timer.o obj-y += rk_early_print.o obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 688bc0f..f026abf 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> #include <ram.h> +#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c new file mode 100644 index 0000000..3a1491c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/grf_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sdram_rk3036.h> +#include <asm/arch/timer.h> +#include <asm/arch/uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GRF_BASE 0x20008000 +static struct rk3036_grf * const grf = (void *)GRF_BASE; + +#define DEBUG_UART_BASE 0x20068000 + +extern void back_to_bootrom(void); + +void board_init_f(ulong dummy) +{ +#ifdef EARLY_DEBUG + /* + * NOTE: sd card and debug uart use same iomux in rk3036, + * so if you enable uart, + * you can not boot from sdcard + */ + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C3_MASK << GPIO1C3_SHIFT | + GPIO1C2_MASK << GPIO1C2_SHIFT, + GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | + GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); + rk_uart_init((void *)DEBUG_UART_BASE); +#endif + rockchip_timer_init(); + sdram_init(); + + /* return to maskrom */ + back_to_bootrom(); +} + +/* Place Holders */ +void board_init_r(gd_t *id, ulong dest_addr) +{ + /* + * Function attribute is no-return + * This Function never executes + */ + while (1) + ; +} diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig new file mode 100644 index 0000000..0fbc58e --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -0,0 +1,17 @@ +if ROCKCHIP_RK3036 + +config TARGET_EVB_RK3036 + bool "EVB_RK3036" + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x400 + +config ROCKCHIP_COMMON + bool "Support rk common fuction" + +source "board/evb_rk3036/evb_rk3036/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 6095777..97d299d 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -10,3 +10,4 @@ obj-y += syscon_rk3036.o endif

obj-y += sdram_rk3036.o +obj-y += save_boot_param.o diff --git a/arch/arm/mach-rockchip/rk3036/save_boot_param.S b/arch/arm/mach-rockchip/rk3036/save_boot_param.S new file mode 100644 index 0000000..778ec83 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/save_boot_param.S @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +.globl SAVE_SP_ADDR +SAVE_SP_ADDR: + .word 0 + +/* + * void save_boot_params + * + * Save sp, lr, r1~r12 + */ +ENTRY(save_boot_params) + push {r1-r12, lr} + ldr r0, =SAVE_SP_ADDR + str sp, [r0] + b save_boot_params_ret @ back to my caller +ENDPROC(save_boot_params) + + +.globl back_to_bootrom +ENTRY(back_to_bootrom) + ldr r0, =SAVE_SP_ADDR + ldr sp, [r0] + mov r0, #0 + pop {r1-r12, pc} +ENDPROC(back_to_bootrom) diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h new file mode 100644 index 0000000..525fabc --- /dev/null +++ b/include/configs/rk3036_common.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_RK3036_COMMON_H +#define __CONFIG_RK3036_COMMON_H + +#include <asm/arch/hardware.h> + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_MEM32 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 +#define CONFIG_SPL_STACK 0x10081fff +#define CONFIG_SPL_TEXT_BASE 0x10081004 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK30" + +#define CONFIG_ROCKCHIP_COMMON + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SDHCI +#define CONFIG_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_TIME + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE (512UL << 20UL) + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#define CONFIG_CMD_I2C + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +/* First try to boot from SD (index 0), then eMMC (index 1 */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include <config_distro_bootcmd.h> + +/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x7fffffff\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#endif

From: Jeffy Chen jeffy.chen@rock-chips.com

Our chips may have different max spl size and spl header, so we need to add configs for that.

Signed-off-by: Jeffy Chen jeffy.chen@rock-chips.com Acked-by: Simon Glass sjg@chromium.org --- Changes in v1: None Changes in v2: None Changes in v3: None Changes in v4: None Changes in v5: - Adviced by Simon: - move CONFIG_ROCKCHIP_MAX_INIT_SIZE and CONFIG_ROCKCHIP_CHIP_TAG - to arch/arm/mach-rokchip/Kconfig Changes in v6: - Adviced by Simon: - Kconfig more descriptive with more detail

arch/arm/mach-rockchip/Kconfig | 15 +++++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 6 ++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 6 ++++++ include/configs/rk3288_common.h | 2 ++ tools/Makefile | 6 ++++++ tools/rkcommon.c | 2 +- tools/rkcommon.h | 1 - tools/rkimage.c | 2 +- tools/rksd.c | 4 ++-- tools/rkspi.c | 4 ++-- 10 files changed, 41 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6b608db..4848018 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -17,6 +17,21 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.

+config ROCKCHIP_SPL_HDR + string "Header of rockchip's spl loader" + help + Rockchip's bootrom requires the spl loader to start with a 4-bytes + header. The content of this header depends on the chip type. + +config ROCKCHIP_MAX_SPL_SIZE + hex "Max size of rockchip's spl loader" + help + Different chip may have different sram size. And if we want to jump + back to the bootrom after spl, we may need to reserve some sram space + for the bootrom. + The max spl loader size should be sram size minus reserved + size(if needed) + config SYS_MALLOC_F default y

diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index 0fbc58e..95fb2b9 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -9,6 +9,12 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400

+config ROCKCHIP_SPL_HDR + default "RK30" + +config ROCKCHIP_MAX_SPL_SIZE + default 0x1000 + config ROCKCHIP_COMMON bool "Support rk common fuction"

diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index d0a7276..3de3878 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -16,6 +16,12 @@ config TARGET_CHROMEBOOK_JERRY WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions.

+config ROCKCHIP_SPL_HDR + default "RK32" + +config ROCKCHIP_MAX_SPL_SIZE + default 0x8000 + config SYS_SOC default "rockchip"

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 5ba084d..1790e91 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -44,6 +44,8 @@ #define CONFIG_SPL_STACK 0xff718000 #define CONFIG_SPL_TEXT_BASE 0xff704004

+ +#define CONFIG_ROCKCHIP_MAX_SPL_SIZE (32 << 10) #define CONFIG_ROCKCHIP_COMMON #define CONFIG_SPL_ROCKCHIP_COMMON

diff --git a/tools/Makefile b/tools/Makefile index 9082bda..2e256d6 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -108,6 +108,12 @@ fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o

# TODO(sjg@chromium.org): Is this correct on Mac OS?

+ifneq ($(CONFIG_ARCH_ROCKCHIP),) +HOST_EXTRACFLAGS += \ + -DCONFIG_ROCKCHIP_MAX_SPL_SIZE=$(CONFIG_ROCKCHIP_MAX_SPL_SIZE) \ + -DCONFIG_ROCKCHIP_SPL_HDR=""$(CONFIG_ROCKCHIP_SPL_HDR)"" +endif + ifneq ($(CONFIG_MX23)$(CONFIG_MX28),) # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c . diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 4389622..18778aa 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -50,7 +50,7 @@ int rkcommon_set_header(void *buf, uint file_size) { struct header0_info *hdr;

- if (file_size > RK_MAX_CODE1_SIZE) + if (file_size > CONFIG_ROCKCHIP_MAX_SPL_SIZE) return -ENOSPC;

memset(buf, '\0', RK_CODE1_OFFSET * RK_BLK_SIZE); diff --git a/tools/rkcommon.h b/tools/rkcommon.h index 57fd726..39b1d52 100644 --- a/tools/rkcommon.h +++ b/tools/rkcommon.h @@ -11,7 +11,6 @@ enum { RK_BLK_SIZE = 512, RK_CODE1_OFFSET = 4, - RK_MAX_CODE1_SIZE = 32 << 10, };

/** diff --git a/tools/rkimage.c b/tools/rkimage.c index 7b292f4..73634e3 100644 --- a/tools/rkimage.c +++ b/tools/rkimage.c @@ -30,7 +30,7 @@ static void rkimage_print_header(const void *buf) static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd, struct image_tool_params *params) { - memcpy(buf, "RK32", 4); + memcpy(buf, CONFIG_ROCKCHIP_SPL_HDR, 4); }

static int rkimage_extract_subimage(void *buf, struct image_tool_params *params) diff --git a/tools/rksd.c b/tools/rksd.c index a8dbe98..30b149d 100644 --- a/tools/rksd.c +++ b/tools/rksd.c @@ -50,7 +50,7 @@ static void rksd_set_header(void *buf, struct stat *sbuf, int ifd, size); }

- memcpy(buf + RKSD_SPL_HDR_START, "RK32", 4); + memcpy(buf + RKSD_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4); }

static int rksd_extract_subimage(void *buf, struct image_tool_params *params) @@ -72,7 +72,7 @@ static int rksd_vrec_header(struct image_tool_params *params, { int pad_size;

- pad_size = RKSD_SPL_HDR_START + RK_MAX_CODE1_SIZE; + pad_size = RKSD_SPL_HDR_START + CONFIG_ROCKCHIP_MAX_SPL_SIZE; debug("pad_size %x\n", pad_size);

return pad_size - params->file_size; diff --git a/tools/rkspi.c b/tools/rkspi.c index a3c4c73..13cc593 100644 --- a/tools/rkspi.c +++ b/tools/rkspi.c @@ -53,7 +53,7 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, size); }

- memcpy(buf + RKSPI_SPL_HDR_START, "RK32", 4); + memcpy(buf + RKSPI_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4);

/* * Spread the image out so we only use the first 2KB of each 4KB @@ -89,7 +89,7 @@ static int rkspi_vrec_header(struct image_tool_params *params, { int pad_size;

- pad_size = (RK_MAX_CODE1_SIZE + 0x7ff) / 0x800 * 0x800; + pad_size = (CONFIG_ROCKCHIP_MAX_SPL_SIZE + 0x7ff) / 0x800 * 0x800; params->orig_file_size = pad_size;

/* We will double the image size due to the SPI format */