From: Konstantin Porotchkin kostap@marvell.com

Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image.

Signed-off-by: Konstantin Porotchkin kostap@marvell.com Cc: Stefan Roese sr@denx.de Cc: Nadav Haklai nadavh@marvell.com Cc: Neta Zur Hershkovits neta@marvell.com Cc: Omri Itach omrii@marvell.com Cc: Igal Liberman igall@marvell.com Cc: Haim Boot hayim@marvell.com Cc: Hanna Hawa hannah@marvell.com --- arch/arm/include/asm/arch-armada8k/cache_llc.h | 21 ++++++++++++++ arch/arm/mach-mvebu/armada8k/Makefile | 1 + arch/arm/mach-mvebu/armada8k/cache_llc.S | 39 ++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 arch/arm/include/asm/arch-armada8k/cache_llc.h create mode 100644 arch/arm/mach-mvebu/armada8k/cache_llc.S

diff --git a/arch/arm/include/asm/arch-armada8k/cache_llc.h b/arch/arm/include/asm/arch-armada8k/cache_llc.h new file mode 100644 index 0000000..8f97e6d --- /dev/null +++ b/arch/arm/include/asm/arch-armada8k/cache_llc.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#ifndef _CACHE_LLC_H_ +#define _CACHE_LLC_H_ + +/* Armada-7K/8K last level cache */ + +#define MVEBU_A8K_REGS_BASE_MSB 0xf000 +#define LLC_BASE_ADDR 0x8000 +#define LLC_CACHE_SYNC 0x700 +#define LLC_CACHE_SYNC_COMPLETE 0x730 +#define LLC_FLUSH_BY_WAY 0x7fc +#define LLC_WAY_MASK 0xffffffff +#define LLC_CACHE_SYNC_MASK 0x1 + +#endif /* _CACHE_LLC_H_ */ diff --git a/arch/arm/mach-mvebu/armada8k/Makefile b/arch/arm/mach-mvebu/armada8k/Makefile index 84c69d9..0facf14 100644 --- a/arch/arm/mach-mvebu/armada8k/Makefile +++ b/arch/arm/mach-mvebu/armada8k/Makefile @@ -5,3 +5,4 @@ #

obj-y = cpu.o +obj-y += cache_llc.o diff --git a/arch/arm/mach-mvebu/armada8k/cache_llc.S b/arch/arm/mach-mvebu/armada8k/cache_llc.S new file mode 100644 index 0000000..71aecb2 --- /dev/null +++ b/arch/arm/mach-mvebu/armada8k/cache_llc.S @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#include <asm/arch-armada8k/cache_llc.h> +#include <linux/linkage.h> + +/* + * int __asm_flush_l3_dcache + * + * flush Armada-8K last level cache. + * + */ +ENTRY(__asm_flush_l3_dcache) + /* flush cache */ + mov x0, #LLC_BASE_ADDR + add x0, x0, #LLC_FLUSH_BY_WAY + movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16 + mov w1, #LLC_WAY_MASK + str w1, [x0] + /* sync cache */ + mov x0, #LLC_BASE_ADDR + add x0, x0, #LLC_CACHE_SYNC + movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16 + str wzr, [x0] + /* check that cache sync completed */ + mov x0, #LLC_BASE_ADDR + add x0, x0, #LLC_CACHE_SYNC_COMPLETE + movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16 +1: ldr w1, [x0] + and w1, w1, #LLC_CACHE_SYNC_MASK + cbnz w1, 1b + /* return success */ + mov x0, #0 + ret +ENDPROC(__asm_flush_l3_dcache)

From: Konstantin Porotchkin kostap@marvell.com

Enable PCIe bus support in Armada-7040 DB default configuration

Signed-off-by: Konstantin Porotchkin kostap@marvell.com Cc: Stefan Roese sr@denx.de Cc: Nadav Haklai nadavh@marvell.com Cc: Neta Zur Hershkovits neta@marvell.com Cc: Omri Itach omrii@marvell.com Cc: Igal Liberman igall@marvell.com Cc: Haim Boot hayim@marvell.com Cc: Hanna Hawa hannah@marvell.com --- configs/mvebu_db-88f7040_defconfig | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/configs/mvebu_db-88f7040_defconfig b/configs/mvebu_db-88f7040_defconfig index e3bdda6..d9de252 100644 --- a/configs/mvebu_db-88f7040_defconfig +++ b/configs/mvebu_db-88f7040_defconfig @@ -37,6 +37,9 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MVEBU=y CONFIG_MVEBU_COMPHY_SUPPORT=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DEBUG_UART=y