[PATCH 1/7] riscv: qemu: Remove the simple-bus driver for the SoC node
Prior to QEMU v3.1.0, QEMU generated the 'virt' SoC node with a "riscv-virtio-soc" compatible string, and a "simple-bus" driver was created to accommodate that special case in U-Boot.
Starting from QEMU v3.1.0, the SoC node was set as a "simple-bus", hence the special simple-bus driver is no longer needed.
Update the doc to mention the latest tested QEMU version 4.2.0.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/riscv/cpu/generic/cpu.c | 14 -------------- doc/board/emulation/qemu-riscv.rst | 2 +- 2 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/arch/riscv/cpu/generic/cpu.c b/arch/riscv/cpu/generic/cpu.c index c0a5288..13a69ef 100644 --- a/arch/riscv/cpu/generic/cpu.c +++ b/arch/riscv/cpu/generic/cpu.c @@ -4,7 +4,6 @@ */
#include <common.h> -#include <dm.h> #include <irq_func.h>
/* @@ -21,16 +20,3 @@ int cleanup_before_linux(void)
return 0; } - -/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */ -static const struct udevice_id riscv_virtio_soc_ids[] = { - { .compatible = "riscv-virtio-soc" }, - { } -}; - -U_BOOT_DRIVER(riscv_virtio_soc) = { - .name = "riscv_virtio_soc", - .id = UCLASS_SIMPLE_BUS, - .of_match = riscv_virtio_soc_ids, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst index fe7505e..c390006 100644 --- a/doc/board/emulation/qemu-riscv.rst +++ b/doc/board/emulation/qemu-riscv.rst @@ -56,7 +56,7 @@ For instructions on how to run U-Boot in supervisor mode on QEMU with OpenSBI, see the documentation available with OpenSBI: https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
-These have been tested in QEMU 3.0.0. +These have been tested in QEMU 4.2.0.
Running U-Boot SPL ------------------
Two consecutive SMP ifdefs blocks can be combined into one.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/riscv/cpu/start.S | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 6b3ff99..ecf0482 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -58,9 +58,7 @@ _start: /* tp: hart id */ li t0, CONFIG_NR_CPUS bge tp, t0, hart_out_of_bounds_loop -#endif
-#ifdef CONFIG_SMP /* set xSIE bit to receive IPIs */ #if CONFIG_IS_ENABLED(RISCV_MMODE) li t0, MIE_MSIE @@ -377,9 +375,7 @@ hart_out_of_bounds_loop: /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ wfi j hart_out_of_bounds_loop -#endif
-#ifdef CONFIG_SMP /* SMP relocation entry */ secondary_hart_relocate: /* a1: new sp */
On Wed, Apr 8, 2020 at 6:41 AM Bin Meng bmeng.cn@gmail.com wrote:
Two consecutive SMP ifdefs blocks can be combined into one.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/riscv/cpu/start.S | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 6b3ff99..ecf0482 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -58,9 +58,7 @@ _start: /* tp: hart id */ li t0, CONFIG_NR_CPUS bge tp, t0, hart_out_of_bounds_loop -#endif
-#ifdef CONFIG_SMP /* set xSIE bit to receive IPIs */ #if CONFIG_IS_ENABLED(RISCV_MMODE) li t0, MIE_MSIE @@ -377,9 +375,7 @@ hart_out_of_bounds_loop: /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ wfi j hart_out_of_bounds_loop -#endif
-#ifdef CONFIG_SMP /* SMP relocation entry */ secondary_hart_relocate: /* a1: new sp */ -- 2.7.4
Reviewed-by: Atish Patra atish.patra@wdc.com
With SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards.
For U-Boot running in SPL, SMP can be turned on, while in U-Boot proper, SMP can be optionally turned off if using SBI v0.2 HSM.
Introduce a new SPL_SMP Kconfig option to support this.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/riscv/Kconfig | 13 ++++++++++++- arch/riscv/cpu/start.S | 14 +++++++------- arch/riscv/include/asm/global_data.h | 2 +- arch/riscv/lib/Makefile | 2 +- arch/riscv/lib/spl.c | 2 +- common/spl/spl_opensbi.c | 2 +- 6 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index cc87da7..10478ae 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -200,10 +200,21 @@ config SMP machine. If you say Y here, U-Boot will run on many, but not all, single processor machines.
+config SPL_SMP + bool "Symmetric Multi-Processing in SPL" + depends on SPL && SPL_RISCV_MMODE + default y + help + This enables support for systems with more than one CPU in SPL. + If you say N here, U-Boot SPL will run on single and multiprocessor + machines, but will use only one CPU of a multiprocessor + machine. If you say Y here, U-Boot SPL will run on many, but not + all, single processor machines. + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 - depends on SMP + depends on SMP || SPL_SMP default 8 help On multiprocessor machines, U-Boot sets up a stack for each CPU. diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index ecf0482..fce0982 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -53,7 +53,7 @@ _start: /* mask all interrupts */ csrw MODE_PREFIX(ie), zero
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* check if hart is within range */ /* tp: hart id */ li t0, CONFIG_NR_CPUS @@ -91,7 +91,7 @@ call_board_init_f_0: mv gp, a0
/* setup stack */ -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, a0, t0 @@ -182,7 +182,7 @@ spl_stack_gd_setup: mv s0, a0
/* setup stack on main hart */ -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, s0, t0 @@ -231,7 +231,7 @@ relocate_code: *Set up the stack */ stack_setup: -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, s2, t0 @@ -326,7 +326,7 @@ clbss_l: blt t0, t1, clbss_l
relocate_secondary_harts: -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* send relocation IPI */ la t0, secondary_hart_relocate add a0, t0, t6 @@ -370,7 +370,7 @@ call_board_init_r: */ jr t4 /* jump to board_init_r() */
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) hart_out_of_bounds_loop: /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ wfi @@ -393,7 +393,7 @@ secondary_hart_relocate: secondary_hart_loop: wfi
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) csrr t0, MODE_PREFIX(ip) #if CONFIG_IS_ENABLED(RISCV_MMODE) andi t0, t0, MIE_MSIE diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index b74bd7e..72fb4b4 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -24,7 +24,7 @@ struct arch_global_data { #ifdef CONFIG_ANDES_PLMT void __iomem *plmt; /* plmt base address */ #endif -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; #endif #ifndef CONFIG_XIP diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index adadbf4..bd7b2c4 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -22,7 +22,7 @@ endif obj-y += interrupts.o obj-y += reset.o obj-y += setjmp.o -obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_$(SPL_)SMP) += smp.o obj-$(CONFIG_SPL_BUILD) += spl.o
# For building EFI apps diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index ae07bbe..4ca038b 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -41,7 +41,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) invalidate_icache_all();
debug("image entry point: 0x%lX\n", spl_image->entry_point); -#ifdef CONFIG_SMP +#ifdef CONFIG_SPL_SMP ret = smp_call_function(spl_image->entry_point, (ulong)fdt_blob, 0, 0); if (ret) hang(); diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index a136073..3519c34 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -76,7 +76,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point; invalidate_icache_all();
-#ifdef CONFIG_SMP +#ifdef CONFIG_SPL_SMP /* * Start OpenSBI on all secondary harts and wait for acknowledgment. *
On Wed, Apr 8, 2020 at 6:42 AM Bin Meng bmeng.cn@gmail.com wrote:
With SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards.
For U-Boot running in SPL, SMP can be turned on, while in U-Boot proper, SMP can be optionally turned off if using SBI v0.2 HSM.
Introduce a new SPL_SMP Kconfig option to support this.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/riscv/Kconfig | 13 ++++++++++++- arch/riscv/cpu/start.S | 14 +++++++------- arch/riscv/include/asm/global_data.h | 2 +- arch/riscv/lib/Makefile | 2 +- arch/riscv/lib/spl.c | 2 +- common/spl/spl_opensbi.c | 2 +- 6 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index cc87da7..10478ae 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -200,10 +200,21 @@ config SMP machine. If you say Y here, U-Boot will run on many, but not all, single processor machines.
+config SPL_SMP
bool "Symmetric Multi-Processing in SPL"depends on SPL && SPL_RISCV_MMODEdefault yhelpThis enables support for systems with more than one CPU in SPL.If you say N here, U-Boot SPL will run on single and multiprocessormachines, but will use only one CPU of a multiprocessormachine. If you say Y here, U-Boot SPL will run on many, but notall, single processor machines.config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32
depends on SMP
depends on SMP || SPL_SMP default 8 help On multiprocessor machines, U-Boot sets up a stack for each CPU.diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index ecf0482..fce0982 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -53,7 +53,7 @@ _start: /* mask all interrupts */ csrw MODE_PREFIX(ie), zero
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* check if hart is within range */ /* tp: hart id */ li t0, CONFIG_NR_CPUS @@ -91,7 +91,7 @@ call_board_init_f_0: mv gp, a0
/* setup stack */-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, a0, t0 @@ -182,7 +182,7 @@ spl_stack_gd_setup: mv s0, a0
/* setup stack on main hart */-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, s0, t0 @@ -231,7 +231,7 @@ relocate_code: *Set up the stack */ stack_setup: -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, s2, t0 @@ -326,7 +326,7 @@ clbss_l: blt t0, t1, clbss_l
relocate_secondary_harts: -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* send relocation IPI */ la t0, secondary_hart_relocate add a0, t0, t6 @@ -370,7 +370,7 @@ call_board_init_r: */ jr t4 /* jump to board_init_r() */
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) hart_out_of_bounds_loop: /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ wfi @@ -393,7 +393,7 @@ secondary_hart_relocate: secondary_hart_loop: wfi
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) csrr t0, MODE_PREFIX(ip) #if CONFIG_IS_ENABLED(RISCV_MMODE) andi t0, t0, MIE_MSIE diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index b74bd7e..72fb4b4 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -24,7 +24,7 @@ struct arch_global_data { #ifdef CONFIG_ANDES_PLMT void __iomem *plmt; /* plmt base address */ #endif -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; #endif #ifndef CONFIG_XIP diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index adadbf4..bd7b2c4 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -22,7 +22,7 @@ endif obj-y += interrupts.o obj-y += reset.o obj-y += setjmp.o -obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_$(SPL_)SMP) += smp.o obj-$(CONFIG_SPL_BUILD) += spl.o
# For building EFI apps diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index ae07bbe..4ca038b 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -41,7 +41,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) invalidate_icache_all();
debug("image entry point: 0x%lX\n", spl_image->entry_point);-#ifdef CONFIG_SMP +#ifdef CONFIG_SPL_SMP ret = smp_call_function(spl_image->entry_point, (ulong)fdt_blob, 0, 0); if (ret) hang(); diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index a136073..3519c34 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -76,7 +76,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point; invalidate_icache_all();
-#ifdef CONFIG_SMP +#ifdef CONFIG_SPL_SMP /* * Start OpenSBI on all secondary harts and wait for acknowledgment. * -- 2.7.4
Reviewed-by: Atish Patra atish.patra@wdc.com
U-Boot proper running in S-mode only need SMP support when using SBI v0.1. With SBI v0.2 HSM extension, it does not need implement multicore boot in U-Boot proper.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 10478ae..502143f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -193,6 +193,7 @@ config SYS_MALLOC_F_LEN
config SMP bool "Symmetric Multi-Processing" + depends on SBI_V01 help This enables support for systems with more than one CPU. If you say N here, U-Boot will run on single and multiprocessor
On 4/8/20 9:41 AM, Bin Meng wrote:
U-Boot proper running in S-mode only need SMP support when using SBI v0.1. With SBI v0.2 HSM extension, it does not need implement multicore boot in U-Boot proper.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 10478ae..502143f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -193,6 +193,7 @@ config SYS_MALLOC_F_LEN
config SMP bool "Symmetric Multi-Processing"
- depends on SBI_V01
So should this be
"depends on SBI_V01 or RISCV_PRIV_1_9"
when the priv spec 1.9 patch gets merged?
help This enables support for systems with more than one CPU. If you say N here, U-Boot will run on single and multiprocessor
--Sean
Hi Sean,
On Wed, Apr 8, 2020 at 10:20 PM Sean Anderson seanga2@gmail.com wrote:
On 4/8/20 9:41 AM, Bin Meng wrote:
U-Boot proper running in S-mode only need SMP support when using SBI v0.1. With SBI v0.2 HSM extension, it does not need implement multicore boot in U-Boot proper.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 10478ae..502143f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -193,6 +193,7 @@ config SYS_MALLOC_F_LEN
config SMP bool "Symmetric Multi-Processing"
depends on SBI_V01So should this be
"depends on SBI_V01 or RISCV_PRIV_1_9"
when the priv spec 1.9 patch gets merged?
I will change the dependency only when U-Boot is working in S-mode. For M-mode, this dependency will not be added.
help This enables support for systems with more than one CPU. If you say N here, U-Boot will run on single and multiprocessor
Regards, Bin
On Wed, Apr 8, 2020 at 6:42 AM Bin Meng bmeng.cn@gmail.com wrote:
U-Boot proper running in S-mode only need SMP support when using SBI v0.1. With SBI v0.2 HSM extension, it does not need implement multicore boot in U-Boot proper.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 10478ae..502143f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -193,6 +193,7 @@ config SYS_MALLOC_F_LEN
config SMP bool "Symmetric Multi-Processing"
depends on SBI_V01
What about RISCV_MMODE ?
help This enables support for systems with more than one CPU. If you say N here, U-Boot will run on single and multiprocessor-- 2.7.4
On Sat, Apr 11, 2020 at 7:55 AM Atish Patra atishp@atishpatra.org wrote:
On Wed, Apr 8, 2020 at 6:42 AM Bin Meng bmeng.cn@gmail.com wrote:
U-Boot proper running in S-mode only need SMP support when using SBI v0.1. With SBI v0.2 HSM extension, it does not need implement multicore boot in U-Boot proper.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 10478ae..502143f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -193,6 +193,7 @@ config SYS_MALLOC_F_LEN
config SMP bool "Symmetric Multi-Processing"
depends on SBI_V01What about RISCV_MMODE ?
Yes this needs to be considered.
help This enables support for systems with more than one CPU. If you say N here, U-Boot will run on single and multiprocessor
Regards, Bin
SBI v0.2 is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/riscv/Kconfig | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 502143f..ae801d3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -226,14 +226,32 @@ config SBI bool default y if RISCV_SMODE || SPL_RISCV_SMODE
+choice + prompt "SBI support" + default SBI_V01 + config SBI_V01 bool "SBI v0.1 support" - default y depends on SBI help This config allows kernel to use SBI v0.1 APIs. This will be deprecated in future once legacy M-mode software are no longer in use.
+config SBI_V02 + bool "SBI v0.2 support" + depends on SBI + help + This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more + scalable and extendable to handle future needs for RISC-V supervisor + interfaces. For example, with SBI v0.2 HSM extension, only a single + hart need to boot and enter operating system. The booting hart can + bring up secondary harts one by one afterwards. + + Choose this option if OpenSBI v0.7 or above release is used together + with U-Boot. + +endchoice + config SBI_IPI bool depends on SBI
On Wed, Apr 8, 2020 at 6:42 AM Bin Meng bmeng.cn@gmail.com wrote:
SBI v0.2 is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/riscv/Kconfig | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 502143f..ae801d3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -226,14 +226,32 @@ config SBI bool default y if RISCV_SMODE || SPL_RISCV_SMODE
+choice
prompt "SBI support"default SBI_V01config SBI_V01 bool "SBI v0.1 support"
default y depends on SBI help This config allows kernel to use SBI v0.1 APIs. This will be deprecated in future once legacy M-mode software are no longer in use.+config SBI_V02
bool "SBI v0.2 support"depends on SBIhelpThis config allows kernel to use SBI v0.2 APIs. SBI v0.2 is morescalable and extendable to handle future needs for RISC-V supervisorinterfaces. For example, with SBI v0.2 HSM extension, only a singlehart need to boot and enter operating system. The booting hart canbring up secondary harts one by one afterwards.Choose this option if OpenSBI v0.7 or above release is used togetherwith U-Boot.+endchoice
config SBI_IPI bool depends on SBI -- 2.7.4
Reviewed-by: Atish Patra atish.patra@wdc.com
Currently generic-asm-offsets.h and asm-offsets.h are generated based on U-Boot proper config options. The same asm-offsets files are used when building U-Boot SPL/TPL.
But the generated macros, e.g.: GD_AVAILABLE_HARTS, create potential mismatch if U-Boot proper has different config options from U-Boot SPL/TPL, like in this case, SMP.
Remove CONFIG_IS_ENABLED(SMP) in global data to get a consistent value of GD_AVAILABLE_HARTS.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/riscv/include/asm/global_data.h | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 72fb4b4..dc9ba1f 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -24,9 +24,7 @@ struct arch_global_data { #ifdef CONFIG_ANDES_PLMT void __iomem *plmt; /* plmt base address */ #endif -#if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; -#endif #ifndef CONFIG_XIP ulong available_harts; #endif
On Wed, Apr 8, 2020 at 6:42 AM Bin Meng bmeng.cn@gmail.com wrote:
Currently generic-asm-offsets.h and asm-offsets.h are generated based on U-Boot proper config options. The same asm-offsets files are used when building U-Boot SPL/TPL.
But the generated macros, e.g.: GD_AVAILABLE_HARTS, create potential mismatch if U-Boot proper has different config options from U-Boot SPL/TPL, like in this case, SMP.
Remove CONFIG_IS_ENABLED(SMP) in global data to get a consistent value of GD_AVAILABLE_HARTS.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/riscv/include/asm/global_data.h | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 72fb4b4..dc9ba1f 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -24,9 +24,7 @@ struct arch_global_data { #ifdef CONFIG_ANDES_PLMT void __iomem *plmt; /* plmt base address */ #endif -#if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; -#endif #ifndef CONFIG_XIP ulong available_harts; #endif
CONFIG_NR_CPUS is only defined for SMP/SPL_SMP. It will result in compilation error if somebody tries to compile non-smp u-boot.
How about moving available_harts to the top right after boot_hart?
-- 2.7.4
-- Regards, Atish
On Sat, Apr 11, 2020 at 9:02 AM Atish Patra atishp@atishpatra.org wrote:
On Wed, Apr 8, 2020 at 6:42 AM Bin Meng bmeng.cn@gmail.com wrote:
Currently generic-asm-offsets.h and asm-offsets.h are generated based on U-Boot proper config options. The same asm-offsets files are used when building U-Boot SPL/TPL.
But the generated macros, e.g.: GD_AVAILABLE_HARTS, create potential mismatch if U-Boot proper has different config options from U-Boot SPL/TPL, like in this case, SMP.
Remove CONFIG_IS_ENABLED(SMP) in global data to get a consistent value of GD_AVAILABLE_HARTS.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/riscv/include/asm/global_data.h | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 72fb4b4..dc9ba1f 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -24,9 +24,7 @@ struct arch_global_data { #ifdef CONFIG_ANDES_PLMT void __iomem *plmt; /* plmt base address */ #endif -#if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; -#endif #ifndef CONFIG_XIP ulong available_harts; #endif
CONFIG_NR_CPUS is only defined for SMP/SPL_SMP. It will result in compilation error if somebody tries to compile non-smp u-boot.
Yes, I noticed when I looked at the CI testing results. Will fix in v2.
How about moving available_harts to the top right after boot_hart?
Sound good to me.
Regards, Bin
To work with latest OpenSBI release (v0.7 or above) that has the HSM extension support, select the SBI v0.2 support by default.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
arch/riscv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ae801d3..9bdaf2d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -228,7 +228,7 @@ config SBI
choice prompt "SBI support" - default SBI_V01 + default SBI_V02
config SBI_V01 bool "SBI v0.1 support"
On Wed, Apr 8, 2020 at 6:42 AM Bin Meng bmeng.cn@gmail.com wrote:
To work with latest OpenSBI release (v0.7 or above) that has the HSM extension support, select the SBI v0.2 support by default.
Just for clarification: OpenSBI v0.7 will be available soon after Linux kernel 5.-7-rc1 is available.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/riscv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ae801d3..9bdaf2d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -228,7 +228,7 @@ config SBI
choice prompt "SBI support"
default SBI_V01
default SBI_V02config SBI_V01 bool "SBI v0.1 support" -- 2.7.4
Reviewed-by: Atish Patra atish.patra@wdc.com
participants (3)
-
Atish Patra -
Bin Meng -
Sean Anderson