[U-Boot] [PATCH 1/5] net: fec_mxc: Add 1000 Mbps selection
From: Troy Kisky troy.kisky@boundarydevices.com
Add 1000 Mbps selection and print negotiated speed
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Marek Vasut marek.vasut@gmail.com --- drivers/net/fec_mxc.c | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index ed73353..9e8ef7a 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -379,6 +379,7 @@ static int fec_set_hwaddr(struct eth_device *dev) static int fec_open(struct eth_device *edev) { struct fec_priv *fec = (struct fec_priv *)edev->priv; + int speed;
debug("fec_open: fec_open(dev)\n"); /* full-duplex, heartbeat disabled */ @@ -428,8 +429,21 @@ static int fec_open(struct eth_device *edev) #endif
miiphy_wait_aneg(edev); - miiphy_speed(edev->name, fec->phy_id); + speed = miiphy_speed(edev->name, fec->phy_id); miiphy_duplex(edev->name, fec->phy_id); +#ifdef CONFIG_MX6Q + { + u32 ecr = readl(&fec->eth->ecntrl) & ~(0x1 << 5); + u32 rcr = (readl(&fec->eth->r_cntrl) & ~0x300) | 0x44; + if (speed == _1000BASET) + ecr |= (0x1 << 5); + else if (speed != _100BASET) + rcr |= (0x1 << 9); + writel(ecr, &fec->eth->ecntrl); + writel(rcr, &fec->eth->r_cntrl); + } +#endif + printf("%s:Speed=%i\n", __func__, speed);
/* * Enable SmartDMA receive task
From: Troy Kisky troy.kisky@boundarydevices.com
Timeouts were happening to soon for some switches.
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Marek Vasut marek.vasut@gmail.com --- drivers/net/fec_mxc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 9e8ef7a..b50e01c 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -226,7 +226,7 @@ static int miiphy_wait_aneg(struct eth_device *dev) */ start = get_timer(0); do { - if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { + if (get_timer(start) > (CONFIG_SYS_HZ * 10)) { printf("%s: Autonegotiation timeout\n", dev->name); return -1; }
From: Troy Kisky troy.kisky@boundarydevices.com
Previously, only GIGE phy was supported in this function.
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Marek Vasut marek.vasut@gmail.com --- common/miiphyutil.c | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 2cc23b4..8cb4748 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -471,7 +471,23 @@ int miiphy_speed(const char *devname, unsigned char addr) (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) return _1000BASET; #endif /* CONFIG_PHY_GIGE */ - +#ifdef CONFIG_PHY_MICREL_KSZ9021 +#define MII_PHY_CTL 0x1f +#define MII_PHY_CTL_1000 (1 << 6) +#define MII_PHY_CTL_100 (1 << 5) +#define MII_PHY_CTL_10 (1 << 4) + u16 btsr; + if (miiphy_read(devname, addr, MII_PHY_CTL, &btsr)) { + printf("PHY 1000BT status"); + goto miiphy_read_failed; + } + if (btsr & MII_PHY_CTL_1000) + return _1000BASET; + if (btsr & MII_PHY_CTL_100) + return _100BASET; + if (btsr & MII_PHY_CTL_10) + return _10BASET; +#endif /* Check Basic Management Control Register first. */ if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { printf("PHY speed");
From: Troy Kisky troy.kisky@boundarydevices.com
Previously, only GIGE phy was supported in this function.
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Marek Vasut marek.vasut@gmail.com
common/miiphyutil.c | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 2cc23b4..8cb4748 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -471,7 +471,23 @@ int miiphy_speed(const char *devname, unsigned char addr) (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) return _1000BASET; #endif /* CONFIG_PHY_GIGE */
+#ifdef CONFIG_PHY_MICREL_KSZ9021 +#define MII_PHY_CTL 0x1f +#define MII_PHY_CTL_1000 (1 << 6) +#define MII_PHY_CTL_100 (1 << 5) +#define MII_PHY_CTL_10 (1 << 4)
- u16 btsr;
- if (miiphy_read(devname, addr, MII_PHY_CTL, &btsr)) {
printf("PHY 1000BT status");
Very helpful message. Please, if you want to print some output, output something understandable.
goto miiphy_read_failed;- }
- if (btsr & MII_PHY_CTL_1000)
return _1000BASET;- if (btsr & MII_PHY_CTL_100)
return _100BASET;- if (btsr & MII_PHY_CTL_10)
return _10BASET;+#endif /* Check Basic Management Control Register first. */ if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { printf("PHY speed");
On Friday 13 January 2012 07:10:02 Dirk Behme wrote:
common/miiphyutil.c | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-)
this is dead code ... i think we're pushing people to use the name phy framework rather than fixing/extending the old one.
--- a/common/miiphyutil.c +++ b/common/miiphyutil.c
+#ifdef CONFIG_PHY_MICREL_KSZ9021 +#define MII_PHY_CTL 0x1f +#define MII_PHY_CTL_1000 (1 << 6) +#define MII_PHY_CTL_100 (1 << 5) +#define MII_PHY_CTL_10 (1 << 4)
are you sure there aren't defines already in linux/mii.h for these ? -mike
On 15.01.2012 01:56, Mike Frysinger wrote:
On Friday 13 January 2012 07:10:02 Dirk Behme wrote:
common/miiphyutil.c | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-)
this is dead code ... i think we're pushing people to use the name phy framework rather than fixing/extending the old one.
Could you point us to an example how to "use the name phy framework"?
Many thanks and best regards
Dirk
On 19.01.2012 13:38, Dirk Behme wrote:
On 15.01.2012 01:56, Mike Frysinger wrote:
On Friday 13 January 2012 07:10:02 Dirk Behme wrote:
common/miiphyutil.c | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-)
this is dead code ... i think we're pushing people to use the name phy framework rather than fixing/extending the old one.
Could you point us to an example how to "use the name phy framework"?
Hmm, is anything like
http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=commitdiff;h=5751aa2f24...
http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=commitdiff;h=fcc0c75dea...
meant here?
Best regards
Dirk
On Thursday 19 January 2012 11:19:52 Dirk Behme wrote:
On 19.01.2012 13:38, Dirk Behme wrote:
On 15.01.2012 01:56, Mike Frysinger wrote:
On Friday 13 January 2012 07:10:02 Dirk Behme wrote:
common/miiphyutil.c | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-)
this is dead code ... i think we're pushing people to use the name phy framework rather than fixing/extending the old one.
Could you point us to an example how to "use the name phy framework"?
Hmm, is anything like
http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=commitdiff;h=5751aa2f2 48a72c3cec7048cec8dfad33dab0979
http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=commitdiff;h=fcc0c75de a90f2bb8394e7031fc33f72119be544
meant here?
yep, that's the ticket -mike
On Thursday 19 January 2012 07:38:44 Dirk Behme wrote:
On 15.01.2012 01:56, Mike Frysinger wrote:
On Friday 13 January 2012 07:10:02 Dirk Behme wrote:
common/miiphyutil.c | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-)
this is dead code ... i think we're pushing people to use the name phy framework rather than fixing/extending the old one.
Could you point us to an example how to "use the name phy framework"?
sorry, typo. i meant "new phy framework". as in the phylib stuff. -mike
Hi Troy,
On 13.01.2012 13:10, Dirk Behme wrote:
From: Troy Kisky troy.kisky@boundarydevices.com
Previously, only GIGE phy was supported in this function.
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Marek Vasut marek.vasut@gmail.com
common/miiphyutil.c | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 2cc23b4..8cb4748 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -471,7 +471,23 @@ int miiphy_speed(const char *devname, unsigned char addr) (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) return _1000BASET; #endif /* CONFIG_PHY_GIGE */
+#ifdef CONFIG_PHY_MICREL_KSZ9021 +#define MII_PHY_CTL 0x1f +#define MII_PHY_CTL_1000 (1 << 6) +#define MII_PHY_CTL_100 (1 << 5) +#define MII_PHY_CTL_10 (1 << 4)
- u16 btsr;
- if (miiphy_read(devname, addr, MII_PHY_CTL, &btsr)) {
printf("PHY 1000BT status");goto miiphy_read_failed;- }
- if (btsr & MII_PHY_CTL_1000)
return _1000BASET;- if (btsr & MII_PHY_CTL_100)
return _100BASET;- if (btsr & MII_PHY_CTL_10)
return _10BASET;+#endif /* Check Basic Management Control Register first. */ if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { printf("PHY speed");
Thilo mentioned that on an ARM2 board he additionally needs
diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 8cb4748..d3ff2af 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -500,6 +500,8 @@ int miiphy_speed(const char *devname, unsigned char addr) printf("PHY AN speed"); goto miiphy_read_failed; } + if (anlpar & LPA_1000XFULL ) + return _1000BASET; return (anlpar & LPA_100) ? _100BASET : _10BASET; } /* Get speed from basic control settings. */
to make GbE work on that board. What do you think?
Best regards
Dirk
From: Troy Kisky troy.kisky@boundarydevices.com
Allow boards to change what is advertised before an autoneg restart happens.
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Marek Vasut marek.vasut@gmail.com --- drivers/net/fec_mxc.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index b50e01c..6271df5 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device *dev) miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, LPA_100FULL | LPA_100HALF | LPA_10FULL | LPA_10HALF | PHY_ANLPAR_PSB_802_3); - miiphy_write(dev->name, fec->phy_id, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); - if (fec->mii_postcall) ret = fec->mii_postcall(fec->phy_id);
+ miiphy_write(dev->name, fec->phy_id, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); + return ret; }
From: Troy Kisky troy.kisky@boundarydevices.com
Allow boards to change what is advertised before an autoneg restart happens.
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Marek Vasut marek.vasut@gmail.com
drivers/net/fec_mxc.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index b50e01c..6271df5 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device *dev) miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, LPA_100FULL | LPA_100HALF | LPA_10FULL | LPA_10HALF | PHY_ANLPAR_PSB_802_3);
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);- if (fec->mii_postcall) ret = fec->mii_postcall(fec->phy_id);
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);- return ret;
}
I think this might break boards using the mii_postcall.
On 1/13/2012 5:44 AM, Marek Vasut wrote:
From: Troy Kiskytroy.kisky@boundarydevices.com
Allow boards to change what is advertised before an autoneg restart happens.
Signed-off-by: Troy Kiskytroy.kisky@boundarydevices.com CC: Troy Kiskytroy.kisky@boundarydevices.com CC: Stefano Babicsbabic@denx.de CC: Marek Vasutmarek.vasut@gmail.com
drivers/net/fec_mxc.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index b50e01c..6271df5 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device *dev) miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, LPA_100FULL | LPA_100HALF | LPA_10FULL | LPA_10HALF | PHY_ANLPAR_PSB_802_3);
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);- if (fec->mii_postcall) ret = fec->mii_postcall(fec->phy_id);
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);- return ret; }
I think this might break boards using the mii_postcall.
Since only 3 boards use this. Perhaps I should code as
if (fec->mii_start_aneg_call) ret = fec->mii_start_aneg_call(fec->phy_id); else miiphy_write(dev->name, fec->phy_id, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
and copy the miiphy_write(dev->name, fec->phy_id, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
into all three callbacks?
Troy
On 13/01/2012 13:10, Dirk Behme wrote:
From: Troy Kisky troy.kisky@boundarydevices.com
Allow boards to change what is advertised before an autoneg restart happens.
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Marek Vasut marek.vasut@gmail.com
drivers/net/fec_mxc.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index b50e01c..6271df5 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device *dev) miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, LPA_100FULL | LPA_100HALF | LPA_10FULL | LPA_10HALF | PHY_ANLPAR_PSB_802_3);
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);- if (fec->mii_postcall) ret = fec->mii_postcall(fec->phy_id);
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);
...but you change the postcall into a precall...
The current implementation is correct. Something is set / written , and after that a specific supplied function (if any) is called, then the name postcall.
Changing the order is not correct if the fec->mii_postcall thinks (as it should be) that the MII_BMCR register was already written.
But you missed to mention why you need such as change : which is the failure / bug you discovered ?
Best regards, Stefano Babic
On 1/13/2012 6:54 AM, Stefano Babic wrote:
On 13/01/2012 13:10, Dirk Behme wrote:
From: Troy Kiskytroy.kisky@boundarydevices.com
Allow boards to change what is advertised before an autoneg restart happens.
Signed-off-by: Troy Kiskytroy.kisky@boundarydevices.com CC: Troy Kiskytroy.kisky@boundarydevices.com CC: Stefano Babicsbabic@denx.de CC: Marek Vasutmarek.vasut@gmail.com
drivers/net/fec_mxc.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index b50e01c..6271df5 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device *dev) miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, LPA_100FULL | LPA_100HALF | LPA_10FULL | LPA_10HALF | PHY_ANLPAR_PSB_802_3);
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);- if (fec->mii_postcall) ret = fec->mii_postcall(fec->phy_id);
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);...but you change the postcall into a precall...
I assumed mii_postcall meant mii_post_init_call not mii_post_aneg_call.
A rename of the function may be desired.
Perhaps we should let the mii_postcall function do the
miiphy_write(dev->name, fec->phy_id, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
as well.
The current implementation is correct. Something is set / written , and after that a specific supplied function (if any) is called, then the name postcall.
Changing the order is not correct if the fec->mii_postcall thinks (as it should be) that the MII_BMCR register was already written.
But you missed to mention why you need such as change : which is the failure / bug you discovered ?
I wanted the sabrelite board to be able to remove 1000BaseT advertisement before aneg starts.
I think it works either way, but is clearer this way and doesn't rely on luck.
Best regards, Stefano Babic
From: Troy Kisky troy.kisky@boundarydevices.com
Enable the usage of PHY_MICREL_KSZ9021, force the master mode and minimize the tx clock delay.
There is an issue with the gigabit ethernet mode at the SabreLite boards: When operating on a Gb LAN, the FEC occasionally receives packets larger than the MTU that appear to be caused by concatenation of multiple received packets into one. The problem was identified on the phy side. The current schematic has the center tap pin 9 of the MAG/JAC USB combo to 3.3 filtered supply. Letting this pin float solves the problem.
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Jason Liu jason.hui@linaro.org --- Note: This patch depends on the basic SabreLite ethernet patch http://patchwork.ozlabs.org/patch/135744/
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 8 ++++++-- include/configs/mx6qsabrelite.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index d80165e..7879049 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -193,13 +193,17 @@ int board_mmc_init(bd_t *bis)
int fecmxc_mii_postcall(int phy) { - /* prefer master mode */ - miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00); + /* force master mode */ + miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00);
/* min rx data delay */ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
+ /* min tx data delay */ + miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106); + miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); + /* max rx/tx clock delay, min rx/tx control delay */ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0); diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 840e271..6a29142 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -66,6 +66,7 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHY_MICREL_KSZ9021
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
On Fri, Jan 13, 2012 at 8:10 PM, Dirk Behme dirk.behme@de.bosch.com wrote:
From: Troy Kisky troy.kisky@boundarydevices.com
Enable the usage of PHY_MICREL_KSZ9021, force the master mode and minimize the tx clock delay.
There is an issue with the gigabit ethernet mode at the SabreLite boards: When operating on a Gb LAN, the FEC occasionally receives packets larger than the MTU that appear to be caused by concatenation of multiple received packets into one. The problem was identified on the phy side. The current schematic has the center tap pin 9 of the MAG/JAC USB combo to 3.3 filtered supply. Letting this pin float solves the problem.
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Jason Liu jason.hui@linaro.org
Note: This patch depends on the basic SabreLite ethernet patch http://patchwork.ozlabs.org/patch/135744/
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 8 ++++++-- include/configs/mx6qsabrelite.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index d80165e..7879049 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -193,13 +193,17 @@ int board_mmc_init(bd_t *bis)
int fecmxc_mii_postcall(int phy) {
- /* prefer master mode */
- miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00);
- /* force master mode */
- miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00);
/* min rx data delay */ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
- /* min tx data delay */
- miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106);
- miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
/* max rx/tx clock delay, min rx/tx control delay */ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0); diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 840e271..6a29142 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -66,6 +66,7 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHY_MICREL_KSZ9021
Acked-by: Jason Liu jason.hui@linaro.org
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -- 1.7.0.4
On 1/16/2012 6:48 AM, Jason Hui wrote:
On Fri, Jan 13, 2012 at 8:10 PM, Dirk Behmedirk.behme@de.bosch.com wrote:
From: Troy Kiskytroy.kisky@boundarydevices.com
Enable the usage of PHY_MICREL_KSZ9021, force the master mode and minimize the tx clock delay.
There is an issue with the gigabit ethernet mode at the SabreLite boards: When operating on a Gb LAN, the FEC occasionally receives packets larger than the MTU that appear to be caused by concatenation of multiple received packets into one.
No, the extra length are usually zero bytes.
The problem was identified on the phy side. The current schematic has the center tap pin 9 of the MAG/JAC USB combo to 3.3 filtered supply. Letting this pin float solves the problem.
Signed-off-by: Troy Kiskytroy.kisky@boundarydevices.com CC: Troy Kiskytroy.kisky@boundarydevices.com CC: Stefano Babicsbabic@denx.de CC: Jason Liujason.hui@linaro.org
Dirk should either signoff or ack
Note: This patch depends on the basic SabreLite ethernet patch http://patchwork.ozlabs.org/patch/135744/
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 8 ++++++-- include/configs/mx6qsabrelite.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index d80165e..7879049 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -193,13 +193,17 @@ int board_mmc_init(bd_t *bis)
int fecmxc_mii_postcall(int phy) {
/* prefer master mode */miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00);
/* force master mode */miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00); /* min rx data delay */ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);/* min tx data delay */miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106);miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);/* max rx/tx clock delay, min rx/tx control delay */ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0);diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 840e271..6a29142 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -66,6 +66,7 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHY_MICREL_KSZ9021
Acked-by: Jason Liujason.hui@linaro.org
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
1.7.0.4
From: Troy Kisky troy.kisky@boundarydevices.com
Add 1000 Mbps selection and print negotiated speed
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com CC: Troy Kisky troy.kisky@boundarydevices.com CC: Stefano Babic sbabic@denx.de CC: Marek Vasut marek.vasut@gmail.com
drivers/net/fec_mxc.c | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index ed73353..9e8ef7a 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -379,6 +379,7 @@ static int fec_set_hwaddr(struct eth_device *dev) static int fec_open(struct eth_device *edev) { struct fec_priv *fec = (struct fec_priv *)edev->priv;
int speed;
debug("fec_open: fec_open(dev)\n"); /* full-duplex, heartbeat disabled */
@@ -428,8 +429,21 @@ static int fec_open(struct eth_device *edev) #endif
miiphy_wait_aneg(edev);
- miiphy_speed(edev->name, fec->phy_id);
- speed = miiphy_speed(edev->name, fec->phy_id); miiphy_duplex(edev->name, fec->phy_id);
+#ifdef CONFIG_MX6Q
- {
u32 ecr = readl(&fec->eth->ecntrl) & ~(0x1 << 5);u32 rcr = (readl(&fec->eth->r_cntrl) & ~0x300) | 0x44;
Why the magic?
if (speed == _1000BASET)ecr |= (0x1 << 5);else if (speed != _100BASET)rcr |= (0x1 << 9);writel(ecr, &fec->eth->ecntrl);writel(rcr, &fec->eth->r_cntrl);- }
+#endif
- printf("%s:Speed=%i\n", __func__, speed);
debug()
/* * Enable SmartDMA receive task
participants (7)
-
Dirk Behme -
Dirk Behme -
Jason Hui -
Marek Vasut -
Mike Frysinger -
Stefano Babic -
Troy Kisky