[PATCH v3 1/5] x86: minnowmax: Fix up adjustment of CONFIG_TEXT_BASE
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Add documentation on how to make this change safely.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 66e2c665f ("x86: minnowmax: Adjust CONFIG_TEXT_BASE") ---
Changes in v3: - Squash commits - Fix ordering of Environment in docs - Fix value of CONFIG_TEXT_BASE in docs - Change the commit message and subject
Changes in v2: - Add new patch which boots while still enabling EFI_LOADER
arch/x86/dts/minnowmax.dts | 2 +- configs/minnowmax_defconfig | 1 + doc/board/intel/minnowmax.rst | 15 +++++++++++++-- 3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 68e0510c68d8..466309f2b8d5 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -206,7 +206,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; + reg = <0x005f0000 0x00010000>; }; }; }; diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 679b6e3de535..b93c0d729f80 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -18,6 +18,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/doc/board/intel/minnowmax.rst b/doc/board/intel/minnowmax.rst index 1ba25b50d21b..d0286bd99374 100644 --- a/doc/board/intel/minnowmax.rst +++ b/doc/board/intel/minnowmax.rst @@ -54,9 +54,9 @@ Offset Description Controlling config 000000 descriptor.bin Hard-coded to 0 in ifdtool 001000 me.bin Set by the descriptor 500000 <spare> +5f0000 MRC cache CONFIG_ENABLE_MRC_CACHE +600000 u-boot-dtb.bin CONFIG_TEXT_BASE 6ef000 Environment CONFIG_ENV_OFFSET -6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE -700000 u-boot-dtb.bin CONFIG_TEXT_BASE 7b0000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR 7f8000 <spare> (depends on size of fsp.bin) @@ -68,3 +68,14 @@ Overall ROM image size is controlled by CONFIG_ROM_SIZE. Note that the debug version of the FSP is bigger in size. If this version is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of the default value 0xfffc0000. + +If you want to change CONFIG_TEXT_BASE from the current value of ffe00000 +you need to check a few other things. CONFIG_SYS_MONITOR_BASE should +automatically update to be the same as CONFIG_TEXT_BASE but +CONFIG_SYS_MONITOR_LEN may need to be adjusted too. It must cover the space +from the start of U-Boot to the end of the RAM, since the 16-bit boot needs to +be able to jump to U-Boot. See the end of arch/x86/lib/fsp1/fsp_car.S which +has these values. + +Also check the MRC cache address in the devicetree ("rw-mrc-cache"). It must +not overlap with U-Boot.
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: f38be308683 ("x86: bayleybay: Adjust CONFIG_TEXT_BASE") ---
Changes in v3: - Add new patch
arch/x86/dts/bayleybay.dts | 2 +- configs/bayleybay_defconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index b92729dd0b0b..f4cbbd61dffe 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -182,7 +182,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006e0000 0x00010000>; + reg = <0x005e0000 0x00010000>; }; }; }; diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 14d435076da8..5035ccb78b04 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -14,6 +14,7 @@ CONFIG_VGA_BIOS_ADDR=0xfffb0000 CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y
On Wed, Mar 15, 2023 at 8:00 AM Simon Glass sjg@chromium.org wrote:
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: f38be308683 ("x86: bayleybay: Adjust CONFIG_TEXT_BASE")
Changes in v3:
- Add new patch
arch/x86/dts/bayleybay.dts | 2 +- configs/bayleybay_defconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 388f93f9635 ("x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE") ---
Changes in v3: - Add new patch
arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +- configs/conga-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + configs/theadorable-x86-conga-qa3-e3845_defconfig | 1 + 5 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 705157ceaa33..d11e789945ac 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -193,7 +193,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; + reg = <0x005f0000 0x00010000>; }; }; }; diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 3a84190bbfdc..f1bfc9653ca7 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -18,6 +18,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index bb8b9ef312a6..09d08a842f09 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -14,6 +14,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 74c4a4967d0f..00fa3544bd10 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -17,6 +17,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index 194b0519ea22..7cf8c551451e 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -16,6 +16,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y
On Wed, Mar 15, 2023 at 8:00 AM Simon Glass sjg@chromium.org wrote:
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 388f93f9635 ("x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE")
Changes in v3:
- Add new patch
arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +- configs/conga-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + configs/theadorable-x86-conga-qa3-e3845_defconfig | 1 + 5 files changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On 3/15/23 00:59, Simon Glass wrote:
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 388f93f9635 ("x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE")
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
Changes in v3:
Add new patch
arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +- configs/conga-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + configs/theadorable-x86-conga-qa3-e3845_defconfig | 1 + 5 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 705157ceaa33..d11e789945ac 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -193,7 +193,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache";
reg = <0x006f0000 0x00010000>;
reg = <0x005f0000 0x00010000>; }; }; };diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 3a84190bbfdc..f1bfc9653ca7 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -18,6 +18,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index bb8b9ef312a6..09d08a842f09 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -14,6 +14,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 74c4a4967d0f..00fa3544bd10 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -17,6 +17,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index 194b0519ea22..7cf8c551451e 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -16,6 +16,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y
Viele Grüße, Stefan Roese
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 5d1c8342aea ("x86: dfi-bt700: Adjust CONFIG_TEXT_BASE") ---
Changes in v3: - Add new patch
arch/x86/dts/dfi-bt700.dtsi | 2 +- configs/dfi-bt700-q7x-151_defconfig | 1 + configs/theadorable-x86-dfi-bt700_defconfig | 1 + 3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index dff2345d60d0..c077a84574f1 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -204,7 +204,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; + reg = <0x005f0000 0x00010000>; }; }; }; diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index bd8b2e1155d4..a48f7c25134c 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -13,6 +13,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 39c8a87fbeea..82c348884559 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -15,6 +15,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y
On Wed, Mar 15, 2023 at 8:00 AM Simon Glass sjg@chromium.org wrote:
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 5d1c8342aea ("x86: dfi-bt700: Adjust CONFIG_TEXT_BASE")
Changes in v3:
- Add new patch
arch/x86/dts/dfi-bt700.dtsi | 2 +- configs/dfi-bt700-q7x-151_defconfig | 1 + configs/theadorable-x86-dfi-bt700_defconfig | 1 + 3 files changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On 3/15/23 00:59, Simon Glass wrote:
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 5d1c8342aea ("x86: dfi-bt700: Adjust CONFIG_TEXT_BASE")
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
Changes in v3:
Add new patch
arch/x86/dts/dfi-bt700.dtsi | 2 +- configs/dfi-bt700-q7x-151_defconfig | 1 + configs/theadorable-x86-dfi-bt700_defconfig | 1 + 3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index dff2345d60d0..c077a84574f1 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -204,7 +204,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache";
reg = <0x006f0000 0x00010000>;
reg = <0x005f0000 0x00010000>; }; }; };diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index bd8b2e1155d4..a48f7c25134c 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -13,6 +13,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 39c8a87fbeea..82c348884559 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -15,6 +15,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y
Viele Grüße, Stefan Roese
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: e23cae30801 ("x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE") ---
Changes in v3: - Add new patch
arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 +- configs/som-db5800-som-6867_defconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index e9b56de7927b..ca7d97f2d48b 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -206,7 +206,7 @@ memory-map = <0xff800000 0x00800000>; rw-mrc-cache { label = "rw-mrc-cache"; - reg = <0x006f0000 0x00010000>; + reg = <0x005f0000 0x00010000>; }; }; }; diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index c4752a2b0a5c..73813500fa11 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -15,6 +15,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_SEABIOS=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y
On Wed, Mar 15, 2023 at 8:00 AM Simon Glass sjg@chromium.org wrote:
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: e23cae30801 ("x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE")
Changes in v3:
- Add new patch
arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 +- configs/som-db5800-som-6867_defconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Wed, Mar 15, 2023 at 8:00 AM Simon Glass sjg@chromium.org wrote:
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Add documentation on how to make this change safely.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 66e2c665f ("x86: minnowmax: Adjust CONFIG_TEXT_BASE")
Changes in v3:
- Squash commits
- Fix ordering of Environment in docs
- Fix value of CONFIG_TEXT_BASE in docs
- Change the commit message and subject
Changes in v2:
- Add new patch which boots while still enabling EFI_LOADER
arch/x86/dts/minnowmax.dts | 2 +- configs/minnowmax_defconfig | 1 + doc/board/intel/minnowmax.rst | 15 +++++++++++++-- 3 files changed, 15 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Thu, Mar 16, 2023 at 3:27 PM Bin Meng bmeng.cn@gmail.com wrote:
On Wed, Mar 15, 2023 at 8:00 AM Simon Glass sjg@chromium.org wrote:
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too.
Add documentation on how to make this change safely.
Signed-off-by: Simon Glass sjg@chromium.org Fixes: 66e2c665f ("x86: minnowmax: Adjust CONFIG_TEXT_BASE")
Changes in v3:
- Squash commits
- Fix ordering of Environment in docs
- Fix value of CONFIG_TEXT_BASE in docs
- Change the commit message and subject
Changes in v2:
- Add new patch which boots while still enabling EFI_LOADER
arch/x86/dts/minnowmax.dts | 2 +- configs/minnowmax_defconfig | 1 + doc/board/intel/minnowmax.rst | 15 +++++++++++++-- 3 files changed, 15 insertions(+), 3 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
series applied to u-boot-x86, thanks!
participants (3)
-
Bin Meng -
Simon Glass -
Stefan Roese