[U-Boot] {Spam?} skip relocation
Hi,
In my previous working version of U-boot I used CONFIG_SKIP_RELOCATION but this doesn't seem to work any more.
Any reason why it doesn't work any more ? Is there another way to skip relocation ?
regards, Marcel
Le 01/01/2011 16:31, Marcel a écrit :
Hi,
In my previous working version of U-boot I used CONFIG_SKIP_RELOCATION but this doesn't seem to work any more.
Any reason why it doesn't work any more ? Is there another way to skip relocation ?
It actually has no sense any more. The current code skips the relocation if, and only if, U-boot is already running at its final destination.
Trying to run U-boot without relocating and without being at the link-time address would not work.
regards, Marcel
Amicalement,
On Saturday, January 01, 2011 11:52:21 pm Albert ARIBAUD wrote:
Le 01/01/2011 16:31, Marcel a écrit :
Hi,
In my previous working version of U-boot I used CONFIG_SKIP_RELOCATION but this doesn't seem to work any more.
Any reason why it doesn't work any more ? Is there another way to skip relocation ?
It actually has no sense any more. The current code skips the relocation if, and only if, U-boot is already running at its final destination.
Trying to run U-boot without relocating and without being at the link-time address would not work.
OK, that does make sense.
In my case u-boot is in NOR. What do I need to boot from NOR ?
Best regards, Marcel
On Sunday, January 02, 2011 10:07:44 am Marcel wrote:
On Saturday, January 01, 2011 11:52:21 pm Albert ARIBAUD wrote:
Le 01/01/2011 16:31, Marcel a écrit :
Hi,
In my previous working version of U-boot I used CONFIG_SKIP_RELOCATION but this doesn't seem to work any more.
Any reason why it doesn't work any more ? Is there another way to skip relocation ?
It actually has no sense any more. The current code skips the relocation if, and only if, U-boot is already running at its final destination.
Trying to run U-boot without relocating and without being at the link-time address would not work.
OK, that does make sense.
In my case u-boot is in NOR. What do I need to boot from NOR ?
Is there any example that boots from NOR ?
Best regards, Marcel
On Sunday, January 02, 2011 07:35:50 pm Marcel wrote:
On Sunday, January 02, 2011 10:07:44 am Marcel wrote:
On Saturday, January 01, 2011 11:52:21 pm Albert ARIBAUD wrote:
Le 01/01/2011 16:31, Marcel a écrit :
Hi,
In my previous working version of U-boot I used CONFIG_SKIP_RELOCATION but this doesn't seem to work any more.
Any reason why it doesn't work any more ? Is there another way to skip relocation ?
It actually has no sense any more. The current code skips the relocation if, and only if, U-boot is already running at its final destination.
Trying to run U-boot without relocating and without being at the link-time address would not work.
OK, that does make sense.
In my case u-boot is in NOR. What do I need to boot from NOR ?
Is there any example that boots from NOR ?
Below is the config I used about 2-3 month ago. Perhaps anyone has a hint how to make it work with the current relocation code ?
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ICNOVA_ARM9 1 /* It's an ICnova SAM9G45 OEM boardR */ #define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC */ #define CONFIG_AT91_LEGACY 1 /* needed for some defines */ #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* USB Host */ #define CONFIG_USB_ATMEL 1 //#define CONFIG_USB_EHCI 1 #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_USB_STORAGE 1
/* USB gadget support for Ethernet over USB */ #define CONFIG_USB_GADGET_ATMEL_USBA 1 #define CONFIG_ARCH_AT91 1 #define CONFIG_USB_GADGET 1 #define CONFIG_USB_ETHER 1 #define CONFIG_USBNET_MANUFACTURER "Atmel AT91SAM9G45" #define CONFIG_USBNET_DEV_ADDR "8e:28:0f:fa:3c:39" #define CONFIG_USBNET_HOST_ADDR "0a:fa:63:8b:e8:0a" #define CONFIG_USB_CDC_VENDOR_ID 0x0525 #define CONFIG_USB_CDC_PRODUCT_ID 0xa4a1 #define CONFIG_USB_RNDIS_VENDOR_ID 0x0525 #define CONFIG_USB_RNDIS_PRODUCT_ID 0xa4a2
#include <asm/arch/memory-map.h> /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_SYS_HZ 1000
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SKIP_RELOCATE_UBOOT
/* * Hardware drivers */ #define CONFIG_AT91_GPIO 1 #define CONFIG_ATMEL_USART 1 #undef CONFIG_USART0 #undef CONFIG_USART1 #undef CONFIG_USART2 #define CONFIG_USART3 1 /* USART 3 is DBGU */
#define CONFIG_SYS_USE_NANDFLASH 1
/* LED */ #define CONFIG_AT91_LED #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
#define CONFIG_BOOTDELAY 3
/* * Command line configuration. */ #include <config_cmd_default.h> #define CONFIG_CMD_ASKENV #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND 1 #define CONFIG_CMD_USB 1
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x70000000 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ #define CONFIG_SYS_GBL_DATA_SIZE 128 #define INTERNAL_SRAM_BASE 0x00300000 #define INTERNAL_SRAM_SIZE 0x00010000 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE) #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) #define CONFIG_SYS_MALLOC_LEN (256*1024) #define CONFIG_SYS_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM + 0x00400000) #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
/* NAND flash */ #define CONFIG_CMD_MTDPARTS 1 #define CONFIG_MTD_DEVICE 1 #define CONFIG_NAND_MAX_CHIPS 1 //#define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 8 #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 11
/* Ethernet */ #define CONFIG_MACB 1 #define CONFIG_RMII 1 #define CONFIG_NET_MULTI 1 #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R 1 #define CONFIG_NET_DO_NOT_TRY_ANOTHER 1 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 #define CONFIG_CMD_DHCP 1 #define CONFIG_CMD_PING 1 #define CONFIG_MACB_SEARCH_PHY 1 /* * BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE 1 #define CONFIG_BOOTP_BOOTPATH 1 #define CONFIG_BOOTP_GATEWAY 1 #define CONFIG_BOOTP_HOSTNAME 1 #define CONFIG_BOOTP_SUBNETMASK
/* NOR flash */ #define CONFIG_CMD_JFFS2 1 #define CONFIG_SYS_FLASH_SIZE 0x00100000 #define CONFIG_SYS_FLASH_SECT 8 #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 #define PHYS_FLASH_1 0x10000000 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MAX_FLASH_SECT 8 #define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MONITOR_SEC 1:0-7 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x000E0000)
#define MTDIDS_DEFAULT "nand0=nand.0" #define MTDPARTS_DEFAULT "mtdparts=nand.0:2M(kernel),16M(root),-(Data)" #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTARGS "root=1F01 rootfstype=jffs2" #define CONFIG_BOOTCOMMAND \ "mtdparts default; nand read 0x71000000 nand0,0; bootm 0x71000000"
#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_SYS_PROMPT "Sam9> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 #define CONFIG_AUTO_COMPLETE 1 #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* * Size of malloc() pool */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (16*2048) /* regular stack */
#ifdef CONFIG_USE_IRQ #error CONFIG_USE_IRQ not supported #endif
#endif
Best regards, Marcel
On Sunday, January 02, 2011 08:00:38 pm Marcel wrote:
On Sunday, January 02, 2011 07:35:50 pm Marcel wrote:
On Sunday, January 02, 2011 10:07:44 am Marcel wrote:
On Saturday, January 01, 2011 11:52:21 pm Albert ARIBAUD wrote:
Le 01/01/2011 16:31, Marcel a écrit :
Hi,
In my previous working version of U-boot I used CONFIG_SKIP_RELOCATION but this doesn't seem to work any more.
Any reason why it doesn't work any more ? Is there another way to skip relocation ?
It actually has no sense any more. The current code skips the relocation if, and only if, U-boot is already running at its final destination.
Trying to run U-boot without relocating and without being at the link-time address would not work.
OK, that does make sense.
In my case u-boot is in NOR. What do I need to boot from NOR ?
Is there any example that boots from NOR ?
Below is the config I used about 2-3 month ago. Perhaps anyone has a hint how to make it work with the current relocation code ?
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_ICNOVA_ARM9 1 /* It's an ICnova SAM9G45 OEM boardR */ #define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC */ #define CONFIG_AT91_LEGACY 1 /* needed for some defines */ #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* USB Host */ #define CONFIG_USB_ATMEL 1 //#define CONFIG_USB_EHCI 1 #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_USB_STORAGE 1
/* USB gadget support for Ethernet over USB */ #define CONFIG_USB_GADGET_ATMEL_USBA 1 #define CONFIG_ARCH_AT91 1 #define CONFIG_USB_GADGET 1 #define CONFIG_USB_ETHER 1 #define CONFIG_USBNET_MANUFACTURER "Atmel AT91SAM9G45" #define CONFIG_USBNET_DEV_ADDR "8e:28:0f:fa:3c:39" #define CONFIG_USBNET_HOST_ADDR "0a:fa:63:8b:e8:0a" #define CONFIG_USB_CDC_VENDOR_ID 0x0525 #define CONFIG_USB_CDC_PRODUCT_ID 0xa4a1 #define CONFIG_USB_RNDIS_VENDOR_ID 0x0525 #define CONFIG_USB_RNDIS_PRODUCT_ID 0xa4a2
#include <asm/arch/memory-map.h> /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_SYS_HZ 1000
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SKIP_RELOCATE_UBOOT
/*
- Hardware drivers
*/ #define CONFIG_AT91_GPIO 1 #define CONFIG_ATMEL_USART 1 #undef CONFIG_USART0 #undef CONFIG_USART1 #undef CONFIG_USART2 #define CONFIG_USART3 1 /* USART 3 is DBGU */
#define CONFIG_SYS_USE_NANDFLASH 1
/* LED */ #define CONFIG_AT91_LED #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
#define CONFIG_BOOTDELAY 3
/*
- Command line configuration.
*/ #include <config_cmd_default.h> #define CONFIG_CMD_ASKENV #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND 1 #define CONFIG_CMD_USB 1
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x70000000 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ #define CONFIG_SYS_GBL_DATA_SIZE 128 #define INTERNAL_SRAM_BASE 0x00300000 #define INTERNAL_SRAM_SIZE 0x00010000 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE) #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) #define CONFIG_SYS_MALLOC_LEN (256*1024) #define CONFIG_SYS_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM + 0x00400000) #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
/* NAND flash */ #define CONFIG_CMD_MTDPARTS 1 #define CONFIG_MTD_DEVICE 1 #define CONFIG_NAND_MAX_CHIPS 1 //#define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 8 #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 11
/* Ethernet */ #define CONFIG_MACB 1 #define CONFIG_RMII 1 #define CONFIG_NET_MULTI 1 #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R 1 #define CONFIG_NET_DO_NOT_TRY_ANOTHER 1 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 #define CONFIG_CMD_DHCP 1 #define CONFIG_CMD_PING 1 #define CONFIG_MACB_SEARCH_PHY 1 /*
- BOOTP options
*/ #define CONFIG_BOOTP_BOOTFILESIZE 1 #define CONFIG_BOOTP_BOOTPATH 1 #define CONFIG_BOOTP_GATEWAY 1 #define CONFIG_BOOTP_HOSTNAME 1 #define CONFIG_BOOTP_SUBNETMASK
/* NOR flash */ #define CONFIG_CMD_JFFS2 1 #define CONFIG_SYS_FLASH_SIZE 0x00100000 #define CONFIG_SYS_FLASH_SECT 8 #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 #define PHYS_FLASH_1 0x10000000 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MAX_FLASH_SECT 8 #define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MONITOR_SEC 1:0-7 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x000E0000)
#define MTDIDS_DEFAULT "nand0=nand.0" #define MTDPARTS_DEFAULT "mtdparts=nand.0:2M(kernel),16M(root),-(Data)" #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTARGS "root=1F01 rootfstype=jffs2" #define CONFIG_BOOTCOMMAND \ "mtdparts default; nand read 0x71000000 nand0,0; bootm 0x71000000"
#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_SYS_PROMPT "Sam9> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 #define CONFIG_AUTO_COMPLETE 1 #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
- Size of malloc() pool
*/ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (16*2048) /* regular stack */
#ifdef CONFIG_USE_IRQ #error CONFIG_USE_IRQ not supported #endif
#endif
Forgot to mention a few items :
I flash the NOR at address 0x10020000 TEXT_BASE is 0x10020000
I'm about to give up on this code and move back to older code of 2-3 months ago where things worked well.
My feeling is that I miss something very simple, but I'm looking for it for days now and will give up on it by tomorrow and move back to old u-boot code of 2-3 months ago just to continue what I really want to get done (making USB device work).
Best regards, Marcel
Dear Marcel,
Is there any example that boots from NOR ?
looking at the defines below, you are not really booting u-boot from NOR...
#define CONFIG_SKIP_LOWLEVEL_INIT
If you do that, you must have an initial boot code before u-boot. See below...
#define CONFIG_SKIP_RELOCATE_UBOOT
Not used anymore.
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x70000000 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
Those defines have had their names changed.
#define CONFIG_SYS_GBL_DATA_SIZE 128
This constant is wrong, use the auto-generated value.
/*
- Size of malloc() pool
*/ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
This constant is wrong, use the auto-generated value.
Forgot to mention a few items :
I flash the NOR at address 0x10020000 TEXT_BASE is 0x10020000
That really implies you have another boot program running before u-boot. Proably AT91 bootstrap? Is it configured to jumo to 0x1002000, or does it copy u-boot to some SDRAM address and jumps there?
Have a look at the current implementation for top9000 in u-boot-arm/master and compare your files to it. Any differences to your code that are not board and/or SoC specific probably have to be fixed in your board code or you should be able to reason why it must be different for your board.
Best Regards, Reinhard
Dear Reinhard,
Dear Marcel,
Is there any example that boots from NOR ?
looking at the defines below, you are not really booting u-boot from NOR...
#define CONFIG_SKIP_LOWLEVEL_INIT
If you do that, you must have an initial boot code before u-boot. See below...
#define CONFIG_SKIP_RELOCATE_UBOOT
Not used anymore.
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x70000000 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
Those defines have had their names changed.
These I have changed already. I think they are fine.
#define CONFIG_SYS_GBL_DATA_SIZE 128
This constant is wrong, use the auto-generated value.
OK
/*
- Size of malloc() pool
*/
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
This constant is wrong, use the auto-generated value.
OK
Forgot to mention a few items :
I flash the NOR at address 0x10020000 TEXT_BASE is 0x10020000
That really implies you have another boot program running before u-boot. Proably AT91 bootstrap? Is it configured to jumo to 0x1002000, or does it copy u-boot to some SDRAM address and jumps there?
Yes I run AT91 bootstrap. Is there a way to skip this ?
That's a good question if at91bootstrap jumps to the right address. How can I tell ? (maybe I find out myself, at least your question got me thinking ! ) Let's say it does copy u-boot to SDRAM, do I need to set that address as TEXT_BASE ?
I tried setting TEXT_BASE to 0x10020000 or 0x73f00000 If I use another address, AT91bootstrap doesn't do anything, but at both of these addresses it behaves the same.
Have a look at the current implementation for top9000 in u-boot-arm/master and compare your files to it. Any differences to your code that are not board and/or SoC specific probably have to be fixed in your board code or you should be able to reason why it must be different for your board.
Thanks a lot for your reply. I have a few new things to try and read (bootstrap)
, Marcel
Dear Marcel,
Dear Reinhard,
Dear Marcel,
Is there any example that boots from NOR ?
looking at the defines below, you are not really booting u-boot from NOR...
#define CONFIG_SKIP_LOWLEVEL_INIT
If you do that, you must have an initial boot code before u-boot. See below...
#define CONFIG_SKIP_RELOCATE_UBOOT
Not used anymore.
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x70000000 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
Those defines have had their names changed.
These I have changed already. I think they are fine.
#define CONFIG_SYS_GBL_DATA_SIZE 128
This constant is wrong, use the auto-generated value.
OK
/*
- Size of malloc() pool
*/
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
This constant is wrong, use the auto-generated value.
OK
Forgot to mention a few items :
I flash the NOR at address 0x10020000 TEXT_BASE is 0x10020000
That really implies you have another boot program running before u-boot. Proably AT91 bootstrap? Is it configured to jumo to 0x1002000, or does it copy u-boot to some SDRAM address and jumps there?
Yes I run AT91 bootstrap. Is there a way to skip this ?
Sure, if you put an u-boot *with low level init* at the begin of NOR and wire BMS to start from CS0 NOR.
However I am not sure a functional low level init (in u-bbot) exists (yet) for your board. Even with NOR it is customary to use at91bootstrap which does the hardware including SDRAM init.
If you touch at91bootstrap, configure it such that it either loads u-boot to start of SDRAM and jumps there, or directly jumps to the address in NOR where u-boot is stored. Make sure CONFIG_SYS_TEXT_BASE is correct!
That's a good question if at91bootstrap jumps to the right address. How can I tell ? (maybe I find out myself, at least your question got me thinking ! ) Let's say it does copy u-boot to SDRAM, do I need to set that address as TEXT_BASE ?
Exactly. CONFIG_SYS_TEXT_BASE must be the address where u-boot is running before relocation. If that address is different, relocation will fail.
I tried setting TEXT_BASE to 0x10020000 or 0x73f00000 If I use another address, AT91bootstrap doesn't do anything, but at both of these addresses it behaves the same.
You should have the source of your at91 bootstrap. Without source its near impossible to tell how it is configured.
Have a look at the current implementation for top9000 in u-boot-arm/master and compare your files to it. Any differences to your code that are not board and/or SoC specific probably have to be fixed in your board code or you should be able to reason why it must be different for your board.
Thanks a lot for your reply. I have a few new things to try and read (bootstrap)
Reinhard
On Sunday, January 02, 2011 10:08:59 pm Reinhard Meyer wrote:
Dear Marcel,
Dear Reinhard,
Dear Marcel,
Is there any example that boots from NOR ?
looking at the defines below, you are not really booting u-boot from NOR...
#define CONFIG_SKIP_LOWLEVEL_INIT
If you do that, you must have an initial boot code before u-boot. See below...
#define CONFIG_SKIP_RELOCATE_UBOOT
Not used anymore.
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x70000000 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
Those defines have had their names changed.
These I have changed already. I think they are fine.
#define CONFIG_SYS_GBL_DATA_SIZE 128
This constant is wrong, use the auto-generated value.
OK
/*
- Size of malloc() pool
*/
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
This constant is wrong, use the auto-generated value.
OK
Forgot to mention a few items :
I flash the NOR at address 0x10020000 TEXT_BASE is 0x10020000
That really implies you have another boot program running before u-boot. Proably AT91 bootstrap? Is it configured to jumo to 0x1002000, or does it copy u-boot to some SDRAM address and jumps there?
Yes I run AT91 bootstrap. Is there a way to skip this ?
Sure, if you put an u-boot *with low level init* at the begin of NOR and wire BMS to start from CS0 NOR.
However I am not sure a functional low level init (in u-bbot) exists (yet) for your board. Even with NOR it is customary to use at91bootstrap which does the hardware including SDRAM init.
If you touch at91bootstrap, configure it such that it either loads u-boot to start of SDRAM and jumps there, or directly jumps to the address in NOR where u-boot is stored. Make sure CONFIG_SYS_TEXT_BASE is correct!
That's a good question if at91bootstrap jumps to the right address. How can I tell ? (maybe I find out myself, at least your question got me thinking ! ) Let's say it does copy u-boot to SDRAM, do I need to set that address as TEXT_BASE ?
Exactly. CONFIG_SYS_TEXT_BASE must be the address where u-boot is running before relocation. If that address is different, relocation will fail.
I tried setting TEXT_BASE to 0x10020000 or 0x73f00000 If I use another address, AT91bootstrap doesn't do anything, but at both of these addresses it behaves the same.
You should have the source of your at91 bootstrap. Without source its near impossible to tell how it is configured.
Have a look at the current implementation for top9000 in u-boot-arm/master and compare your files to it. Any differences to your code that are not board and/or SoC specific probably have to be fixed in your board code or you should be able to reason why it must be different for your board.
I have the AT91bootstrap code and compiled it also once a couple of months ago. I will first start form there and see what AT91bootstrap is really doing on my board. I guess I know enough for now to keep me busy for while. I'll report back f I find any issue or made it work.
Thanks again for your reply, Marcel
On Sunday, January 02, 2011 10:08:59 pm Reinhard Meyer wrote:
Dear Marcel,
Dear Reinhard,
Dear Marcel,
Is there any example that boots from NOR ?
looking at the defines below, you are not really booting u-boot from NOR...
#define CONFIG_SKIP_LOWLEVEL_INIT
If you do that, you must have an initial boot code before u-boot. See below...
#define CONFIG_SKIP_RELOCATE_UBOOT
Not used anymore.
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x70000000 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
Those defines have had their names changed.
These I have changed already. I think they are fine.
#define CONFIG_SYS_GBL_DATA_SIZE 128
This constant is wrong, use the auto-generated value.
OK
/*
- Size of malloc() pool
*/
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
This constant is wrong, use the auto-generated value.
OK
Forgot to mention a few items :
I flash the NOR at address 0x10020000 TEXT_BASE is 0x10020000
That really implies you have another boot program running before u-boot. Proably AT91 bootstrap? Is it configured to jumo to 0x1002000, or does it copy u-boot to some SDRAM address and jumps there?
Yes I run AT91 bootstrap. Is there a way to skip this ?
Sure, if you put an u-boot *with low level init* at the begin of NOR and wire BMS to start from CS0 NOR.
However I am not sure a functional low level init (in u-bbot) exists (yet) for your board. Even with NOR it is customary to use at91bootstrap which does the hardware including SDRAM init.
If you touch at91bootstrap, configure it such that it either loads u-boot to start of SDRAM and jumps there, or directly jumps to the address in NOR where u-boot is stored. Make sure CONFIG_SYS_TEXT_BASE is correct!
That's a good question if at91bootstrap jumps to the right address. How can I tell ? (maybe I find out myself, at least your question got me thinking ! ) Let's say it does copy u-boot to SDRAM, do I need to set that address as TEXT_BASE ?
Exactly. CONFIG_SYS_TEXT_BASE must be the address where u-boot is running before relocation. If that address is different, relocation will fail.
I tried setting TEXT_BASE to 0x10020000 or 0x73f00000 If I use another address, AT91bootstrap doesn't do anything, but at both of these addresses it behaves the same.
You should have the source of your at91 bootstrap. Without source its near impossible to tell how it is configured.
Have a look at the current implementation for top9000 in u-boot-arm/master and compare your files to it. Any differences to your code that are not board and/or SoC specific probably have to be fixed in your board code or you should be able to reason why it must be different for your board.
I did find a couple of addresses in my AT91bootstrap :
******************************************************************* */ /* BootStrap Settings */ /* */ /* ******************************************************************* */ #define IMG_ADDRESS 0x20000 /* Image Address in NandFlash */ #define IMG_SIZE 0x40000 /* Image Size in NandFlash */
#define MACH_TYPE 0x86F /* AT91SAM9G45- EKES */ #define JUMP_ADDR 0x73F00000 /* Final Jump Address */
I used 0x73f00000 before without success. But I'm very much wondering about the comment in this file saying " Image address in NAND flash"
Could it be that AT91bootstrap is jumping to 0x20000 and than expects u-boot to boot from NAND flash instead of SDRAM ?
I tried to set CONFIG_SYS_TEXT_BASE to both 0x73f00000 and 0x00020000. In both case AT91bootstrap starts u-boot but it hangs at relocation.
I'll first check my board config to see if I find anything strange in there.
Regards, Marcel
On Monday, January 03, 2011 07:57:33 pm Marcel wrote:
On Sunday, January 02, 2011 10:08:59 pm Reinhard Meyer wrote:
Dear Marcel,
Dear Reinhard,
Dear Marcel,
Is there any example that boots from NOR ?
looking at the defines below, you are not really booting u-boot from NOR...
#define CONFIG_SKIP_LOWLEVEL_INIT
If you do that, you must have an initial boot code before u-boot. See below...
#define CONFIG_SKIP_RELOCATE_UBOOT
Not used anymore.
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x70000000 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
Those defines have had their names changed.
These I have changed already. I think they are fine.
#define CONFIG_SYS_GBL_DATA_SIZE 128
This constant is wrong, use the auto-generated value.
OK
/*
- Size of malloc() pool
*/
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data
*/
This constant is wrong, use the auto-generated value.
OK
Forgot to mention a few items :
I flash the NOR at address 0x10020000 TEXT_BASE is 0x10020000
That really implies you have another boot program running before u-boot. Proably AT91 bootstrap? Is it configured to jumo to 0x1002000, or does it copy u-boot to some SDRAM address and jumps there?
Yes I run AT91 bootstrap. Is there a way to skip this ?
Sure, if you put an u-boot *with low level init* at the begin of NOR and wire BMS to start from CS0 NOR.
However I am not sure a functional low level init (in u-bbot) exists (yet) for your board. Even with NOR it is customary to use at91bootstrap which does the hardware including SDRAM init.
If you touch at91bootstrap, configure it such that it either loads u-boot to start of SDRAM and jumps there, or directly jumps to the address in NOR where u-boot is stored. Make sure CONFIG_SYS_TEXT_BASE is correct!
That's a good question if at91bootstrap jumps to the right address. How can I tell ? (maybe I find out myself, at least your question got me thinking ! ) Let's say it does copy u-boot to SDRAM, do I need to set that address as TEXT_BASE ?
Exactly. CONFIG_SYS_TEXT_BASE must be the address where u-boot is running before relocation. If that address is different, relocation will fail.
I tried setting TEXT_BASE to 0x10020000 or 0x73f00000 If I use another address, AT91bootstrap doesn't do anything, but at both of these addresses it behaves the same.
You should have the source of your at91 bootstrap. Without source its near impossible to tell how it is configured.
Have a look at the current implementation for top9000 in u-boot-arm/master and compare your files to it. Any differences to your code that are not board and/or SoC specific probably have to be fixed in your board code or you should be able to reason why it must be different for your board.
I did find a couple of addresses in my AT91bootstrap :
******************************************************************* */ /* BootStrap Settings */ /* */ /* ******************************************************************* */ #define IMG_ADDRESS 0x20000 /* Image Address in NandFlash */ #define IMG_SIZE 0x40000 /* Image Size in NandFlash */
#define MACH_TYPE 0x86F /* AT91SAM9G45- EKES */ #define JUMP_ADDR 0x73F00000 /* Final Jump Address */
I used 0x73f00000 before without success. But I'm very much wondering about the comment in this file saying " Image address in NAND flash"
Could it be that AT91bootstrap is jumping to 0x20000 and than expects u-boot to boot from NAND flash instead of SDRAM ?
I tried to set CONFIG_SYS_TEXT_BASE to both 0x73f00000 and 0x00020000. In both case AT91bootstrap starts u-boot but it hangs at relocation.
I'll first check my board config to see if I find anything strange in there.
Great, I've got it to boot.
I have no idea why it suddenly works, but I guess after reviewing my config and changing a couple of things one of those things must have been the cause.
CONFIG_SYS_TEXT_BASE is 0x7f300000 which is the final jump address as mentioned in AT91bootstrap.
I guess the issue is solved now and I'll certainly check out at91bootstrap to create my own low level init in u-boot. It eventually saves time at production level I think and I generally like to keep things as simple as possible anyways. Since all initialisation code is in at91bootstrap I guess I can just move it from there to u-boot (sounds easy, but I guess there's some more to it).
Thanks for all the help and I hope at some time in the near future I can submit some code for this board. Since I travel a lot it may take some time before I can submit something that's clean enough, but if someone is interested in my current code I can send it.
Best regards, Marcel
Dear Marcel,
On Monday, January 03, 2011 07:57:33 pm Marcel wrote:
Great, I've got it to boot.
I have no idea why it suddenly works, but I guess after reviewing my config and changing a couple of things one of those things must have been the cause.
CONFIG_SYS_TEXT_BASE is 0x7f300000 which is the final jump address as mentioned in AT91bootstrap.
If this address is near end of SDRAM, and since u-boot relocates itself to end of SDRAM, you might risk an overlap, depending on malloc and stack sizes.
I'd advise to have AT91Bootstrap load u-boot to the very SDRAM start (so I did for our board).
I guess the issue is solved now and I'll certainly check out at91bootstrap to create my own low level init in u-boot. It eventually saves time at production level I think and I generally like to keep things as simple as possible anyways. Since all initialisation code is in at91bootstrap I guess I can just move it from there to u-boot (sounds easy, but I guess there's some more to it).
It might not be THAT easy. Also be aware that at91bootstrap is not GPL-ed...
Reinhard
On Monday, January 03, 2011 09:34:34 pm Reinhard Meyer wrote:
Dear Marcel,
On Monday, January 03, 2011 07:57:33 pm Marcel wrote:
Great, I've got it to boot.
I have no idea why it suddenly works, but I guess after reviewing my config and changing a couple of things one of those things must have been the cause.
CONFIG_SYS_TEXT_BASE is 0x7f300000 which is the final jump address as mentioned in AT91bootstrap.
If this address is near end of SDRAM, and since u-boot relocates itself to end of SDRAM, you might risk an overlap, depending on malloc and stack sizes.
I'd advise to have AT91Bootstrap load u-boot to the very SDRAM start (so I did for our board).
OK, thanks for the advice. If seems the SDRAM end address is 0x80000000
I guess the issue is solved now and I'll certainly check out at91bootstrap to create my own low level init in u-boot. It eventually saves time at production level I think and I generally like to keep things as simple as possible anyways. Since all initialisation code is in at91bootstrap I guess I can just move it from there to u-boot (sounds easy, but I guess there's some more to it).
It might not be THAT easy. Also be aware that at91bootstrap is not GPL-ed...
Does that really make a difference if all these values basically can be read from specs ? I know what you mean however and I respect code if it is not OK to copy. I didn't realise at91bootstrap wasn't GPL, so thanks for letting me know.
I did check the code already today and it does seem to be not all that complex. However, I also have no real need to bypass at91bootstrap. As long as it works for me, basically the only need would be to simplify my production procedure and that's just a very minor step. I don't expect I'll focus on this for some time.
Best regards, Marcel
Dear Marcel, Dear Reinhard,
I have the same problem with my board and the actual u-boot-atmel (git from 5th Aug. 2011). It even looks like I am using the same board. It is a in-circuit ICnova SAM9G45 OEM on a ADB1000 with a 5" display.
Actually I use the u-boot from in-circuit, which is a patched version basing on u-boot from 2009. I would like to upgrade this old version to the actual u-boot version. Some time ago somebody tried to get the in-circuit patch into the u-boot mainstream, but the patch was rejected because of not meeting the coding rules.
Marcel, can you give me a hint what you changed to get your configuration running ? I used the latest code for the at91sam9m10g45ek as reference and added/changed it.
Starting the old u-boot version with patches from in-circuit: -------------------------------------------------------------
Start AT91Bootstrap
U-Boot 2009.11 (Jun 18 2011 - 19:57:09)
DRAM: 128 MB Flash: 1 MB NAND: 256 MiB In: serial Out: serial Err: serial MMC: Atmel MCI: 0 Net: macb0 Hit any key to stop autoboot: 0 ICnova>
Starting u-boot-atmel (git) from 5th Aug. 2011: ------------------------------------------------
Start AT91Bootstrap
U-Boot 2011.06 (Aug 10 2011 - 20:49:32)
U-Boot code: 73F00000 -> 73F45494 BSS: -> 73F87110 CPU: AT91SAM9G45 Crystal frequency: 12 MHz CPU clock : 400 MHz Master clock : 133.333 MHz monitor len: 00087110 ramsize: 08000000 TLB table at: 77ff0000 Top of RAM usable for U-Boot at: 77ff0000 Reserving 540k for U-Boot at: 77f68000 Reserving 384k for malloc() at: 77f08000 Reserving 24 Bytes for Board Info at: 77f07fe8 Reserving 144 Bytes for Global Data at: 77f07f58 New Stack Pointer is: 77f07f48 RAM Configuration: Bank #0: 70000000 128 MiB relocation Offset is: 04068000
no more output, it seems the relocation fails. I have a #DEBUG in lib/board.c to get the above output.
Here is my configuration:
/* * Configuation settings for the ICNOVA ADB1000 with SAM9G45 OEM and 5" TFT. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */
#ifndef __CONFIG_H #define __CONFIG_H
#include <asm/hardware.h>
#define CONFIG_AT91_LEGACY #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
/* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_SYS_HZ 1000
#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
/* serial console */ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS
/* * This needs to be defined for the OHCI code to work but it is defined as * ATMEL_ID_UHPHS in the CPU specific header files. */ #define ATMEL_ID_UHP ATMEL_ID_UHPHS
/* * Specify the clock enable bit in the PMC_SCER register. */ #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
/* LCD */ #define CONFIG_LCD #define LCD_BPP LCD_COLOR8 #define CONFIG_LCD_LOGO #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_ATMEL_LCD #define CONFIG_ATMEL_LCD_RGB565 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* board specific(not enough SRAM) */ #define CONFIG_ICNOVA_LCD_BASE 0x73E00000
#define CONFIG_BOOTDELAY 3
/* * Command line configuration. */ #include <config_cmd_default.h> #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP #define CONFIG_CMD_USB #define CONFIG_CMD_NAND #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS #define CONFIG_MTD_NAND_ECC_JFFS2 //#define CONFIG_CMD_UBIFS #define CONFIG_CMD_PING #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_FLASH #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION 1 #undef CONFIG_CMD_FPGA
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x70000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* NOR flash */ #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x00100000 #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_FLASH_SECT 8 #define CONFIG_SYS_MAX_FLASH_SECT (CONFIG_SYS_FLASH_SECT+1) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* NAND flash */ #define CONFIG_JFFS2_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_NAND_ATMEL #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC8 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC11
#define MTDIDS_DEFAULT "nand0=nand.0" #define MTDPARTS_DEFAULT "mtdparts=nand.0:2M(kernel),16M(root),-(Data)"
/* MCI */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_GENERIC_ATMEL_MCI #define MMCI_BASE 0xFFF80000
/* Ethernet */ #define CONFIG_MACB #define CONFIG_NET_MULTI
/* USB */ #define CONFIG_USB_ATMEL #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE */ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "adb1000" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000) /* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE)
/* bootstrap + u-boot + env in norflash */ #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE (CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_FLASH_SECT) #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_SYS_PROMPT "u-boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (256*1024)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000)
#ifdef CONFIG_USE_IRQ #error CONFIG_USE_IRQ not supported #endif
#endif
and this is my board file:
/* * (C) Copyright 2007-2008 * Stelian Pop stelian.pop@leadtechdesign.com * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */
#include <common.h> #include <asm/io.h> #include <asm/arch/at91sam9g45_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <lcd.h> #include <mmc.h> #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> #endif #include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */ /* * Miscelaneous platform dependent initialisations */
#ifdef CONFIG_CMD_NAND void icnova_nand_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa;
/* Enable CS3 */ csa = readl(&matrix->ebicsa); csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */ writel(AT91_SMC_SETUP_NWE(8) | AT91_SMC_SETUP_NCS_WR(0) | AT91_SMC_SETUP_NRD(8) | AT91_SMC_SETUP_NCS_RD(0), &smc->cs[3].setup); writel(AT91_SMC_PULSE_NWE(28) | AT91_SMC_PULSE_NCS_WR(20) | AT91_SMC_PULSE_NRD(28) | AT91_SMC_PULSE_NCS_RD(20), &smc->cs[3].pulse); writel(AT91_SMC_CYCLE_NWE(36) | AT91_SMC_CYCLE_NRD(36), &smc->cs[3].cycle); writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ AT91_SMC_MODE_DBW_8 | #endif AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode);
writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
/* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif
#ifdef CONFIG_CMD_USB static void icnova_usb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
at91_set_gpio_output(AT91_PIN_PD1, 0); at91_set_gpio_output(AT91_PIN_PD3, 0); } #endif
#ifdef CONFIG_MACB static void icnova_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* * Disable pull-up on: * RXDV (PA15) => PHY normal mode (not Test mode) * ERX0 (PA12) => PHY ADDR0 * ERX1 (PA13) => PHY ADDR1 * ERX2 (PA8) => PHY ADDR2 * ERX3 (PA9) => PHY ADDR3 * ECRS (PA29) => PHY ADDR4 => PHYADDR = 0x0 * ECOL (PA30) => full MII interface * ERXER (PA16) => no repeater * ETXCLK (PA17) => no isolate */ unsigned long phy_mask = 0; /* Reset and pdwn-pins */ unsigned long rst = pin_to_mask(AT91_PIN_PA27); unsigned long pdwn = 0;
phy_mask = pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA8) | pin_to_mask(AT91_PIN_PA9) | pin_to_mask(AT91_PIN_PA12) | pin_to_mask(AT91_PIN_PA13) | pin_to_mask(AT91_PIN_PA29) | pin_to_mask(AT91_PIN_PA30) | pin_to_mask(AT91_PIN_PA16) | pin_to_mask(AT91_PIN_PA17); rst = pin_to_mask(AT91_PIN_PA26); pdwn = pin_to_mask(AT91_PIN_PA25);
/* Enable clock */ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
/* * Set up Pins */ writel(rst | pdwn | phy_mask, pin_to_controller(AT91_PIN_PA0) + PIO_PER); writel(rst | pdwn | phy_mask, pin_to_controller(AT91_PIN_PA0) + PIO_OER); writel(rst | pdwn | phy_mask, pin_to_controller(AT91_PIN_PA0) + PIO_CODR); udelay(1000); writel(rst, pin_to_controller(AT91_PIN_PA0) + PIO_SODR); udelay(500000); // phy-mask will be resetted by internal hardware
/* And the pins. */ at91_macb_hw_init(); } #endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = { vl_col: 800, vl_row: 480, vl_clk: 33260000, vl_sync: ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL, vl_bpix: 3, vl_tft: 1, vl_hsync_len: 40, vl_left_margin: 176, vl_right_margin:38, vl_vsync_len: 2, vl_upper_margin:35, vl_lower_margin:8, mmio : ATMEL_BASE_LCDC, };
void lcd_enable(void) { at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ }
void lcd_disable(void) { at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ }
static void icnova_lcd_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
gd->fb_base = CONFIG_ICNOVA_LCD_BASE; }
#ifdef CONFIG_LCD_INFO #include <nand.h> #include <version.h>
void lcd_show_board_info(void) { ulong dram_size, nand_size; int i; char temp[32];
lcd_printf ("%s\n", U_BOOT_VERSION); lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate()));
dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += nand_info[i].size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); } #endif /* CONFIG_LCD_INFO */ #endif
int board_early_init_f(void) { at91_seriald_hw_init(); return 0; }
#ifdef CONFIG_MMC static void icnova_mmc_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_A_periph(AT91_PIN_PA0, 0); at91_set_A_periph(AT91_PIN_PA1, 1); at91_set_A_periph(AT91_PIN_PA2, 1); at91_set_A_periph(AT91_PIN_PA3, 1); at91_set_A_periph(AT91_PIN_PA4, 1); at91_set_A_periph(AT91_PIN_PA5, 1);
writel(1 << ATMEL_ID_MCI0, &pmc->pcer); }
int board_mmc_init(bd_t *bd) { icnova_mmc_init(); return atmel_mci_init(bd); } #endif
int board_init(void) { /* Enable Ctrlc */ console_init_f();
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
/* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND icnova_nand_hw_init(); #endif
#ifdef CONFIG_CMD_USB icnova_usb_hw_init(); #endif
#ifdef CONFIG_MACB icnova_macb_hw_init(); #endif #ifdef CONFIG_LCD icnova_lcd_hw_init(); #endif return 0; }
int dram_init(void) { gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); return 0; }
#ifdef CONFIG_RESET_PHY_R void reset_phy(void) { #ifdef CONFIG_MACB /* * Initialize ethernet HW addr prior to starting Linux, * needed for nfsroot */ eth_init(gd->bd); #endif } #endif
int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; }
Can you see anything that could cause the relocation problem?
I would also like to get rid of the AT91Bootstrap. Marcel, did you manage to include the NOR boot code into u-boot?
I am using the ELDK-4.2 as toolchain, could this cause the problem?
Cajus
Dear Cajus Hahn,
Dear Marcel, Dear Reinhard,
I have the same problem with my board and the actual u-boot-atmel (git from 5th Aug. 2011). It even looks like I am using the same board. It is a in-circuit ICnova SAM9G45 OEM on a ADB1000 with a 5" display.
Actually I use the u-boot from in-circuit, which is a patched version basing on u-boot from 2009. I would like to upgrade this old version to the actual u-boot version. Some time ago somebody tried to get the in-circuit patch into the u-boot mainstream, but the patch was rejected because of not meeting the coding rules.
Marcel, can you give me a hint what you changed to get your configuration running ? I used the latest code for the at91sam9m10g45ek as reference and added/changed it.
First, let me clear up a thing: Most ARM boards were "runtime broken" when relocation was introduced. We additionally broke the AT91 boards by cleaning up the SoC header and source files. This second brokenness has been removed by the recent patches for most of the AT91 SoCs. What probably has not been fixed in all cases is the brokeness due to the relocation.
It might well be, that boards build clean, but might not run beyond relocation. You probably have such an issue.
Please refer to the "doc/README.ARM-relocation".
Make sure TEXT_BASE is exactly the address where at91bootstrap loads u-boot. Make sure that at91bootstrap loads the full u-boot image (u-boot became larger quite a bit due to relocation and other changes). Make sure that area is not overlapping the final location of the relocated u-boot (top of RAM). The default at91bootstraps tend to load the image already quite high into RAM, if relocation overlaps this, you are doomed.
Starting the old u-boot version with patches from in-circuit:
Start AT91Bootstrap
U-Boot 2009.11 (Jun 18 2011 - 19:57:09)
DRAM: 128 MB Flash: 1 MB NAND: 256 MiB In: serial Out: serial Err: serial MMC: Atmel MCI: 0 Net: macb0 Hit any key to stop autoboot: 0 ICnova>
Starting u-boot-atmel (git) from 5th Aug. 2011:
Start AT91Bootstrap
U-Boot 2011.06 (Aug 10 2011 - 20:49:32)
U-Boot code: 73F00000 -> 73F45494 BSS: -> 73F87110
I do not see any TEXT_BASE definition in the files below. Have you merged current u-boot with some old patches?
CPU: AT91SAM9G45 Crystal frequency: 12 MHz CPU clock : 400 MHz Master clock : 133.333 MHz monitor len: 00087110 ramsize: 08000000 TLB table at: 77ff0000 Top of RAM usable for U-Boot at: 77ff0000 Reserving 540k for U-Boot at: 77f68000 Reserving 384k for malloc() at: 77f08000 Reserving 24 Bytes for Board Info at: 77f07fe8 Reserving 144 Bytes for Global Data at: 77f07f58 New Stack Pointer is: 77f07f48 RAM Configuration: Bank #0: 70000000 128 MiB relocation Offset is: 04068000
no more output, it seems the relocation fails. I have a #DEBUG in lib/board.c to get the above output.
Here is my configuration:
/*
- Configuation settings for the ICNOVA ADB1000 with SAM9G45 OEM and 5" TFT.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
*/
#ifndef __CONFIG_H #define __CONFIG_H
#include <asm/hardware.h>
Where is the definition that an AT91SAM9G45 is used? It MUST BE defined before hardware.h is included.
#define CONFIG_AT91_LEGACY #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
/* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_SYS_HZ 1000
#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
/* serial console */ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS
/*
- This needs to be defined for the OHCI code to work but it is defined as
- ATMEL_ID_UHPHS in the CPU specific header files.
*/ #define ATMEL_ID_UHP ATMEL_ID_UHPHS
How does this compile? It is already defined in at91sam9g45.h
/*
- Specify the clock enable bit in the PMC_SCER register.
*/ #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
Same here.
/* LCD */ #define CONFIG_LCD #define LCD_BPP LCD_COLOR8 #define CONFIG_LCD_LOGO #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO #define CONFIG_SYS_WHITE_ON_BLACK #define CONFIG_ATMEL_LCD #define CONFIG_ATMEL_LCD_RGB565 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* board specific(not enough SRAM) */ #define CONFIG_ICNOVA_LCD_BASE 0x73E00000
#define CONFIG_BOOTDELAY 3
/*
- Command line configuration.
*/ #include <config_cmd_default.h> #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP #define CONFIG_CMD_USB #define CONFIG_CMD_NAND #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS #define CONFIG_MTD_NAND_ECC_JFFS2 //#define CONFIG_CMD_UBIFS #define CONFIG_CMD_PING #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_FLASH #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION 1 #undef CONFIG_CMD_FPGA
/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x70000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* NOR flash */ #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x00100000 #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_FLASH_SECT 8 #define CONFIG_SYS_MAX_FLASH_SECT (CONFIG_SYS_FLASH_SECT+1) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* NAND flash */ #define CONFIG_JFFS2_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_NAND_ATMEL #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC8 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC11
#define MTDIDS_DEFAULT "nand0=nand.0" #define MTDPARTS_DEFAULT "mtdparts=nand.0:2M(kernel),16M(root),-(Data)"
/* MCI */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_GENERIC_ATMEL_MCI #define MMCI_BASE 0xFFF80000
/* Ethernet */ #define CONFIG_MACB #define CONFIG_NET_MULTI
/* USB */ #define CONFIG_USB_ATMEL #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE */ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "adb1000" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000) /* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE)
Testing ALL the memory, including where u-boot and stacks reside?
/* bootstrap + u-boot + env in norflash */ #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE (CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_FLASH_SECT) #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_SYS_PROMPT "u-boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
- Size of malloc() pool
*/ #define CONFIG_SYS_MALLOC_LEN (256*1024)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000)
This misses subtraction of generated GD size.
#ifdef CONFIG_USE_IRQ #error CONFIG_USE_IRQ not supported #endif
#endif
and this is my board file:
/*
- (C) Copyright 2007-2008
- Stelian Pop stelian.pop@leadtechdesign.com
- Lead Tech Design <www.leadtechdesign.com>
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
*/
#include <common.h> #include <asm/io.h> #include <asm/arch/at91sam9g45_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <lcd.h> #include <mmc.h> #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> #endif #include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */ /*
- Miscelaneous platform dependent initialisations
*/
#ifdef CONFIG_CMD_NAND void icnova_nand_hw_init(void) { struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa;
/* Enable CS3 */ csa = readl(&matrix->ebicsa); csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */ writel(AT91_SMC_SETUP_NWE(8) | AT91_SMC_SETUP_NCS_WR(0) | AT91_SMC_SETUP_NRD(8) | AT91_SMC_SETUP_NCS_RD(0), &smc->cs[3].setup); writel(AT91_SMC_PULSE_NWE(28) | AT91_SMC_PULSE_NCS_WR(20) | AT91_SMC_PULSE_NRD(28) | AT91_SMC_PULSE_NCS_RD(20), &smc->cs[3].pulse); writel(AT91_SMC_CYCLE_NWE(36) | AT91_SMC_CYCLE_NRD(36), &smc->cs[3].cycle); writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ AT91_SMC_MODE_DBW_8 | #endif AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode);
writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
/* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif
#ifdef CONFIG_CMD_USB static void icnova_usb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
at91_set_gpio_output(AT91_PIN_PD1, 0); at91_set_gpio_output(AT91_PIN_PD3, 0); } #endif
#ifdef CONFIG_MACB static void icnova_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* * Disable pull-up on: * RXDV (PA15) => PHY normal mode (not Test mode) * ERX0 (PA12) => PHY ADDR0 * ERX1 (PA13) => PHY ADDR1 * ERX2 (PA8) => PHY ADDR2 * ERX3 (PA9) => PHY ADDR3 * ECRS (PA29) => PHY ADDR4 => PHYADDR = 0x0 * ECOL (PA30) => full MII interface * ERXER (PA16) => no repeater * ETXCLK (PA17) => no isolate */ unsigned long phy_mask = 0; /* Reset and pdwn-pins */ unsigned long rst = pin_to_mask(AT91_PIN_PA27); unsigned long pdwn = 0;
phy_mask = pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA8) | pin_to_mask(AT91_PIN_PA9) | pin_to_mask(AT91_PIN_PA12) | pin_to_mask(AT91_PIN_PA13) | pin_to_mask(AT91_PIN_PA29) | pin_to_mask(AT91_PIN_PA30) | pin_to_mask(AT91_PIN_PA16) | pin_to_mask(AT91_PIN_PA17); rst = pin_to_mask(AT91_PIN_PA26); pdwn = pin_to_mask(AT91_PIN_PA25);
/* Enable clock */ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
/* * Set up Pins */ writel(rst | pdwn | phy_mask, pin_to_controller(AT91_PIN_PA0) + PIO_PER); writel(rst | pdwn | phy_mask, pin_to_controller(AT91_PIN_PA0) + PIO_OER); writel(rst | pdwn | phy_mask, pin_to_controller(AT91_PIN_PA0) + PIO_CODR); udelay(1000); writel(rst, pin_to_controller(AT91_PIN_PA0) + PIO_SODR); udelay(500000); // phy-mask will be resetted by internal hardware
/* And the pins. */ at91_macb_hw_init(); } #endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = { vl_col: 800, vl_row: 480, vl_clk: 33260000, vl_sync: ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL, vl_bpix: 3, vl_tft: 1, vl_hsync_len: 40, vl_left_margin: 176, vl_right_margin:38, vl_vsync_len: 2, vl_upper_margin:35, vl_lower_margin:8, mmio : ATMEL_BASE_LCDC, };
void lcd_enable(void) { at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ }
void lcd_disable(void) { at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ }
static void icnova_lcd_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
gd->fb_base = CONFIG_ICNOVA_LCD_BASE; }
#ifdef CONFIG_LCD_INFO #include <nand.h> #include <version.h>
void lcd_show_board_info(void) { ulong dram_size, nand_size; int i; char temp[32];
lcd_printf ("%s\n", U_BOOT_VERSION); lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate()));
dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += nand_info[i].size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); } #endif /* CONFIG_LCD_INFO */ #endif
int board_early_init_f(void) { at91_seriald_hw_init(); return 0; }
#ifdef CONFIG_MMC static void icnova_mmc_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_A_periph(AT91_PIN_PA0, 0); at91_set_A_periph(AT91_PIN_PA1, 1); at91_set_A_periph(AT91_PIN_PA2, 1); at91_set_A_periph(AT91_PIN_PA3, 1); at91_set_A_periph(AT91_PIN_PA4, 1); at91_set_A_periph(AT91_PIN_PA5, 1);
writel(1 << ATMEL_ID_MCI0, &pmc->pcer); }
int board_mmc_init(bd_t *bd) { icnova_mmc_init(); return atmel_mci_init(bd); } #endif
int board_init(void) { /* Enable Ctrlc */ console_init_f();
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
/* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND icnova_nand_hw_init(); #endif
#ifdef CONFIG_CMD_USB icnova_usb_hw_init(); #endif
#ifdef CONFIG_MACB icnova_macb_hw_init(); #endif #ifdef CONFIG_LCD icnova_lcd_hw_init(); #endif return 0; }
int dram_init(void) { gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); return 0; }
#ifdef CONFIG_RESET_PHY_R void reset_phy(void) { #ifdef CONFIG_MACB /* * Initialize ethernet HW addr prior to starting Linux, * needed for nfsroot */
This should not be needed anymore.
eth_init(gd->bd); #endif } #endif
int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; }
Can you see anything that could cause the relocation problem?
No clear indications. But check what I pointed out.
I would also like to get rid of the AT91Bootstrap.
Attack one problem first...
Marcel, did you manage to include the NOR boot code into u-boot?
I am using the ELDK-4.2 as toolchain, could this cause the problem?
Most likely not.
Best Regards, Reinhard
Dear Reinhard,
finally I found the relocation problem.
Make sure that at91bootstrap loads the full u-boot image (u-boot became larger quite a bit due to relocation and other changes).
That was the solution!
I left the old at91bootstrap from in-circuit on the board. This one only copies 256k from NOR flash to RAM, but the actual u-boot is 350k long. Besides that I fixed all the issues you pointed out.
Now I can see the menu from u-boot, but I spent the whole weekend searching for the problems with the I/O. - Ethernet won't work (TX timeout) - SSD card access freezes u-boot (seems to be a timing issue as adding #DEBUG to the driver will make some commands work a little more) - USB (which I do not really need, except if SSD card is not working) device is detected, but cannot be accessed. - The LCD display works great (I can see the denx logo and more) which hasn't done in the original u-boot from in-circuit
I think I will start a separate thread for reach issue, after some more searching. Thank You again!
Best Regards Cajus
participants (4)
-
Albert ARIBAUD -
Cajus Hahn -
Marcel -
Reinhard Meyer