Hi Peng,

On 20/10/2015 13:39, Peng Fan wrote:

Change mxs_set_lcdclk prototype to add a new parameter base_addr. There are two LCD interfaces for i.MX6SX, we may support LCDIF1 or LCDIF2.

ok - from your commit message I am waiting that both LCDIF1 and LCDIF2 can be supported, and a user (board maintainer) can switch between them. And in later patch mxs_set_lcdclk() is avalilable for mx6sx and mx6ul, that makes this inconsistent.

But I do not understand how the support for the second LCDIF is implemented. I should see that the register set points to LCDIF1 or LCDIF2.

More as extending to both LCDIF1 and LCDIF2, it looks to me that this is consistent with mxs_set_lcdclk() in mx7.

Signed-off-by: Peng Fan Peng.Fan@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Anatolij Gustschin agust@denx.de

---

V2: none

arch/arm/cpu/arm926ejs/mxs/clock.c | 2 +- arch/arm/include/asm/arch-mxs/clock.h | 2 +- drivers/video/mxsfb.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index e9d8800..dac8dc6 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -309,7 +309,7 @@ void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq) bus, tgtclk, freq); }

-void mxs_set_lcdclk(uint32_t freq) +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h

This patch should generate warnings, because base_addr is not used. You should at least add an __maybe_unused attribute.

Anyway, I am asking myself if it makes sense to pass an address. Really, you want to pass an index if you want to support LCDIF1 or LCDIF2. This makes more sense as passing an address. In you code later (patch 7/14), you check the address like an index:

if (base_addr == LCDIF1_BASE_ADDR) {

This makes inconsistent. If you need it as address, this means you will use it as address later, casting to a register structure. If you use as I understand as index, that please use an enumeration for it.

index fc9d75b..8840335 100644 --- a/arch/arm/include/asm/arch-mxs/clock.h +++ b/arch/arm/include/asm/arch-mxs/clock.h @@ -46,7 +46,7 @@ uint32_t mxc_get_clock(enum mxc_clock clk); void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq); void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq); -void mxs_set_lcdclk(uint32_t freq); +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);

/* Compatibility with the FEC Ethernet driver */ #define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK) diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 03b0f88..eed57d5 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -55,7 +55,7 @@ static void mxs_lcd_init(GraphicDevice *panel, uint8_t valid_data = 0;

/* Kick in the LCDIF clock */

• mxs_set_lcdclk(PS2KHZ(mode->pixclock));

• mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));

  /* Restart the LCDIF block */ mxs_reset_block(&regs->hw_lcdif_ctrl_reg);

Best regards, Stefano Babic

Hi Stefano,

On Tue, Oct 20, 2015 at 03:10:38PM +0200, Stefano Babic wrote:

On 20/10/2015 13:39, Peng Fan wrote:

...

board_mxsfb_system_setup shoule be named mxsfb_system_setup.

		^---should

But really it is better *must*, else it is dead code as we currently have.

Will fix the typo in V3.

Thanks, Peng.

...

Signed-off-by: Peng Fan Peng.Fan@freescale.com Cc: Marek Vasut marek.vasut@gmail.com Cc: Stefano Babic sbabic@denx.de

---

V2: none

board/creative/xfi3/xfi3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/creative/xfi3/xfi3.c b/board/creative/xfi3/xfi3.c index 1d83ea8..509c671 100644 --- a/board/creative/xfi3/xfi3.c +++ b/board/creative/xfi3/xfi3.c @@ -163,7 +163,7 @@ static const struct { { 0x21, 0, 0x0000 }, };

-void board_mxsfb_system_setup(void) +void mxsfb_system_setup(void) { struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; int i;

Best regards, Stefano Babic

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================

--

Hi Peng,

On 20/10/2015 13:39, Peng Fan wrote:

Move 'struct mxs_lcdif_regs' and lcdif related macro definitions to arch/arm/include/asm/imx-common/regs-lcdif.h.

i.MX6SX/UL/28 have similar register layout and bit definitions of registers.

I do not like this approach. Please split this patch into two: the first patch moves only into imx-common (and please use -M in format-patch to detect renaming), and the second one changes what you need to change. There is then no trace about changes in commit.

Signed-off-by: Peng Fan Peng.Fan@freescale.com Cc: Stefano Babic sbabic@denx.de

---

V2: none

arch/arm/include/asm/arch-mxs/regs-lcdif.h | 201 +----------------------- arch/arm/include/asm/imx-common/regs-lcdif.h | 222 +++++++++++++++++++++++++++ 2 files changed, 223 insertions(+), 200 deletions(-) create mode 100644 arch/arm/include/asm/imx-common/regs-lcdif.h

diff --git a/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/arch/arm/include/asm/arch-mxs/regs-lcdif.h index 8915d84..bee1f9a 100644 --- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h +++ b/arch/arm/include/asm/arch-mxs/regs-lcdif.h @@ -13,205 +13,6 @@ #ifndef __MX28_REGS_LCDIF_H__ #define __MX28_REGS_LCDIF_H__

-#include <asm/imx-common/regs-common.h>

-#ifndef __ASSEMBLY__ -struct mxs_lcdif_regs {

• mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
• mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */

-#if defined(CONFIG_MX28)

• mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */

-#endif

• mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
• mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */
• mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */

-#if defined(CONFIG_MX23)

• uint32_t reserved1[4];

-#endif

• mxs_reg_32(hw_lcdif_timing) /* 0x60 */
• mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
• mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
• mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
• mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
• mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
• mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
• mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
• mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
• mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
• mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
• mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
• mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
• mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
• mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
• mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
• mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
• mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */

-#if defined(CONFIG_MX23)

• uint32_t reserved2[12];

-#endif

• mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
• mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */

-#if defined(CONFIG_MX28)

• mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */

-#endif

• mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
• mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */
• mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
• mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
• mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */

-}; -#endif

-#define LCDIF_CTRL_SFTRST (1 << 31) -#define LCDIF_CTRL_CLKGATE (1 << 30) -#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) -#define LCDIF_CTRL_READ_WRITEB (1 << 28) -#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) -#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) -#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) -#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 -#define LCDIF_CTRL_DVI_MODE (1 << 20) -#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) -#define LCDIF_CTRL_VSYNC_MODE (1 << 18) -#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) -#define LCDIF_CTRL_DATA_SELECT (1 << 16) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 -#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) -#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) -#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) -#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 -#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) -#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) -#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) -#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) -#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) -#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) -#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) -#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) -#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) -#define LCDIF_CTRL_RUN (1 << 0)

-#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) -#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) -#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) -#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) -#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) -#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) -#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) -#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 -#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) -#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) -#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) -#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) -#define LCDIF_CTRL1_MODE86 (1 << 1) -#define LCDIF_CTRL1_RESET (1 << 0)

-#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) -#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 -#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) -#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) -#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) -#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) -#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) -#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 -#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) -#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1

-#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) -#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 -#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) -#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0

-#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff -#define LCDIF_CUR_BUF_ADDR_OFFSET 0

-#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff -#define LCDIF_NEXT_BUF_ADDR_OFFSET 0

-#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) -#define LCDIF_TIMING_CMD_HOLD_OFFSET 24 -#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) -#define LCDIF_TIMING_CMD_SETUP_OFFSET 16 -#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) -#define LCDIF_TIMING_DATA_HOLD_OFFSET 8 -#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) -#define LCDIF_TIMING_DATA_SETUP_OFFSET 0

-#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) -#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) -#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) -#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) -#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) -#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) -#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) -#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) -#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0

-#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff -#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0

-#if defined(CONFIG_MX23) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24 -#elif defined(CONFIG_MX28) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 -#endif -#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff -#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0

-#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) -#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0

-#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 -#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 +#include <asm/imx-common/regs-lcdif.h>

#endif /* __MX28_REGS_LCDIF_H__ */ diff --git a/arch/arm/include/asm/imx-common/regs-lcdif.h b/arch/arm/include/asm/imx-common/regs-lcdif.h new file mode 100644 index 0000000..b077003 --- /dev/null +++ b/arch/arm/include/asm/imx-common/regs-lcdif.h @@ -0,0 +1,222 @@ +/*

• • Freescale i.MX28/6SX/6UL LCDIF Register Definitions
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __IMX_REGS_LCDIF_H__ +#define __IMX_REGS_LCDIF_H__

+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <linux/types.h> +#include <asm/imx-common/regs-common.h>

+/* eLCDIF controller registers */ +struct mxs_lcdif_regs {

• mxs_reg_32(hw_lcdif_ctrl)
• mxs_reg_32(hw_lcdif_ctrl1)

+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)

• mxs_reg_32(hw_lcdif_ctrl2)

+#endif

• mxs_reg_32(hw_lcdif_transfer_count)
• mxs_reg_32(hw_lcdif_cur_buf)
• mxs_reg_32(hw_lcdif_next_buf)

+#if defined(CONFIG_MX23)

• uint32_t reserved1[4];

+#endif

• mxs_reg_32(hw_lcdif_timing)
• mxs_reg_32(hw_lcdif_vdctrl0)
• mxs_reg_32(hw_lcdif_vdctrl1)
• mxs_reg_32(hw_lcdif_vdctrl2)
• mxs_reg_32(hw_lcdif_vdctrl3)
• mxs_reg_32(hw_lcdif_vdctrl4)
• mxs_reg_32(hw_lcdif_dvictrl0)
• mxs_reg_32(hw_lcdif_dvictrl1)
• mxs_reg_32(hw_lcdif_dvictrl2)
• mxs_reg_32(hw_lcdif_dvictrl3)
• mxs_reg_32(hw_lcdif_dvictrl4)
• mxs_reg_32(hw_lcdif_csc_coeffctrl0)
• mxs_reg_32(hw_lcdif_csc_coeffctrl1)
• mxs_reg_32(hw_lcdif_csc_coeffctrl2)
• mxs_reg_32(hw_lcdif_csc_coeffctrl3)
• mxs_reg_32(hw_lcdif_csc_coeffctrl4)
• mxs_reg_32(hw_lcdif_csc_offset)
• mxs_reg_32(hw_lcdif_csc_limit)

+#if defined(CONFIG_MX23)

• uint32_t reserved2[12];

+#endif

• mxs_reg_32(hw_lcdif_data)
• mxs_reg_32(hw_lcdif_bm_error_stat)

+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)

• mxs_reg_32(hw_lcdif_crc_stat)

+#endif

• mxs_reg_32(hw_lcdif_lcdif_stat)
• mxs_reg_32(hw_lcdif_version)
• mxs_reg_32(hw_lcdif_debug0)
• mxs_reg_32(hw_lcdif_debug1)
• mxs_reg_32(hw_lcdif_debug2)

+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)

• mxs_reg_32(hw_lcdif_thres)
• mxs_reg_32(hw_lcdif_as_ctrl)
• mxs_reg_32(hw_lcdif_as_buf)
• mxs_reg_32(hw_lcdif_as_next_buf)
• mxs_reg_32(hw_lcdif_as_clrkeylow)
• mxs_reg_32(hw_lcdif_as_clrkeyhigh)
• mxs_reg_32(hw_lcdif_as_sync_delay)
• mxs_reg_32(hw_lcdif_as_debug3)
• mxs_reg_32(hw_lcdif_as_debug4)
• mxs_reg_32(hw_lcdif_as_debug5)

+#endif +}; +#endif

+#define LCDIF_CTRL_SFTRST (1 << 31) +#define LCDIF_CTRL_CLKGATE (1 << 30) +#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) +#define LCDIF_CTRL_READ_WRITEB (1 << 28) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) +#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) +#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 +#define LCDIF_CTRL_DVI_MODE (1 << 20) +#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) +#define LCDIF_CTRL_VSYNC_MODE (1 << 18) +#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) +#define LCDIF_CTRL_DATA_SELECT (1 << 16) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) +#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 +#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) +#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) +#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) +#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) +#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) +#define LCDIF_CTRL_RUN (1 << 0)

+#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) +#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) +#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) +#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) +#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) +#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) +#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) +#define LCDIF_CTRL1_MODE86 (1 << 1) +#define LCDIF_CTRL1_RESET (1 << 0)

+#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) +#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) +#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1

+#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) +#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) +#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0

+#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff +#define LCDIF_CUR_BUF_ADDR_OFFSET 0

+#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff +#define LCDIF_NEXT_BUF_ADDR_OFFSET 0

+#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) +#define LCDIF_TIMING_CMD_HOLD_OFFSET 24 +#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) +#define LCDIF_TIMING_CMD_SETUP_OFFSET 16 +#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) +#define LCDIF_TIMING_DATA_HOLD_OFFSET 8 +#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) +#define LCDIF_TIMING_DATA_SETUP_OFFSET 0

+#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) +#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) +#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) +#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) +#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) +#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) +#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) +#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0

+#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff +#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0

+#if defined(CONFIG_MX23) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24 +#else +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 +#endif

+#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff +#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0

+#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) +#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0

+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0

+#endif /* __IMX_REGS_LCDIF_H__ */

Best regards, Stefano Babic

On 20/10/2015 13:39, Peng Fan wrote:

Add i.MX6UL/SX LCDIF related macros. Discard uneccessary '#ifdef xxx'.

Signed-off-by: Peng Fan Peng.Fan@freescale.com Cc: Stefano Babic sbabic@denx.de

---

V2: none

arch/arm/include/asm/arch-mx6/crm_regs.h | 34 ++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 10306cd..13e0a3d 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -174,6 +174,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 +/* LCDIF on i.MX6SX/UL */ +#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) @@ -210,7 +213,10 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 -/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */ +/* LCFIF2_PODF on i.MX6SX */ +#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) +#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 +/* ACLK_EMI on i.MX6DQ/SDL/DQP */ #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 /* CSCMR1_GPMI/BCH exist on i.MX6UL */ @@ -400,6 +406,20 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) +/* LCDIF1 on i.MX6SX/UL */ +#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) +#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 +#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) +#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 +#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 +/* LCDIF2 on i.MX6SX */ +#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 +#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3) +#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3 +#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) +#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0

/* All IPU2_DI1 are LCDIF1 on MX6SX */ #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) @@ -622,17 +642,16 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) -#ifdef CONFIG_MX6SX +/* i.MX6SX/UL LCD and PXP */ #define MXC_CCM_CCGR2_LCD_OFFSET 28 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) #define MXC_CCM_CCGR2_PXP_OFFSET 30 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) -#else

#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) -#endif

/* Exist on i.MX6SX */ #define MXC_CCM_CCGR3_M4_OFFSET 2 @@ -685,6 +704,13 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)

+#define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6 +#define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8 +#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET) +#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10 +#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET) /* AXI on i.MX6UL */ #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)

Reviewed-by: Stefano Babic sbabic@denx.de

Best regards, Stefano Babic

Hi Peng,

On 20/10/2015 13:39, Peng Fan wrote:

Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video. The three API can be used to configure lcdif related clock when CONFIG_VIDEO_MXS enabled.

Signed-off-by: Peng Fan Peng.Fan@freescale.com Cc: Stefano Babic sbabic@denx.de

---

V2: none

arch/arm/cpu/armv7/mx6/clock.c | 239 ++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 2 + 2 files changed, 241 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 11efd12..8a88378 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -473,6 +473,245 @@ static u32 get_mmdc_ch0_clk(void) } }

+#if defined(CONFIG_VIDEO_MXS) +static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,

• 	    u32 post_div)
  

+{

• u32 reg = 0;
• ulong start;
• debug("pll5 div = %d, num = %d, denom = %d\n",

•      pll_div, pll_num, pll_denom);
  

• /* Power up PLL5 video */
• writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |

•       BM_ANADIG_PLL_VIDEO_BYPASS |
  

•       BM_ANADIG_PLL_VIDEO_DIV_SELECT |
  

•       BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
  

•       &imx_ccm->analog_pll_video_clr);
  

• /* Set div, num and denom */
• switch (post_div) {
• case 1:

• writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  

•        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
  

•        &imx_ccm->analog_pll_video_set);
  

• break;
  

• case 2:

• writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  

•        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
  

•        &imx_ccm->analog_pll_video_set);
  

• break;
  

• case 4:

• writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  

•        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
  

•        &imx_ccm->analog_pll_video_set);
  

• break;
  

• default:

• puts("Wrong test_div!\n");
  

• return -EINVAL;
  

• }
• writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),

•       &imx_ccm->analog_pll_video_num);
  

• writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),

•       &imx_ccm->analog_pll_video_denom);
  

• /* Wait PLL5 lock */
• start = get_timer(0); /* Get current timestamp */
• do {

• reg = readl(&imx_ccm->analog_pll_video);
  

• if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
  

• 	/* Enable PLL out */
  

• 	writel(BM_ANADIG_PLL_VIDEO_ENABLE,
  

• 	       &imx_ccm->analog_pll_video_set);
  

• 	return 0;
  

• }
  

• } while (get_timer(0) < (start + 10)); /* Wait 10ms */
• printf("Lock PLL5 timeout\n");

Maybe puts() is better here

• return -ETIME;

+}

+/*

• • 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
• • 'freq' using KHz as unit, see driver/video/mxsfb.c.
• */

+void mxs_set_lcdclk(u32 base_addr, u32 freq) +{

• u32 reg = 0;
• u32 hck = MXC_HCLK / 1000;
• /* DIV_SELECT ranges from 27 to 54 */
• u32 min = hck * 27;
• u32 max = hck * 54;
• u32 temp, best = 0;
• u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
• u32 pll_div, pll_num, pll_denom, post_div = 1;
• debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
• if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL))

• return;
  

• if (base_addr == LCDIF1_BASE_ADDR) {

As mentioned before: base_addr is really an index, it is not used as address. The interface is then confusing.

• reg = readl(&imx_ccm->cscdr2);
  

• /* Can't change clocks when clock not from pre-mux */
  

• if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
  

• 	return;
  

• }
• if (is_cpu_type(MXC_CPU_MX6SX)) {

• reg = readl(&imx_ccm->cscdr2);
  

• /* Can't change clocks when clock not from pre-mux */
  

• if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
  

• 	return;
  

• }
• temp = freq * max_pred * max_postd;
• if (temp > max) {

• puts("Please decrease freq, too large!\n");
  

• return;
  

• }
• if (temp < min) {

• /*
  

•  * Register: PLL_VIDEO
  

•  * Bit Field: POST_DIV_SELECT
  

•  * 00 — Divide by 4.
  

•  * 01 — Divide by 2.
  

•  * 10 — Divide by 1.
  

•  * 11 — Reserved
  

•  * No need to check post_div(1)
  

•  */
  

• for (post_div = 2; post_div <= 4; post_div <<= 1) {
  

• 	if ((temp * post_div) > min) {
  

• 		freq *= post_div;
  

• 		break;
  

• 	}
  

• }
  

• if (post_div > 4) {
  

• 	printf("Fail to set rate to %dkhz", freq);
  

• 	return;
  

• }
  

• }

It is not clear what happens in the calling function in error case. The error is not propagate to the caller. Of course, we see the error on the console. Is it enough ? The caller will tzry to go on setting the LCD controller even in case this function fails.

• /* Choose the best pred and postd to match freq for lcd */
• for (i = 1; i <= max_pred; i++) {

• for (j = 1; j <= max_postd; j++) {
  

• 	temp = freq * i * j;
  

• 	if (temp > max || temp < min)
  

• 		continue;
  

• 	if (best == 0 || temp < best) {
  

• 		best = temp;
  

• 		pred = i;
  

• 		postd = j;
  

• 	}
  

• }
  

• }
• if (best == 0) {

• printf("Fail to set rate to %dKHz", freq);
  

• return;
  

• }
• debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
• pll_div = best / hck;
• pll_denom = 1000000;
• pll_num = (best - hck * pll_div) * pll_denom / hck;
• /*

• *                                  pll_num
  

• *             (24MHz * (pll_div + --------- ))
  

• *                                 pll_denom
  

• *freq KHz =  --------------------------------
  

• *             post_div * pred * postd * 1000
  

• */
  

• if (base_addr == LCDIF1_BASE_ADDR) {

• if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  

• 	return;
  

• /* Select pre-lcd clock to PLL5 and set pre divider */
  

• clrsetbits_le32(&imx_ccm->cscdr2,
  

• 		MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
  

• 		MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
  

• 		(0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
  

• 		((pred - 1) <<
  

• 		 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
  

• /* Set the post divider */
  

• clrsetbits_le32(&imx_ccm->cbcmr,
  

• 		MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
  

• 		((postd - 1) <<
  

• 		 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
  

• }
• if (is_cpu_type(MXC_CPU_MX6SX)) {

• if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  

• 	return;
  

This is not very good readable. If the cpu is i.MX6SX and LCD is LCDIF1, is enable_pll_video called twice ? Why ?

Should we not use something like:

if (lcd == LCDIF1 || is_cpu_type(MXC_CPU_MX6SX)) { if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) return;

}

• /* Select pre-lcd clock to PLL5 and set pre divider */
  

• clrsetbits_le32(&imx_ccm->cscdr2,
  

• 		MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
  

• 		MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
  

• 		(0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
  

• 		((pred - 1) <<
  

• 		 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
  

• /* Set the post divider */
  

• clrsetbits_le32(&imx_ccm->cscmr1,
  

• 		MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
  

• 		((postd - 1) <<
  

• 		 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
  

• }

+}

+void enable_lcdif_clock(u32 index) +{

You see, you are already using an index. Now you have a mix sometimes with an enumeration (this index), sometimes with "base_addr".

• u32 reg = 0;
• u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
• if (is_cpu_type(MXC_CPU_MX6SX)) {

• if (index > 1)
  

• 	return;
  

• /* Set to pre-mux clock at default */
  

• lcdif_clk_sel_mask = (index == 1) ?
  

• 	MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
  

• 	MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
  

• lcdif_ccgr3_mask = (index == 1) ?
  

• 	(MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
  

• 	 MXC_CCM_CCGR3_DISP_AXI_MASK) :
  

• 	(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
  

• 	 MXC_CCM_CCGR3_DISP_AXI_MASK);
  

• } else if (is_cpu_type(MXC_CPU_MX6UL)) {

• if (index > 0)
  

• 	return;
  

• /* Set to pre-mux clock at default */
  

• lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
  

• lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
  

• } else {

• return;
  

• }
• reg = readl(&imx_ccm->cscdr2);
• reg &= ~lcdif_clk_sel_mask;
• writel(reg, &imx_ccm->cscdr2);
• /* Enable the LCDIF pix clock */
• reg = readl(&imx_ccm->CCGR3);
• reg |= lcdif_ccgr3_mask;
• writel(reg, &imx_ccm->CCGR3);
• reg = readl(&imx_ccm->CCGR2);
• reg |= MXC_CCM_CCGR2_LCD_MASK;
• writel(reg, &imx_ccm->CCGR2);

+} +#endif

#ifdef CONFIG_FSL_QSPI /* qspi_num can be from 0 - 1 */ void enable_qspi_clk(int qspi_num) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 2b220d6..15d14f0 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -66,6 +66,8 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); +void enable_lcdif_clock(unsigned int index); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); +void mxs_set_lcdclk(u32 base_addr, u32 freq); #endif /* __ASM_ARCH_CLOCK_H */

Best regards, Stefano Babic

Hi Stefano,

On Tue, Oct 20, 2015 at 03:39:32PM +0200, Stefano Babic wrote:

Hi Peng,

On 20/10/2015 13:39, Peng Fan wrote:

...

Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video. The three API can be used to configure lcdif related clock when CONFIG_VIDEO_MXS enabled.

Signed-off-by: Peng Fan Peng.Fan@freescale.com Cc: Stefano Babic sbabic@denx.de

---

V2: none

arch/arm/cpu/armv7/mx6/clock.c | 239 ++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 2 + 2 files changed, 241 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 11efd12..8a88378 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -473,6 +473,245 @@ static u32 get_mmdc_ch0_clk(void) } }

+#if defined(CONFIG_VIDEO_MXS) +static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,

• 	    u32 post_div)
  

+{

• u32 reg = 0;
• ulong start;
• debug("pll5 div = %d, num = %d, denom = %d\n",

•      pll_div, pll_num, pll_denom);
  

• /* Power up PLL5 video */
• writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |

•       BM_ANADIG_PLL_VIDEO_BYPASS |
  

•       BM_ANADIG_PLL_VIDEO_DIV_SELECT |
  

•       BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
  

•       &imx_ccm->analog_pll_video_clr);
  

• /* Set div, num and denom */
• switch (post_div) {
• case 1:

• writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  

•        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
  

•        &imx_ccm->analog_pll_video_set);
  

• break;
  

• case 2:

• writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  

•        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
  

•        &imx_ccm->analog_pll_video_set);
  

• break;
  

• case 4:

• writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
  

•        BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
  

•        &imx_ccm->analog_pll_video_set);
  

• break;
  

• default:

• puts("Wrong test_div!\n");
  

• return -EINVAL;
  

• }
• writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),

•       &imx_ccm->analog_pll_video_num);
  

• writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),

•       &imx_ccm->analog_pll_video_denom);
  

• /* Wait PLL5 lock */
• start = get_timer(0); /* Get current timestamp */
• do {

• reg = readl(&imx_ccm->analog_pll_video);
  

• if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
  

• 	/* Enable PLL out */
  

• 	writel(BM_ANADIG_PLL_VIDEO_ENABLE,
  

• 	       &imx_ccm->analog_pll_video_set);
  

• 	return 0;
  

• }
  

• } while (get_timer(0) < (start + 10)); /* Wait 10ms */
• printf("Lock PLL5 timeout\n");

Maybe puts() is better here

...

• return -ETIME;

+}

+/*

• • 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
• • 'freq' using KHz as unit, see driver/video/mxsfb.c.
• */

+void mxs_set_lcdclk(u32 base_addr, u32 freq) +{

• u32 reg = 0;
• u32 hck = MXC_HCLK / 1000;
• /* DIV_SELECT ranges from 27 to 54 */
• u32 min = hck * 27;
• u32 max = hck * 54;
• u32 temp, best = 0;
• u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
• u32 pll_div, pll_num, pll_denom, post_div = 1;
• debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
• if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL))

• return;
  

• if (base_addr == LCDIF1_BASE_ADDR) {

As mentioned before: base_addr is really an index, it is not used as address. The interface is then confusing.

...

• reg = readl(&imx_ccm->cscdr2);
  

• /* Can't change clocks when clock not from pre-mux */
  

• if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
  

• 	return;
  

• }
• if (is_cpu_type(MXC_CPU_MX6SX)) {

• reg = readl(&imx_ccm->cscdr2);
  

• /* Can't change clocks when clock not from pre-mux */
  

• if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
  

• 	return;
  

• }
• temp = freq * max_pred * max_postd;
• if (temp > max) {

• puts("Please decrease freq, too large!\n");
  

• return;
  

• }
• if (temp < min) {

• /*
  

•  * Register: PLL_VIDEO
  

•  * Bit Field: POST_DIV_SELECT
  

•  * 00 — Divide by 4.
  

•  * 01 — Divide by 2.
  

•  * 10 — Divide by 1.
  

•  * 11 — Reserved
  

•  * No need to check post_div(1)
  

•  */
  

• for (post_div = 2; post_div <= 4; post_div <<= 1) {
  

• 	if ((temp * post_div) > min) {
  

• 		freq *= post_div;
  

• 		break;
  

• 	}
  

• }
  

• if (post_div > 4) {
  

• 	printf("Fail to set rate to %dkhz", freq);
  

• 	return;
  

• }
  

• }

It is not clear what happens in the calling function in error case. The error is not propagate to the caller. Of course, we see the error on the console. Is it enough ? The caller will tzry to go on setting the LCD controller even in case this function fails.

...

• /* Choose the best pred and postd to match freq for lcd */
• for (i = 1; i <= max_pred; i++) {

• for (j = 1; j <= max_postd; j++) {
  

• 	temp = freq * i * j;
  

• 	if (temp > max || temp < min)
  

• 		continue;
  

• 	if (best == 0 || temp < best) {
  

• 		best = temp;
  

• 		pred = i;
  

• 		postd = j;
  

• 	}
  

• }
  

• }
• if (best == 0) {

• printf("Fail to set rate to %dKHz", freq);
  

• return;
  

• }
• debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
• pll_div = best / hck;
• pll_denom = 1000000;
• pll_num = (best - hck * pll_div) * pll_denom / hck;
• /*

• *                                  pll_num
  

• *             (24MHz * (pll_div + --------- ))
  

• *                                 pll_denom
  

• *freq KHz =  --------------------------------
  

• *             post_div * pred * postd * 1000
  

• */
  

• if (base_addr == LCDIF1_BASE_ADDR) {

• if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  

• 	return;
  

• /* Select pre-lcd clock to PLL5 and set pre divider */
  

• clrsetbits_le32(&imx_ccm->cscdr2,
  

• 		MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
  

• 		MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
  

• 		(0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
  

• 		((pred - 1) <<
  

• 		 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
  

• /* Set the post divider */
  

• clrsetbits_le32(&imx_ccm->cbcmr,
  

• 		MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
  

• 		((postd - 1) <<
  

• 		 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
  

• }
• if (is_cpu_type(MXC_CPU_MX6SX)) {

• if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
  

• 	return;
  

This is not very good readable. If the cpu is i.MX6SX and LCD is LCDIF1, is enable_pll_video called twice ? Why ?

Should we not use something like:

if (lcd == LCDIF1 || is_cpu_type(MXC_CPU_MX6SX)) { if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) return;

}

...

• /* Select pre-lcd clock to PLL5 and set pre divider */
  

• clrsetbits_le32(&imx_ccm->cscdr2,
  

• 		MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
  

• 		MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
  

• 		(0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
  

• 		((pred - 1) <<
  

• 		 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
  

• /* Set the post divider */
  

• clrsetbits_le32(&imx_ccm->cscmr1,
  

• 		MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
  

• 		((postd - 1) <<
  

• 		 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
  

• }

+}

+void enable_lcdif_clock(u32 index) +{

You see, you are already using an index. Now you have a mix sometimes with an enumeration (this index), sometimes with "base_addr".

After a thought, I think use base_addr is better. In drivers/video/mxs_fb.c, MXS_LCDIF_BASE is used, I do not want to introduce another macro such as MXS_LCDIF_INDEX. So choose base_addr can avoid add more macro definitions in board header files. I'll switch to use base_addr in the patch set.

Regards, Peng.

...

• u32 reg = 0;
• u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
• if (is_cpu_type(MXC_CPU_MX6SX)) {

• if (index > 1)
  

• 	return;
  

• /* Set to pre-mux clock at default */
  

• lcdif_clk_sel_mask = (index == 1) ?
  

• 	MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
  

• 	MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
  

• lcdif_ccgr3_mask = (index == 1) ?
  

• 	(MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
  

• 	 MXC_CCM_CCGR3_DISP_AXI_MASK) :
  

• 	(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
  

• 	 MXC_CCM_CCGR3_DISP_AXI_MASK);
  

• } else if (is_cpu_type(MXC_CPU_MX6UL)) {

• if (index > 0)
  

• 	return;
  

• /* Set to pre-mux clock at default */
  

• lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
  

• lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
  

• } else {

• return;
  

• }
• reg = readl(&imx_ccm->cscdr2);
• reg &= ~lcdif_clk_sel_mask;
• writel(reg, &imx_ccm->cscdr2);
• /* Enable the LCDIF pix clock */
• reg = readl(&imx_ccm->CCGR3);
• reg |= lcdif_ccgr3_mask;
• writel(reg, &imx_ccm->CCGR3);
• reg = readl(&imx_ccm->CCGR2);
• reg |= MXC_CCM_CCGR2_LCD_MASK;
• writel(reg, &imx_ccm->CCGR2);

+} +#endif

#ifdef CONFIG_FSL_QSPI /* qspi_num can be from 0 - 1 */ void enable_qspi_clk(int qspi_num) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 2b220d6..15d14f0 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -66,6 +66,8 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); +void enable_lcdif_clock(unsigned int index); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); +void mxs_set_lcdclk(u32 base_addr, u32 freq); #endif /* __ASM_ARCH_CLOCK_H */

Best regards, Stefano Babic

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================

--

Hi Peng,

On 20/10/2015 13:39, Peng Fan wrote:

Support lcdif display:

1. Add pinmux and pad settings for LCDIF
2. Introduce setup_lcd to do the settings for LCDIF
3. Enable VIDEO related macros in board header files
4. Add a new env videomode which is needed by mxsfb.c. The settings for videomode in this patch is for TFT43AB.
5. Tested on mx6ul 14x14/9x9 evk.

Signed-off-by: Peng Fan Peng.Fan@freescale.com Cc: Stefano Babic sbabic@denx.de

---

V2: Rebased to Latest U-Boot, resolve conflicts.

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 63 +++++++++++++++++++++++ include/configs/mx6ul_14x14_evk.h | 18 +++++++ 2 files changed, 81 insertions(+)

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 8650f35..287a421 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -52,6 +52,9 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)

+#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \

• PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)

#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)

@@ -568,6 +571,62 @@ int board_phy_config(struct phy_device *phydev) } #endif

+#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = {

• MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
• /* LCD_RST */
• MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
• /* Use GPIO for Brightness adjustment, duty cycle = period. */
• MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+static int setup_lcd(void) +{

• enable_lcdif_clock(0);
• imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
• /* Reset the LCD */
• gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
• udelay(500);
• gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);

Just a curiosity: a display reset ? Why is this needed ?

• /* Set Brightness to high */
• gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
• return 0;

+} +#endif

int board_early_init_f(void) { setup_iomux_uart(); @@ -600,6 +659,10 @@ int board_init(void) board_qspi_init(); #endif

+#ifdef CONFIG_VIDEO_MXS

• setup_lcd();

+#endif

• return 0;

}

diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index d5faae6..5779632 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -77,6 +77,7 @@ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \

• "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \

Why this ? Setup is in device tree, we should not need it, do we ?

"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ @@ -242,4 +243,21 @@

#define CONFIG_IMX_THERMAL

+#define CONFIG_VIDEO +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#endif

#endif

Best regards, Stefano Babic

Hi Stefano,

On Tue, Oct 20, 2015 at 03:59:18PM +0200, Stefano Babic wrote:

Hi Peng,

On 20/10/2015 13:39, Peng Fan wrote:

...

Introudce a new function lcdif_power_down.

1. Waits for a VSYNC interrupt to guarantee the reset is done at the VSYNC edge, which somehow makes the LCDIF consume the display FIFO(?) and helps the LCDIF work normally at the kernel stage.
2. Add power down function to stop lcdif.

The reason to introduce lcdif_power_down is that we want lcdif to be in initial state when doing uboot reset or before kernel boot to make system stable, otherwise system may hang.

The explanation is independent from the processor type. But checking in the next patch, this code runs only for 6UL. Why not for the 6sx ?

We met the issue on i.MX6UL EVK, but did not met issue on i.MX6SX SDB. So I add the check. After a thought, it should be open to CONFIG_VIDEO_MXS.

To those which use LPDDR2 or LPDDR3, if LCDIF is enabled, lcdif_power_down is a must, since there is no reset pin as DDR3. No reset pin will make ddr not stable. Anyway lcdif_power_down do not hurts to those use DDR3.

Will use #ifdef CONFIG_VIDEO_MXS lcdif_power_down(); #endif

Regards, Peng.

...

Signed-off-by: Peng Fan Peng.Fan@freescale.com Cc: Stefano Babic sbabic@denx.de Cc: Anatolij Gustschin agust@denx.de

---

V2: none

arch/arm/include/asm/imx-common/sys_proto.h | 2 ++ drivers/video/mxsfb.c | 17 +++++++++++++++++ 2 files changed, 19 insertions(+)

diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h index 5673fb4..386c2dc 100644 --- a/arch/arm/include/asm/imx-common/sys_proto.h +++ b/arch/arm/include/asm/imx-common/sys_proto.h @@ -47,6 +47,8 @@ int fecmxc_initialize(bd_t *bis); u32 get_ahb_clk(void); u32 get_periph_clk(void);

+void lcdif_power_down(void);

int mxs_reset_block(struct mxs_register_32 *reg); int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index eed57d5..ddbb118 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -131,6 +131,23 @@ static void mxs_lcd_init(GraphicDevice *panel, writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set); }

+void lcdif_power_down(void) +{

• struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
• int timeout = 1000000;
• writel(panel.frameAdrs, &regs->hw_lcdif_cur_buf_reg);
• writel(panel.frameAdrs, &regs->hw_lcdif_next_buf_reg);
• writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
• while (--timeout) {

• if (readl(&regs->hw_lcdif_ctrl1_reg) &
  

•     LCDIF_CTRL1_VSYNC_EDGE_IRQ)
  

• 	break;
  

• udelay(1);
  

• }
• mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);

+}

void *video_hw_init(void) { int bpp = -1;

Best regards, Stefano Babic

--

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