Please pull u-boot-marvell/master
Hi Tom,
please pull the next batch of Marvell Armada related patches. Here the summary log:
---------------------------------------------------------------- - Add base support for Marvell OcteonTX2 CN9130 DB (mostly done by Kostya) - Sync Armada mvpp2 ethernet driver with Marvell version (misc Marvell authors) - Sync Armada 8k MMU setup with Marvell version (misc Marvell authors) - spi: kirkwood: Some fixes especially for baudrate generation (misc Marvell authors) - mvebu: x530: Reduce SPL image size (Stefan) - Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan) ----------------------------------------------------------------
Here the Azure build:
https://dev.azure.com/sr0718/u-boot/_build/results?buildId=87&view=resul...
It shows some issues with xilinx_versal_virt, which seem to be not related to this patch set and also occurred yesterday.
Thanks, Stefan
The following changes since commit ea184cbff99ea1d82dcf94c95afe054e95da5069:
Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti (2021-05-12 10:07:21 -0400)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-marvell.git
for you to fetch changes up to e0a6df9efa69bfe662def66d12b8702ad1cf3a51:
arm: octeontx2: Add Octeon TX2 CN913x DB support (2021-05-13 08:18:19 +0200)
---------------------------------------------------------------- Ben Peled (3): net: mvpp2: AN Bypass in 1000 and 2500 basex mode net: mvpp2: remove unused define MVPP22_SMI_PHY_ADDR_REG net: mvpp2: fix missing switch case break
Grzegorz Jaszczyk (4): spi: kirkwood: prevent limiting speed to 0 arm64: mvebu: do not map firmware RT service region arm64: mvebu: a8k: move firmware related definitions to fw info arm64: mvebu: extend the mmio region
Ken Ma (1): spi: kirkwood: support extended baud rates
Konstantin Porotchkin (2): arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB arm: octeontx2: Add Octeon TX2 CN913x DB support
Marcin Wojtas (4): net: mvpp2: remove redundant SMI address configuration net: mvpp2: add explicit sgmii-2500 support spi: kirkwood: prevent configuring speed exceeding max controller freq pcie: designware: mvebu: do not configure ATU for IO when not used
Stefan Chulski (5): phy: introduce 1000BaseX and 2500BaseX modes net: mvpp2: add CP115 port1 10G/5G SFI support net: mvpp2: add 1000BaseX and 2500BaseX ppv2 support net: mvpp2: Fix 2.5G GMII_SPEED configurations net: mvpp2: allow MDIO registration for fixed links
Stefan Roese (2): mvebu: x530: Reduce SPL image size cmd: mvebu: Rename rx_training to mvebu_comphy_rx_training
jinghua (1): arm64: mvebu: a8k: align memory regions
arch/arm/dts/Makefile | 6 + arch/arm/dts/cn9130-db-A.dts | 55 ++++ arch/arm/dts/cn9130-db-B.dts | 51 ++++ arch/arm/dts/cn9130-db-dev-info.dtsi | 44 +++ arch/arm/dts/cn9130-db.dtsi | 316 ++++++++++++++++++++++ arch/arm/dts/cn9131-db-A.dts | 54 ++++ arch/arm/dts/cn9131-db-B.dts | 69 +++++ arch/arm/dts/cn9131-db.dtsi | 166 ++++++++++++ arch/arm/dts/cn9132-db-A.dts | 13 + arch/arm/dts/cn9132-db-B.dts | 13 + arch/arm/dts/cn9132-db.dtsi | 217 +++++++++++++++ arch/arm/mach-mvebu/armada8k/cpu.c | 70 ++--- arch/arm/mach-mvebu/include/mach/fw_info.h | 18 ++ board/Marvell/octeontx2_cn913x/MAINTAINERS | 1 + board/Marvell/octeontx2_cn913x/README | 24 ++ cmd/mvebu/Kconfig | 9 +- cmd/mvebu/Makefile | 2 +- cmd/mvebu/{rx_training.c => comphy_rx_training.c} | 10 +- configs/mvebu_db_cn9130_defconfig | 89 ++++++ configs/x530_defconfig | 2 +- drivers/net/mvpp2.c | 257 +++++++++++------- drivers/pci/pcie_dw_mvebu.c | 37 ++- drivers/spi/kirkwood_spi.c | 67 ++++- include/phy_interface.h | 4 + 24 files changed, 1413 insertions(+), 181 deletions(-) create mode 100644 arch/arm/dts/cn9130-db-A.dts create mode 100644 arch/arm/dts/cn9130-db-B.dts create mode 100644 arch/arm/dts/cn9130-db-dev-info.dtsi create mode 100644 arch/arm/dts/cn9130-db.dtsi create mode 100644 arch/arm/dts/cn9131-db-A.dts create mode 100644 arch/arm/dts/cn9131-db-B.dts create mode 100644 arch/arm/dts/cn9131-db.dtsi create mode 100644 arch/arm/dts/cn9132-db-A.dts create mode 100644 arch/arm/dts/cn9132-db-B.dts create mode 100644 arch/arm/dts/cn9132-db.dtsi create mode 100644 arch/arm/mach-mvebu/include/mach/fw_info.h create mode 100644 board/Marvell/octeontx2_cn913x/README rename cmd/mvebu/{rx_training.c => comphy_rx_training.c} (74%) create mode 100644 configs/mvebu_db_cn9130_defconfig
On Thu, May 13, 2021 at 12:21:38PM +0200, Stefan Roese wrote:
Hi Tom,
please pull the next batch of Marvell Armada related patches. Here the summary log:
- Add base support for Marvell OcteonTX2 CN9130 DB (mostly done by Kostya)
- Sync Armada mvpp2 ethernet driver with Marvell version (misc Marvell authors)
- Sync Armada 8k MMU setup with Marvell version (misc Marvell authors)
- spi: kirkwood: Some fixes especially for baudrate generation (misc Marvell authors)
- mvebu: x530: Reduce SPL image size (Stefan)
- Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)
Here the Azure build:
https://dev.azure.com/sr0718/u-boot/_build/results?buildId=87&view=resul...
Note that this isn't publicly viewable, I think there's some permission stuff on your profile you need to adjust.
It shows some issues with xilinx_versal_virt, which seem to be not related to this patch set and also occurred yesterday.
I bisected this down to: commit 368b3f6db4540f913c436e5287be8356bc9a2891 Author: Stefan Chulski stefanc@marvell.com Date: Mon May 3 08:08:44 2021 +0200
phy: introduce 1000BaseX and 2500BaseX modes
Signed-off-by: Stefan Chulski stefanc@marvell.com Signed-off-by: Stefan Roese sr@denx.de
And while I'm not sure off-hand how it does it, it's causing the breakage. Maybe something is overflowing now?
Hi Tom,
On 13.05.21 17:37, Tom Rini wrote:
On Thu, May 13, 2021 at 12:21:38PM +0200, Stefan Roese wrote:
Hi Tom,
please pull the next batch of Marvell Armada related patches. Here the summary log:
- Add base support for Marvell OcteonTX2 CN9130 DB (mostly done by Kostya)
- Sync Armada mvpp2 ethernet driver with Marvell version (misc Marvell authors)
- Sync Armada 8k MMU setup with Marvell version (misc Marvell authors)
- spi: kirkwood: Some fixes especially for baudrate generation (misc Marvell authors)
- mvebu: x530: Reduce SPL image size (Stefan)
- Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)
Here the Azure build:
https://dev.azure.com/sr0718/u-boot/_build/results?buildId=87&view=resul...
Note that this isn't publicly viewable, I think there's some permission stuff on your profile you need to adjust.
Are you sure? I opened this link with some other web browsers, also on the smartphone without any account login and was able to see the results.
It shows some issues with xilinx_versal_virt, which seem to be not related to this patch set and also occurred yesterday.
I bisected this down to: commit 368b3f6db4540f913c436e5287be8356bc9a2891 Author: Stefan Chulski stefanc@marvell.com Date: Mon May 3 08:08:44 2021 +0200
phy: introduce 1000BaseX and 2500BaseX modes Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>And while I'm not sure off-hand how it does it, it's causing the breakage. Maybe something is overflowing now?
Thanks. I don't see, what is problematic with this patch though. Michal, do you have an idea?
I'm dropping this network / mvpp2 series from the pull-request for now.
Thanks, Stefan
On Sat, May 15, 2021 at 10:03:29AM +0200, Stefan Roese wrote:
Hi Tom,
On 13.05.21 17:37, Tom Rini wrote:
On Thu, May 13, 2021 at 12:21:38PM +0200, Stefan Roese wrote:
Hi Tom,
please pull the next batch of Marvell Armada related patches. Here the summary log:
- Add base support for Marvell OcteonTX2 CN9130 DB (mostly done by Kostya)
- Sync Armada mvpp2 ethernet driver with Marvell version (misc Marvell authors)
- Sync Armada 8k MMU setup with Marvell version (misc Marvell authors)
- spi: kirkwood: Some fixes especially for baudrate generation (misc Marvell authors)
- mvebu: x530: Reduce SPL image size (Stefan)
- Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)
Here the Azure build:
https://dev.azure.com/sr0718/u-boot/_build/results?buildId=87&view=resul...
Note that this isn't publicly viewable, I think there's some permission stuff on your profile you need to adjust.
Are you sure? I opened this link with some other web browsers, also on the smartphone without any account login and was able to see the results.
Works for me now, odd.
participants (2)
-
Stefan Roese -
Tom Rini