imx8mn SPL serial output does not work after powerup
Hi,
After a powerup the SPL output is not seen.
[Powerup] Core: 140 devices, 19 uclasses, devicetree: separate WDT: Started watchdog@30280000 with servicing (60s timeout) MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@30890000 Out: serial@30890000 Err: serial@30890000 Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 u-boot=>
Only after a softreset the output from SPL can be seen.
u-boot=> reset resetting ...
U-Boot SPL 2022.07-rc4-00012-g4b48844ba4 (Jun 13 2022 - 21:06:16 +0200) Normal Boot Failed to find clock node. Check device tree Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 NOTICE: BL31: v2.6(release):v2.6-5-g9b1a4d832 NOTICE: BL31: Built : 14:03:53, May 10 2022
U-Boot 2022.07-rc4-00012-g4b48844ba4 (Jun 13 2022 - 21:06:16 +0200)
CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz Reset cause: WDOG Model: NXP i.MX8MNano DDR3L EVK board DRAM: 1 GiB Core: 140 devices, 19 uclasses, devicetree: separate WDT: Started watchdog@30280000 with servicing (60s timeout) MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@30890000 Out: serial@30890000 Err: serial@30890000 Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 u-boot=>
Can anyone confirm the behavior?
-- Heiko
Hi Heiko,
On Mon, Jun 13, 2022 at 4:16 PM Heiko Thiery heiko.thiery@gmail.com wrote:
Can anyone confirm the behavior?
imx8mn ddr4 evk prints the SPL part just fine.
Take a look at arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi .
It passes:
&uart2 { u-boot,dm-spl; };
&pinctrl_uart2 { u-boot,dm-spl; };
Are you doing the same for the imx8mn ddr3 u-boot dtsi?
Hi,
Am Mo., 13. Juni 2022 um 21:28 Uhr schrieb Fabio Estevam festevam@gmail.com:
Hi Heiko,
On Mon, Jun 13, 2022 at 4:16 PM Heiko Thiery heiko.thiery@gmail.com wrote:
Can anyone confirm the behavior?
imx8mn ddr4 evk prints the SPL part just fine.
Take a look at arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi .
It passes:
&uart2 { u-boot,dm-spl; };
&pinctrl_uart2 { u-boot,dm-spl; };
Are you doing the same for the imx8mn ddr3 u-boot dtsi?
Indeed these are missing. Now I see the whole output from U-Boot but the output from SPL is still missing. When enabloing SPL_DM_SERIAL the board does not start.
Hi
Il lun 13 giu 2022, 21:43 Heiko Thiery heiko.thiery@gmail.com ha scritto:
Hi,
Am Mo., 13. Juni 2022 um 21:28 Uhr schrieb Fabio Estevam < festevam@gmail.com>:
Hi Heiko,
On Mon, Jun 13, 2022 at 4:16 PM Heiko Thiery heiko.thiery@gmail.com
wrote:
Can anyone confirm the behavior?
imx8mn ddr4 evk prints the SPL part just fine.
Take a look at arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi .
It passes:
&uart2 { u-boot,dm-spl; };
&pinctrl_uart2 { u-boot,dm-spl; };
Are you doing the same for the imx8mn ddr3 u-boot dtsi?
Indeed these are missing. Now I see the whole output from U-Boot but the output from SPL is still missing. When enabloing SPL_DM_SERIAL the board does not start.
Check if you have UART clock enabled in sol
Michael
-- Heiko
Am Mo., 13. Juni 2022 um 21:43 Uhr schrieb Heiko Thiery heiko.thiery@gmail.com:
Hi,
Am Mo., 13. Juni 2022 um 21:28 Uhr schrieb Fabio Estevam festevam@gmail.com:
Hi Heiko,
On Mon, Jun 13, 2022 at 4:16 PM Heiko Thiery heiko.thiery@gmail.com wrote:
Can anyone confirm the behavior?
imx8mn ddr4 evk prints the SPL part just fine.
Take a look at arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi .
It passes:
&uart2 { u-boot,dm-spl; };
&pinctrl_uart2 { u-boot,dm-spl; };
Are you doing the same for the imx8mn ddr3 u-boot dtsi?
Indeed these are missing. Now I see the whole output from U-Boot but the output from SPL is still missing. When enabloing SPL_DM_SERIAL the board does not start.
I now did include the whole "imx8mn-ddr4-evk-u-boot.dtsi" like it is done in "imx8mn-evk-u-boot.dtsi". Then it works.
-- Heiko
在 2022/6/14 3:49, Heiko Thiery 写道:
Am Mo., 13. Juni 2022 um 21:43 Uhr schrieb Heiko Thiery heiko.thiery@gmail.com:
Hi,
Am Mo., 13. Juni 2022 um 21:28 Uhr schrieb Fabio Estevam festevam@gmail.com:
Hi Heiko,
On Mon, Jun 13, 2022 at 4:16 PM Heiko Thiery heiko.thiery@gmail.com wrote:
Can anyone confirm the behavior?
imx8mn ddr4 evk prints the SPL part just fine.
Take a look at arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi .
It passes:
&uart2 { u-boot,dm-spl; };
&pinctrl_uart2 { u-boot,dm-spl; };
Are you doing the same for the imx8mn ddr3 u-boot dtsi?
Indeed these are missing. Now I see the whole output from U-Boot but the output from SPL is still missing. When enabloing SPL_DM_SERIAL the board does not start.
I now did include the whole "imx8mn-ddr4-evk-u-boot.dtsi" like it is done in "imx8mn-evk-u-boot.dtsi". Then it works.
make sure preload_console_init is called after spl_early_init or spl_init, not before.
Regards, Peng.
-- Heiko
Hi Peng,
Am Di., 14. Juni 2022 um 03:46 Uhr schrieb Peng Fan (OSS) peng.fan@oss.nxp.com:
在 2022/6/14 3:49, Heiko Thiery 写道:
Am Mo., 13. Juni 2022 um 21:43 Uhr schrieb Heiko Thiery heiko.thiery@gmail.com:
Hi,
Am Mo., 13. Juni 2022 um 21:28 Uhr schrieb Fabio Estevam festevam@gmail.com:
Hi Heiko,
On Mon, Jun 13, 2022 at 4:16 PM Heiko Thiery heiko.thiery@gmail.com wrote:
Can anyone confirm the behavior?
imx8mn ddr4 evk prints the SPL part just fine.
Take a look at arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi .
It passes:
&uart2 { u-boot,dm-spl; };
&pinctrl_uart2 { u-boot,dm-spl; };
Are you doing the same for the imx8mn ddr3 u-boot dtsi?
Indeed these are missing. Now I see the whole output from U-Boot but the output from SPL is still missing. When enabloing SPL_DM_SERIAL the board does not start.
I now did include the whole "imx8mn-ddr4-evk-u-boot.dtsi" like it is done in "imx8mn-evk-u-boot.dtsi". Then it works.
make sure preload_console_init is called after spl_early_init or spl_init, not before.
The board init code is used from imx8mn_evk [1]. So the init sequence seems to be correct.
[1] https://source.denx.de/u-boot/u-boot/-/blob/master/board/freescale/imx8mn_ev...
-- Heiko
participants (4)
-
Fabio Estevam -
Heiko Thiery -
Michael Nazzareno Trimarchi -
Peng Fan (OSS)