[U-Boot] [PATCH 1/2] net: mv88e61xx: add configuration for RGMII delay
Some hardware designs connect a CPU MAC directly to the RGMII interface of a mv88e61xx device. On such devices a delay on the RX/TX lines is required, this can either be achieved by adding extra length to the traces on the PCB or by implementing the delay in silicon. This is an implementation of the latter.
Signed-off-by: Chris Packham judge.packham@gmail.com ---
drivers/net/phy/Kconfig | 4 ++++ drivers/net/phy/mv88e61xx.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index f5821dfed96d..98cd57eea977 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -59,6 +59,10 @@ config MV88E61XX_PHY_PORTS config MV88E61XX_FIXED_PORTS hex "Bitmask of PHYless serdes Ports"
+config MV88E61XX_RGMII_DELAY + bool "Add delay to RGMII outputs" + default n + endif # MV88E61XX_SWITCH
config PHYLIB_10G diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index ea54a1531053..d258ba1ef0f3 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -69,6 +69,7 @@ #define PORT_REG_CTRL 0x04 #define PORT_REG_VLAN_MAP 0x06 #define PORT_REG_VLAN_ID 0x07 +#define PORT_REG_RGMII_TIMING 0x1A
/* Phy registers */ #define PHY_REG_CTRL1 0x10 @@ -122,6 +123,9 @@ #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
+#define PORT_REG_RGMII_TIMING_RX_DELAY BIT(10) +#define PORT_REG_RGMII_TIMING_TX_DELAY BIT(9) + #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8 @@ -705,6 +709,24 @@ unforce: return res; }
+static int mv88e61xx_rgmii_timing_cfg(struct phy_device *phydev) +{ +#ifdef CONFIG_MV88E61XX_RGMII_DELAY + int val; + + val = mv88e61xx_port_read(phydev, 6, PORT_REG_RGMII_TIMING); + if (val < 0) + return val; + + val |= PORT_REG_RGMII_TIMING_RX_DELAY | + PORT_REG_RGMII_TIMING_TX_DELAY; + + return mv88e61xx_port_write(phydev, 6, PORT_REG_RGMII_TIMING, val); +#else + return 0; +#endif +} + static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) { int val; @@ -774,6 +796,10 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev) return val; } } else { + val = mv88e61xx_rgmii_timing_cfg(phydev); + if (val < 0) + return val; + val = mv88e61xx_fixed_port_setup(phydev, CONFIG_MV88E61XX_CPU_PORT); if (val < 0)
This is a series of line cards for Allied Telesis's SBx8100 chassis switch. The CPU block is common to the SBx81GP24 and SBx81GT24 cards cards collectively referred to as SBx81LIFXCAT in u-boot.
Signed-off-by: Chris Packham judge.packham@gmail.com ---
arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts | 145 ++++++++++++++++++ arch/arm/mach-kirkwood/Kconfig | 4 + board/alliedtelesis/SBx81LIFXCAT/Kconfig | 12 ++ board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS | 7 + board/alliedtelesis/SBx81LIFXCAT/Makefile | 7 + board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg | 49 ++++++ .../alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c | 134 ++++++++++++++++ configs/SBx81LIFXCAT_defconfig | 44 ++++++ include/configs/SBx81LIFXCAT.h | 114 ++++++++++++++ 9 files changed, 516 insertions(+) create mode 100644 arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts create mode 100644 board/alliedtelesis/SBx81LIFXCAT/Kconfig create mode 100644 board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS create mode 100644 board/alliedtelesis/SBx81LIFXCAT/Makefile create mode 100644 board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg create mode 100644 board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c create mode 100644 configs/SBx81LIFXCAT_defconfig create mode 100644 include/configs/SBx81LIFXCAT.h
diff --git a/arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts b/arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts new file mode 100644 index 000000000000..c23444993623 --- /dev/null +++ b/arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-98dx4122.dtsi" + +/ { + model = "Allied Telesis SBx81LIFXCAT Board"; + compatible = "atl,SBx8LIFXCAT", "marvell,kirkwood-98DX4122", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; /* 128 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + ethernet0 = ð0; + i2c0 = &i2c0; + spi0 = &spi0; + }; + + dsa { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + dsa,ethernet = <ð0>; + dsa,mii-bus = <&mdio>; + status = "okay"; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1 0>; + + port@0 { + reg = <0>; + label = "internal0"; + }; + port@1 { + reg = <1>; + label = "internal1"; + }; + port@8 { + reg = <8>; + label = "internal8"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + port@9 { + reg = <9>; + label = "internal9"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + port@10 { + reg = <10>; + label = "cpu"; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + ledn { + label = "status:ledn"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + }; + + ledp { + label = "status:ledp"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor", "spi-flash"; + reg = <0>; + spi-max-frequency = <50000000>; + mode = <0>; + + partition@u-boot { + reg = <0x00000000 0x00c00000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x00c00000 0x00040000>; + label = "u-boot-env"; + }; + partition@unused { + reg = <0x00100000 0x00f00000>; + label = "unused"; + }; + }; +}; + +&i2c0 { + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; + + gpio3: gpio@76 { + #gpio-cells = <2>; + compatible = "nxp,pca9539"; + reg = <0x76>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 5a5a63cea719..3b860c4f55fe 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -62,6 +62,9 @@ config TARGET_NSA310S config TARGET_SBx81LIFKW bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"
+config TARGET_SBx81LIFXCAT + bool "Allied Telesis SBx81GP24/SBx81GT24" + endchoice
config SYS_SOC @@ -85,5 +88,6 @@ source "board/Seagate/goflexhome/Kconfig" source "board/Seagate/nas220/Kconfig" source "board/zyxel/nsa310s/Kconfig" source "board/alliedtelesis/SBx81LIFKW/Kconfig" +source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
endif diff --git a/board/alliedtelesis/SBx81LIFXCAT/Kconfig b/board/alliedtelesis/SBx81LIFXCAT/Kconfig new file mode 100644 index 000000000000..524c2900892e --- /dev/null +++ b/board/alliedtelesis/SBx81LIFXCAT/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SBx81LIFXCAT + +config SYS_BOARD + default "SBx81LIFXCAT" + +config SYS_VENDOR + default "alliedtelesis" + +config SYS_CONFIG_NAME + default "SBx81LIFXCAT" + +endif diff --git a/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS b/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS new file mode 100644 index 000000000000..6b722ded250e --- /dev/null +++ b/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS @@ -0,0 +1,7 @@ +SBx81LIFXCAT BOARD +M: Chris Packham chris.packham@alliedtelesis.co.nz +S: Maintained +F: board/alliedtelesis/SBx81LIFXCAT/ +F: include/configs/SBx81LIFXCAT +F: configs/SBx81LIFXCAT_defconfig +F: arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts diff --git a/board/alliedtelesis/SBx81LIFXCAT/Makefile b/board/alliedtelesis/SBx81LIFXCAT/Makefile new file mode 100644 index 000000000000..f21c8ef9d6ee --- /dev/null +++ b/board/alliedtelesis/SBx81LIFXCAT/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010, 2018 +# Allied Telesis <www.alliedtelesis.com> +# + +obj-y += sbx81lifxcat.o diff --git a/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg b/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg new file mode 100644 index 000000000000..53d4812f34a2 --- /dev/null +++ b/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2018 Allied Telesis +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed +DATA 0xffd100e0 0x1b1b1b1b +DATA 0xffd20134 0xffffffff +DATA 0xffd20138 0x009fffff +DATA 0xffd20154 0x00000000 +DATA 0xffd2014c 0x00000000 +DATA 0xffd20148 0x00000001 + +# Dram initalization for 1 x x16 +# DDR II Micron part number MT47H64M16HR-3 +# MClk 333MHz, Size 128MB, ECC disable +# +DATA 0xffd01400 0x43000618 +DATA 0xffd01404 0x38543000 +DATA 0xffd01408 0x23125441 +DATA 0xffd0140c 0x00000832 +DATA 0xffd01410 0x0000000D +DATA 0xffd01414 0x00000000 +DATA 0xffd01418 0x00000000 +DATA 0xffd0141c 0x00000652 +DATA 0xffd01420 0x00000042 +DATA 0xffd01424 0x0000F0FF +DATA 0xffd01428 0x00074410 +DATA 0xffd0147C 0x00007441 +DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000 +DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB +DATA 0xffd01508 0x10000000 +DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled +DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled +DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled +DATA 0xffd01494 0x84210000 +DATA 0xffd01498 0x00000000 +DATA 0xffd0149c 0x0000F80F +DATA 0xffd01480 0x00000001 + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c b/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c new file mode 100644 index 000000000000..c584fc0e982f --- /dev/null +++ b/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010, 2018 + * Allied Telesis <www.alliedtelesis.com> + */ + +#include <common.h> +#include <miiphy.h> +#include <netdev.h> +#include <led.h> +#include <linux/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#define SBX81LIFXCAT_OE_LOW (~0) +#define SBX81LIFXCAT_OE_HIGH (~BIT(11)) +#define SBX81LIFXCAT_OE_VAL_LOW (0) +#define SBX81LIFXCAT_OE_VAL_HIGH (BIT(11)) + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(SBX81LIFXCAT_OE_VAL_LOW, + SBX81LIFXCAT_OE_VAL_HIGH, + SBX81LIFXCAT_OE_LOW, SBX81LIFXCAT_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, + MPP13_UART1_TXD, + MPP14_UART1_RXD, + MPP15_GPIO, + MPP16_GPIO, + MPP17_GPIO, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GE1_8, + MPP29_GE1_9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* automatically defined by kirkwood config.h */ +void reset_phy(void) +{ +} +#endif + +#ifdef CONFIG_MV88E61XX_SWITCH +int mv88e61xx_hw_reset(struct phy_device *phydev) +{ + phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full; + + return 0; +} +#endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + struct udevice *dev; + int ret; + + ret = led_get_by_label("status:ledp", &dev); + if (!ret) + led_set_state(dev, LEDST_ON); + + ret = led_get_by_label("status:ledn", &dev); + if (!ret) + led_set_state(dev, LEDST_OFF); + + return 0; +} +#endif diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig new file mode 100644 index 000000000000..89921a5c0d3c --- /dev/null +++ b/configs/SBx81LIFXCAT_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_SYS_TEXT_BASE=0x00600000 +CONFIG_TARGET_SBx81LIFXCAT=y +CONFIG_IDENT_STRING="\nSBx81LIFXCAT" +CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifxcat" +# CONFIG_SYS_MALLOC_F is not set +CONFIG_BOOTDELAY=3 +CONFIG_SILENT_CONSOLE=y +CONFIG_SILENT_U_BOOT_ONLY=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_DHCP=y +CONFIG_BOOTP_NTPSERVER=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +# CONFIG_CMD_LED is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +# CONFIG_MMC is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_MV88E61XX_SWITCH=y +CONFIG_MV88E61XX_CPU_PORT=10 +CONFIG_MV88E61XX_PHY_PORTS=0x003 +CONFIG_MV88E61XX_FIXED_PORTS=0x300 +CONFIG_MV88E61XX_RGMII_DELAY=y +CONFIG_SPI=y +CONFIG_KIRKWOOD_SPI=y diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h new file mode 100644 index 000000000000..0491832feee4 --- /dev/null +++ b/include/configs/SBx81LIFXCAT.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Allied Telesis <www.alliedtelesis.co.nz> + */ + +#ifndef _CONFIG_SBX81LIFXCAT_H +#define _CONFIG_SBX81LIFXCAT_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg +#define CONFIG_BUILD_TARGET "u-boot.kwb" + +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ +#define CONFIG_KIRKWOOD_GPIO 1 + +#define CONFIG_MISC_INIT_R /* call misc_init_r */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" +#define MTDPARTS_MTDOOPS "errlog" +#define CONFIG_DOS_PARTITION + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */ +#define CONFIG_ENV_SIZE 0x02000 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here - 768K */ + +/* + * U-Boot bootcode configuration + */ + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ + +/* size in bytes reserved for initial data */ + +#include <asm/arch/config.h> +/* There is no PHY directly connected so don't ask it for link status */ +#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN + +/* + * Other required minimal configurations + */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi over miiphy interface */ +#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */ +#define CONFIG_PHY_BASE_ADR 0x01 +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#endif /* CONFIG_CMD_NET */ + +#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ + +#endif /* _CONFIG_SBX81LIFXCAT_H */
On Mon, Jun 25, 2018 at 5:34 AM, Chris Packham judge.packham@gmail.com wrote:
Some hardware designs connect a CPU MAC directly to the RGMII interface of a mv88e61xx device. On such devices a delay on the RX/TX lines is required, this can either be achieved by adding extra length to the traces on the PCB or by implementing the delay in silicon. This is an implementation of the latter.
Signed-off-by: Chris Packham judge.packham@gmail.com
drivers/net/phy/Kconfig | 4 ++++ drivers/net/phy/mv88e61xx.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index f5821dfed96d..98cd57eea977 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -59,6 +59,10 @@ config MV88E61XX_PHY_PORTS config MV88E61XX_FIXED_PORTS hex "Bitmask of PHYless serdes Ports"
+config MV88E61XX_RGMII_DELAY
bool "Add delay to RGMII outputs"default n
Not sure why you would need this line. default n is implied, no?
endif # MV88E61XX_SWITCH
config PHYLIB_10G diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index ea54a1531053..d258ba1ef0f3 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -69,6 +69,7 @@ #define PORT_REG_CTRL 0x04 #define PORT_REG_VLAN_MAP 0x06 #define PORT_REG_VLAN_ID 0x07 +#define PORT_REG_RGMII_TIMING 0x1A
/* Phy registers */ #define PHY_REG_CTRL1 0x10 @@ -122,6 +123,9 @@ #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
+#define PORT_REG_RGMII_TIMING_RX_DELAY BIT(10) +#define PORT_REG_RGMII_TIMING_TX_DELAY BIT(9)
#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8 @@ -705,6 +709,24 @@ unforce: return res; }
+static int mv88e61xx_rgmii_timing_cfg(struct phy_device *phydev) +{ +#ifdef CONFIG_MV88E61XX_RGMII_DELAY
It seems like this would be more appropriate as a device tree property rather than a board config.
int val;val = mv88e61xx_port_read(phydev, 6, PORT_REG_RGMII_TIMING);if (val < 0)return val;val |= PORT_REG_RGMII_TIMING_RX_DELAY |PORT_REG_RGMII_TIMING_TX_DELAY;return mv88e61xx_port_write(phydev, 6, PORT_REG_RGMII_TIMING, val);+#else
return 0;+#endif +}
static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) { int val; @@ -774,6 +796,10 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev) return val; } } else {
val = mv88e61xx_rgmii_timing_cfg(phydev);if (val < 0)return val;val = mv88e61xx_fixed_port_setup(phydev, CONFIG_MV88E61XX_CPU_PORT); if (val < 0)-- 2.18.0
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On Tue, Jun 26, 2018 at 6:10 AM Joe Hershberger joe.hershberger@ni.com wrote:
On Mon, Jun 25, 2018 at 5:34 AM, Chris Packham judge.packham@gmail.com wrote:
Some hardware designs connect a CPU MAC directly to the RGMII interface of a mv88e61xx device. On such devices a delay on the RX/TX lines is required, this can either be achieved by adding extra length to the traces on the PCB or by implementing the delay in silicon. This is an implementation of the latter.
Signed-off-by: Chris Packham judge.packham@gmail.com
drivers/net/phy/Kconfig | 4 ++++ drivers/net/phy/mv88e61xx.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index f5821dfed96d..98cd57eea977 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -59,6 +59,10 @@ config MV88E61XX_PHY_PORTS config MV88E61XX_FIXED_PORTS hex "Bitmask of PHYless serdes Ports"
+config MV88E61XX_RGMII_DELAY
bool "Add delay to RGMII outputs"default nNot sure why you would need this line. default n is implied, no?
I'll remove it in v2.
endif # MV88E61XX_SWITCH
config PHYLIB_10G diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index ea54a1531053..d258ba1ef0f3 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -69,6 +69,7 @@ #define PORT_REG_CTRL 0x04 #define PORT_REG_VLAN_MAP 0x06 #define PORT_REG_VLAN_ID 0x07 +#define PORT_REG_RGMII_TIMING 0x1A
/* Phy registers */ #define PHY_REG_CTRL1 0x10 @@ -122,6 +123,9 @@ #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
+#define PORT_REG_RGMII_TIMING_RX_DELAY BIT(10) +#define PORT_REG_RGMII_TIMING_TX_DELAY BIT(9)
#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8 @@ -705,6 +709,24 @@ unforce: return res; }
+static int mv88e61xx_rgmii_timing_cfg(struct phy_device *phydev) +{ +#ifdef CONFIG_MV88E61XX_RGMII_DELAY
It seems like this would be more appropriate as a device tree property rather than a board config.
Yes, as would the assignment of ports. It would make sense to follow the dsa bindings used by Linux which would be a fairly significant piece of work.
int val;val = mv88e61xx_port_read(phydev, 6, PORT_REG_RGMII_TIMING);if (val < 0)return val;val |= PORT_REG_RGMII_TIMING_RX_DELAY |PORT_REG_RGMII_TIMING_TX_DELAY;return mv88e61xx_port_write(phydev, 6, PORT_REG_RGMII_TIMING, val);+#else
return 0;+#endif +}
static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) { int val; @@ -774,6 +796,10 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev) return val; } } else {
val = mv88e61xx_rgmii_timing_cfg(phydev);if (val < 0)return val;val = mv88e61xx_fixed_port_setup(phydev, CONFIG_MV88E61XX_CPU_PORT); if (val < 0)-- 2.18.0
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On Tue, Jun 26, 2018 at 5:34 AM, Chris Packham judge.packham@gmail.com wrote:
On Tue, Jun 26, 2018 at 6:10 AM Joe Hershberger joe.hershberger@ni.com wrote:
On Mon, Jun 25, 2018 at 5:34 AM, Chris Packham judge.packham@gmail.com wrote:
Some hardware designs connect a CPU MAC directly to the RGMII interface of a mv88e61xx device. On such devices a delay on the RX/TX lines is required, this can either be achieved by adding extra length to the traces on the PCB or by implementing the delay in silicon. This is an implementation of the latter.
Signed-off-by: Chris Packham judge.packham@gmail.com
drivers/net/phy/Kconfig | 4 ++++ drivers/net/phy/mv88e61xx.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index f5821dfed96d..98cd57eea977 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -59,6 +59,10 @@ config MV88E61XX_PHY_PORTS config MV88E61XX_FIXED_PORTS hex "Bitmask of PHYless serdes Ports"
+config MV88E61XX_RGMII_DELAY
bool "Add delay to RGMII outputs"default nNot sure why you would need this line. default n is implied, no?
I'll remove it in v2.
endif # MV88E61XX_SWITCH
config PHYLIB_10G diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index ea54a1531053..d258ba1ef0f3 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -69,6 +69,7 @@ #define PORT_REG_CTRL 0x04 #define PORT_REG_VLAN_MAP 0x06 #define PORT_REG_VLAN_ID 0x07 +#define PORT_REG_RGMII_TIMING 0x1A
/* Phy registers */ #define PHY_REG_CTRL1 0x10 @@ -122,6 +123,9 @@ #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
+#define PORT_REG_RGMII_TIMING_RX_DELAY BIT(10) +#define PORT_REG_RGMII_TIMING_TX_DELAY BIT(9)
#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8 @@ -705,6 +709,24 @@ unforce: return res; }
+static int mv88e61xx_rgmii_timing_cfg(struct phy_device *phydev) +{ +#ifdef CONFIG_MV88E61XX_RGMII_DELAY
It seems like this would be more appropriate as a device tree property rather than a board config.
Yes, as would the assignment of ports. It would make sense to follow the dsa bindings used by Linux which would be a fairly significant piece of work.
By that do you mean too much work?
int val;val = mv88e61xx_port_read(phydev, 6, PORT_REG_RGMII_TIMING);if (val < 0)return val;val |= PORT_REG_RGMII_TIMING_RX_DELAY |PORT_REG_RGMII_TIMING_TX_DELAY;return mv88e61xx_port_write(phydev, 6, PORT_REG_RGMII_TIMING, val);+#else
return 0;+#endif +}
static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) { int val; @@ -774,6 +796,10 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev) return val; } } else {
val = mv88e61xx_rgmii_timing_cfg(phydev);if (val < 0)return val;val = mv88e61xx_fixed_port_setup(phydev, CONFIG_MV88E61XX_CPU_PORT); if (val < 0)-- 2.18.0
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U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On Wed, Jun 27, 2018 at 2:25 AM Joe Hershberger joe.hershberger@ni.com wrote:
On Tue, Jun 26, 2018 at 5:34 AM, Chris Packham judge.packham@gmail.com wrote:
On Tue, Jun 26, 2018 at 6:10 AM Joe Hershberger joe.hershberger@ni.com wrote:
On Mon, Jun 25, 2018 at 5:34 AM, Chris Packham judge.packham@gmail.com wrote:
Some hardware designs connect a CPU MAC directly to the RGMII interface of a mv88e61xx device. On such devices a delay on the RX/TX lines is required, this can either be achieved by adding extra length to the traces on the PCB or by implementing the delay in silicon. This is an implementation of the latter.
Signed-off-by: Chris Packham judge.packham@gmail.com
drivers/net/phy/Kconfig | 4 ++++ drivers/net/phy/mv88e61xx.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index f5821dfed96d..98cd57eea977 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -59,6 +59,10 @@ config MV88E61XX_PHY_PORTS config MV88E61XX_FIXED_PORTS hex "Bitmask of PHYless serdes Ports"
+config MV88E61XX_RGMII_DELAY
bool "Add delay to RGMII outputs"default nNot sure why you would need this line. default n is implied, no?
I'll remove it in v2.
endif # MV88E61XX_SWITCH
config PHYLIB_10G diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index ea54a1531053..d258ba1ef0f3 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -69,6 +69,7 @@ #define PORT_REG_CTRL 0x04 #define PORT_REG_VLAN_MAP 0x06 #define PORT_REG_VLAN_ID 0x07 +#define PORT_REG_RGMII_TIMING 0x1A
/* Phy registers */ #define PHY_REG_CTRL1 0x10 @@ -122,6 +123,9 @@ #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
+#define PORT_REG_RGMII_TIMING_RX_DELAY BIT(10) +#define PORT_REG_RGMII_TIMING_TX_DELAY BIT(9)
#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8 @@ -705,6 +709,24 @@ unforce: return res; }
+static int mv88e61xx_rgmii_timing_cfg(struct phy_device *phydev) +{ +#ifdef CONFIG_MV88E61XX_RGMII_DELAY
It seems like this would be more appropriate as a device tree property rather than a board config.
Yes, as would the assignment of ports. It would make sense to follow the dsa bindings used by Linux which would be a fairly significant piece of work.
By that do you mean too much work?
Certainly more work than I have time for u-boot hacking. I can add it to my "someday" list.
One pre-requisite for the full dsa switch binding would be the mdio bus uclass (added Ken to the Cc list). We could come up with some u-boot specific device tree bindings which would be easier to implement at the cost of the device trees deviating from Linux.
int val;val = mv88e61xx_port_read(phydev, 6, PORT_REG_RGMII_TIMING);if (val < 0)return val;val |= PORT_REG_RGMII_TIMING_RX_DELAY |PORT_REG_RGMII_TIMING_TX_DELAY;return mv88e61xx_port_write(phydev, 6, PORT_REG_RGMII_TIMING, val);+#else
return 0;+#endif +}
static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) { int val; @@ -774,6 +796,10 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev) return val; } } else {
val = mv88e61xx_rgmii_timing_cfg(phydev);if (val < 0)return val;val = mv88e61xx_fixed_port_setup(phydev, CONFIG_MV88E61XX_CPU_PORT); if (val < 0)-- 2.18.0
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participants (2)
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Chris Packham -
Joe Hershberger