This is Marvell's Kirkwood development board. It has the following features

- 512M DDR2 - 2 PCI connectors - 1 x1 PCI-e interface - 1 Gigabit Ethernet Port - 2 SATA Ports - USB 2.0 Interface - SDIO - 128M NAND Flash - 16M SPI Flash

It can be strapped to boot from SPI or NAND.

Signed-off-by: Chris Packham judge.packham@gmail.com ---

arch/arm/dts/kirkwood-db-88f6281-spi.dts | 48 +++++++++ arch/arm/dts/kirkwood-db-88f6281.dts | 26 +++++ arch/arm/dts/kirkwood-db.dtsi | 94 +++++++++++++++++ arch/arm/mach-kirkwood/Kconfig | 4 + board/Marvell/db-88f6281-bp/Kconfig | 12 +++ board/Marvell/db-88f6281-bp/MAINTAINERS | 10 ++ board/Marvell/db-88f6281-bp/Makefile | 3 + board/Marvell/db-88f6281-bp/db-88f6281-bp.c | 103 +++++++++++++++++++ board/Marvell/db-88f6281-bp/kwbimage.cfg | 36 +++++++ configs/db-88f6281-bp-spi_defconfig | 54 ++++++++++ configs/db-88f6281-bp_defconfig | 53 ++++++++++ include/configs/db-88f6281-bp.h | 107 ++++++++++++++++++++ 12 files changed, 550 insertions(+) create mode 100644 arch/arm/dts/kirkwood-db-88f6281-spi.dts create mode 100644 arch/arm/dts/kirkwood-db-88f6281.dts create mode 100644 arch/arm/dts/kirkwood-db.dtsi create mode 100644 board/Marvell/db-88f6281-bp/Kconfig create mode 100644 board/Marvell/db-88f6281-bp/MAINTAINERS create mode 100644 board/Marvell/db-88f6281-bp/Makefile create mode 100644 board/Marvell/db-88f6281-bp/db-88f6281-bp.c create mode 100644 board/Marvell/db-88f6281-bp/kwbimage.cfg create mode 100644 configs/db-88f6281-bp-spi_defconfig create mode 100644 configs/db-88f6281-bp_defconfig create mode 100644 include/configs/db-88f6281-bp.h

diff --git a/arch/arm/dts/kirkwood-db-88f6281-spi.dts b/arch/arm/dts/kirkwood-db-88f6281-spi.dts new file mode 100644 index 000000000000..50b1b0d4a535 --- /dev/null +++ b/arch/arm/dts/kirkwood-db-88f6281-spi.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell DB-88F6281-BP Development Board Setup + * + * Saeed Bishara saeed@marvell.com + * Thomas Petazzoni thomas.petazzoni@free-electrons.com + * + */ + +/dts-v1/; + +#include "kirkwood-db-88f6281.dts" + +/ { + aliases { + spi0 = &spi0; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor", "spi-flash"; + reg = <0>; + spi-max-frequency = <50000000>; + mode = <0>; + + partition@u-boot { + reg = <0x00000000 0x00c00000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x00c00000 0x00040000>; + label = "u-boot-env"; + }; + partition@unused { + reg = <0x00100000 0x00f00000>; + label = "unused"; + }; + }; +}; + +&nand { + status = "disabled"; +}; diff --git a/arch/arm/dts/kirkwood-db-88f6281.dts b/arch/arm/dts/kirkwood-db-88f6281.dts new file mode 100644 index 000000000000..2adb17c955aa --- /dev/null +++ b/arch/arm/dts/kirkwood-db-88f6281.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell DB-88F6281-BP Development Board Setup + * + * Saeed Bishara saeed@marvell.com + * Thomas Petazzoni thomas.petazzoni@free-electrons.com + * + */ + +/dts-v1/; + +#include "kirkwood-db.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Marvell DB-88F6281-BP Development Board"; + compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/dts/kirkwood-db.dtsi b/arch/arm/dts/kirkwood-db.dtsi new file mode 100644 index 000000000000..b81d8e8298a3 --- /dev/null +++ b/arch/arm/dts/kirkwood-db.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Marvell DB-{88F6281,88F6282}-BP Development Board Setup + * + * Saeed Bishara saeed@marvell.com + * Thomas Petazzoni thomas.petazzoni@free-electrons.com + * + * This file contains the definitions that are common between the 6281 + * and 6282 variants of the Marvell Kirkwood Development Board. + */ + +#include "kirkwood.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + aliases { + ethernet0 = &eth0; + spi0 = &spi0; + }; + + ocp@f1000000 { + pin-controller@10000 { + pmx_sdio_gpios: pmx-sdio-gpios { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + nr-ports = <2>; + status = "okay"; + }; + + ehci@50000 { + status = "okay"; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio_gpios>; + pinctrl-names = "default"; + wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&nand { + chip-delay = <25>; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x1fb00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +&eth0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <&ethphy0>; + }; +}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 3b860c4f55fe..7c4170399afb 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -65,6 +65,9 @@ config TARGET_SBx81LIFKW config TARGET_SBx81LIFXCAT bool "Allied Telesis SBx81GP24/SBx81GT24"

+config TARGET_DB_88F6281_BP + bool "Marvell DB-88F6281-BP" + endchoice

config SYS_SOC @@ -89,5 +92,6 @@ source "board/Seagate/nas220/Kconfig" source "board/zyxel/nsa310s/Kconfig" source "board/alliedtelesis/SBx81LIFKW/Kconfig" source "board/alliedtelesis/SBx81LIFXCAT/Kconfig" +source "board/Marvell/db-88f6281-bp/Kconfig"

endif diff --git a/board/Marvell/db-88f6281-bp/Kconfig b/board/Marvell/db-88f6281-bp/Kconfig new file mode 100644 index 000000000000..38467399e688 --- /dev/null +++ b/board/Marvell/db-88f6281-bp/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DB_88F6281_BP + +config SYS_BOARD + default "db-88f6281-bp" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "db-88f6281-bp" + +endif diff --git a/board/Marvell/db-88f6281-bp/MAINTAINERS b/board/Marvell/db-88f6281-bp/MAINTAINERS new file mode 100644 index 000000000000..f31d3be70bae --- /dev/null +++ b/board/Marvell/db-88f6281-bp/MAINTAINERS @@ -0,0 +1,10 @@ +DB_88F6820_AMC BOARD +M: Chris Packham judge.packham@gmail.com +S: Maintained +F: arch/arm/dts/kirkwood-db-88f6281.dts +F: arch/arm/dts/kirkwood-db-88f6281-spi.dts +F: arch/arm/dts/kirkwood-db.dtsi +F: board/Marvell/db-88f6281-bp/ +F: include/configs/db-88f6281-bp.h +F: configs/db-88f6281-bp_defconfig +F: configs/db-88f6281-bp-spi_defconfig diff --git a/board/Marvell/db-88f6281-bp/Makefile b/board/Marvell/db-88f6281-bp/Makefile new file mode 100644 index 000000000000..38ff522ca1c8 --- /dev/null +++ b/board/Marvell/db-88f6281-bp/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := db-88f6281-bp.o diff --git a/board/Marvell/db-88f6281-bp/db-88f6281-bp.c b/board/Marvell/db-88f6281-bp/db-88f6281-bp.c new file mode 100644 index 000000000000..b68f2f3c895b --- /dev/null +++ b/board/Marvell/db-88f6281-bp/db-88f6281-bp.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <linux/io.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#define DB_88F6281_OE_LOW ~(BIT(7)) +#define DB_88F6281_OE_HIGH ~(BIT(15) | BIT(14) | BIT(13) | BIT(4)) +#define DB_88F6281_OE_VAL_LOW BIT(7) +#define DB_88F6281_OE_VAL_HIGH 0 + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + mvebu_config_gpio(DB_88F6281_OE_VAL_LOW, + DB_88F6281_OE_VAL_HIGH, + DB_88F6281_OE_LOW, DB_88F6281_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { +#ifdef CONFIG_CMD_NAND + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, +#else + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, +#endif + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* automatically defined by kirkwood config.h */ +void reset_phy(void) +{ +} +#endif diff --git a/board/Marvell/db-88f6281-bp/kwbimage.cfg b/board/Marvell/db-88f6281-bp/kwbimage.cfg new file mode 100644 index 000000000000..49a637078682 --- /dev/null +++ b/board/Marvell/db-88f6281-bp/kwbimage.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xd00100e0 0x1b1b1b9b +DATA 0xd0020134 0xbbbbbbbb +DATA 0xd0020138 0x00bbbbbb +DATA 0xd0020154 0x00000200 +DATA 0xd002014c 0x00001c00 +DATA 0xd0020148 0x00000001 + +DATA 0xd0001400 0x43000c30 +DATA 0xd0001404 0x39543000 +DATA 0xd0001408 0x22125451 +DATA 0xd000140c 0x00000833 +DATA 0xd0001410 0x000000cc +DATA 0xd0001414 0x00000000 +DATA 0xd0001418 0x00000000 +DATA 0xd000141c 0x00000c52 +DATA 0xd0001420 0x00000044 +DATA 0xd0001424 0x0000f1ff +DATA 0xd0001428 0x00085520 +DATA 0xd000147c 0x00008552 +DATA 0xd0001504 0x0ffffff1 +DATA 0xd0001508 0x10000000 +DATA 0xd000150c 0x0ffffff5 +DATA 0xd0001514 0x00000000 +DATA 0xd000151c 0x00000000 +DATA 0xd0001494 0x84210000 +DATA 0xd0001498 0x00000000 +DATA 0xd000149c 0x0000f40f +DATA 0xd0001480 0x00000001 + +# End of Header extension +DATA 0x0 0x0 diff --git a/configs/db-88f6281-bp-spi_defconfig b/configs/db-88f6281-bp-spi_defconfig new file mode 100644 index 000000000000..93e125af5b2d --- /dev/null +++ b/configs/db-88f6281-bp-spi_defconfig @@ -0,0 +1,54 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_KIRKWOOD=y +CONFIG_SYS_TEXT_BASE=0x600000 +CONFIG_TARGET_DB_88F6281_BP=y +CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP" +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_IDE=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" +CONFIG_ISO_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="kirkwood-db-88f6281-spi" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_MVSATA_IDE=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MARVELL=y +CONFIG_DM_ETH=y +CONFIG_MVGBE=y +CONFIG_MII=y +CONFIG_DM_RTC=y +CONFIG_RTC_MV=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_LZMA=y +CONFIG_LZO=y diff --git a/configs/db-88f6281-bp_defconfig b/configs/db-88f6281-bp_defconfig new file mode 100644 index 000000000000..6360ef5e8280 --- /dev/null +++ b/configs/db-88f6281-bp_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_KIRKWOOD=y +CONFIG_SYS_TEXT_BASE=0x600000 +CONFIG_TARGET_DB_88F6281_BP=y +CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP" +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_IDE=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" +CONFIG_ISO_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="kirkwood-db-88f6281" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_MVSATA_IDE=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MARVELL=y +CONFIG_DM_ETH=y +CONFIG_MVGBE=y +CONFIG_MII=y +CONFIG_DM_RTC=y +CONFIG_RTC_MV=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_LZMA=y +CONFIG_LZO=y diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h new file mode 100644 index 000000000000..e2da9fdacf29 --- /dev/null +++ b/include/configs/db-88f6281-bp.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _CONFIG_DB_88F6281_BP_H +#define _CONFIG_DB_88F6281_BP_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_TCLK 166666667 +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg +#define CONFIG_BUILD_TARGET "u-boot.kwb" + +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ +#define CONFIG_KIRKWOOD_GPIO 1 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */ +#define CONFIG_ENV_SIZE 0x01000 +#define CONFIG_ENV_OFFSET 0xC0000 + +/* + * U-Boot bootcode configuration + */ + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ + +/* size in bytes reserved for initial data */ + +#include <asm/arch/config.h> +/* There is no PHY directly connected so don't ask it for link status */ +#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN + +/* + * Other required minimal configurations + */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + +/* + * SDIO/MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MVEBU_MMC +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE +#endif /* CONFIG_CMD_MMC */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ + +#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ + +#endif /* _CONFIG_DB_88F6281_BP_H */

KW_DEFADR_PCI_IO_REMAP has the same value as KW_DEFADR_PCI_IO and is only used to set up a 1:1 mapping. Remove it and update the mapping to use KW_DEFADR_PCI_IO.

Signed-off-by: Chris Packham judge.packham@gmail.com ---

arch/arm/mach-kirkwood/cpu.c | 2 +- arch/arm/mach-kirkwood/include/mach/cpu.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 1e733dc5fbc1..95dd07f840ca 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -76,7 +76,7 @@ int kw_config_adr_windows(void) writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl); writel(KW_DEFADR_PCI_IO, &winregs[1].base); - writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo); + writel(KW_DEFADR_PCI_IO, &winregs[1].remap_lo); writel(0x0, &winregs[1].remap_hi);

/* Window 2: NAND Flash address space */ diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index 91d21518d852..c35cace844ae 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -63,7 +63,6 @@ enum kwcpu_attrib { */ #define KW_DEFADR_PCI_MEM 0x90000000 #define KW_DEFADR_PCI_IO 0xC0000000 -#define KW_DEFADR_PCI_IO_REMAP 0xC0000000 #define KW_DEFADR_SASRAM 0xC8010000 #define KW_DEFADR_NANDF 0xD8000000 #define KW_DEFADR_SPIF 0xE8000000

Now that kirkwood is using the mvebu mbus this function is no longer needed.

Signed-off-by: Chris Packham judge.packham@gmail.com ---

arch/arm/mach-kirkwood/cpu.c | 64 ----------------------- arch/arm/mach-kirkwood/include/mach/cpu.h | 1 - 2 files changed, 65 deletions(-)

diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 009b49287b7f..8b21db107153 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -46,70 +46,6 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval) return (0x0000ffff & j); }

-/* - * kw_config_adr_windows - Configure address Windows - * - * There are 8 address windows supported by Kirkwood Soc to addess different - * devices. Each window can be configured for size, BAR and remap addr - * Below configuration is standard for most of the cases - * - * If remap function not used, remap_lo must be set as base - * - * Reference Documentation: - * Mbus-L to Mbus Bridge Registers Configuration. - * (Sec 25.1 and 25.3 of Datasheet) - */ -int kw_config_adr_windows(void) -{ - struct kwwin_registers *winregs = - (struct kwwin_registers *)MVEBU_CPU_WIN_BASE; - - /* Window 0: PCIE MEM address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE, - KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl); - - writel(KW_DEFADR_PCI_MEM, &winregs[0].base); - writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo); - writel(0x0, &winregs[0].remap_hi); - - /* Window 1: PCIE IO address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE, - KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl); - writel(KW_DEFADR_PCI_IO, &winregs[1].base); - writel(KW_DEFADR_PCI_IO, &winregs[1].remap_lo); - writel(0x0, &winregs[1].remap_hi); - - /* Window 2: NAND Flash address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, - KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl); - writel(KW_DEFADR_NANDF, &winregs[2].base); - writel(KW_DEFADR_NANDF, &winregs[2].remap_lo); - writel(0x0, &winregs[2].remap_hi); - - /* Window 3: SPI Flash address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, - KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl); - writel(KW_DEFADR_SPIF, &winregs[3].base); - writel(KW_DEFADR_SPIF, &winregs[3].remap_lo); - writel(0x0, &winregs[3].remap_hi); - - /* Window 4: BOOT Memory address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, - KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl); - writel(KW_DEFADR_BOOTROM, &winregs[4].base); - - /* Window 5: Security SRAM address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM, - KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl); - writel(KW_DEFADR_SASRAM, &winregs[5].base); - - /* Window 6-7: Disabled */ - writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl); - writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl); - - return 0; -} - static struct mbus_win windows[] = { /* Window 0: PCIE MEM address space */ { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256, diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index 3d6b15568a8a..ea42182cf9c6 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -150,7 +150,6 @@ extern struct mvebu_mbus_state mbus_state; unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); -int kw_config_adr_windows(void); int mvebu_mbus_probe(struct mbus_win windows[], int count); void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe);