Copy the best rational approximation calculation routines from Linux. Typical usecase for these routines is to calculate the M/N divider values for PLLs to reach a specific clock rate.

Signed-off-by: Tero Kristo t-kristo@ti.com --- include/linux/rational.h | 20 ++++++++ lib/Kconfig | 7 +++ lib/Makefile | 2 + lib/rational.c | 99 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 128 insertions(+) create mode 100644 include/linux/rational.h create mode 100644 lib/rational.c

diff --git a/include/linux/rational.h b/include/linux/rational.h new file mode 100644 index 0000000000..33f5f5fc3e --- /dev/null +++ b/include/linux/rational.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * rational fractions + * + * Copyright (C) 2009 emlix GmbH, Oskar Schirmer oskar@scara.com + * + * helper functions when coping with rational numbers, + * e.g. when calculating optimum numerator/denominator pairs for + * pll configuration taking into account restricted register size + */ + +#ifndef _LINUX_RATIONAL_H +#define _LINUX_RATIONAL_H + +void rational_best_approximation( + unsigned long given_numerator, unsigned long given_denominator, + unsigned long max_numerator, unsigned long max_denominator, + unsigned long *best_numerator, unsigned long *best_denominator); + +#endif /* _LINUX_RATIONAL_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 37aae73a26..2c6021c486 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -660,6 +660,13 @@ config SMBIOS_PRODUCT_NAME The product name to store in SMBIOS structures. Change this to override the default one (CONFIG_SYS_BOARD).

+config LIB_RATIONAL + bool "enable continued fraction calculation routines" + +config SPL_LIB_RATIONAL + bool "enable continued fraction calculation routines for SPL" + depends on SPL + endmenu

config ASN1_COMPILER diff --git a/lib/Makefile b/lib/Makefile index 0cd7bea282..b921691169 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -70,6 +70,8 @@ obj-$(CONFIG_$(SPL_)LZO) += lzo/ obj-$(CONFIG_$(SPL_)LZMA) += lzma/ obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o

+obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o + obj-$(CONFIG_LIBAVB) += libavb/

obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/ diff --git a/lib/rational.c b/lib/rational.c new file mode 100644 index 0000000000..316db3b590 --- /dev/null +++ b/lib/rational.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rational fractions + * + * Copyright (C) 2009 emlix GmbH, Oskar Schirmer oskar@scara.com + * Copyright (C) 2019 Trent Piepho tpiepho@gmail.com + * + * helper functions when coping with rational numbers + */ + +#include <linux/rational.h> +#include <linux/compiler.h> +#include <linux/kernel.h> + +/* + * calculate best rational approximation for a given fraction + * taking into account restricted register size, e.g. to find + * appropriate values for a pll with 5 bit denominator and + * 8 bit numerator register fields, trying to set up with a + * frequency ratio of 3.1415, one would say: + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ + +void rational_best_approximation( + unsigned long given_numerator, unsigned long given_denominator, + unsigned long max_numerator, unsigned long max_denominator, + unsigned long *best_numerator, unsigned long *best_denominator) +{ + /* n/d is the starting rational, which is continually + * decreased each iteration using the Euclidean algorithm. + * + * dp is the value of d from the prior iteration. + * + * n2/d2, n1/d1, and n0/d0 are our successively more accurate + * approximations of the rational. They are, respectively, + * the current, previous, and two prior iterations of it. + * + * a is current term of the continued fraction. + */ + unsigned long n, d, n0, d0, n1, d1, n2, d2; + n = given_numerator; + d = given_denominator; + n0 = d1 = 0; + n1 = d0 = 1; + + for (;;) { + unsigned long dp, a; + + if (d == 0) + break; + /* Find next term in continued fraction, 'a', via + * Euclidean algorithm. + */ + dp = d; + a = n / d; + d = n % d; + n = dp; + + /* Calculate the current rational approximation (aka + * convergent), n2/d2, using the term just found and + * the two prior approximations. + */ + n2 = n0 + a * n1; + d2 = d0 + a * d1; + + /* If the current convergent exceeds the maxes, then + * return either the previous convergent or the + * largest semi-convergent, the final term of which is + * found below as 't'. + */ + if ((n2 > max_numerator) || (d2 > max_denominator)) { + unsigned long t = min((max_numerator - n0) / n1, + (max_denominator - d0) / d1); + + /* This tests if the semi-convergent is closer + * than the previous convergent. + */ + if (2u * t > a || (2u * t == a && d0 * dp > d1 * d)) { + n1 = n0 + t * n1; + d1 = d0 + t * d1; + } + break; + } + n0 = n1; + n1 = n2; + d0 = d1; + d1 = d2; + } + *best_numerator = n1; + *best_denominator = d1; +}

With the sysfw rearch, sysfw PM calls are no longer available from SPL level. To properly support this, remove the is_on checks and the reset assertion from the R5 remoteproc driver as these are not supported. Attempting to access unavailable services will cause the device to hang.

Signed-off-by: Tero Kristo t-kristo@ti.com --- drivers/remoteproc/ti_k3_r5f_rproc.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 9332a63d21..b2902e7fd3 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -781,7 +781,9 @@ static int k3_r5f_probe(struct udevice *dev) { struct k3_r5f_cluster *cluster = dev_get_priv(dev->parent); struct k3_r5f_core *core = dev_get_priv(dev); +#ifdef CONFIG_CLK_TI_SCI bool r_state; +#endif int ret;

dev_dbg(dev, "%s\n", __func__); @@ -804,6 +806,7 @@ static int k3_r5f_probe(struct udevice *dev) return ret; }

+#ifdef CONFIG_CLK_TI_SCI ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id, &r_state, &core->in_use); if (ret) @@ -817,6 +820,7 @@ static int k3_r5f_probe(struct udevice *dev)

/* Make sure Local reset is asserted. Redundant? */ reset_assert(&core->reset); +#endif

ret = k3_r5f_rproc_configure(core); if (ret) {

Current driver only supports registering fixed rate clocks from DT. Add new API which makes it possible to register fixed rate clocks directly from e.g. platform specific clock drivers.

Signed-off-by: Tero Kristo t-kristo@ti.com --- drivers/clk/clk_fixed_rate.c | 45 +++++++++++++++++++++++++++++++++++- include/linux/clk-provider.h | 3 +++ 2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 55e1f8caa5..5556acaf86 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -8,6 +8,9 @@ #include <dm.h> #include <linux/clk-provider.h>

+#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock" +#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock" + static ulong clk_fixed_rate_get_rate(struct clk *clk) { return to_clk_fixed_rate(clk->dev)->fixed_rate; @@ -24,6 +27,15 @@ const struct clk_ops clk_fixed_rate_ops = { .enable = dummy_enable, };

+static ulong clk_fixed_rate_raw_get_rate(struct clk *clk) +{ + return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate; +} + +const struct clk_ops clk_fixed_rate_raw_ops = { + .get_rate = clk_fixed_rate_raw_get_rate, +}; + static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) { struct clk *clk = &to_clk_fixed_rate(dev)->clk; @@ -39,6 +51,30 @@ static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) return 0; }

+struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + ulong rate) +{ + struct clk *clk; + struct clk_fixed_rate *fixed; + int ret; + + fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); + if (!fixed) + return ERR_PTR(-ENOMEM); + + fixed->fixed_rate = rate; + + clk = &fixed->clk; + + ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL); + if (ret) { + kfree(fixed); + return ERR_PTR(ret); + } + + return clk; +} + static const struct udevice_id clk_fixed_rate_match[] = { { .compatible = "fixed-clock", @@ -47,7 +83,7 @@ static const struct udevice_id clk_fixed_rate_match[] = { };

U_BOOT_DRIVER(clk_fixed_rate) = { - .name = "fixed_rate_clock", + .name = UBOOT_DM_CLK_FIXED_RATE, .id = UCLASS_CLK, .of_match = clk_fixed_rate_match, .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata, @@ -55,3 +91,10 @@ U_BOOT_DRIVER(clk_fixed_rate) = { .ops = &clk_fixed_rate_ops, .flags = DM_FLAG_PRE_RELOC, }; + +U_BOOT_DRIVER(clk_fixed_rate_raw) = { + .name = UBOOT_DM_CLK_FIXED_RATE_RAW, + .id = UCLASS_CLK, + .ops = &clk_fixed_rate_raw_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 79dce8f0ad..6b50c42214 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -186,6 +186,9 @@ struct clk *clk_register_mux(struct device *dev, const char *name, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags);

+struct clk *clk_register_fixed_rate(struct device *dev, const char *name, + ulong rate); + const char *clk_hw_get_name(const struct clk *hw); ulong clk_generic_get_rate(struct clk *clk);

Add new clk subcommand "clk setfreq", for setting up a clock rate directly from u-boot cmdline. This is handy for any debugging purposes towards clocks.

Signed-off-by: Tero Kristo t-kristo@ti.com --- cmd/clk.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/cmd/clk.c b/cmd/clk.c index 0245b97136..fd7944c02e 100644 --- a/cmd/clk.c +++ b/cmd/clk.c @@ -98,8 +98,52 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int argc, return ret; }

+struct udevice *clk_lookup(const char *name) +{ + int i = 0; + struct udevice *dev; + + do { + uclass_get_device(UCLASS_CLK, i++, &dev); + if (!strcmp(name, dev->name)) + return dev; + } while (dev); + + return NULL; +} + +static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct clk *clk = NULL; + s32 freq; + struct udevice *dev; + + freq = simple_strtoul(argv[2], NULL, 10); + + dev = clk_lookup(argv[1]); + + if (dev) + clk = dev_get_clk_ptr(dev); + + if (!clk) { + printf("clock '%s' not found.\n", argv[1]); + return -EINVAL; + } + + freq = clk_set_rate(clk, freq); + if (freq < 0) { + printf("set_rate failed: %d\n", freq); + return CMD_RET_FAILURE; + } + + printf("set_rate returns %u\n", freq); + return 0; +} + static struct cmd_tbl cmd_clk_sub[] = { U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""), + U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""), };

static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc, @@ -124,7 +168,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,

#ifdef CONFIG_SYS_LONGHELP static char clk_help_text[] = - "dump - Print clock frequencies"; + "dump - Print clock frequencies\n" + "setfreq [clk] [freq] - Set clock frequency"; #endif

-U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text); +U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);

Set rate should return the new clock rate on success, and negative error value on failure. Fix this, as currently set_rate returns 0 on success.

Signed-off-by: Tero Kristo t-kristo@ti.com --- drivers/clk/clk-ti-sci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-ti-sci.c b/drivers/clk/clk-ti-sci.c index 7a9a645137..e2ad18e96b 100644 --- a/drivers/clk/clk-ti-sci.c +++ b/drivers/clk/clk-ti-sci.c @@ -111,10 +111,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong rate) #endif

ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX); - if (ret) + if (ret) { dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret); + return ret; + }

- return ret; + return rate; }

static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent)

Clock rates are cached within the individual clock nodes, and right now if one changes a clock rate somewhere in the middle of the tree, none of its child clocks notice the change. To fix this, clear up all the cached rates for us and our child clocks.

Signed-off-by: Tero Kristo t-kristo@ti.com --- drivers/clk/clk-uclass.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 79d5af3d1f..9a5c061304 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -544,6 +544,22 @@ long long clk_get_parent_rate(struct clk *clk) return pclk->rate; }

+static void clk_clean_rate_cache(struct clk *clk) +{ + struct udevice *child_dev; + struct clk *clkp; + + if (!clk) + return; + + clk->rate = 0; + + list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) { + clkp = dev_get_clk_ptr(child_dev); + clk_clean_rate_cache(clkp); + } +} + ulong clk_set_rate(struct clk *clk, ulong rate) { const struct clk_ops *ops; @@ -556,6 +572,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate) if (!ops->set_rate) return -ENOSYS;

+ /* Clean up cached rates for us and all child clocks */ + clk_clean_rate_cache(clk); + return ops->set_rate(clk, rate); }

Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles.

Signed-off-by: Tero Kristo t-kristo@ti.com --- drivers/clk/Kconfig | 10 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-k3.c | 340 +++++++++++++++++++++++++++++++++++++++++++ include/k3-clk.h | 162 +++++++++++++++++++++ 4 files changed, 513 insertions(+) create mode 100644 drivers/clk/clk-k3.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b2e9458f85..003a28f7ac 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -106,6 +106,16 @@ config CLK_TI_SCI available on some new TI's SoCs. If you wish to use clock resources managed by the TI System Controller, say Y here. Otherwise, say N.

+config CLK_K3 + bool "Clock support for K3 SoC family of devices" + depends on CLK + help + Enables the clock translation layer from DT to device clocks. + +config SPL_CLK_K3 + bool "Clock support for K3 SoC family of devices" + depends on CLK && SPL + config CLK_K3_PLL bool "PLL clock support for K3 SoC family of devices" depends on CLK && LIB_RATIONAL diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 6009eab800..2f0cb80cb9 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -49,5 +49,6 @@ obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o obj-$(CONFIG_STM32H7) += clk_stm32h7.o obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o +obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o obj-$(CONFIG_CLK_VERSAL) += clk_versal.o obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o diff --git a/drivers/clk/clk-k3.c b/drivers/clk/clk-k3.c new file mode 100644 index 0000000000..f0392aad5d --- /dev/null +++ b/drivers/clk/clk-k3.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments K3 clock driver + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo t-kristo@ti.com + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <soc.h> +#include <clk-uclass.h> +#include "k3-clk.h" + +#define PLL_MIN_FREQ 800000000 +#define PLL_MAX_FREQ 3200000000UL + +/** + * struct clk_map - mapping from dev/clk id tuples towards physical clocks + * @dev_id: device ID for the clock + * @clk_id: clock ID for the clock + * @clk: pointer to the registered clock entry for the mapping + */ +struct clk_map { + u16 dev_id; + u32 clk_id; + struct clk *clk; +}; + +/** + * struct ti_clk_data - clock controller information structure + * @map: mapping from dev/clk id tuples to physical clock entries + * @size: number of entries in the map + */ +struct ti_clk_data { + struct clk_map *map; + int size; +}; + +static ulong osc_freq; + +static void clk_add_map(struct ti_clk_data *data, struct clk *clk, + u32 dev_id, u32 clk_id) +{ + struct clk_map *map; + + debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__, + clk, data, dev_id, clk_id); + if (!clk) + return; + + map = data->map + data->size++; + + map->dev_id = dev_id; + map->clk_id = clk_id; + map->clk = clk; +} + +static const struct soc_attr ti_k3_soc_clk_data[] = { +#ifdef CONFIG_SOC_K3_J721E + { + .family = "J721E", + .data = &j721e_clk_platdata, + }, + { + .family = "J7200", + .data = &j7200_clk_platdata, + }, +#endif + { /* sentinel */ } +}; + +static int ti_clk_probe(struct udevice *dev) +{ + struct ti_clk_data *data = dev_get_priv(dev); + struct clk *clk; + const char *name; + const struct clk_data *ti_clk_data; + int i, j; + const struct soc_attr *soc_match_data; + const struct ti_k3_clk_platdata *pdata; + + debug("%s(dev=%p)\n", __func__, dev); + + soc_match_data = soc_device_match(ti_k3_soc_clk_data); + if (!soc_match_data) + return -ENODEV; + + pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data; + + data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map), + GFP_KERNEL); + data->size = 0; + + for (i = 0; i < pdata->clk_list_cnt; i++) { + ti_clk_data = &pdata->clk_list[i]; + + switch (ti_clk_data->type) { + case CLK_TYPE_FIXED_RATE: + name = ti_clk_data->clk.fixed_rate.name; + clk = clk_register_fixed_rate(NULL, + name, + ti_clk_data->clk.fixed_rate.rate); + break; + case CLK_TYPE_DIV: + name = ti_clk_data->clk.div.name; + clk = clk_register_divider(NULL, name, + ti_clk_data->clk.div.parent, + ti_clk_data->clk.div.flags, + map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE), + ti_clk_data->clk.div.shift, + ti_clk_data->clk.div.width, + 0); + break; + case CLK_TYPE_MUX: + name = ti_clk_data->clk.mux.name; + clk = clk_register_mux(NULL, name, + ti_clk_data->clk.mux.parents, + ti_clk_data->clk.mux.num_parents, + ti_clk_data->clk.mux.flags, + map_physmem(ti_clk_data->clk.mux.reg, 0, MAP_NOCACHE), + ti_clk_data->clk.mux.shift, + ti_clk_data->clk.mux.width, + 0); + break; + case CLK_TYPE_PLL: + name = ti_clk_data->clk.pll.name; + clk = clk_register_ti_pll(name, + ti_clk_data->clk.pll.parent, + map_physmem(ti_clk_data->clk.pll.reg, 0, MAP_NOCACHE)); + + if (!osc_freq) + osc_freq = clk_get_rate(clk_get_parent(clk)); + break; + default: + name = NULL; + clk = NULL; + printf("WARNING: %s has encountered unknown clk type %d\n", + __func__, ti_clk_data->type); + } + + if (clk && ti_clk_data->default_freq) + clk_set_rate(clk, ti_clk_data->default_freq); + + if (clk && name) { + for (j = 0; j < pdata->soc_dev_clk_data_cnt; j++) { + if (!strcmp(name, pdata->soc_dev_clk_data[j].clk_name)) { + clk_add_map(data, clk, pdata->soc_dev_clk_data[j].dev_id, + pdata->soc_dev_clk_data[j].clk_id); + } + } + } + } + + return 0; +} + +static int _clk_cmp(u32 dev_id, u32 clk_id, const struct clk_map *map) +{ + if (map->dev_id == dev_id && map->clk_id == clk_id) + return 0; + if (map->dev_id > dev_id || + (map->dev_id == dev_id && map->clk_id > clk_id)) + return -1; + return 1; +} + +static int bsearch(u32 dev_id, u32 clk_id, struct clk_map *map, int num) +{ + int result; + int idx; + + for (idx = 0; idx < num; idx++) { + result = _clk_cmp(dev_id, clk_id, &map[idx]); + + if (result == 0) + return idx; + } + + return -ENOENT; +} + +static int ti_clk_of_xlate(struct clk *clk, + struct ofnode_phandle_args *args) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + int idx; + + debug("%s(clk=%p, args_count=%d [0]=%d [1]=%d)\n", __func__, clk, args->args_count, args->args[0], args->args[1]); + + if (args->args_count != 2) { + debug("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (!data->size) + return -EPROBE_DEFER; + + idx = bsearch(args->args[0], args->args[1], data->map, data->size); + if (idx < 0) + return idx; + + clk->id = idx; + + return 0; +} + +static ulong ti_clk_get_rate(struct clk *clk) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + + return clk_get_rate(clkp); +} + +static ulong ti_clk_set_rate(struct clk *clk, ulong rate) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + int div = 1; + ulong child_rate; + const struct clk_ops *ops; + ulong new_rate; + ulong diff; + + /* + * We must propagate rate change to parent if current clock type + * does not allow setting it. + */ + while (clkp) { + ops = clkp->dev->driver->ops; + if (ops->set_rate) + break; + + /* + * Store child rate so we can calculate the clock rate + * that must be passed to parent + */ + child_rate = clk_get_rate(clkp); + clkp = clk_get_parent(clkp); + if (clkp) + div *= clk_get_rate(clkp) / child_rate; + } + + if (!clkp) + return -ENOSYS; + + child_rate = clk_get_rate(clkp); + + new_rate = clk_set_rate(clkp, rate / div); + + /* + * If the new rate differs by at least 10% of the target, + * modify parent. This handles typical cases where we have a hsdiv + * following directly a PLL + */ + + diff = abs(new_rate - rate / div); + + debug("%s: clk=%s, div=%d, rate=%u, new_rate=%u, diff=%u\n", __func__, + clkp->dev->name, div, (u32)rate, (u32)new_rate, (u32)diff); + + if (diff > rate / div / 10) { + ulong pll_tgt; + int pll_div; + + clk = clkp; + + debug("%s: propagating rate change to parent, rate=%u.\n", + __func__, (u32)rate / div); + + clkp = clk_get_parent(clkp); + + if (rate > osc_freq) { + pll_div = PLL_MAX_FREQ / rate / div; + pll_tgt = rate / div * pll_div; + } else { + pll_tgt = osc_freq; + pll_div = rate / div / osc_freq; + } + + debug("%s: pll_tgt=%u, rate=%u, div=%u\n", __func__, + (u32)pll_tgt, (u32)rate, pll_div); + + clk_set_rate(clkp, pll_tgt); + + return clk_set_rate(clk, rate / div) * div; + } + + return new_rate; +} + +static int ti_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + struct clk *parentp = data->map[parent->id].clk; + + return clk_set_parent(clkp, parentp); +} + +static int ti_clk_enable(struct clk *clk) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + + return clk_enable(clkp); +} + +static int ti_clk_disable(struct clk *clk) +{ + struct ti_clk_data *data = dev_get_priv(clk->dev); + struct clk *clkp = data->map[clk->id].clk; + + return clk_disable(clkp); +} + +static const struct udevice_id ti_clk_of_match[] = { + { .compatible = "ti,k2g-sci-clk" }, + { /* sentinel */ }, +}; + +static const struct clk_ops ti_clk_ops = { + .of_xlate = ti_clk_of_xlate, + .set_rate = ti_clk_set_rate, + .get_rate = ti_clk_get_rate, + .enable = ti_clk_enable, + .disable = ti_clk_disable, + .set_parent = ti_clk_set_parent, +}; + +U_BOOT_DRIVER(ti_clk) = { + .name = "ti-clk", + .id = UCLASS_CLK, + .of_match = ti_clk_of_match, + .probe = ti_clk_probe, + .priv_auto_alloc_size = sizeof(struct ti_clk_data), + .ops = &ti_clk_ops, +}; diff --git a/include/k3-clk.h b/include/k3-clk.h index fc84378d03..36f0ddf7cc 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -7,7 +7,169 @@ #ifndef __K3_CLK_H__ #define __K3_CLK_H__

+#include <common.h> +#include <asm/io.h> +#include <linux/bitops.h> #include <linux/clk-provider.h> +#include <linux/types.h> +#include <stdint.h> + +struct dev_clk { + int dev_id; + int clk_id; + const char *clk_name; +}; + +#define DEV_CLK(_dev_id, _clk_id, _clk_name) { .dev_id = _dev_id, \ + .clk_id = _clk_id, .clk_name = _clk_name, } + +#define CLK_TYPE_MUX 0x01 +#define CLK_TYPE_DIV 0x02 +#define CLK_TYPE_PLL 0x03 +#define CLK_TYPE_HFOSC 0x04 +#define CLK_TYPE_POSTDIV 0x05 +#define CLK_TYPE_MUX_PLLCTRL 0x06 +#define CLK_TYPE_FIXED_RATE 0x07 + +struct pll_data { + u32 reg; + const char *name; + const char *parent; + u32 flags; +}; + +struct mux_data { + u32 reg; + const char *name; + const char * const *parents; + int num_parents; + u32 flags; + int shift; + int width; +}; + +struct div_data { + u32 reg; + const char *name; + const char *parent; + u32 flags; + int shift; + int width; +}; + +struct hfosc_data { + const char *name; + u32 flags; +}; + +struct fixed_rate_data { + const char *name; + u64 rate; + u32 flags; +}; + +struct postdiv_data { + const char *name; + const char *parent; + int width; + u32 flags; +}; + +struct mux_pllctrl_data { + u32 reg; + const char *name; + const char * const *parents; + int num_parents; + u32 flags; +}; + +struct clk_data { + int type; + u32 default_freq; + union { + struct pll_data pll; + struct mux_data mux; + struct div_data div; + struct hfosc_data hfosc; + struct postdiv_data postdiv; + struct mux_pllctrl_data mux_pllctrl; + struct fixed_rate_data fixed_rate; + } clk; +}; + +#define CLK_MUX(_name, _parents, _num_parents, _reg, _shift, _width, _flags) \ + { \ + .type = CLK_TYPE_MUX, \ + .clk.mux = { .name = _name, .parents = _parents, \ + .reg = _reg, \ + .num_parents = _num_parents, .shift = _shift, \ + .width = _width, .flags = _flags } \ + } + +#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags) \ + { \ + .type = CLK_TYPE_DIV, \ + .clk.div = {.name = _name, .parent = _parent, .reg = _reg, .shift = _shift, .width = _width, .flags = _flags } \ + } + +#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _freq) \ + { \ + .type = CLK_TYPE_DIV, \ + .default_freq = _freq, \ + .clk.div = { \ + .name = _name, .parent = _parent, \ + .reg = _reg, .shift = _shift, \ + .width = _width, .flags = _flags } \ + } + +#define CLK_PLL(_name, _parent, _reg, _flags) \ + { \ + .type = CLK_TYPE_PLL, \ + .clk.pll = {.name = _name, .parent = _parent, .reg = _reg, .flags = _flags } \ + } + +#define CLK_PLL_DEFFREQ(_name, _parent, _reg, _flags, _freq) \ + { \ + .type = CLK_TYPE_PLL, \ + .default_freq = _freq, \ + .clk.pll = { .name = _name, .parent = _parent, \ + .reg = _reg, .flags = _flags } \ + } + +#define CLK_HFOSC(_name, _flags) \ + { \ + .type = CLK_TYPE_HFOSC, \ + .clk.hfosc = { .name = _name, .flags = _flags } \ + } + +#define CLK_FIXED_RATE(_name, _rate, _flags) \ + { \ + .type = CLK_TYPE_FIXED_RATE, \ + .clk.fixed_rate = { .name = _name, .rate = _rate, .flags = _flags } \ + } + +#define CLK_POSTDIV(_name, _parent, _width, _flags) \ + { \ + .type = CLK_TYPE_POSTDIV, \ + .clk.postdiv = {.name = _name, .parent = _parent, .width = _width, .flags = _flags } \ + } + +#define CLK_MUX_PLLCTRL(_name, _parents, _num_parents, _reg, _flags) \ + { \ + .type = CLK_TYPE_MUX, \ + .clk.mux_pllctrl = { .name = _name, .parents = _parents,\ + .num_parents = _num_parents, .flags = _flags } \ + } + +struct ti_k3_clk_platdata { + const struct clk_data *clk_list; + int clk_list_cnt; + const struct dev_clk *soc_dev_clk_data; + int soc_dev_clk_data_cnt; +}; + +extern const struct ti_k3_clk_platdata j721e_clk_platdata; +extern const struct ti_k3_clk_platdata j7200_clk_platdata;

struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg);

Add support command for debugging K3 power domains. This is useful with the HSM rearch setup, where power domains are directly controlled by SPL instead of going through the TI SCI layer. The debugging support is only available in the u-boot codebase though, so the raw register access power domain layer must be enabled on u-boot side for this to work. By default, u-boot side uses the TI SCI layer, and R5 SPL only uses the direct access methods.

Signed-off-by: Tero Kristo t-kristo@ti.com --- cmd/ti/Kconfig | 8 ++ cmd/ti/Makefile | 1 + cmd/ti/pd.c | 185 +++++++++++++++++++++++++ drivers/power/domain/ti-power-domain.c | 6 +- include/k3-dev.h | 9 ++ 5 files changed, 206 insertions(+), 3 deletions(-) create mode 100644 cmd/ti/pd.c

diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig index efeff0d482..db557445a8 100644 --- a/cmd/ti/Kconfig +++ b/cmd/ti/Kconfig @@ -7,4 +7,12 @@ config CMD_DDR3 supports memory verification, memory comapre and ecc verification if supported.

+config CMD_PD + bool "command for verifying power domains" + depends on TI_POWER_DOMAIN + help + Debug command for K3 power domains. For this to work, the + K3 power domain driver must be enabled for the u-boot; by + default it is only enabled for SPL. + endmenu diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile index 16fbade9ed..045593396b 100644 --- a/cmd/ti/Makefile +++ b/cmd/ti/Makefile @@ -5,4 +5,5 @@ obj- += dummy.o

ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_DDR3) += ddr3.o +obj-$(CONFIG_CMD_PD) += pd.o endif diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c new file mode 100644 index 0000000000..a53ccdcc40 --- /dev/null +++ b/cmd/ti/pd.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Power Domain test commands + * + * Copyright (C) 2020 Texas Instruments Incorporated, <www.ti.com> + */ + +#include <common.h> +#include <command.h> +#include <dm.h> +#include <k3-dev.h> + +static const struct udevice_id ti_pd_of_match[] = { + { .compatible = "ti,sci-pm-domain" }, + { /* sentinel */ } +}; + +static struct ti_k3_pd_platdata *ti_pd_find_data(void) +{ + struct udevice *dev; + int i = 0; + + while (1) { + uclass_get_device(UCLASS_POWER_DOMAIN, i++, &dev); + if (!dev) + return NULL; + + if (device_is_compatible(dev, + ti_pd_of_match[0].compatible)) + return dev_get_priv(dev); + } + + return NULL; +} + +static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd) +{ + int i; + struct ti_lpsc *lpsc; + u8 state; + static const char * const lpsc_states[] = { + "swrstdis", "syncrst", "disable", "enable", "autosleep", + "autowake", "unknown", + }; + + for (i = 0; i < data->num_lpsc; i++) { + lpsc = &data->lpsc[i]; + if (lpsc->pd != pd) + continue; + state = lpsc_get_state(lpsc); + if (state > ARRAY_SIZE(lpsc_states)) + state = ARRAY_SIZE(lpsc_states) - 1; + printf(" LPSC%d: state=%s, usecount=%d\n", + lpsc->id, lpsc_states[state], lpsc->usecount); + } +} + +static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc) +{ + int i; + struct ti_pd *pd; + u8 state; + static const char * const pd_states[] = { + "off", "on", "unknown" + }; + + for (i = 0; i < data->num_pd; i++) { + pd = &data->pd[i]; + if (pd->psc != psc) + continue; + state = ti_pd_state(pd); + if (state > ARRAY_SIZE(pd_states)) + state = ARRAY_SIZE(pd_states) - 1; + printf(" PD%d: state=%s, usecount=%d:\n", + pd->id, pd_states[state], pd->usecount); + dump_lpsc(data, pd); + } +} + +static void dump_psc(struct ti_k3_pd_platdata *data) +{ + int i; + struct ti_psc *psc; + + for (i = 0; i < data->num_psc; i++) { + psc = &data->psc[i]; + printf("PSC%d [%p]:\n", psc->id, psc->base); + dump_pd(data, psc); + } +} + +static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct ti_k3_pd_platdata *data; + + data = ti_pd_find_data(); + if (!data) + return CMD_RET_FAILURE; + + dump_psc(data); + + return 0; +} + +static int do_pd_endis(int argc, char *const argv[], u8 state) +{ + u32 psc_id; + u32 lpsc_id; + int i; + struct ti_k3_pd_platdata *data; + struct ti_lpsc *lpsc; + int ret; + + if (argc < 3) + return CMD_RET_FAILURE; + + data = ti_pd_find_data(); + if (!data) + return CMD_RET_FAILURE; + + psc_id = simple_strtoul(argv[1], NULL, 10); + lpsc_id = simple_strtoul(argv[2], NULL, 10); + + for (i = 0; i < data->num_lpsc; i++) { + lpsc = &data->lpsc[i]; + if (lpsc->pd->psc->id != psc_id) + continue; + if (lpsc->id != lpsc_id) + continue; + printf("%s pd [PSC:%d,LPSC:%d]...\n", + state == MDSTAT_STATE_ENABLE ? "Enabling" : "Disabling", + psc_id, lpsc_id); + ret = ti_lpsc_transition(lpsc, state); + if (ret) + return CMD_RET_FAILURE; + else + return 0; + } + + printf("No matching psc/lpsc found.\n"); + + return CMD_RET_FAILURE; +} + +static int do_pd_enable(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + return do_pd_endis(argc, argv, MDSTAT_STATE_ENABLE); +} + +static int do_pd_disable(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + return do_pd_endis(argc, argv, MDSTAT_STATE_SWRSTDISABLE); +} + +static struct cmd_tbl cmd_pd[] = { + U_BOOT_CMD_MKENT(dump, 1, 0, do_pd_dump, "", ""), + U_BOOT_CMD_MKENT(enable, 3, 0, do_pd_enable, "", ""), + U_BOOT_CMD_MKENT(disable, 3, 0, do_pd_disable, "", ""), +}; + +static int ti_do_pd(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct cmd_tbl *c; + + argc--; + argv++; + + c = find_cmd_tbl(argv[0], cmd_pd, ARRAY_SIZE(cmd_pd)); + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +U_BOOT_CMD(pd, 4, 1, ti_do_pd, + "TI power domain control", +#ifdef CONFIG_SYS_LONGHELP + "dump - show power domain status\n" + "enable [psc] [lpsc] - enable power domain\n" + "disable [psc] [lpsc] - disable power domain\n" +#endif +); diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index a2d8983540..dfbd75878d 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -134,7 +134,7 @@ static void ti_pd_transition(struct ti_pd *pd) psc_write(BIT(pd->id), pd->psc, PSC_PTCMD); }

-static u8 ti_pd_state(struct ti_pd *pd) +u8 ti_pd_state(struct ti_pd *pd) { u32 pdctl;

@@ -233,7 +233,7 @@ static int ti_lpsc_wait(struct ti_lpsc *lpsc) return -ETIMEDOUT; }

-static u8 lpsc_get_state(struct ti_lpsc *lpsc) +u8 lpsc_get_state(struct ti_lpsc *lpsc) { u32 mdctl;

@@ -241,7 +241,7 @@ static u8 lpsc_get_state(struct ti_lpsc *lpsc) return mdctl & MDSTAT_STATE_MASK; }

-static int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state) +int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state) { struct ti_pd *psc_pd; int ret; diff --git a/include/k3-dev.h b/include/k3-dev.h index de3a8bdf9e..55c5057db3 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -22,6 +22,11 @@ #define PSC_PD_ALWAYSON BIT(1) #define PSC_PD_DEPENDS BIT(2)

+#define MDSTAT_STATE_MASK 0x3f +#define MDSTAT_BUSY_MASK 0x30 +#define MDSTAT_STATE_SWRSTDISABLE 0x0 +#define MDSTAT_STATE_ENABLE 0x3 + struct ti_psc { int id; void __iomem *base; @@ -73,4 +78,8 @@ struct ti_k3_pd_platdata { extern const struct ti_k3_pd_platdata j721e_pd_platdata; extern const struct ti_k3_pd_platdata j7200_pd_platdata;

+u8 ti_pd_state(struct ti_pd *pd); +u8 lpsc_get_state(struct ti_lpsc *lpsc); +int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state); + #endif

From: Dave Gerlach d-gerlach@ti.com

Add platform clock and powerdomain data for J721e and J7200. This data is used by the corresponding drivers to register all the required device clocks and powerdomains.

Signed-off-by: Dave Gerlach d-gerlach@ti.com --- arch/arm/mach-k3/Makefile | 2 +- arch/arm/mach-k3/j7200/Makefile | 5 + arch/arm/mach-k3/j7200/clk-data.c | 232 ++++++++++++++++++++++++++ arch/arm/mach-k3/j7200/dev-data.c | 71 ++++++++ arch/arm/mach-k3/j721e/Makefile | 5 + arch/arm/mach-k3/j721e/clk-data.c | 259 ++++++++++++++++++++++++++++++ arch/arm/mach-k3/j721e/dev-data.c | 67 ++++++++ 7 files changed, 640 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-k3/j7200/Makefile create mode 100644 arch/arm/mach-k3/j7200/clk-data.c create mode 100644 arch/arm/mach-k3/j7200/dev-data.c create mode 100644 arch/arm/mach-k3/j721e/Makefile create mode 100644 arch/arm/mach-k3/j721e/clk-data.c create mode 100644 arch/arm/mach-k3/j721e/dev-data.c

diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 7572f56925..534ddfcd49 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -4,7 +4,7 @@ # Lokesh Vutla lokeshvutla@ti.com

obj-$(CONFIG_SOC_K3_AM6) += am6_init.o -obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o +obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/ obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_TI_SECURE_DEVICE) += security.o diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile new file mode 100644 index 0000000000..ff9abd78ea --- /dev/null +++ b/arch/arm/mach-k3/j7200/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c new file mode 100644 index 0000000000..f5bdbdd55e --- /dev/null +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J7200 specific clock platform data + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + "osc_19_2_mhz", + "osc_20_mhz", + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + "osc_27_mhz", +}; + +static const char * const main_pll_hfosc_sel_out1_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { + "fss_mcu_0_ospi_0_ospi_oclk_clk", +}; + +static const char * const wkup_fref_clksel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { + "wkup_fref_clksel_out0", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcuusart_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv2_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out12_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out3_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out7_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out8_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "main_pll_hfosc_sel_out0", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const emmcsd_refclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const emmcsd_refclk_sel_out1_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const gtc_clk_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv2_16fft_main_0_hsdivout6_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 1, 0x43008084, 0, 1, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 1, 0x40f08030, 4, 1, 0), + CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0), + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), + CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), + CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 1, 0x43008080, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 1, 0x430080b0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 1, 0x4300808c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 1, 0x4300809c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 1, 0x430080a0, 0, 1, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), + CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0), + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 4, 0x108030, 0, 4, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 1, "gtc_clk_mux_out0"), + DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"), + DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"), + DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"), + DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"), + DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"), + DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(149, 2, "mcuusart_clk_sel_out0"), + DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"), + DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"), + DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), +}; + +const struct ti_k3_clk_platdata j7200_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 63, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 61, +}; diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c new file mode 100644 index 0000000000..6c0ee688e0 --- /dev/null +++ b/arch/arm/mach-k3/j7200/dev-data.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J7200 specific device platform data + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), + [1] = PSC(1, 0x42000000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(2, &soc_psc_list[0], &soc_pd_list[5]), + [2] = PSC_PD(14, &soc_psc_list[0], NULL), + [3] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[2]), + [4] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[2]), + [5] = PSC_PD(0, &soc_psc_list[1], NULL), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(9, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[13]), + [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]), + [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL), + [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL), + [5] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL), + [6] = PSC_LPSC(54, &soc_psc_list[0], &soc_pd_list[1], NULL), + [7] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[2], NULL), + [8] = PSC_LPSC(79, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[7]), + [9] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]), + [10] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[7]), + [11] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[5], NULL), + [12] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[5], NULL), + [13] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[5], NULL), + [14] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[5], NULL), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(30, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[1]), + PSC_DEV(90, &soc_lpsc_list[2]), + PSC_DEV(8, &soc_lpsc_list[3]), + PSC_DEV(92, &soc_lpsc_list[4]), + PSC_DEV(91, &soc_lpsc_list[5]), + PSC_DEV(146, &soc_lpsc_list[6]), + PSC_DEV(4, &soc_lpsc_list[7]), + PSC_DEV(4, &soc_lpsc_list[8]), + PSC_DEV(202, &soc_lpsc_list[9]), + PSC_DEV(203, &soc_lpsc_list[10]), + PSC_DEV(103, &soc_lpsc_list[11]), + PSC_DEV(104, &soc_lpsc_list[11]), + PSC_DEV(154, &soc_lpsc_list[11]), + PSC_DEV(149, &soc_lpsc_list[11]), + PSC_DEV(197, &soc_lpsc_list[12]), + PSC_DEV(103, &soc_lpsc_list[13]), + PSC_DEV(104, &soc_lpsc_list[14]), +}; + +const struct ti_k3_pd_platdata j7200_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = 2, + .num_pd = 6, + .num_lpsc = 15, + .num_devs = 18, +}; diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile new file mode 100644 index 0000000000..ff9abd78ea --- /dev/null +++ b/arch/arm/mach-k3/j721e/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c new file mode 100644 index 0000000000..455cb81a56 --- /dev/null +++ b/arch/arm/mach-k3/j721e/clk-data.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J721E specific clock platform data + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + "osc_19_2_mhz", + "osc_20_mhz", + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + "osc_27_mhz", +}; + +static const char * const main_pll_hfosc_sel_out1_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { + "fss_mcu_0_ospi_0_ospi_oclk_clk", +}; + +static const char * const mcu_ospi1_iclk_sel_out0_parents[] = { + "fss_mcu_0_ospi_1_ospi_oclk_clk", +}; + +static const char * const wkup_fref_clksel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { + "wkup_fref_clksel_out0", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcuusart_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv3_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out12_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out2_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out3_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out7_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out8_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "main_pll_hfosc_sel_out0", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const emmcsd_refclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const emmcsd_refclk_sel_out1_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const gtc_clk_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 1, 0x43008084, 0, 1, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 1, 0x40f08030, 4, 1, 0), + CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 1, 0x40f08034, 4, 1, 0), + CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0), + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), + CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), + CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), + CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 1, 0x43008080, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 1, 0x430080b0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 1, 0x43008088, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 1, 0x4300808c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 1, 0x4300809c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 1, 0x430080a0, 0, 1, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), + CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0), + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 4, 0x108030, 0, 4, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(4, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(4, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 12, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(47, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(47, 2, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(47, 0, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(47, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 1, "gtc_clk_mux_out0"), + DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 1, "emmcsd_refclk_sel_out0"), + DEV_CLK(91, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(91, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(91, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(91, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 6, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(92, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(92, 0, "emmcsd_refclk_sel_out1"), + DEV_CLK(92, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(92, 2, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(92, 3, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(92, 4, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 4, "mcu_ospi0_iclk_sel_out0"), + DEV_CLK(103, 6, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(103, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"), + DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(104, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 4, "mcu_ospi1_iclk_sel_out0"), + DEV_CLK(104, 6, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 0, "mcu_ospi_ref_clk_sel_out1"), + DEV_CLK(104, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(104, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(149, 0, "mcuusart_clk_sel_out0"), + DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"), + DEV_CLK(149, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 0, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(197, 0, "wkup_i2c0_mcupll_bypass_clksel_out0"), + DEV_CLK(197, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(197, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), +}; + +const struct ti_k3_clk_platdata j721e_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 69, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 69, +}; diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c new file mode 100644 index 0000000000..e140454c1e --- /dev/null +++ b/arch/arm/mach-k3/j721e/dev-data.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J721E specific device platform data + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), + [1] = PSC(1, 0x42000000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(14, &soc_psc_list[0], NULL), + [2] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[1]), + [3] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[1]), + [4] = PSC_PD(0, &soc_psc_list[1], NULL), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(7, &soc_psc_list[0], &soc_pd_list[0], NULL), + [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]), + [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL), + [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL), + [5] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL), + [6] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[1], NULL), + [7] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[6]), + [8] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]), + [9] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[4], NULL), + [10] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[4], NULL), + [11] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[4], NULL), + [12] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[4], NULL), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(30, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(146, &soc_lpsc_list[1]), + PSC_DEV(90, &soc_lpsc_list[2]), + PSC_DEV(47, &soc_lpsc_list[3]), + PSC_DEV(92, &soc_lpsc_list[4]), + PSC_DEV(91, &soc_lpsc_list[5]), + PSC_DEV(4, &soc_lpsc_list[6]), + PSC_DEV(202, &soc_lpsc_list[7]), + PSC_DEV(203, &soc_lpsc_list[8]), + PSC_DEV(103, &soc_lpsc_list[9]), + PSC_DEV(104, &soc_lpsc_list[9]), + PSC_DEV(154, &soc_lpsc_list[9]), + PSC_DEV(149, &soc_lpsc_list[9]), + PSC_DEV(197, &soc_lpsc_list[10]), + PSC_DEV(103, &soc_lpsc_list[11]), + PSC_DEV(104, &soc_lpsc_list[12]), +}; + +const struct ti_k3_pd_platdata j721e_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = 2, + .num_pd = 5, + .num_lpsc = 13, + .num_devs = 17, +};

With the new raw register mode access PM drivers, A72 core is not enabled via ti-sci services, leading into bad usecounts for the core. This effectively shuts down the A72 core when SPL goes down. Prevent the problem by force enabling the A72 core once, which increases the use count.

Signed-off-by: Tero Kristo t-kristo@ti.com --- arch/arm/mach-k3/j721e_init.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index a36e4ed603..d00a9477a2 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -306,6 +306,7 @@ u32 spl_boot_device(void)

#ifdef CONFIG_SYS_K3_SPL_ATF

+#define J721E_DEV_A72SS0_CORE0 202 #define J721E_DEV_MCU_RTI0 262 #define J721E_DEV_MCU_RTI1 263 #define J721E_DEV_MCU_ARMSS0_CPU0 250 @@ -324,10 +325,23 @@ void release_resources_for_core_shutdown(void) J721E_DEV_MCU_RTI1, };

+ const u32 get_device_ids[] = { + J721E_DEV_A72SS0_CORE0 + }; + ti_sci = get_ti_sci_handle(); dev_ops = &ti_sci->ops.dev_ops; proc_ops = &ti_sci->ops.proc_ops;

+ /* Iterate through list of devices to get (enable) */ + for (i = 0; i < ARRAY_SIZE(get_device_ids); i++) { + u32 id = get_device_ids[i]; + + ret = dev_ops->get_device(ti_sci, id); + if (ret) + panic("Failed to get device %u (%d)\n", id, ret); + } + /* Iterate through list of devices to put (shutdown) */ for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { u32 id = put_device_ids[i];

Copy the contents of the board config loaded from sysfw.itb into an EXTBOOT shared memory buffer that gets passed to sciserver. This only needs to be done if EXTBOOT area has not been populated by ROM code yet.

Signed-off-by: Tero Kristo t-kristo@ti.com --- arch/arm/mach-k3/sysfw-loader.c | 98 +++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 154d2df049..c20b601848 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -39,6 +39,43 @@ DECLARE_GLOBAL_DATA_PTR; */ #define K3_SYSTEM_CONTROLLER_RPROC_ID 0

+#define BOARDCFG_ADDRESS 0x41c80000 + +#define COMP_TYPE_SBL_DATA 0x11 +#define DESC_TYPE_BOARDCFG_PM_INDEX 0x2 +#define DESC_TYPE_BOARDCFG_RM_INDEX 0x3 + +#define BOARD_CONFIG_RM_DESC_TYPE 0x000c +#define BOARD_CONFIG_PM_DESC_TYPE 0x000e + +struct extboot_comp { + u32 comp_type; + u32 boot_core; + u32 comp_opts; + u64 dest_addr; + u32 comp_size; +} __packed; + +struct extboot_header { + u8 magic[8]; + u32 num_comps; + struct extboot_comp comps[5]; +} __packed; + +struct bcfg_desc { + u16 type; + u16 offset; + u16 size; + u8 devgrp; + u8 reserved; +} __packed; + +struct bcfg_header { + u8 num_elems; + u8 sw_rev; + struct bcfg_desc descs[4]; +} __packed; + static bool sysfw_loaded; static void *sysfw_load_address;

@@ -130,6 +167,15 @@ static void k3_sysfw_configure_using_fit(void *fit, const void *cfg_fragment_addr; size_t cfg_fragment_size; int ret; +#ifndef CONFIG_CLK_TI_SCI + u8 *buf; + struct extboot_header *common_header; + struct bcfg_header *bcfg_header; + struct extboot_comp *comp; + struct bcfg_desc *desc; + u32 addr; + bool copy_bcfg = false; +#endif

/* Find the node holding the images information */ images = fdt_path_offset(fit, FIT_IMAGES_PATH); @@ -164,6 +210,46 @@ static void k3_sysfw_configure_using_fit(void *fit, (u32)cfg_fragment_size); if (ret) panic("Failed to set board PM configuration (%d)\n", ret); +#else + /* Initialize shared memory boardconfig buffer */ + buf = (u8 *)BOARDCFG_ADDRESS; + common_header = (struct extboot_header *)buf; + + /* Check if we have a struct populated by ROM in memory already */ + if (strcmp((char *)common_header->magic, "EXTBOOT")) + copy_bcfg = true; + + if (copy_bcfg) { + strcpy((char *)common_header->magic, "EXTBOOT"); + common_header->num_comps = 1; + + comp = &common_header->comps[0]; + + comp->comp_type = COMP_TYPE_SBL_DATA; + comp->boot_core = 0x10; + comp->comp_opts = 0; + addr = (u32)buf + sizeof(*common_header); + comp->dest_addr = addr; + comp->comp_size = sizeof(*bcfg_header); + + bcfg_header = (struct bcfg_header *)addr; + + bcfg_header->num_elems = 2; + bcfg_header->sw_rev = 0; + + desc = &bcfg_header->descs[0]; + + desc->type = BOARD_CONFIG_PM_DESC_TYPE; + desc->offset = sizeof(*bcfg_header); + desc->size = cfg_fragment_size; + comp->comp_size += desc->size; + desc->devgrp = 0; + desc->reserved = 0; + memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr, + cfg_fragment_size); + + bcfg_header->descs[1].offset = desc->offset + desc->size; + } #endif

/* Extract resource management (RM) specific configuration from FIT */ @@ -180,6 +266,18 @@ static void k3_sysfw_configure_using_fit(void *fit, (u32)cfg_fragment_size); if (ret) panic("Failed to set board RM configuration (%d)\n", ret); +#else + if (copy_bcfg) { + desc = &bcfg_header->descs[1]; + + desc->type = BOARD_CONFIG_RM_DESC_TYPE; + desc->size = cfg_fragment_size; + comp->comp_size += desc->size; + desc->devgrp = 0; + desc->reserved = 0; + memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr, + cfg_fragment_size); + } #endif

/* Extract security specific configuration from FIT */

With the sysfw rearch, PM services are no longer available for R5 SPL to use. Instead, we will be using the raw PM register level access drivers for any PM. Thus, disable the SCI PM drivers to reflect this.

Signed-off-by: Tero Kristo t-kristo@ti.com --- configs/j721e_evm_r5_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 514867635c..62586b2f3b 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -72,7 +72,7 @@ CONFIG_SPL_REGMAP=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_CLK_TI_SCI=y +# CONFIG_CLK_TI_SCI is not set CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -102,7 +102,7 @@ CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_GENERIC is not set CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y +# CONFIG_TI_SCI_POWER_DOMAIN is not set CONFIG_DM_PMIC=y CONFIG_PMIC_TPS65941=y CONFIG_DM_REGULATOR=y

From: Dave Gerlach d-gerlach@ti.com

Sysfw is not going to provide access to power management features in the new architecture, so SPL must implement these itself. Enable all the raw register access based clock + power domain drivers.

Signed-off-by: Dave Gerlach d-gerlach@ti.com --- configs/j7200_evm_r5_defconfig | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 3820fc508b..19ba12e89f 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -75,7 +75,7 @@ CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_CLK_TI_SCI=y +# CONFIG_CLK_TI_SCI is not set CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -110,7 +110,7 @@ CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_GENERIC is not set CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y +# CONFIG_TI_SCI_POWER_DOMAIN is not set CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_DM_RESET=y @@ -142,3 +142,12 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6164 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_SPL_CLK_CCF=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y