[U-Boot] [PATCH] armv8: fsl-layerscape: Update ddr erratum a008336

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[U-Boot] [RESEND Patch v2] net:...

Shengzhou Liu

26 Aug 2016 26 Aug '16

12:30 p.m.

DDR erratum A008336 only applies to DDR controller v5.2.0. DDR controller v5.2.1 already has default 0x43b30002 in EDDRTQCR1 register for optimal performance.

Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index f62b78d..28928b3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -58,11 +58,13 @@ static void erratum_a008336(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; - out_le32(eddrtqcr1, 0x63b30002); + if (fsl_ddr_get_version(0) == 0x50200) + out_le32(eddrtqcr1, 0x63b30002); #endif #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; - out_le32(eddrtqcr1, 0x63b30002); + if (fsl_ddr_get_version(0) == 0x50200) + out_le32(eddrtqcr1, 0x63b30002); #endif #endif }

-- 2.1.0.27.g96db324

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Shengzhou Liu

26 Aug 26 Aug

12:30 p.m.

New subject: [U-Boot] [PATCH] driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a

This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future.

Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/LS1012AFRDM.

Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com --- Makefile | 1 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +- board/freescale/ls1012afrdm/ls1012afrdm.c | 116 ---------------- board/freescale/ls1012aqds/ls1012aqds.c | 116 ---------------- board/freescale/ls1012ardb/ls1012ardb.c | 116 ---------------- drivers/ddr/fsl/Makefile | 1 + drivers/ddr/fsl/fsl_mmdc.c | 156 ++++++++++++++++++++++ include/configs/ls1012afrdm.h | 22 ++- include/configs/ls1012aqds.h | 23 +++- include/configs/ls1012ardb.h | 21 ++- include/fsl_mmdc.h | 95 +++++++------ 11 files changed, 262 insertions(+), 409 deletions(-) create mode 100644 drivers/ddr/fsl/fsl_mmdc.c

diff --git a/Makefile b/Makefile index 99cc8cf..1bf6c6a 100644 --- a/Makefile +++ b/Makefile @@ -647,6 +647,7 @@ libs-y += drivers/power/ \ libs-y += drivers/spi/ libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ +libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/ libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/ libs-y += drivers/serial/ libs-y += drivers/usb/dwc3/ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b0ad4b4..d1d76be 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -15,7 +15,9 @@ #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ #endif

-#ifndef CONFIG_LS1012A +#ifdef CONFIG_LS1012A +#define CONFIG_SYS_FSL_MMDC /* Freescale MMDC driver */ +#else #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #endif diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index a94a458..0bbb558 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -18,20 +18,6 @@

DECLARE_GLOBAL_DATA_PTR;

-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) -{ - int timeout = 1000; - - out_be32(ptr, value); - - while (in_be32(ptr) & bits) { - udelay(100); - timeout--; - } - if (timeout <= 0) - puts("Error: wait for clear timeout.\n"); -} - int checkboard(void) { puts("Board: LS1012AFRDM "); @@ -39,108 +25,6 @@ int checkboard(void) return 0; }

DECLARE_GLOBAL_DATA_PTR;

-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) -{ - int timeout = 1000; - - out_be32(ptr, value); - - while (in_be32(ptr) & bits) { - udelay(100); - timeout--; - } - if (timeout <= 0) - puts("Error: wait for clear timeout.\n"); -} - int checkboard(void) { char buf[64]; @@ -67,108 +53,6 @@ int checkboard(void) return 0; }

DECLARE_GLOBAL_DATA_PTR;

-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) -{ - int timeout = 1000; - - out_be32(ptr, value); - - while (in_be32(ptr) & bits) { - udelay(100); - timeout--; - } - if (timeout <= 0) - puts("Error: wait for clear timeout.\n"); -} - int checkboard(void) { u8 in1; @@ -71,108 +57,6 @@ int checkboard(void) return 0; }

-void mmdc_init(void) -{ - struct mmdc_p_regs *mmdc = - (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; - - out_be32(&mmdc->mdscr, CONFIGURATION_REQ); - - /* configure timing parms */ - out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); - out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); - out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); - out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); - - /* other parms */ - out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); - out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); - out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); - out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); - - /* out of reset delays */ - out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); - - /* physical parms */ - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); - out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); - - /* Enable MMDC */ - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); - - /* dram init sequence: update MRs */ - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | - CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); - - /* dram init sequence: ZQCL */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); - set_wait_for_bits_clear(&mmdc->mpzqhwctrl, - CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, - FORCE_ZQ_AUTO_CALIBRATION); - - /* Calibrations now: wr lvl */ - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | - CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); - set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); - - mdelay(1); - - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, CONFIGURATION_REQ); - - mdelay(1); - - /* Calibrations now: Read DQS gating calibration */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); - out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); - set_wait_for_bits_clear(&mmdc->mpdgctrl0, - AUTO_RD_DQS_GATING_CALIBRATION_EN, - AUTO_RD_DQS_GATING_CALIBRATION_EN); - - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - - /* Calibrations now: Read calibration */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); - set_wait_for_bits_clear(&mmdc->mprddlhwctl, - AUTO_RD_CALIBRATION_EN, - AUTO_RD_CALIBRATION_EN); - - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - - /* PD, SR */ - out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); - out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); - - /* refresh scheme */ - set_wait_for_bits_clear(&mmdc->mdref, - CONFIG_SYS_MMDC_CORE_REFRESH_CTL, - START_REFRESH); - - /* disable CON_REQ */ - out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); -} - int dram_init(void) { mmdc_init(); diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile index 01ea862..00dea42 100644 --- a/drivers/ddr/fsl/Makefile +++ b/drivers/ddr/fsl/Makefile @@ -33,3 +33,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o +obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c new file mode 100644 index 0000000..1e35967 --- /dev/null +++ b/drivers/ddr/fsl/fsl_mmdc.c @@ -0,0 +1,156 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Generic driver for Freescale MMDC(Multi Mode DDR Controller). + */ + +#include <common.h> +#include <fsl_mmdc.h> +#include <asm/io.h> + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + printf("Error: %p wait for clear timeout.\n", ptr); +} + +void mmdc_init(void) +{ + struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR; + unsigned int tmp; + + /* 1. set configuration request */ + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ); + + /* 2. configure the desired timing parameters */ + out_be32(&mmdc->mdotc, CONFIG_MMDC_MDOTC); + out_be32(&mmdc->mdcfg0, CONFIG_MMDC_MDCFG0); + out_be32(&mmdc->mdcfg1, CONFIG_MMDC_MDCFG1); + out_be32(&mmdc->mdcfg2, CONFIG_MMDC_MDCFG2); + + /* 3. configure DDR type and other miscellaneous parameters */ + out_be32(&mmdc->mdmisc, CONFIG_MMDC_MDMISC); + out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR); + out_be32(&mmdc->mdrwd, CONFIG_MMDC_MDRWD); + out_be32(&mmdc->mpodtctrl, CONFIG_MMDC_MPODTCTRL); + + /* 4. configure the required delay while leaving reset */ + out_be32(&mmdc->mdor, CONFIG_MMDC_MDOR); + + /* 5. configure DDR physical parameters */ + /* set row/column address width, burst length, data bus width */ + tmp = CONFIG_MMDC_MDCTL & ~(MDCTL_SDE0 | MDCTL_SDE1); + out_be32(&mmdc->mdctl, tmp); + /* configure address space partition */ + out_be32(&mmdc->mdasp, CONFIG_MMDC_MDASP); + + /* 6. perform a ZQ calibration - not needed here, doing in #8b */ + + /* 7. enable MMDC with the desired chip select */ +#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1) + out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0); +#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2) + out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1); +#endif + + /* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */ + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2); + + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3); + + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1); + + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | + MDSCR_ENABLE_CON_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0); + + /* 8b. ZQ calibration */ + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0); + + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, CONFIG_MMDC_MPZQHWCTRL, + MPZQHWCTRL_ZQ_HW_FORCE); + + /* 9a. calibrations now, wr lvl */ + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0x84) | + MDSCR_ENABLE_CON_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1); + + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN | + CMD_NORMAL); + + set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN, + MPWLGCR_HW_WL_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1); + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ); + + mdelay(1); + + /* 9b. read DQS gating calibration */ + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0); + + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3); + + out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN); + + /* set absolute read delay offset */ +#if defined(CONFIG_MMDC_MPRDDLCTL) + out_be32(&mmdc->mprddlctl, CONFIG_MMDC_MPRDDLCTL); +#else + out_be32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY); +#endif + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3); + + /* 9c. read calibration */ + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0); + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3); + out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN, + MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3); + + /* 10. configure power-down, self-refresh entry, exit parameters */ + out_be32(&mmdc->mdpdc, CONFIG_MMDC_MDPDC); + out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT); + + /* 11. ZQ config again? do nothing here */ + + /* 12. refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, CONFIG_MMDC_MDREF, + MDREF_START_REFRESH); + + /* 13. disable CON_REQ */ + out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ); +} diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index ad81142..3d83d47 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -9,19 +9,33 @@

#include "ls1012a_common.h"

+/* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000 -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000 - +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff

+/* DDR board-specific timing parameters */ +#define CONFIG_MMDC_MDCTL 0x04180000 +#define CONFIG_MMDC_MDPDC 0x00030035 +#define CONFIG_MMDC_MDOTC 0x12554000 +#define CONFIG_MMDC_MDCFG0 0xbabf7954 +#define CONFIG_MMDC_MDCFG1 0xdb328f64 +#define CONFIG_MMDC_MDCFG2 0x01ff00db +#define CONFIG_MMDC_MDMISC 0x00001680 +#define CONFIG_MMDC_MDREF 0x0f3c8000 +#define CONFIG_MMDC_MDRWD 0x00002000 +#define CONFIG_MMDC_MDOR 0x00bf1023 +#define CONFIG_MMDC_MDASP 0x0000003f +#define CONFIG_MMDC_MPODTCTRL 0x0000022a +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 + + /* * USB */ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 6e31ca0..233ed7e 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -9,14 +9,31 @@

#include "ls1012a_common.h"

- +/* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* DDR board-specific timing parameters */ +#define CONFIG_MMDC_MDCTL 0x05180000 +#define CONFIG_MMDC_MDPDC 0x00030035 +#define CONFIG_MMDC_MDOTC 0x12554000 +#define CONFIG_MMDC_MDCFG0 0xbabf7954 +#define CONFIG_MMDC_MDCFG1 0xdb328f64 +#define CONFIG_MMDC_MDCFG2 0x01ff00db +#define CONFIG_MMDC_MDMISC 0x00001680 +#define CONFIG_MMDC_MDREF 0x0f3c8000 +#define CONFIG_MMDC_MDRWD 0x00002000 +#define CONFIG_MMDC_MDOR 0x00bf1023 +#define CONFIG_MMDC_MDASP 0x0000003f +#define CONFIG_MMDC_MPODTCTRL 0x0000022a +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003

-#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000 -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000

/* * QIXIS Definitions diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 6046ab7..b36467a 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -9,20 +9,31 @@

#include "ls1012a_common.h"

- +/* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 - -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000 -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000 - #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff

+/* DDR board-specific timing parameters */ +#define CONFIG_MMDC_MDCTL 0x05180000 +#define CONFIG_MMDC_MDPDC 0x00030035 +#define CONFIG_MMDC_MDOTC 0x12554000 +#define CONFIG_MMDC_MDCFG0 0xbabf7954 +#define CONFIG_MMDC_MDCFG1 0xdb328f64 +#define CONFIG_MMDC_MDCFG2 0x01ff00db +#define CONFIG_MMDC_MDMISC 0x00001680 +#define CONFIG_MMDC_MDREF 0x0f3c8000 +#define CONFIG_MMDC_MDRWD 0x00002000 +#define CONFIG_MMDC_MDOR 0x00bf1023 +#define CONFIG_MMDC_MDASP 0x0000003f +#define CONFIG_MMDC_MPODTCTRL 0x0000022a +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 + /* * USB */ diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h index a939d89..1d09ff4 100644 --- a/include/fsl_mmdc.h +++ b/include/fsl_mmdc.h @@ -7,63 +7,39 @@ #ifndef FSL_MMDC_H #define FSL_MMDC_H

-#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000 -#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954 -#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64 -#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db - -#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680 -#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800 -#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000 -#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a - -#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023 - -#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f - -#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003 - -#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16) - -/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */ -#define WR_LVL_HW_EN 0x00000001 +/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */ +#define MPWLGCR_HW_WL_EN (1 << 0)

/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */ -#define MPR_COMPARE_EN 0x00000001 +#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)

-#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040

/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */ -#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000 +#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)

/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */ -#define AUTO_RD_CALIBRATION_EN 0x00000010 - -#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035 +#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)

-#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067 +/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */ +#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067

-#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000 - -#define START_REFRESH 0x00000001 +/* MMDC Core Refresh Control Register (MMDC_MDREF) */ +#define MDREF_START_REFRESH (1 << 0)

/* MMDC Core Special Command Register (MDSCR) */ -#define CMD_ADDR_MSB_MR_OP(x) (x << 24) - -#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16) - -#define DISABLE_CFG_REQ 0x0 -#define CONFIGURATION_REQ (0x1 << 15) -#define WL_EN (0x1 << 9) - -#define CMD_NORMAL (0x0 << 4) -#define CMD_PRECHARGE (0x1 << 4) -#define CMD_AUTO_REFRESH (0x2 << 4) -#define CMD_LOAD_MODE_REG (0x3 << 4) -#define CMD_ZQ_CALIBRATION (0x4 << 4) -#define CMD_PRECHARGE_BANK_OPEN (0x5 << 4) -#define CMD_MRR (0x6 << 4) - +#define CMD_ADDR_MSB_MR_OP(x) (x << 24) +#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16) +#define MDSCR_DISABLE_CFG_REQ (0 << 15) +#define MDSCR_ENABLE_CON_REQ (1 << 15) +#define MDSCR_CON_ACK (1 << 14) +#define MDSCR_WL_EN (1 << 9) +#define CMD_NORMAL (0 << 4) +#define CMD_PRECHARGE (1 << 4) +#define CMD_AUTO_REFRESH (2 << 4) +#define CMD_LOAD_MODE_REG (3 << 4) +#define CMD_ZQ_CALIBRATION (4 << 4) +#define CMD_PRECHARGE_BANK_OPEN (5 << 4) +#define CMD_MRR (6 << 4) #define CMD_BANK_ADDR_0 0x0 #define CMD_BANK_ADDR_1 0x1 #define CMD_BANK_ADDR_2 0x2 @@ -73,8 +49,22 @@ #define CMD_BANK_ADDR_6 0x6 #define CMD_BANK_ADDR_7 0x7

+/* MMDC Core Control Register (MDCTL) */ +#define MDCTL_SDE0 (1 << 31) +#define MDCTL_SDE1 (1 << 30) + +/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */ +#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16) + +/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */ +#define MMDC_MPMUR0_FRC_MSR (1 << 11) + +/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */ +/* default 64 for a quarter cycle delay */ +#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040 + /* MMDC Registers */ -struct mmdc_p_regs { +struct mmdc_regs { u32 mdctl; u32 mdpdc; u32 mdotc; @@ -120,7 +110,10 @@ struct mmdc_p_regs { u32 mprddqby1dl; u32 mprddqby2dl; u32 mprddqby3dl; - u32 res5[4]; + u32 mpwrdqby0dl; + u32 mpwrdqby1dl; + u32 mpwrdqby2dl; + u32 mpwrdqby3dl; u32 mpdgctrl0; u32 mpdgctrl1; u32 mpdgdlst0; @@ -157,4 +150,10 @@ struct mmdc_p_regs { u32 mpdccr; };

+void mmdc_init(void); + +#if !defined(CONFIG_MMDC_MDCTL) +#error Must configure board-specific timing CONFIG_MMDC_* in <board>.h for MMDC +#endif + #endif /* FSL_MMDC_H */

-- 2.1.0.27.g96db324

york sun

20 Sep 20 Sep

8:05 p.m.

New subject: [U-Boot] [PATCH] driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a

On 08/26/2016 03:42 AM, Shengzhou Liu wrote:

...

This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future.

Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/LS1012AFRDM.

Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com

Applied to fsl-qoriq master. Awaiting upstream. Thanks.

York

york sun

7:59 p.m.

New subject: [U-Boot] [PATCH] armv8: fsl-layerscape: Update ddr erratum a008336

On 08/26/2016 03:42 AM, Shengzhou Liu wrote:

...

DDR erratum A008336 only applies to DDR controller v5.2.0. DDR controller v5.2.1 already has default 0x43b30002 in EDDRTQCR1 register for optimal performance.

Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com

Applied to fsl-qoriq master. Awaiting upstream. Thanks.

York

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