[PATCH 00/15] imx8m: convert to DM_SERIAL
From: Peng Fan peng.fan@nxp.com
This patchset is to convert some i.MX8M boards to DM SERIAL
Note: this is based on my experience on i.MX8M*-EVK from NXP, I not have the following boards. If possible, please test.
Peng Fan (15): imx: imx8mp_rsb3720a1: convert to DM_SERIAL imx: imx8m[m/n/p]_venice: Enable SPL_DM_SERIAL imx: imx8mm_mx8menlo: Enable DM_SERIAL imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL imx: imx8mm-cl-iot-gate: Enable DM_SERIAL imx: imx8mm_icore: Enable SPL_DM_SERIAL imx: imx8m[m/p]_phycore: Enable DM_SERIAL imx: imx8mn_var_som: enable DM_SERIAL imx: imx8mm_edm_sbc: Enable SPL_DM_SERIAL imx: kontron-sl-mx8mm: enable DM_SERIAL imx: imx8mn_bsh_smm_s2: drop CONFIG_MXC_UART_BASE imx: dts: move common changes to imx8mq-u-boot.dtsi imx: imx8mq-cm: enable CONFIG_DM_SERIAL imx: imx8mq-pico: enable CONFIG_DM_SERIAL imx: imx8mq-phandle: enable CONFIG_DM_SERIAL
arch/arm/dts/imx8mq-cm-u-boot.dtsi | 8 +++++++ arch/arm/dts/imx8mq-evk-u-boot.dtsi | 24 ------------------- arch/arm/dts/imx8mq-phanbell-u-boot.dtsi | 8 +++++++ arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi | 9 +++++++ arch/arm/dts/imx8mq-u-boot.dtsi | 24 +++++++++++++++++++ .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 8 ------- board/beacon/imx8mm/spl.c | 12 ++-------- board/beacon/imx8mn/spl.c | 11 ++------- board/compulab/imx8mm-cl-iot-gate/spl.c | 12 ++-------- board/data_modul/imx8mm_edm_sbc/spl.c | 12 ++-------- board/engicam/imx8mm/spl.c | 14 +++-------- board/gateworks/venice/spl.c | 22 ++--------------- board/kontron/sl-mx8mm/spl.c | 12 ++-------- board/menlo/mx8menlo/mx8menlo.c | 9 ------- board/phytec/phycore_imx8mm/spl.c | 12 ++-------- board/phytec/phycore_imx8mp/spl.c | 8 ------- board/variscite/imx8mn_var_som/spl.c | 11 ++------- configs/imx8mm-cl-iot-gate-optee_defconfig | 1 + configs/imx8mm-cl-iot-gate_defconfig | 1 + configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 - configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 - configs/imx8mm-mx8menlo_defconfig | 1 + configs/imx8mm_beacon_defconfig | 1 - configs/imx8mm_data_modul_edm_sbc_defconfig | 1 - configs/imx8mm_venice_defconfig | 1 - configs/imx8mn_beacon_2g_defconfig | 1 - configs/imx8mn_beacon_defconfig | 1 - configs/imx8mn_var_som_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 - configs/imx8mp_rsb3720a1_4G_defconfig | 1 + configs/imx8mp_rsb3720a1_6G_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 - configs/imx8mq_cm_defconfig | 1 + configs/imx8mq_phanbell_defconfig | 1 + configs/kontron-sl-mx8mm_defconfig | 1 + configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + configs/pico-imx8mq_defconfig | 1 + include/configs/imx8mm-cl-iot-gate.h | 2 -- include/configs/imx8mm-mx8menlo.h | 3 --- include/configs/imx8mm_beacon.h | 2 -- include/configs/imx8mm_data_modul_edm_sbc.h | 2 -- include/configs/imx8mm_icore_mx8mm.h | 3 --- include/configs/imx8mm_venice.h | 3 --- include/configs/imx8mn_beacon.h | 2 -- include/configs/imx8mn_bsh_smm_s2_common.h | 2 -- include/configs/imx8mn_var_som.h | 2 -- include/configs/imx8mn_venice.h | 3 --- include/configs/imx8mp_rsb3720.h | 2 -- include/configs/imx8mp_venice.h | 3 --- include/configs/kontron-sl-mx8mm.h | 1 - include/configs/phycore_imx8mm.h | 3 --- include/configs/phycore_imx8mp.h | 3 --- 53 files changed, 80 insertions(+), 193 deletions(-) create mode 100644 arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi
Hi Peng,
On Sat, Apr 30, 2022 at 9:01 AM Peng Fan (OSS) peng.fan@oss.nxp.com wrote:
From: Peng Fan peng.fan@nxp.com
This patchset is to convert some i.MX8M boards to DM SERIAL
Note: this is based on my experience on i.MX8M*-EVK from NXP, I not have the following boards. If possible, please test.
The series looks good, thanks.
Just one minor comment on the last patch:
Peng Fan (15): imx: imx8mp_rsb3720a1: convert to DM_SERIAL imx: imx8m[m/n/p]_venice: Enable SPL_DM_SERIAL imx: imx8mm_mx8menlo: Enable DM_SERIAL imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL imx: imx8mm-cl-iot-gate: Enable DM_SERIAL imx: imx8mm_icore: Enable SPL_DM_SERIAL imx: imx8m[m/p]_phycore: Enable DM_SERIAL imx: imx8mn_var_som: enable DM_SERIAL imx: imx8mm_edm_sbc: Enable SPL_DM_SERIAL imx: kontron-sl-mx8mm: enable DM_SERIAL imx: imx8mn_bsh_smm_s2: drop CONFIG_MXC_UART_BASE imx: dts: move common changes to imx8mq-u-boot.dtsi imx: imx8mq-cm: enable CONFIG_DM_SERIAL imx: imx8mq-pico: enable CONFIG_DM_SERIAL imx: imx8mq-phandle: enable CONFIG_DM_SERIAL
In the Subject: s/phandle/phanbell
Reviewed-by: Fabio Estevam festevam@denx.de
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 8 -------- configs/imx8mp_rsb3720a1_4G_defconfig | 1 + configs/imx8mp_rsb3720a1_6G_defconfig | 1 + include/configs/imx8mp_rsb3720.h | 2 -- 4 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index 782025dc785..f129ebd429b 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -28,14 +28,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static const iomux_v3_cfg_t uart_pads[] = { - MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static const iomux_v3_cfg_t wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -81,8 +75,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - init_uart_clk(2);
return 0; diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index a7585ba71f0..b5a2add43da 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -135,6 +135,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_RTC_S35392A=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index 5d06dc4a88d..5f04f392ede 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -136,6 +136,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_RTC_S35392A=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index c5dd545471e..f2d9fa8cbf9 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -169,8 +169,6 @@ #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ #endif
-#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/gateworks/venice/spl.c | 22 ++-------------------- configs/imx8mm_venice_defconfig | 1 - configs/imx8mn_venice_defconfig | 1 - configs/imx8mp_venice_defconfig | 1 - include/configs/imx8mm_venice.h | 3 --- include/configs/imx8mn_venice.h | 3 --- include/configs/imx8mp_venice.h | 3 --- 7 files changed, 2 insertions(+), 32 deletions(-)
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 223f22d3463..af196e5b87c 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -87,33 +87,17 @@ static void spl_dram_init(int size) ddr_init(dram_timing); }
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#ifdef CONFIG_IMX8MM -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; #elif CONFIG_IMX8MN -static const iomux_v3_cfg_t uart_pads[] = { - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static const iomux_v3_cfg_t wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; #elif CONFIG_IMX8MP -static const iomux_v3_cfg_t uart_pads[] = { - MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static const iomux_v3_cfg_t wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -128,8 +112,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; }
@@ -276,8 +258,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
@@ -287,6 +267,8 @@ void board_init_f(ulong dummy) hang(); }
+ preloader_console_init(); + enable_tzc380();
/* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */ diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 490de193181..0165a4e5df0 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -113,7 +113,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 639fee7e5f1..63a65497371 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -112,7 +112,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 97c8bb59211..626ac247881 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -112,7 +112,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 1b26e0280e1..c3e92b76141 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -101,9 +101,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index a4826779022..41062b139f8 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -97,9 +97,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index aa0396db8b8..5242b56ad8c 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -97,9 +97,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64
On Sat, Apr 30, 2022 at 5:01 AM Peng Fan (OSS) peng.fan@oss.nxp.com wrote:
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com
board/gateworks/venice/spl.c | 22 ++-------------------- configs/imx8mm_venice_defconfig | 1 - configs/imx8mn_venice_defconfig | 1 - configs/imx8mp_venice_defconfig | 1 - include/configs/imx8mm_venice.h | 3 --- include/configs/imx8mn_venice.h | 3 --- include/configs/imx8mp_venice.h | 3 --- 7 files changed, 2 insertions(+), 32 deletions(-)
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 223f22d3463..af196e5b87c 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -87,33 +87,17 @@ static void spl_dram_init(int size) ddr_init(dram_timing); }
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#ifdef CONFIG_IMX8MM -static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; #elif CONFIG_IMX8MN -static const iomux_v3_cfg_t uart_pads[] = {
IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
static const iomux_v3_cfg_t wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; #elif CONFIG_IMX8MP -static const iomux_v3_cfg_t uart_pads[] = {
MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
static const iomux_v3_cfg_t wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -128,8 +112,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));return 0;}
@@ -276,8 +258,6 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();/* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);@@ -287,6 +267,8 @@ void board_init_f(ulong dummy) hang(); }
preloader_console_init();enable_tzc380(); /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 490de193181..0165a4e5df0 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -113,7 +113,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 639fee7e5f1..63a65497371 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -112,7 +112,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 97c8bb59211..626ac247881 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -112,7 +112,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 1b26e0280e1..c3e92b76141 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -101,9 +101,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index a4826779022..41062b139f8 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -97,9 +97,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index aa0396db8b8..5242b56ad8c 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -97,9 +97,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
2.36.0
Peng,
Thanks for doing this.
Acked-by: Tim Harvey tharvey@gateworks.com
It would be nice to get rid of the wdog pinmux as well... do you know if we can do that now as well?
This
On 2022/5/3 0:59, Tim Harvey wrote:
On Sat, Apr 30, 2022 at 5:01 AM Peng Fan (OSS) peng.fan@oss.nxp.com wrote:
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com
board/gateworks/venice/spl.c | 22 ++-------------------- configs/imx8mm_venice_defconfig | 1 - configs/imx8mn_venice_defconfig | 1 - configs/imx8mp_venice_defconfig | 1 - include/configs/imx8mm_venice.h | 3 --- include/configs/imx8mn_venice.h | 3 --- include/configs/imx8mp_venice.h | 3 --- 7 files changed, 2 insertions(+), 32 deletions(-)
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 223f22d3463..af196e5b87c 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -87,33 +87,17 @@ static void spl_dram_init(int size) ddr_init(dram_timing); }
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#ifdef CONFIG_IMX8MM -static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
- static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; #elif CONFIG_IMX8MN
-static const iomux_v3_cfg_t uart_pads[] = {
IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
- static const iomux_v3_cfg_t wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; #elif CONFIG_IMX8MP
-static const iomux_v3_cfg_t uart_pads[] = {
MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
- static const iomux_v3_cfg_t wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), };
@@ -128,8 +112,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));return 0;@@ -276,8 +258,6 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();/* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);@@ -287,6 +267,8 @@ void board_init_f(ulong dummy) hang(); }
preloader_console_init();enable_tzc380(); /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 490de193181..0165a4e5df0 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -113,7 +113,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 639fee7e5f1..63a65497371 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -112,7 +112,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 97c8bb59211..626ac247881 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -112,7 +112,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 1b26e0280e1..c3e92b76141 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -101,9 +101,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
- /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index a4826779022..41062b139f8 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -97,9 +97,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
- /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64
diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index aa0396db8b8..5242b56ad8c 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -97,9 +97,6 @@ #define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
- /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64
-- 2.36.0
Peng,
Thanks for doing this.
Acked-by: Tim Harvey tharvey@gateworks.com
It would be nice to get rid of the wdog pinmux as well... do you know if we can do that now as well?
watchdog needs Watchdog driver model enabled, should be doable. I could give a look.
Regards, Peng.
This
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/menlo/mx8menlo/mx8menlo.c | 9 --------- configs/imx8mm-mx8menlo_defconfig | 1 + include/configs/imx8mm-mx8menlo.h | 3 --- 3 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index a4d0becdcc8..95ff95ad360 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -12,15 +12,8 @@ #include <asm/mach-imx/iomux-v3.h> #include <spl.h>
-#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-/* Verdin UART_3, Console/Debug UART */ -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -48,8 +41,6 @@ void board_early_init(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - init_uart_clk(1);
setup_snvs(); diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index 0d3e19e5e31..a4164951de0 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -105,6 +105,7 @@ CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h index fd1831622f0..530ecd1d460 100644 --- a/include/configs/imx8mm-mx8menlo.h +++ b/include/configs/imx8mm-mx8menlo.h @@ -30,7 +30,4 @@ "initrd_addr=0x43800000\0" \ "kernel_image=fitImage\0"
-#undef CONFIG_MXC_UART_BASE -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - #endif /* __IMX8MM_MX8MENLO_H */
On 4/30/22 14:43, Peng Fan (OSS) wrote:
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl.
Signed-off-by: Peng Fan peng.fan@nxp.com
board/menlo/mx8menlo/mx8menlo.c | 9 --------- configs/imx8mm-mx8menlo_defconfig | 1 + include/configs/imx8mm-mx8menlo.h | 3 --- 3 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index a4d0becdcc8..95ff95ad360 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -12,15 +12,8 @@ #include <asm/mach-imx/iomux-v3.h> #include <spl.h>
-#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-/* Verdin UART_3, Console/Debug UART */ -static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
- static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), };
@@ -48,8 +41,6 @@ void board_early_init(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
- init_uart_clk(1);
But that means the UART is available much later in SPL ?
Also, init_uart_clk(1) still hard-codes UART number , can the UART driver init those UART clock instead too ?
On Sat, Apr 30, 2022 at 12:00 PM Marek Vasut marex@denx.de wrote:
On 4/30/22 14:43, Peng Fan (OSS) wrote:
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl.
Signed-off-by: Peng Fan peng.fan@nxp.com
board/menlo/mx8menlo/mx8menlo.c | 9 --------- configs/imx8mm-mx8menlo_defconfig | 1 + include/configs/imx8mm-mx8menlo.h | 3 --- 3 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index a4d0becdcc8..95ff95ad360 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -12,15 +12,8 @@ #include <asm/mach-imx/iomux-v3.h> #include <spl.h>
-#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-/* Verdin UART_3, Console/Debug UART */ -static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
- static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), };
@@ -48,8 +41,6 @@ void board_early_init(void)
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));init_uart_clk(1);But that means the UART is available much later in SPL ?
Also, init_uart_clk(1) still hard-codes UART number , can the UART driver init those UART clock instead too ?
I just submitted an RFC to address that [1]. The RTC is based on the work Peng did.
If people are OK with my proposal or changing the serial driver, I can work on porting the 8mn and 8mp clocks to let the drivers enable the clocks.
[1] - https://patchwork.ozlabs.org/project/uboot/patch/20220430161422.558361-2-afo...
adam
[1] - https://patchwork.ozlabs.org/project/uboot/patch/20220430161422.558361-2-afo...
On 4/30/22 19:32, Adam Ford wrote:
On Sat, Apr 30, 2022 at 12:00 PM Marek Vasut marex@denx.de wrote:
On 4/30/22 14:43, Peng Fan (OSS) wrote:
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl.
Signed-off-by: Peng Fan peng.fan@nxp.com
board/menlo/mx8menlo/mx8menlo.c | 9 --------- configs/imx8mm-mx8menlo_defconfig | 1 + include/configs/imx8mm-mx8menlo.h | 3 --- 3 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index a4d0becdcc8..95ff95ad360 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -12,15 +12,8 @@ #include <asm/mach-imx/iomux-v3.h> #include <spl.h>
-#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-/* Verdin UART_3, Console/Debug UART */ -static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
- static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), };
@@ -48,8 +41,6 @@ void board_early_init(void)
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));init_uart_clk(1);But that means the UART is available much later in SPL ?
Also, init_uart_clk(1) still hard-codes UART number , can the UART driver init those UART clock instead too ?
I just submitted an RFC to address that [1]. The RTC is based on the work Peng did.
If people are OK with my proposal or changing the serial driver, I can work on porting the 8mn and 8mp clocks to let the drivers enable the clocks.
[1] - https://patchwork.ozlabs.org/project/uboot/patch/20220430161422.558361-2-afo...
That still works only after spl_early_init() is called, right ?
On Sat, Apr 30, 2022 at 1:04 PM Marek Vasut marex@denx.de wrote:
On 4/30/22 19:32, Adam Ford wrote:
On Sat, Apr 30, 2022 at 12:00 PM Marek Vasut marex@denx.de wrote:
On 4/30/22 14:43, Peng Fan (OSS) wrote:
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl.
Signed-off-by: Peng Fan peng.fan@nxp.com
board/menlo/mx8menlo/mx8menlo.c | 9 --------- configs/imx8mm-mx8menlo_defconfig | 1 + include/configs/imx8mm-mx8menlo.h | 3 --- 3 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index a4d0becdcc8..95ff95ad360 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -12,15 +12,8 @@ #include <asm/mach-imx/iomux-v3.h> #include <spl.h>
-#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-/* Verdin UART_3, Console/Debug UART */ -static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
- static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), };
@@ -48,8 +41,6 @@ void board_early_init(void)
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));init_uart_clk(1);But that means the UART is available much later in SPL ?
Also, init_uart_clk(1) still hard-codes UART number , can the UART driver init those UART clock instead too ?
I just submitted an RFC to address that [1]. The RTC is based on the work Peng did.
If people are OK with my proposal or changing the serial driver, I can work on porting the 8mn and 8mp clocks to let the drivers enable the clocks.
[1] - https://patchwork.ozlabs.org/project/uboot/patch/20220430161422.558361-2-afo...
That still works only after spl_early_init() is called, right ?
As far as I can tell, we need spl init to run to get the device tree stuff functional in order to enable either the clocks or the serial port. However, I have noticed the README states that board_init_f should not call board_init_r directly and BSS isn't not available. It seems like there might be more work to do on cleaning up the various board_init_f functions. It seems like everyone clears BSS and calls board_init_r directly.
I wonder if we could consolidate all these boards files into a platform specific startup function and let people who have board-specific stuff they need done to do it in early init or something.
adam
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/beacon/imx8mm/spl.c | 12 ++---------- board/beacon/imx8mn/spl.c | 11 ++--------- configs/imx8mm_beacon_defconfig | 1 - configs/imx8mn_beacon_2g_defconfig | 1 - configs/imx8mn_beacon_defconfig | 1 - include/configs/imx8mm_beacon.h | 2 -- include/configs/imx8mn_beacon.h | 2 -- 7 files changed, 4 insertions(+), 26 deletions(-)
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 12266b22a42..f92b4c3ed0a 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -59,14 +59,8 @@ int board_fit_config_name_match(const char *name) } #endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -79,8 +73,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; }
@@ -128,8 +120,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
@@ -139,6 +129,8 @@ void board_init_f(ulong dummy) hang(); }
+ preloader_console_init(); + ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev); diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index bb51be01c52..4563446db19 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -68,7 +68,6 @@ int board_fit_config_name_match(const char *name) } #endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
@@ -76,11 +75,6 @@ static iomux_v3_cfg_t const pwm_pads[] = { IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL), };
-static iomux_v3_cfg_t const uart_pads[] = { - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -95,7 +89,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); init_uart_clk(1);
return 0; @@ -114,14 +107,14 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init(); - ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); }
+ preloader_console_init(); + enable_tzc380();
/* DDR initialization */ diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 9cd8ac97285..a8981975f66 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -112,7 +112,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 145f96d491d..cf1720725d0 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -114,7 +114,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 9052e68e967..882a6044989 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -118,7 +118,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 7c17f14964f..4c9b5491f78 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -91,8 +91,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 41ce3c1c8ce..c16dda5e22c 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -107,8 +107,6 @@ #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ #endif
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64
On Sat, Apr 30, 2022 at 7:01 AM Peng Fan (OSS) peng.fan@oss.nxp.com wrote:
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_init to make sure driver model work.
Thanks for doing this!
Tested-by: Adam Ford aford173@gmail.com #imx8mm_beacon
Signed-off-by: Peng Fan peng.fan@nxp.com
board/beacon/imx8mm/spl.c | 12 ++---------- board/beacon/imx8mn/spl.c | 11 ++--------- configs/imx8mm_beacon_defconfig | 1 - configs/imx8mn_beacon_2g_defconfig | 1 - configs/imx8mn_beacon_defconfig | 1 - include/configs/imx8mm_beacon.h | 2 -- include/configs/imx8mn_beacon.h | 2 -- 7 files changed, 4 insertions(+), 26 deletions(-)
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 12266b22a42..f92b4c3ed0a 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -59,14 +59,8 @@ int board_fit_config_name_match(const char *name) } #endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -79,8 +73,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));return 0;}
@@ -128,8 +120,6 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();/* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);@@ -139,6 +129,8 @@ void board_init_f(ulong dummy) hang(); }
preloader_console_init();ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev);diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index bb51be01c52..4563446db19 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -68,7 +68,6 @@ int board_fit_config_name_match(const char *name) } #endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
@@ -76,11 +75,6 @@ static iomux_v3_cfg_t const pwm_pads[] = { IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL), };
-static iomux_v3_cfg_t const uart_pads[] = {
IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),-};
static iomux_v3_cfg_t const wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -95,7 +89,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); init_uart_clk(1); return 0;@@ -114,14 +107,14 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); }
preloader_console_init();enable_tzc380(); /* DDR initialization */diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 9cd8ac97285..a8981975f66 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -112,7 +112,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 145f96d491d..cf1720725d0 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -114,7 +114,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 9052e68e967..882a6044989 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -118,7 +118,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 7c17f14964f..4c9b5491f78 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -91,8 +91,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 41ce3c1c8ce..c16dda5e22c 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -107,8 +107,6 @@ #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ #endif
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
2.36.0
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart3 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/compulab/imx8mm-cl-iot-gate/spl.c | 12 ++---------- configs/imx8mm-cl-iot-gate-optee_defconfig | 1 + configs/imx8mm-cl-iot-gate_defconfig | 1 + include/configs/imx8mm-cl-iot-gate.h | 2 -- 4 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c index 2dc62d6682e..f183704c9d2 100644 --- a/board/compulab/imx8mm-cl-iot-gate/spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -83,14 +83,8 @@ int board_fit_config_name_match(const char *name) } #endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -103,8 +97,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; }
@@ -155,8 +147,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
@@ -166,6 +156,8 @@ void board_init_f(ulong dummy) hang(); }
+ preloader_console_init(); + ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev); diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index 0bde51a91f5..bcabc0d91d8 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -110,6 +110,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_RTC_ABX80X=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index d734586a60c..2088ad47dbf 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -113,6 +113,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_RTC_ABX80X=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index c20c32b6951..fcb46c16605 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -145,8 +145,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/engicam/imx8mm/spl.c | 14 +++----------- configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 - configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 - include/configs/imx8mm_icore_mx8mm.h | 3 --- 4 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c index f9be769ec59..f75f2dc634c 100644 --- a/board/engicam/imx8mm/spl.c +++ b/board/engicam/imx8mm/spl.c @@ -54,19 +54,11 @@ int board_fit_config_name_match(const char *name) } #endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - int board_early_init_f(void) { - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - - return 0; + return 0; }
void board_init_f(ulong dummy) @@ -81,8 +73,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
@@ -92,6 +82,8 @@ void board_init_f(ulong dummy) hang(); }
+ preloader_console_init(); + enable_tzc380();
/* DDR initialization */ diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index 535ff6dcba5..d95a74a7237 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -74,7 +74,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 101d5a00bc7..43c697a39d8 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -74,7 +74,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index f521add5b04..1a439370c09 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -65,9 +65,6 @@ #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ #define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/phytec/phycore_imx8mm/spl.c | 12 ++---------- board/phytec/phycore_imx8mp/spl.c | 8 -------- configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + include/configs/phycore_imx8mm.h | 3 --- include/configs/phycore_imx8mp.h | 3 --- 6 files changed, 4 insertions(+), 24 deletions(-)
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index d54145ef995..7f24a3affc8 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -57,14 +57,8 @@ int board_fit_config_name_match(const char *name) return 0; }
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
-static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -77,8 +71,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; }
@@ -92,8 +84,6 @@ void board_init_f(ulong dummy)
board_early_init_f();
- preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
@@ -103,6 +93,8 @@ void board_init_f(ulong dummy) hang(); }
+ preloader_console_init(); + enable_tzc380();
/* DDR initialization */ diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 19c486e5517..38a581bef57 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -89,14 +89,8 @@ int board_fit_config_name_match(const char *name) return 0; }
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = { - MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -109,8 +103,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; }
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index ba5833f7060..9da222afc54 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -107,6 +107,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 86d0f4df7f6..a851b1bdccb 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -98,6 +98,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 71f0c42ec0c..564b8125ba3 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -83,9 +83,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
-/* UART */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 0c963b62b3b..3e4315f2b81 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -83,9 +83,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000
-/* UART */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64
Hello Peng,
Am Samstag, dem 30.04.2022 um 20:43 +0800 schrieb Peng Fan (OSS):
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work.
thank you for the patch. Works for phyCORE-i.MX8MM and phyCORE-i.MX8MP.
Tested-by: Teresa Remmet t.remmet@phytec.de
Regards, Teresa
Signed-off-by: Peng Fan peng.fan@nxp.com
board/phytec/phycore_imx8mm/spl.c | 12 ++---------- board/phytec/phycore_imx8mp/spl.c | 8 -------- configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + include/configs/phycore_imx8mm.h | 3 --- include/configs/phycore_imx8mp.h | 3 --- 6 files changed, 4 insertions(+), 24 deletions(-)
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index d54145ef995..7f24a3affc8 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -57,14 +57,8 @@ int board_fit_config_name_match(const char *name) return 0; }
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -77,8 +71,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads,
ARRAY_SIZE(uart_pads));
- return 0;
}
@@ -92,8 +84,6 @@ void board_init_f(ulong dummy)
board_early_init_f();
- preloader_console_init();
- /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
@@ -103,6 +93,8 @@ void board_init_f(ulong dummy) hang(); }
preloader_console_init();
enable_tzc380();
/* DDR initialization */
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 19c486e5517..38a581bef57 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -89,14 +89,8 @@ int board_fit_config_name_match(const char *name) return 0; }
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = {
- MX8MP_PAD_UART1_RXD__UART1_DCE_RX |
MUX_PAD_CTRL(UART_PAD_CTRL),
- MX8MP_PAD_UART1_TXD__UART1_DCE_TX |
MUX_PAD_CTRL(UART_PAD_CTRL), -};
static iomux_v3_cfg_t const wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -109,8 +103,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads,
ARRAY_SIZE(uart_pads));
- return 0;
}
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore- imx8mm_defconfig index ba5833f7060..9da222afc54 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -107,6 +107,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore- imx8mp_defconfig index 86d0f4df7f6..a851b1bdccb 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -98,6 +98,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 71f0c42ec0c..564b8125ba3 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -83,9 +83,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
-/* UART */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 0c963b62b3b..3e4315f2b81 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -83,9 +83,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000
-/* UART */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/variscite/imx8mn_var_som/spl.c | 11 ++--------- configs/imx8mn_var_som_defconfig | 1 + include/configs/imx8mn_var_som.h | 2 -- 3 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c index 32703c5f0b3..1a8b64fc0a9 100644 --- a/board/variscite/imx8mn_var_som/spl.c +++ b/board/variscite/imx8mn_var_som/spl.c @@ -40,14 +40,8 @@ void spl_board_init(void) puts("Failed to find clock node. Check device tree\n"); }
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static const iomux_v3_cfg_t uart_pads[] = { - IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static const iomux_v3_cfg_t wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -59,7 +53,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); init_uart_clk(3);
return 0; @@ -78,14 +71,14 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init(); - ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); }
+ preloader_console_init(); + /* DDR initialization */ spl_dram_init();
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 5ec82f2a926..39209f62c46 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -83,6 +83,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 318289b76bc..6ce60b0d704 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -64,8 +64,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
-#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64
Hi Peng,
On 4/30/22 09:43, Peng Fan (OSS) wrote:
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com
board/variscite/imx8mn_var_som/spl.c | 11 ++--------- configs/imx8mn_var_som_defconfig | 1 + include/configs/imx8mn_var_som.h | 2 -- 3 files changed, 3 insertions(+), 11 deletions(-)
Reviewed-by: Ariel D'Alessandro ariel.dalessandro@collabora.com
Thanks!
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_SPL_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/data_modul/imx8mm_edm_sbc/spl.c | 12 ++---------- configs/imx8mm_data_modul_edm_sbc_defconfig | 1 - include/configs/imx8mm_data_modul_edm_sbc.h | 2 -- 3 files changed, 2 insertions(+), 13 deletions(-)
diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c index 36cad14fc41..f5063eb8c19 100644 --- a/board/data_modul/imx8mm_edm_sbc/spl.c +++ b/board/data_modul/imx8mm_edm_sbc/spl.c @@ -28,14 +28,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static const iomux_v3_cfg_t uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static const iomux_v3_cfg_t wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -47,8 +41,6 @@ static void data_modul_imx8mm_edm_sbc_early_init_f(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); }
static int data_modul_imx8mm_edm_sbc_board_power_init(void) @@ -149,8 +141,6 @@ void board_init_f(ulong dummy)
data_modul_imx8mm_edm_sbc_early_init_f();
- preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
@@ -160,6 +150,8 @@ void board_init_f(ulong dummy) hang(); }
+ preloader_console_init(); + ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev); diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index afc8c43ca99..dd3c2e19e52 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -200,7 +200,6 @@ CONFIG_DM_RTC=y CONFIG_RTC_M41T62=y CONFIG_CONS_INDEX=2 CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 33778a2365e..ff98095d27d 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -41,8 +41,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */
-#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com --- board/kontron/sl-mx8mm/spl.c | 12 ++---------- configs/kontron-sl-mx8mm_defconfig | 1 + include/configs/kontron-sl-mx8mm.h | 1 - 3 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 4ef03c8c172..a58a75dc958 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -32,7 +32,6 @@ enum {
#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23) @@ -51,11 +50,6 @@ static iomux_v3_cfg_t const touch_gpio[] = { IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL) };
-static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -230,8 +224,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; }
@@ -273,8 +265,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
@@ -284,6 +274,8 @@ void board_init_f(ulong dummy) hang(); }
+ preloader_console_init(); + enable_tzc380();
/* PMIC initialization */ diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 1375c78a8c4..44ed4f3fb1f 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -103,6 +103,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_RTC=y CONFIG_RTC_RV8803=y CONFIG_CONS_INDEX=2 +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 1b429f7dbe2..20f7f7a74f5 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -28,7 +28,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Board and environment settings */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR #define CONFIG_HOSTNAME "kontron-mx8mm"
#ifdef CONFIG_USB_EHCI_HCD
Am 30.04.22 um 14:43 schrieb Peng Fan (OSS):
From: Peng Fan peng.fan@nxp.com
Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_init to make sure driver model work.
Signed-off-by: Peng Fan peng.fan@nxp.com
Acked-by: Frieder Schrempf frieder.schrempf@kontron.de
board/kontron/sl-mx8mm/spl.c | 12 ++---------- configs/kontron-sl-mx8mm_defconfig | 1 + include/configs/kontron-sl-mx8mm.h | 1 - 3 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 4ef03c8c172..a58a75dc958 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -32,7 +32,6 @@ enum {
#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23) @@ -51,11 +50,6 @@ static iomux_v3_cfg_t const touch_gpio[] = { IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL) };
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -230,8 +224,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
- return 0;
}
@@ -273,8 +265,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
- /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
@@ -284,6 +274,8 @@ void board_init_f(ulong dummy) hang(); }
preloader_console_init();
enable_tzc380();
/* PMIC initialization */
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 1375c78a8c4..44ed4f3fb1f 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -103,6 +103,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_RTC=y CONFIG_RTC_RV8803=y CONFIG_CONS_INDEX=2 +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 1b429f7dbe2..20f7f7a74f5 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -28,7 +28,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Board and environment settings */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR #define CONFIG_HOSTNAME "kontron-mx8mm"
#ifdef CONFIG_USB_EHCI_HCD
From: Peng Fan peng.fan@nxp.com
CONFIG_DM_SERIAL is enabled, this macro not needed.
Signed-off-by: Peng Fan peng.fan@nxp.com --- include/configs/imx8mn_bsh_smm_s2_common.h | 2 -- 1 file changed, 2 deletions(-)
diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 6387576c2da..57be38d9433 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -45,8 +45,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000
-#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64
Hi
Il sab 30 apr 2022, 14:02 Peng Fan (OSS) peng.fan@oss.nxp.com ha scritto:
From: Peng Fan peng.fan@nxp.com
CONFIG_DM_SERIAL is enabled, this macro not needed.
Signed-off-by: Peng Fan peng.fan@nxp.com
include/configs/imx8mn_bsh_smm_s2_common.h | 2 -- 1 file changed, 2 deletions(-)
diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 6387576c2da..57be38d9433 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -45,8 +45,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000
-#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
2.36.0
Reviewed-by: Michael Trimarchi michael@amarulasolutions.com
Thank you
Hi Stefano,
On 2022/4/30 20:43, Peng Fan (OSS) wrote:
From: Peng Fan peng.fan@nxp.com
CONFIG_DM_SERIAL is enabled, this macro not needed.
I squashed this patch to
"[PATCH V2] imx: drop CONFIG_MXC_UART_BASE"
Thanks, Peng.
Signed-off-by: Peng Fan peng.fan@nxp.com
include/configs/imx8mn_bsh_smm_s2_common.h | 2 -- 1 file changed, 2 deletions(-)
diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 6387576c2da..57be38d9433 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -45,8 +45,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000
-#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
- /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64
From: Peng Fan peng.fan@nxp.com
Move some common changes to imx8mq-u-boot.dtsi, so others could reuse it
Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/imx8mq-evk-u-boot.dtsi | 24 ------------------------ arch/arm/dts/imx8mq-u-boot.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi index 919c1f66d38..67da69a2eb3 100644 --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -2,30 +2,6 @@
#include "imx8mq-u-boot.dtsi"
-&{/soc@0} { - u-boot,dm-spl; -}; - -&{/soc@0/bus@30000000} { - u-boot,dm-spl; -}; - -&{/soc@0/bus@30400000} { - u-boot,dm-spl; -}; - -&{/soc@0/bus@30800000} { - u-boot,dm-spl; -}; - -&{/soc@0/bus@32c00000} { - u-boot,dm-spl; -}; - -&iomuxc { - u-boot,dm-spl; -}; - &pinctrl_uart1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 1dc060ce0c2..912a3d4a356 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -10,6 +10,30 @@
};
+&{/soc@0} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30000000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30400000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@32c00000} { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + &binman { u-boot-spl-ddr { align = <4>;
From: Peng Fan peng.fan@nxp.com
Marked related nodes as u-boot,dm-spl for serial driver model Enable CONFIG_DM_SERIAL
Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/imx8mq-cm-u-boot.dtsi | 8 ++++++++ configs/imx8mq_cm_defconfig | 1 + 2 files changed, 9 insertions(+)
diff --git a/arch/arm/dts/imx8mq-cm-u-boot.dtsi b/arch/arm/dts/imx8mq-cm-u-boot.dtsi index 476a8e3dba2..e2f4b0e740d 100644 --- a/arch/arm/dts/imx8mq-cm-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi @@ -9,6 +9,14 @@ }; };
+&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&uart1 { + u-boot,dm-spl; +}; + &binman { u-boot-spl-ddr { filename = "u-boot-spl-ddr.bin"; diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index 1cca21ec55a..8e024604378 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -78,6 +78,7 @@ CONFIG_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y
From: Peng Fan peng.fan@nxp.com
Marked related nodes as u-boot,dm-spl for serial driver model Enable CONFIG_DM_SERIAL
Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi | 9 +++++++++ configs/pico-imx8mq_defconfig | 1 + 2 files changed, 10 insertions(+) create mode 100644 arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi
diff --git a/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi b/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi new file mode 100644 index 00000000000..9537aedf29e --- /dev/null +++ b/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&uart1 { + u-boot,dm-spl; +}; diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index 1b0d12cf8d4..91aca29e830 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -83,5 +83,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y
From: Peng Fan peng.fan@nxp.com
Marked related nodes as u-boot,dm-spl for serial driver model Enable CONFIG_DM_SERIAL
Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/imx8mq-phanbell-u-boot.dtsi | 8 ++++++++ configs/imx8mq_phanbell_defconfig | 1 + 2 files changed, 9 insertions(+)
diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi index a65a942ee7a..8d6f3058295 100644 --- a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi @@ -5,3 +5,11 @@ ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; + +&uart1 { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index a86311b7cc5..095e42e6ba1 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -83,5 +83,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y
participants (9)
-
Adam Ford -
Ariel D'Alessandro -
Fabio Estevam -
Frieder Schrempf -
Marek Vasut -
Michael Nazzareno Trimarchi -
Peng Fan (OSS) -
Teresa Remmet -
Tim Harvey