The change fixes PHY write operation, which incorrectly waits for released busy state before issuing a write operation, this breaks sequential write/read operation logic, because read operation starts immediately on request and it completes, when busy state is gone.

Instead of adding the second preceding busy state check to read function, do busy state release check after issuing a write operation, this method of operation is also recommended by the LPC32xx User's Manual, see MII Mgmt Indicators Register notes:

For PHY Write if scan is not used: 1. Write 0 to MCMD 2. Write PHY address and register address to MADR 3. Write data to MWTD 4. Wait for busy bit to be cleared in MIND

Reported-by: Alexandre Messier amessier@tycoint.com Signed-off-by: Vladimir Zapolskiy vz@mleia.com Tested-by: Alexandre Messier amessier@tycoint.com ---

The change replaces: https://patchwork.ozlabs.org/patch/557713/

drivers/net/lpc32xx_eth.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c index e76e9bc..3ba5b4b 100644 --- a/drivers/net/lpc32xx_eth.c +++ b/drivers/net/lpc32xx_eth.c @@ -304,6 +304,13 @@ static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) return -EFAULT; }

+ /* write the phy and reg addressse into the MII address reg */ + writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), + &regs->madr); + + /* write data to the MII write register */ + writel(data, &regs->mwtd); + /* wait till the MII is not busy */ timeout = MII_TIMEOUT; do { @@ -319,13 +326,6 @@ static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) return -EFAULT; }

- /* write the phy and reg addressse into the MII address reg */ - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), - &regs->madr); - - /* write data to the MII write register */ - writel(data, &regs->mwtd); - /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr, reg_ofs, data);*/