[PATCH 1/3] Revert "sama5d3: Fix Galois Field Table offsets"
This reverts commit 786f888b743e9b83c9095cb9b5548ebe2e29afc5.
Looks like the datasheet at https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D3-Series-Data-sheet-D... is wrong, and the testing was poorly done, because the PMECC did not raise any error, but also didn't correct any bitflips. Restoring the offsets as they were before, makes the PMECC on sama5d3x capable of correcting bitflips.
Fixes: 786f888b74 ("sama5d3: Fix Galois Field Table offsets") Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- arch/arm/mach-at91/include/mach/sama5d3.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index f4f05676f7..83f18a8148 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -190,8 +190,8 @@ /* * PMECC table in ROM */ -#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 -#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 +#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000
/* * SAMA5D3 specific prototypes
Enable NAND on mmc defconfig for greater flexibility and for consistency reasons. All our other boards that have a NAND flash integrated, enable NAND regardless of the type of the defconfig.
Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- configs/sam9x60ek_mmc_defconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index e97b20aeb3..e5edf45fee 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -25,6 +25,8 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -48,6 +50,11 @@ CONFIG_MICROCHIP_FLEXCOM=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=8 CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MACB=y
From: "Kai Stuhlemmer (ebee Engineering)" kai.stuhlemmer@ebee.de
Not correcting anything in case of empty ECC data area is not an appropriate strategy, because an uncorrected bit-flip in an empty sector may cause upper layers (namely UBI) fail to work properly. Therefore the approach chosen in Linux kernel and other u-boot mtd drivers has been adopted, where a heuristic implemented by nand_check_erased_ecc_chunk() is used in order to detect and correct empty sectors.
Tested with sama5d3_xplained and sam9x60-ek.
Signed-off-by: Kai Stuhlemmer (ebee Engineering) kai.stuhlemmer@ebee.de Tested-by: Tudor Ambarus tudor.ambarus@microchip.com [ta: reorder if conditions, change commit subject, s/uint8_t/u8.] Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com --- drivers/mtd/nand/raw/atmel_nand.c | 37 +++++++++++++++---------------- 1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index abc432c862..6541c3bea8 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -493,21 +493,9 @@ static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf, { struct nand_chip *nand_chip = mtd_to_nand(mtd); struct atmel_nand_host *host = nand_get_controller_data(nand_chip); - int i, err_nbr, eccbytes; - uint8_t *buf_pos; - - /* SAMA5D4 PMECC IP can correct errors for all 0xff page */ - if (host->pmecc_version >= PMECC_VERSION_SAMA5D4) - goto normal_check; - - eccbytes = nand_chip->ecc.bytes; - for (i = 0; i < eccbytes; i++) - if (ecc[i] != 0xff) - goto normal_check; - /* Erased page, return OK */ - return 0; + int i, err_nbr; + u8 *buf_pos, *ecc_pos;
-normal_check: for (i = 0; i < host->pmecc_sector_number; i++) { err_nbr = 0; if (pmecc_stat & 0x1) { @@ -518,15 +506,26 @@ normal_check: pmecc_get_sigma(mtd);
err_nbr = pmecc_err_location(mtd); - if (err_nbr == -1) { + if (err_nbr >= 0) { + pmecc_correct_data(mtd, buf_pos, ecc, i, + host->pmecc_bytes_per_sector, + err_nbr); + } else if (host->pmecc_version < PMECC_VERSION_SAMA5D4) { + ecc_pos = ecc + i * host->pmecc_bytes_per_sector; + + err_nbr = nand_check_erased_ecc_chunk( + buf_pos, host->pmecc_sector_size, + ecc_pos, host->pmecc_bytes_per_sector, + NULL, 0, host->pmecc_corr_cap); + } + + if (err_nbr < 0) { dev_err(mtd->dev, "PMECC: Too many errors\n"); mtd->ecc_stats.failed++; return -EBADMSG; - } else { - pmecc_correct_data(mtd, buf_pos, ecc, i, - host->pmecc_bytes_per_sector, err_nbr); - mtd->ecc_stats.corrected += err_nbr; } + + mtd->ecc_stats.corrected += err_nbr; } pmecc_stat >>= 1; }
On 5/21/21 11:52 AM, Tudor Ambarus wrote:
This reverts commit 786f888b743e9b83c9095cb9b5548ebe2e29afc5.
Looks like the datasheet at https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D3-Series-Data-sheet-D... is wrong, and the testing was poorly done, because the PMECC did not raise any error, but also didn't correct any bitflips. Restoring the offsets as they were before, makes the PMECC on sama5d3x capable of correcting bitflips.
Fixes: 786f888b74 ("sama5d3: Fix Galois Field Table offsets") Signed-off-by: Tudor Ambarus tudor.ambarus@microchip.com
Applied series to u-boot-atmel/next, thanks !
participants (2)
-
Eugen.Hristev＠microchip.com -
Tudor Ambarus