[U-Boot] [PATCH 0/5] MIPS Release 6 Support
This series introduces support for building U-Boot for release 6 of the MIPS architecture. This is supported by CPUs such as the M62xx, I6400 & P6600 as well as by emulators such as QEMU.
Paul Burton (5): MIPS: Use unchecked immediate addition/subtraction MIPS: Simplify CONFIG_SYS_CPU values MIPS: Support for targetting MIPSr6 malta: Remove ".set mips32" directive malta: Support MIPS32r6 configurations
arch/mips/Kconfig | 39 ++++++++++++++++++++++++++++++-------- arch/mips/Makefile | 2 ++ arch/mips/cpu/start.S | 22 +++++++++++---------- arch/mips/lib/cache_init.S | 2 +- board/imgtec/malta/lowlevel_init.S | 1 - 5 files changed, 46 insertions(+), 20 deletions(-)
In MIPS assembly there have historically been 2 variants of immediate addition - the standard "addi" which traps if an overflow occurs, and the unchecked "addiu" which does not trap on overflow. In release 6 of the MIPS architecture the trapping variants of immediate addition & subtraction have been removed. In preparation for supporting MIPSr6, stop using the trapping instructions from assembly & switch to their unchecked variants.
Signed-off-by: Paul Burton paul.burton@imgtec.com ---
arch/mips/cpu/start.S | 22 ++++++++++++---------- arch/mips/lib/cache_init.S | 2 +- 2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 1b56ca3..fc6dd66 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -164,12 +164,14 @@ reset: li t0, -16 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR and sp, t1, t0 # force 16 byte alignment - PTR_SUB sp, sp, GD_SIZE # reserve space for gd + PTR_SUBU \ + sp, sp, GD_SIZE # reserve space for gd and sp, sp, t0 # force 16 byte alignment move k0, sp # save gd pointer #ifdef CONFIG_SYS_MALLOC_F_LEN li t2, CONFIG_SYS_MALLOC_F_LEN - PTR_SUB sp, sp, t2 # reserve space for early malloc + PTR_SUBU \ + sp, sp, t2 # reserve space for early malloc and sp, sp, t0 # force 16 byte alignment #endif move fp, sp @@ -179,7 +181,7 @@ reset: 1: PTR_S zero, 0(t0) blt t0, t1, 1b - PTR_ADDI t0, PTRSIZE + PTR_ADDIU t0, PTRSIZE
#ifdef CONFIG_SYS_MALLOC_F_LEN PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset @@ -237,7 +239,7 @@ ENTRY(relocate_code) move a0, s2 # a0 <-- destination address
/* Jump to where we've relocated ourselves */ - PTR_ADDI t0, s2, in_ram - _start + PTR_ADDIU t0, s2, in_ram - _start jr t0 nop
@@ -257,7 +259,7 @@ in_ram: PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_ - PTR_ADDI t8, t8, 2 * PTRSIZE # skipping first two entries + PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries PTR_LI t2, 2 1: PTR_L t1, 0(t8) @@ -265,16 +267,16 @@ in_ram: PTR_ADD t1, s1 PTR_S t1, 0(t8) 2: - PTR_ADDI t2, 1 + PTR_ADDIU t2, 1 blt t2, t3, 1b - PTR_ADDI t8, PTRSIZE + PTR_ADDIU t8, PTRSIZE
/* Update dynamic relocations */ PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
b 2f # skip first reserved entry - PTR_ADDI t1, 2 * PTRSIZE + PTR_ADDIU t1, 2 * PTRSIZE
1: lw t8, -4(t1) # t8 <-- relocation info @@ -293,7 +295,7 @@ in_ram:
2: blt t1, t2, 1b - PTR_ADDI t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes + PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
/* * Clear BSS @@ -307,7 +309,7 @@ in_ram: 1: PTR_S zero, 0(t1) blt t1, t2, 1b - PTR_ADDI t1, PTRSIZE + PTR_ADDIU t1, PTRSIZE
move a0, s0 # a0 <-- gd move a1, s2 diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 14cc2c4..08b7c3a 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -64,7 +64,7 @@ /* detect associativity */ srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF) - addi \sz, \sz, 1 + addiu \sz, \sz, 1
/* sz *= line_sz */ mul \sz, \sz, \line_sz
Rather than having the values for CONFIG_SYS_CPU depend upon each architecture revision, have them depend upon the more general CONFIG_CPU_MIPS32 & CONFIG_CPU_MIPS64 which in turn depend upon the architecture revisions.
This is done in preparation for adding MIPSr6 support, which would otherwise need to introduce new cases here.
Signed-off-by: Paul Burton paul.burton@imgtec.com ---
arch/mips/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fe37d1f..0520b30 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -5,8 +5,8 @@ config SYS_ARCH default "mips"
config SYS_CPU - default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2 - default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2 + default "mips32" if CPU_MIPS32 + default "mips64" if CPU_MIPS64
choice prompt "Target select"
Add support for targetting MIPS32r6 & MIPS64r6 systems, in the same way that we currently select release 1 or release 2 targets. MIPSr6 is not entirely backwards compatible with earlier releases of the architecture. Some instructions are encoded differently, some are removed, some are reused, so it is not practical to run U-Boot built for earlier revisions on a MIPSr6 system. Update their Kconfig help text to reflect that.
Signed-off-by: Paul Burton paul.burton@imgtec.com ---
arch/mips/Kconfig | 34 ++++++++++++++++++++++++++++------ arch/mips/Makefile | 2 ++ 2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0520b30..e53fa83 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -98,7 +98,7 @@ config CPU_MIPS32_R1 depends on SUPPORTS_CPU_MIPS32_R1 select 32BIT help - Choose this option to build an U-Boot for release 1 or later of the + Choose this option to build an U-Boot for release 1 through 5 of the MIPS32 architecture.
config CPU_MIPS32_R2 @@ -106,7 +106,15 @@ config CPU_MIPS32_R2 depends on SUPPORTS_CPU_MIPS32_R2 select 32BIT help - Choose this option to build an U-Boot for release 2 or later of the + Choose this option to build an U-Boot for release 2 through 5 of the + MIPS32 architecture. + +config CPU_MIPS32_R6 + bool "MIPS32 Release 6" + depends on SUPPORTS_CPU_MIPS32_R6 + select 32BIT + help + Choose this option to build an U-Boot for release 6 or later of the MIPS32 architecture.
config CPU_MIPS64_R1 @@ -114,7 +122,7 @@ config CPU_MIPS64_R1 depends on SUPPORTS_CPU_MIPS64_R1 select 64BIT help - Choose this option to build a kernel for release 1 or later of the + Choose this option to build a kernel for release 1 through 5 of the MIPS64 architecture.
config CPU_MIPS64_R2 @@ -122,7 +130,15 @@ config CPU_MIPS64_R2 depends on SUPPORTS_CPU_MIPS64_R2 select 64BIT help - Choose this option to build a kernel for release 2 or later of the + Choose this option to build a kernel for release 2 through 5 of the + MIPS64 architecture. + +config CPU_MIPS64_R6 + bool "MIPS64 Release 6" + depends on SUPPORTS_CPU_MIPS64_R6 + select 64BIT + help + Choose this option to build a kernel for release 6 or later of the MIPS64 architecture.
endchoice @@ -169,19 +185,25 @@ config SUPPORTS_CPU_MIPS32_R1 config SUPPORTS_CPU_MIPS32_R2 bool
+config SUPPORTS_CPU_MIPS32_R6 + bool + config SUPPORTS_CPU_MIPS64_R1 bool
config SUPPORTS_CPU_MIPS64_R2 bool
+config SUPPORTS_CPU_MIPS64_R6 + bool + config CPU_MIPS32 bool - default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 + default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
config CPU_MIPS64 bool - default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 + default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
config MIPS_TUNE_4KC bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index aec5a15..c822178 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -18,8 +18,10 @@ PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) # Optimize for MIPS architectures arch-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 arch-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 +arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6 arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 +arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
# Allow extra optimization for specific CPUs/SoCs tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
We always build for a mips32 or higher ISA, so this ".set mips32" directive is redundant. Once MIPSr6 support is added it will become harmful since some instruction encodings change & this directive will cause the older encodings to be incorrectly emitted instead of the appropriate ones for the build.
In preparation for supporting MIPSr6, remove this redundant directive.
Signed-off-by: Paul Burton paul.burton@imgtec.com ---
board/imgtec/malta/lowlevel_init.S | 1 - 1 file changed, 1 deletion(-)
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index ae09c27..534db1d 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -24,7 +24,6 @@
.text .set noreorder - .set mips32
.globl lowlevel_init lowlevel_init:
Both real Malta boards & QEMU's Malta emulation can feature MIPS32r6 CPUs. Allow building U-Boot for such systems by selecting CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta.
Signed-off-by: Paul Burton paul.burton@imgtec.com
---
arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e53fa83..fbf3e4c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -28,6 +28,7 @@ config TARGET_MALTA select SUPPORTS_LITTLE_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_CPU_MIPS32_R6 select SWAP_IO_SPACE select MIPS_L1_CACHE_SHIFT_6
Am 16.05.2016 um 11:52 schrieb Paul Burton:
This series introduces support for building U-Boot for release 6 of the MIPS architecture. This is supported by CPUs such as the M62xx, I6400 & P6600 as well as by emulators such as QEMU.
Paul Burton (5): MIPS: Use unchecked immediate addition/subtraction MIPS: Simplify CONFIG_SYS_CPU values MIPS: Support for targetting MIPSr6 malta: Remove ".set mips32" directive malta: Support MIPS32r6 configurations
arch/mips/Kconfig | 39 ++++++++++++++++++++++++++++++-------- arch/mips/Makefile | 2 ++ arch/mips/cpu/start.S | 22 +++++++++++---------- arch/mips/lib/cache_init.S | 2 +- board/imgtec/malta/lowlevel_init.S | 1 - 5 files changed, 46 insertions(+), 20 deletions(-)
all patches applied to u-boot-mips/next, thanks
participants (2)
-
Daniel Schwierzeck -
Paul Burton