[U-Boot] [PATCH 0/4] ARM: OMAP5/DRA7: Update ABB Configuration for all valid domains
Original intent when Adaptive Body Bias(ABB) was supported in bootloader was two fold: a) ABB is mandatory for all OMAP5/DRA7 support b) expectation was that linux kernel/Operating system will setup ABB and voltage depending on the requirements of the platform.
However, over the last few years, few things changed: i) DRA7 SoCs do not permit for voltage scaling beyond the bootloader's initial settings thanks to a few silicon limitations. This implies that the bootloader has to setup the correct voltage at boot for all domains. Only the MPU voltage domain is excempt from this rule. ii) software stack evolution tied up the voltage rails and ABB setup together for obvious reasons of ABB is fundamentally related to voltage rail configuration.
As a result of these, Linux and operating system just configures just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot.
Given that OMAP5 closely matches DRA7, this series setsup ABB for all domains consistent with the voltage configuration for all domains that have need for ABB.
Series is based on v2016.05-rc2 Boot Log: OMAP5uevm: http://pastebin.ubuntu.com/15971620/ AM572x-X15: http://pastebin.ubuntu.com/15971707/
Nishanth Menon (4): ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2 ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structure ARM: OMAP5: Enable ABB configuration for MM voltage domain ARM: DRA7: Add ABB setup for all domains
arch/arm/cpu/armv7/omap-common/clocks-common.c | 41 +++++++++++++++++++++++--- arch/arm/cpu/armv7/omap5/hw_data.c | 10 +++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 16 ++++++++-- arch/arm/include/asm/arch-omap5/omap.h | 4 +++ arch/arm/include/asm/omap_common.h | 16 +++++++++- board/ti/am57xx/board.c | 4 +++ 6 files changed, 84 insertions(+), 7 deletions(-)
This information is already available under vcores->volts.efuse.reg. There is no reason for duplicating the information since AVS Class 0 definitions are common for OMAP5 and DRA7 and defined with STD_FUSE_OPP_* macros. This allows a central location of defining the ABB and voltage definitions especially since they are reused.
This also makes it simpler to prevent mistakes involved when changing the boot OPP for the device.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 ++-- arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 -- arch/arm/include/asm/omap_common.h | 1 - 3 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index cb41055b91e6..27e6871fde86 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -584,7 +584,7 @@ void scale_vcores(struct vcores_data const *vcores) debug("mpu: %d\n", vcores->mpu.value); do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic); /* Configure MPU ABB LDO after scale */ - abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2, + abb_setup(vcores->mpu.efuse.reg, (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, (*prcm)->prm_abbldo_mpu_setup, (*prcm)->prm_abbldo_mpu_ctrl, @@ -621,7 +621,7 @@ void scale_vcores(struct vcores_data const *vcores) do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
/* Configure MPU ABB LDO after scale */ - abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2, + abb_setup(vcores->mpu.efuse.reg, (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, (*prcm)->prm_abbldo_mpu_setup, (*prcm)->prm_abbldo_mpu_ctrl, diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index cd289ddd2be3..c55c6af9e566 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -297,7 +297,6 @@ struct prcm_regs const omap5_es1_prcm = {
struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, - .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, .control_std_fuse_die_id_0 = 0x4A002200, .control_std_fuse_die_id_1 = 0x4A002208, .control_std_fuse_die_id_2 = 0x4A00220C, @@ -440,7 +439,6 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_srcomp_code_latch = 0x4A002E84, .control_ddr_control_ext_0 = 0x4A002E88, .control_padconf_core_base = 0x4A003400, - .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20, .control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, .control_port_emif2_sdram_config = 0x4AE0C118, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8c85f46db6ef..2daa440432c3 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -363,7 +363,6 @@ struct omap_sys_ctrl_regs { u32 control_core_mac_id_0_hi; u32 control_core_mac_id_1_lo; u32 control_core_mac_id_1_hi; - u32 control_std_fuse_opp_vdd_mpu_2; u32 control_phy_power_usb; u32 control_core_mmr_lock1; u32 control_core_mmr_lock2;
On Thu, Apr 21, 2016 at 02:34:22PM -0500, Nishanth Menon wrote:
This information is already available under vcores->volts.efuse.reg. There is no reason for duplicating the information since AVS Class 0 definitions are common for OMAP5 and DRA7 and defined with STD_FUSE_OPP_* macros. This allows a central location of defining the ABB and voltage definitions especially since they are reused.
This also makes it simpler to prevent mistakes involved when changing the boot OPP for the device.
Signed-off-by: Nishanth Menon nm@ti.com
Applied to u-boot/master, thanks!
ABB TX_DONE mask will vary depending on ABB module. For example, 3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain, DRA7 has it on all domains with the exception of CORE, RTC.
Hence, move the txdone mask definition over to structure describing voltage domain.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 ++-- arch/arm/cpu/armv7/omap5/hw_data.c | 3 +++ arch/arm/include/asm/omap_common.h | 2 ++ board/ti/am57xx/board.c | 1 + 4 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 27e6871fde86..8fe695b992b1 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -589,7 +589,7 @@ void scale_vcores(struct vcores_data const *vcores) (*prcm)->prm_abbldo_mpu_setup, (*prcm)->prm_abbldo_mpu_ctrl, (*prcm)->prm_irqstatus_mpu_2, - OMAP_ABB_MPU_TXDONE_MASK, + vcores->mpu.abb_tx_done_mask, OMAP_ABB_FAST_OPP);
/* The .mm member is not used for the DRA7xx */ @@ -626,7 +626,7 @@ void scale_vcores(struct vcores_data const *vcores) (*prcm)->prm_abbldo_mpu_setup, (*prcm)->prm_abbldo_mpu_ctrl, (*prcm)->prm_irqstatus_mpu_2, - OMAP_ABB_MPU_TXDONE_MASK, + vcores->mpu.abb_tx_done_mask, OMAP_ABB_FAST_OPP);
val = optimize_vcore_voltage(&vcores->mm); diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index b69c0d13715a..a4b31e42e2c3 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -352,6 +352,7 @@ struct vcores_data omap5430_volts_es2 = { .mpu.value = VDD_MPU_ES2, .mpu.addr = SMPS_REG_ADDR_12_MPU, .mpu.pmic = &palmas, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.core.value = VDD_CORE_ES2, .core.addr = SMPS_REG_ADDR_8_CORE, @@ -368,6 +369,7 @@ struct vcores_data dra752_volts = { .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.eve.value = VDD_EVE_DRA752, .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, @@ -400,6 +402,7 @@ struct vcores_data dra722_volts = { .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS65917_REG_ADDR_SMPS1, .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.core.value = VDD_CORE_DRA72x, .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2daa440432c3..d3e841752844 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -540,6 +540,8 @@ struct volts { u32 addr; struct volts_efuse_data efuse; struct pmic_data *pmic; + + u32 abb_tx_done_mask; };
struct vcores_data { diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 17620896130d..2404eb586757 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -221,6 +221,7 @@ struct vcores_data beagle_x15_volts = { .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.eve.value = VDD_EVE_DRA752, .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
On Thu, Apr 21, 2016 at 02:34:23PM -0500, Nishanth Menon wrote:
ABB TX_DONE mask will vary depending on ABB module. For example, 3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain, DRA7 has it on all domains with the exception of CORE, RTC.
Hence, move the txdone mask definition over to structure describing voltage domain.
Signed-off-by: Nishanth Menon nm@ti.com
Applied to u-boot/master, thanks!
Since we setup the voltage and frequency for the MM domain, we *must* setup the ABB configuration needed for the domain as well. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units.
Reported-by: Richard Woodruff r-woodruff2@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 9 +++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 1 + arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 ++++ arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/omap_common.h | 4 ++++ 5 files changed, 19 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 8fe695b992b1..da57b385c922 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -632,6 +632,15 @@ void scale_vcores(struct vcores_data const *vcores) val = optimize_vcore_voltage(&vcores->mm); do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
+ /* Configure MM ABB LDO after scale */ + abb_setup(vcores->mm.efuse.reg, + (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl, + (*prcm)->prm_abbldo_mm_setup, + (*prcm)->prm_abbldo_mm_ctrl, + (*prcm)->prm_irqstatus_mpu, + vcores->mm.abb_tx_done_mask, + OMAP_ABB_FAST_OPP); + val = optimize_vcore_voltage(&vcores->gpu); do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index a4b31e42e2c3..dfb1df6bce30 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -361,6 +361,7 @@ struct vcores_data omap5430_volts_es2 = { .mm.value = VDD_MM_ES2, .mm.addr = SMPS_REG_ADDR_45_IVA, .mm.pmic = &palmas, + .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, };
struct vcores_data dra752_volts = { diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index c55c6af9e566..d126a3223192 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -352,6 +352,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_emif1_sdram_config_ext = 0x4AE0C144, .control_emif2_sdram_config_ext = 0x4AE0C148, .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318, + .control_wkup_ldovbb_mm_voltage_ctrl = 0x4AE0C314, .control_padconf_wkup_base = 0x4AE0C800, .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, @@ -722,6 +723,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0,
/* prm irqstatus regs */ + .prm_irqstatus_mpu = 0x4ae06010, .prm_irqstatus_mpu_2 = 0x4ae06014,
/* l4 wkup regs */ @@ -751,6 +753,8 @@ struct prcm_regs const omap5_es2_prcm = {
.prm_abbldo_mpu_setup = 0x4ae07cdc, .prm_abbldo_mpu_ctrl = 0x4ae07ce0, + .prm_abbldo_mm_setup = 0x4ae07ce4, + .prm_abbldo_mm_ctrl = 0x4ae07ce8,
/* SCRM stuff, used by some boards */ .scrm_auxclk0 = 0x4ae0a310, diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 1eeb8d5f626f..cfec5b063c21 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -215,6 +215,7 @@ struct s32ktimer {
/* ABB tranxdone mask */ #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) +#define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31)
/* ABB efuse masks */ #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index d3e841752844..14c07fab34ab 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -234,6 +234,7 @@ struct prcm_regs { u32 cm_l3init_usb_otg_ss1_clkctrl; u32 cm_l3init_usb_otg_ss2_clkctrl;
+ u32 prm_irqstatus_mpu; u32 prm_irqstatus_mpu_2;
/* cm2.l4per */ @@ -321,6 +322,8 @@ struct prcm_regs { u32 prm_vc_cfg_i2c_clk; u32 prm_abbldo_mpu_setup; u32 prm_abbldo_mpu_ctrl; + u32 prm_abbldo_mm_setup; + u32 prm_abbldo_mm_ctrl;
u32 cm_div_m4_dpll_core; u32 cm_div_m5_dpll_core; @@ -441,6 +444,7 @@ struct omap_sys_ctrl_regs { u32 control_emif1_sdram_config_ext; u32 control_emif2_sdram_config_ext; u32 control_wkup_ldovbb_mpu_voltage_ctrl; + u32 control_wkup_ldovbb_mm_voltage_ctrl; u32 control_smart1nopmio_padconf_0; u32 control_smart1nopmio_padconf_1; u32 control_padconf_mode;
On Thu, Apr 21, 2016 at 02:34:24PM -0500, Nishanth Menon wrote:
Since we setup the voltage and frequency for the MM domain, we *must* setup the ABB configuration needed for the domain as well. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units.
Reported-by: Richard Woodruff r-woodruff2@ti.com Signed-off-by: Nishanth Menon nm@ti.com
Applied to u-boot/master, thanks!
ABB should be initialized for all required domains voltage domain for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot.
Reported-by: Richard Woodruff r-woodruff2@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 24 ++++++++++++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 6 ++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 10 ++++++++++ arch/arm/include/asm/arch-omap5/omap.h | 3 +++ arch/arm/include/asm/omap_common.h | 9 +++++++++ board/ti/am57xx/board.c | 3 +++ 6 files changed, 55 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index da57b385c922..ef2ac982171f 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -596,10 +596,34 @@ void scale_vcores(struct vcores_data const *vcores)
debug("gpu: %d\n", vcores->gpu.value); do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic); + /* Configure GPU ABB LDO after scale */ + abb_setup(vcores->gpu.efuse.reg, + (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl, + (*prcm)->prm_abbldo_gpu_setup, + (*prcm)->prm_abbldo_gpu_ctrl, + (*prcm)->prm_irqstatus_mpu, + vcores->gpu.abb_tx_done_mask, + OMAP_ABB_FAST_OPP); debug("eve: %d\n", vcores->eve.value); do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic); + /* Configure EVE ABB LDO after scale */ + abb_setup(vcores->eve.efuse.reg, + (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl, + (*prcm)->prm_abbldo_eve_setup, + (*prcm)->prm_abbldo_eve_ctrl, + (*prcm)->prm_irqstatus_mpu, + vcores->eve.abb_tx_done_mask, + OMAP_ABB_FAST_OPP); debug("iva: %d\n", vcores->iva.value); do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic); + /* Configure IVA ABB LDO after scale */ + abb_setup(vcores->iva.efuse.reg, + (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl, + (*prcm)->prm_abbldo_iva_setup, + (*prcm)->prm_abbldo_iva_ctrl, + (*prcm)->prm_irqstatus_mpu, + vcores->iva.abb_tx_done_mask, + OMAP_ABB_FAST_OPP); /* Might need udelay(1000) here if debug is enabled to see all prints */ #else u32 val; diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index dfb1df6bce30..88e8920bad31 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -377,12 +377,14 @@ struct vcores_data dra752_volts = { .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value = VDD_GPU_DRA752, .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS6, .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value = VDD_CORE_DRA752, .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, @@ -395,6 +397,7 @@ struct vcores_data dra752_volts = { .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS8, .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, };
struct vcores_data dra722_volts = { @@ -420,18 +423,21 @@ struct vcores_data dra722_volts = { .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS65917_REG_ADDR_SMPS3, .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.eve.value = VDD_EVE_DRA72x, .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS65917_REG_ADDR_SMPS3, .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.iva.value = VDD_IVA_DRA72x, .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS65917_REG_ADDR_SMPS3, .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, };
/* diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index d126a3223192..655e92ba2765 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -446,6 +446,9 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_emif1_sdram_config_ext = 0x4AE0C144, .control_emif2_sdram_config_ext = 0x4AE0C148, .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158, + .control_wkup_ldovbb_iva_voltage_ctrl = 0x4A002470, + .control_wkup_ldovbb_eve_voltage_ctrl = 0x4A00246C, + .control_wkup_ldovbb_gpu_voltage_ctrl = 0x4AE0C154, .control_std_fuse_die_id_0 = 0x4AE0C200, .control_std_fuse_die_id_1 = 0x4AE0C208, .control_std_fuse_die_id_2 = 0x4AE0C20C, @@ -831,6 +834,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_ipu_i2c5_clkctrl = 0x4a005578,
/* prm irqstatus regs */ + .prm_irqstatus_mpu = 0x4ae06010, .prm_irqstatus_mpu_2 = 0x4ae06014,
/* cm2.ckgen */ @@ -999,6 +1003,12 @@ struct prcm_regs const dra7xx_prcm = {
.prm_abbldo_mpu_setup = 0x4AE07DDC, .prm_abbldo_mpu_ctrl = 0x4AE07DE0, + .prm_abbldo_iva_setup = 0x4AE07E34, + .prm_abbldo_iva_ctrl = 0x4AE07E24, + .prm_abbldo_eve_setup = 0x4AE07E30, + .prm_abbldo_eve_ctrl = 0x4AE07E20, + .prm_abbldo_gpu_setup = 0x4AE07DE4, + .prm_abbldo_gpu_ctrl = 0x4AE07DE8,
/*l3main1 edma*/ .cm_l3main1_tptc1_clkctrl = 0x4a008778, diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index cfec5b063c21..2fd5cda6238f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -216,6 +216,9 @@ struct s32ktimer { /* ABB tranxdone mask */ #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) #define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31) +#define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30) +#define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29) +#define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28)
/* ABB efuse masks */ #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 14c07fab34ab..8fb05e18b93f 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -324,6 +324,12 @@ struct prcm_regs { u32 prm_abbldo_mpu_ctrl; u32 prm_abbldo_mm_setup; u32 prm_abbldo_mm_ctrl; + u32 prm_abbldo_iva_setup; + u32 prm_abbldo_iva_ctrl; + u32 prm_abbldo_eve_setup; + u32 prm_abbldo_eve_ctrl; + u32 prm_abbldo_gpu_setup; + u32 prm_abbldo_gpu_ctrl;
u32 cm_div_m4_dpll_core; u32 cm_div_m5_dpll_core; @@ -445,6 +451,9 @@ struct omap_sys_ctrl_regs { u32 control_emif2_sdram_config_ext; u32 control_wkup_ldovbb_mpu_voltage_ctrl; u32 control_wkup_ldovbb_mm_voltage_ctrl; + u32 control_wkup_ldovbb_iva_voltage_ctrl; + u32 control_wkup_ldovbb_eve_voltage_ctrl; + u32 control_wkup_ldovbb_gpu_voltage_ctrl; u32 control_smart1nopmio_padconf_0; u32 control_smart1nopmio_padconf_1; u32 control_padconf_mode; diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 2404eb586757..86b8f6e8951a 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -228,12 +228,14 @@ struct vcores_data beagle_x15_volts = { .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value = VDD_GPU_DRA752, .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS45, .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value = VDD_CORE_DRA752, .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, @@ -246,6 +248,7 @@ struct vcores_data beagle_x15_volts = { .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS45, .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, };
#ifdef CONFIG_SPL_BUILD
On Thu, Apr 21, 2016 at 02:34:25PM -0500, Nishanth Menon wrote:
ABB should be initialized for all required domains voltage domain for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot.
Reported-by: Richard Woodruff r-woodruff2@ti.com Signed-off-by: Nishanth Menon nm@ti.com
Applied to u-boot/master, thanks!
participants (2)
-
Nishanth Menon -
Tom Rini