[U-Boot] [PATCH re-send v6 00/17] device model bring-up of ti-qspi on dra72, dra74 and am437x-sk evm

Mugunthan V N

23 Dec 2015 23 Dec '15

4:09 p.m.

Resending the patches as I have missed 01/17 patch while sending v6 series

This patch series enables ti_qspi to adopt driver model. This has been tested on dra72, dra74 and am437x-sk evms (logs [1]). Also pushed a branch for testing [2]

This patch series is based on u-boot-spi/next and a fix for Macronix flash Quad Enable as per the comments in thread [3].

[1]: http://pastebin.ubuntu.com/14164638/ [2]: git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-qspi-v6

Changes from v5->v6: * Removed adding flash compatibles to flash driver and added "spi-flash" compatible to dts as done by other flash devices.

Changes from v4->v5: * Adopt to latest spi framework changes by Jagan [3] and [4]

[3]: http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/245039 [4]: https://www.mail-archive.com/u-boot@lists.denx.de/msg196464.html

Changes from v3->v4: * used op_mode_{t/r}x to hold flash tx/rx modes.

Changes from v2->v3: * removed usage of spi_slave structure in driver model and introduced required variables in qspi priv itself. * Used fdt_addr_cells() and fdt_size_cells() instead of hard-coding size of each address-size pair. * Changed qspi dts entries to be same as in kernel qspi dts patch for avoiding future conflicts. * Fixed some typos and added more info in commits. * Added error check on chip select passed from framework. * Removed un-used define QSPI_RD_DUAL.

Changes from Initial version: * Split "prepare driver for DM conversion" for easier review * added memory map mode to the driver * Fixed the cosmetic reviews from Simon * Modified the dev_get_addr_index to adopt OF_TRANSULATE as well and also removed code duplicate. * Added compatibles for spi flashed found in DRA7xx and AM437x SK

Mugunthan V N (17): drivers: spi: ti_qspi: do not hard code chip select for memory map configuration drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model conversion drivers: spi: ti_qspi: prepare driver for DM conversion dm: core: Add a new api to get indexed device address spi: Add support for dual and quad mode dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl dts: dra7: add spi alias for qspi drivers: spi: ti_qspi: convert driver to adopt device driver model arm: dts: dra7: add qspi register maps for memory map and control module arm: dts: am437x-gp-evm: add spi-flash comaptible for flash arm: dts: dra7-evm: add spi-flash comaptible for flash arm: dts: dra72-evm: add spi-flash comaptible for flash defconfig: dra72_evm: enable spi driver model defconfig: dra74_evm: enable spi driver model am43xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl arm: dts: am4372: add qspi register maps for memory map defconfig: am437x_sk_evm: enable spi driver model

-- 2.7.0.rc1.5.gf3adf45

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Mugunthan V N

23 Dec 23 Dec

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 01/17] drivers: spi: ti_qspi: do not hard code chip select for memory map configuration

To enable memory map in dra7xx, specific chip select must be written to control module register. But this hard coded to chip select 1, fixing it by writing the specific chip select value to control module register.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com Reviewed-by: Jagan Teki jteki@openedev.com --- drivers/spi/ti_qspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 26616eb..d5a06b8 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -41,7 +41,7 @@ #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) #define QSPI_XFER_DONE QSPI_WC #define MM_SWITCH 0x01 -#define MEM_CS 0x100 +#define MEM_CS(cs) ((cs + 1) << 8) #define MEM_CS_UNSELECT 0xfffff0ff #define MMAP_START_ADDR_DRA 0x5c000000 #define MMAP_START_ADDR_AM43x 0x30000000 @@ -267,7 +267,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, writel(MM_SWITCH, &qslave->base->memswitch); #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) val = readl(CORE_CTRL_IO); - val |= MEM_CS; + val |= MEM_CS(slave->cs); writel(val, CORE_CTRL_IO); #endif return 0;

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 02/17] drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model conversion

Changing the ti_qspi_priv structure and its instance names from to priv for driver mode conversion.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com Reviewed-by: Jagan Teki jteki@openedev.com --- drivers/spi/ti_qspi.c | 120 +++++++++++++++++++++++++------------------------- 1 file changed, 60 insertions(+), 60 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index d5a06b8..a9f996d 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -85,8 +85,8 @@ struct ti_qspi_regs { u32 data3; };

-/* ti qspi slave */ -struct ti_qspi_slave { +/* ti qspi priv */ +struct ti_qspi_priv { struct spi_slave slave; struct ti_qspi_regs *base; unsigned int mode; @@ -94,14 +94,14 @@ struct ti_qspi_slave { u32 dc; };

-static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave) +static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) { - return container_of(slave, struct ti_qspi_slave, slave); + return container_of(slave, struct ti_qspi_priv, slave); }

-static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) +static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) { - struct spi_slave *slave = &qslave->slave; + struct spi_slave *slave = &priv->slave; u32 memval = 0;

#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) @@ -123,12 +123,12 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) QSPI_NUM_DUMMY_BITS; #endif

- writel(memval, &qslave->base->setup0); + writel(memval, &priv->base->setup0); }

static void ti_spi_set_speed(struct spi_slave *slave, uint hz) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); uint clk_div;

debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); @@ -139,8 +139,8 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz) clk_div = (QSPI_FCLK / hz) - 1;

/* disable SCLK */ - writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN, - &qslave->base->clk_ctrl); + writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, + &priv->base->clk_ctrl);

/* assign clk_div values */ if (clk_div < 0) @@ -149,7 +149,7 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz) clk_div = QSPI_CLK_DIV_MAX;

/* enable SCLK */ - writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl); + writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); }

int spi_cs_is_valid(unsigned int bus, unsigned int cs) @@ -165,11 +165,11 @@ void spi_cs_activate(struct spi_slave *slave)

void spi_cs_deactivate(struct spi_slave *slave) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);

- writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd); + writel(priv->cmd | QSPI_INVAL, &priv->base->cmd); /* dummy readl to ensure bus sync */ readl(&qslave->base->cmd); } @@ -182,73 +182,73 @@ void spi_init(void) struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { - struct ti_qspi_slave *qslave; + struct ti_qspi_priv *priv;

#ifdef CONFIG_AM43XX gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); #endif

- qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs); - if (!qslave) { - printf("SPI_error: Fail to allocate ti_qspi_slave\n"); + priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs); + if (!priv) { + printf("SPI_error: Fail to allocate ti_qspi_priv\n"); return NULL; }

- qslave->base = (struct ti_qspi_regs *)QSPI_BASE; - qslave->mode = mode; + priv->base = (struct ti_qspi_regs *)QSPI_BASE; + priv->mode = mode;

- ti_spi_set_speed(&qslave->slave, max_hz); + ti_spi_set_speed(&priv->slave, max_hz);

#ifdef CONFIG_TI_SPI_MMAP - ti_spi_setup_spi_register(qslave); + ti_spi_setup_spi_register(priv); #endif

- return &qslave->slave; + return &priv->slave; }

void spi_free_slave(struct spi_slave *slave) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); - free(qslave); + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + free(priv); }

int spi_claim_bus(struct spi_slave *slave) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);

- qslave->dc = 0; - if (qslave->mode & SPI_CPHA) - qslave->dc |= QSPI_CKPHA(slave->cs); - if (qslave->mode & SPI_CPOL) - qslave->dc |= QSPI_CKPOL(slave->cs); - if (qslave->mode & SPI_CS_HIGH) - qslave->dc |= QSPI_CSPOL(slave->cs); + priv->dc = 0; + if (priv->mode & SPI_CPHA) + priv->dc |= QSPI_CKPHA(slave->cs); + if (priv->mode & SPI_CPOL) + priv->dc |= QSPI_CKPOL(slave->cs); + if (priv->mode & SPI_CS_HIGH) + priv->dc |= QSPI_CSPOL(slave->cs);

- writel(qslave->dc, &qslave->base->dc); - writel(0, &qslave->base->cmd); - writel(0, &qslave->base->data); + writel(priv->dc, &priv->base->dc); + writel(0, &priv->base->cmd); + writel(0, &priv->base->data);

return 0; }

void spi_release_bus(struct spi_slave *slave) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);

debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);

- writel(0, &qslave->base->dc); - writel(0, &qslave->base->cmd); - writel(0, &qslave->base->data); + writel(0, &priv->base->dc); + writel(0, &priv->base->cmd); + writel(0, &priv->base->data); }

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave); + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); uint words = bitlen >> 3; /* fixed 8-bit word length */ const uchar *txp = dout; uchar *rxp = din; @@ -264,7 +264,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,

/* Setup mmap flags */ if (flags & SPI_XFER_MMAP) { - writel(MM_SWITCH, &qslave->base->memswitch); + writel(MM_SWITCH, &priv->base->memswitch); #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) val = readl(CORE_CTRL_IO); val |= MEM_CS(slave->cs); @@ -272,7 +272,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, #endif return 0; } else if (flags & SPI_XFER_MMAP_END) { - writel(~MM_SWITCH, &qslave->base->memswitch); + writel(~MM_SWITCH, &priv->base->memswitch); #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) val = readl(CORE_CTRL_IO); val &= MEM_CS_UNSELECT; @@ -290,12 +290,12 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, }

/* Setup command reg */ - qslave->cmd = 0; - qslave->cmd |= QSPI_WLEN(8); - qslave->cmd |= QSPI_EN_CS(slave->cs); - if (qslave->mode & SPI_3WIRE) - qslave->cmd |= QSPI_3_PIN; - qslave->cmd |= 0xfff; + priv->cmd = 0; + priv->cmd |= QSPI_WLEN(8); + priv->cmd |= QSPI_EN_CS(slave->cs); + if (priv->mode & SPI_3WIRE) + priv->cmd |= QSPI_3_PIN; + priv->cmd |= 0xfff;

/* FIXME: This delay is required for successfull * completion of read/write/erase. Once its root @@ -307,39 +307,39 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, while (words--) { if (txp) { debug("tx cmd %08x dc %08x data %02x\n", - qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp); - writel(*txp++, &qslave->base->data); - writel(qslave->cmd | QSPI_WR_SNGL, - &qslave->base->cmd); - status = readl(&qslave->base->status); + priv->cmd | QSPI_WR_SNGL, priv->dc, *txp); + writel(*txp++, &priv->base->data); + writel(priv->cmd | QSPI_WR_SNGL, + &priv->base->cmd); + status = readl(&priv->base->status); timeout = QSPI_TIMEOUT; while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { if (--timeout < 0) { printf("spi_xfer: TX timeout!\n"); return -1; } - status = readl(&qslave->base->status); + status = readl(&priv->base->status); } debug("tx done, status %08x\n", status); } if (rxp) { - qslave->cmd |= QSPI_RD_SNGL; + priv->cmd |= QSPI_RD_SNGL; debug("rx cmd %08x dc %08x\n", - qslave->cmd, qslave->dc); + priv->cmd, priv->dc); #ifdef CONFIG_DRA7XX udelay(500); #endif - writel(qslave->cmd, &qslave->base->cmd); - status = readl(&qslave->base->status); + writel(priv->cmd, &priv->base->cmd); + status = readl(&priv->base->status); timeout = QSPI_TIMEOUT; while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { if (--timeout < 0) { printf("spi_xfer: RX timeout!\n"); return -1; } - status = readl(&qslave->base->status); + status = readl(&priv->base->status); } - *rxp++ = readl(&qslave->base->data); + *rxp++ = readl(&priv->base->data); debug("rx done, status %08x, read %02x\n", status, *(rxp-1)); }

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 03/17] drivers: spi: ti_qspi: prepare driver for DM conversion

Prepare driver for DM conversion.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- drivers/spi/ti_qspi.c | 279 +++++++++++++++++++++++++++----------------------- 1 file changed, 153 insertions(+), 126 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index a9f996d..36d3193 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -89,46 +89,14 @@ struct ti_qspi_regs { struct ti_qspi_priv { struct spi_slave slave; struct ti_qspi_regs *base; + void *ctrl_mod_mmap; unsigned int mode; u32 cmd; u32 dc; };

-static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) -{ - return container_of(slave, struct ti_qspi_priv, slave); -} - -static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) -{ - struct spi_slave *slave = &priv->slave; - u32 memval = 0; - -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - slave->memory_map = (void *)MMAP_START_ADDR_DRA; -#else - slave->memory_map = (void *)MMAP_START_ADDR_AM43x; -#endif - -#ifdef CONFIG_QSPI_QUAD_SUPPORT - memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | - QSPI_SETUP0_NUM_D_BYTES_8_BITS | - QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | - QSPI_NUM_DUMMY_BITS); - slave->mode_rx = SPI_RX_QUAD; -#else - memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | - QSPI_SETUP0_NUM_D_BYTES_NO_BITS | - QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | - QSPI_NUM_DUMMY_BITS; -#endif - - writel(memval, &priv->base->setup0); -} - -static void ti_spi_set_speed(struct spi_slave *slave, uint hz) +static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) { - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); uint clk_div;

debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); @@ -152,132 +120,77 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz) writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); }

-int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return 1; -} - -void spi_cs_activate(struct spi_slave *slave) +static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) { - /* CS handled in xfer */ - return; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - - debug("spi_cs_deactivate: 0x%08x\n", (u32)slave); - writel(priv->cmd | QSPI_INVAL, &priv->base->cmd); /* dummy readl to ensure bus sync */ - readl(&qslave->base->cmd); + readl(&priv->base->cmd); }

-void spi_init(void) +static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) { - /* nothing to do */ -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct ti_qspi_priv *priv; - -#ifdef CONFIG_AM43XX - gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); - gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); -#endif - - priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs); - if (!priv) { - printf("SPI_error: Fail to allocate ti_qspi_priv\n"); - return NULL; - } - - priv->base = (struct ti_qspi_regs *)QSPI_BASE; - priv->mode = mode; - - ti_spi_set_speed(&priv->slave, max_hz); - -#ifdef CONFIG_TI_SPI_MMAP - ti_spi_setup_spi_register(priv); -#endif - - return &priv->slave; -} + priv->dc = 0; + if (mode & SPI_CPHA) + priv->dc |= QSPI_CKPHA(0); + if (mode & SPI_CPOL) + priv->dc |= QSPI_CKPOL(0); + if (mode & SPI_CS_HIGH) + priv->dc |= QSPI_CSPOL(0);

-void spi_free_slave(struct spi_slave *slave) -{ - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - free(priv); + return 0; }

-int spi_claim_bus(struct spi_slave *slave) +static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs) { - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - - debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs); - - priv->dc = 0; - if (priv->mode & SPI_CPHA) - priv->dc |= QSPI_CKPHA(slave->cs); - if (priv->mode & SPI_CPOL) - priv->dc |= QSPI_CKPOL(slave->cs); - if (priv->mode & SPI_CS_HIGH) - priv->dc |= QSPI_CSPOL(slave->cs); - writel(priv->dc, &priv->base->dc); writel(0, &priv->base->cmd); writel(0, &priv->base->data);

+ priv->dc <<= cs * 8; + writel(priv->dc, &priv->base->dc); + return 0; }

-void spi_release_bus(struct spi_slave *slave) +static void __ti_qspi_release_bus(struct ti_qspi_priv *priv) { - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); - - debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs); - writel(0, &priv->base->dc); writel(0, &priv->base->cmd); writel(0, &priv->base->data); }

-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable) +{ + u32 val; + + val = readl(ctrl_mod_mmap); + if (enable) + val |= MEM_CS(cs); + else + val &= MEM_CS_UNSELECT; + writel(val, ctrl_mod_mmap); +} + +static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, + const void *dout, void *din, unsigned long flags, + u32 cs) { - struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); uint words = bitlen >> 3; /* fixed 8-bit word length */ const uchar *txp = dout; uchar *rxp = din; uint status; int timeout;

-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - int val; -#endif - - debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", - slave->bus, slave->cs, bitlen, words, flags); - /* Setup mmap flags */ if (flags & SPI_XFER_MMAP) { writel(MM_SWITCH, &priv->base->memswitch); -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - val = readl(CORE_CTRL_IO); - val |= MEM_CS(slave->cs); - writel(val, CORE_CTRL_IO); -#endif + if (priv->ctrl_mod_mmap) + ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true); return 0; } else if (flags & SPI_XFER_MMAP_END) { writel(~MM_SWITCH, &priv->base->memswitch); -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - val = readl(CORE_CTRL_IO); - val &= MEM_CS_UNSELECT; - writel(val, CORE_CTRL_IO); -#endif + if (priv->ctrl_mod_mmap) + ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false); return 0; }

@@ -292,7 +205,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* Setup command reg */ priv->cmd = 0; priv->cmd |= QSPI_WLEN(8); - priv->cmd |= QSPI_EN_CS(slave->cs); + priv->cmd |= QSPI_EN_CS(cs); if (priv->mode & SPI_3WIRE) priv->cmd |= QSPI_3_PIN; priv->cmd |= 0xfff; @@ -347,7 +260,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,

/* Terminate frame */ if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + ti_qspi_cs_deactivate(priv);

return 0; } @@ -374,3 +287,117 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len) *((unsigned int *)offset) += len; } #endif + +static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) +{ + return container_of(slave, struct ti_qspi_priv, slave); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* CS handled in xfer */ + return; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + ti_qspi_cs_deactivate(priv); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) +{ + u32 memval = 0; + +#ifdef CONFIG_QSPI_QUAD_SUPPORT + struct spi_slave *slave = &priv->slave; + memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_8_BITS | + QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS); + slave->mode_rx = SPI_RX_QUAD; +#else + memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_NO_BITS | + QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS; +#endif + + writel(memval, &priv->base->setup0); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct ti_qspi_priv *priv; + +#ifdef CONFIG_AM43XX + gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); + gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); +#endif + + priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs); + if (!priv) { + printf("SPI_error: Fail to allocate ti_qspi_priv\n"); + return NULL; + } + + priv->base = (struct ti_qspi_regs *)QSPI_BASE; + priv->mode = mode; +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO; + priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA; +#else + priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x; +#endif + + ti_spi_set_speed(priv, max_hz); + +#ifdef CONFIG_TI_SPI_MMAP + ti_spi_setup_spi_register(priv); +#endif + + return &priv->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + free(priv); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + + debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); + __ti_qspi_set_mode(priv, priv->mode); + return __ti_qspi_claim_bus(priv, priv->slave.cs); +} +void spi_release_bus(struct spi_slave *slave) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + + debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs); + __ti_qspi_release_bus(priv); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct ti_qspi_priv *priv = to_ti_qspi_priv(slave); + + debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n", + priv->slave.bus, priv->slave.cs, bitlen, flags); + return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs); +}

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 04/17] dm: core: Add a new api to get indexed device address

Add new api to get device address based on index.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- drivers/core/device.c | 31 +++++++++++++++++++++++++++---- include/dm/device.h | 11 +++++++++++ 2 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/drivers/core/device.c b/drivers/core/device.c index 758f390..d3b2570 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -581,17 +581,35 @@ const char *dev_get_uclass_name(struct udevice *dev) return dev->uclass->uc_drv->name; }

-fdt_addr_t dev_get_addr(struct udevice *dev) +fdt_addr_t dev_get_addr_index(struct udevice *dev, int index) { #if CONFIG_IS_ENABLED(OF_CONTROL) fdt_addr_t addr;

if (CONFIG_IS_ENABLED(OF_TRANSLATE)) { const fdt32_t *reg; + int len = 0; + int na, ns;

- reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL); - if (!reg) + na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset); + if (na < 1) { + debug("bad #address-cells\n"); return FDT_ADDR_T_NONE; + } + + ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset); + if (ns < 0) { + debug("bad #size-cells\n"); + return FDT_ADDR_T_NONE; + } + + reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len); + if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) { + debug("Req index out of range\n"); + return FDT_ADDR_T_NONE; + } + + reg += index * (na + ns);

/* * Use the full-fledged translate function for complex @@ -608,7 +626,7 @@ fdt_addr_t dev_get_addr(struct udevice *dev) addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, dev->parent->of_offset, dev->of_offset, "reg", - 0, NULL); + index, NULL); if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) { if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS) addr = simple_bus_translate(dev->parent, addr); @@ -620,6 +638,11 @@ fdt_addr_t dev_get_addr(struct udevice *dev) #endif }

+fdt_addr_t dev_get_addr(struct udevice *dev) +{ + return dev_get_addr_index(dev, 0); +} + bool device_has_children(struct udevice *dev) { return !list_empty(&dev->child_head); diff --git a/include/dm/device.h b/include/dm/device.h index 7fb9935..d608137 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -454,6 +454,17 @@ int device_find_next_child(struct udevice **devp); fdt_addr_t dev_get_addr(struct udevice *dev);

/** + * dev_get_addr_index() - Get the indexed reg property of a device + * + * @dev: Pointer to a device + * @index: the 'reg' property can hold a list of <addr, size> pairs + * and @index is used to select which one is required + * + * @return addr + */ +fdt_addr_t dev_get_addr_index(struct udevice *dev, int index); + +/** * device_has_children() - check if a device has any children * * @dev: Device to check

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 05/17] spi: Add support for dual and quad mode

spi bus can support dual and quad wire data transfers for tx and rx. So defining dual and quad modes for both tx and rx. Also add support to parse bus width used for spi tx and rx transfers.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- drivers/spi/spi-uclass.c | 31 +++++++++++++++++++++++++++++++ include/spi.h | 4 ++++ 2 files changed, 35 insertions(+)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index e0f6b25..e5df2c2 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -157,6 +157,7 @@ static int spi_child_pre_probe(struct udevice *dev)

slave->max_hz = plat->max_hz; slave->mode = plat->mode; + slave->mode_rx = plat->mode_rx;

return 0; } @@ -369,6 +370,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, struct dm_spi_slave_platdata *plat) { int mode = 0; + int value;

plat->cs = fdtdec_get_int(blob, node, "reg", -1); plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0); @@ -382,6 +384,35 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, mode |= SPI_3WIRE; if (fdtdec_get_bool(blob, node, "spi-half-duplex")) mode |= SPI_PREAMBLE; + + /* Device DUAL/QUAD mode */ + value = fdtdec_get_uint(blob, node, "spi-tx-bus-width", 1); + switch (value) { + case 1: + break; + case 4: + mode |= SPI_TX_QUAD; + break; + default: + error("spi-tx-bus-width %d not supported\n", value); + break; + } + + value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + plat->mode_rx |= SPI_RX_DUAL; + break; + case 4: + plat->mode_rx |= SPI_RX_QUAD; + break; + default: + error("spi-rx-bus-width %d not supported\n", value); + break; + } + plat->mode = mode;

return 0; diff --git a/include/spi.h b/include/spi.h index 803fb40..94d8a32 100644 --- a/include/spi.h +++ b/include/spi.h @@ -38,11 +38,15 @@ struct dm_spi_bus { * @cs: Chip select number (0..n-1) * @max_hz: Maximum bus speed that this slave can tolerate * @mode: SPI mode to use for this device (see SPI mode flags) + * @mode_rx: SPI RX operation mode. + * @mode_tx: SPI TX operation mode. */ struct dm_spi_slave_platdata { unsigned int cs; uint max_hz; uint mode; + u8 mode_rx; + u8 mode_tx; };

#endif /* CONFIG_DM_SPI */

-- 2.7.0.rc1.5.gf3adf45

Jagan Teki

28 Dec 28 Dec

3:49 p.m.

New subject: [U-Boot] [PATCH re-send v6 05/17] spi: Add support for dual and quad mode

On 23 December 2015 at 20:39, Mugunthan V N mugunthanvnm@ti.com wrote:

...

spi bus can support dual and quad wire data transfers for tx and rx. So defining dual and quad modes for both tx and rx. Also add support to parse bus width used for spi tx and rx transfers.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com

drivers/spi/spi-uclass.c | 31 +++++++++++++++++++++++++++++++ include/spi.h | 4 ++++ 2 files changed, 35 insertions(+)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index e0f6b25..e5df2c2 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -157,6 +157,7 @@ static int spi_child_pre_probe(struct udevice *dev)
    slave->max_hz = plat->max_hz;
    slave->mode = plat->mode;
  slave->mode_rx = plat->mode_rx;

  return 0;
} @@ -369,6 +370,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, struct dm_spi_slave_platdata *plat) { int mode = 0;
  int value;

  plat->cs = fdtdec_get_int(blob, node, "reg", -1);
  plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
@@ -382,6 +384,35 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, mode |= SPI_3WIRE; if (fdtdec_get_bool(blob, node, "spi-half-duplex")) mode |= SPI_PREAMBLE;
  /* Device DUAL/QUAD mode */
  value = fdtdec_get_uint(blob, node, "spi-tx-bus-width", 1);
  switch (value) {
  case 1:
          break;

I think it missed case 2 for dual

...

  case 4:
          mode |= SPI_TX_QUAD;
          break;
  default:
          error("spi-tx-bus-width %d not supported\n", value);
          break;
  }
  value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
  switch (value) {
  case 1:
          break;
  case 2:
          plat->mode_rx |= SPI_RX_DUAL;
          break;
  case 4:
          plat->mode_rx |= SPI_RX_QUAD;
          break;
  default:
          error("spi-rx-bus-width %d not supported\n", value);
          break;
  }
  plat->mode = mode;

  return 0;
diff --git a/include/spi.h b/include/spi.h index 803fb40..94d8a32 100644 --- a/include/spi.h +++ b/include/spi.h @@ -38,11 +38,15 @@ struct dm_spi_bus {

@cs: Chip select number (0..n-1)

@max_hz: Maximum bus speed that this slave can tolerate

@mode: SPI mode to use for this device (see SPI mode flags)

@mode_rx: SPI RX operation mode.

@mode_tx: SPI TX operation mode.

*/

struct dm_spi_slave_platdata { unsigned int cs; uint max_hz; uint mode;
  u8 mode_rx;
  u8 mode_tx;

mode_tx not required and you defined but not used.

...

};

#endif /* CONFIG_DM_SPI */

2.7.0.rc1.5.gf3adf45

thanks!

-- Jagan.

Mugunthan V N

30 Dec 30 Dec

6:55 a.m.

New subject: [U-Boot] [PATCH re-send v6 05/17] spi: Add support for dual and quad mode

On Monday 28 December 2015 08:19 PM, Jagan Teki wrote:

...

On 23 December 2015 at 20:39, Mugunthan V N mugunthanvnm@ti.com wrote:

...
spi bus can support dual and quad wire data transfers for tx and rx. So defining dual and quad modes for both tx and rx. Also add support to parse bus width used for spi tx and rx transfers.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com

drivers/spi/spi-uclass.c | 31 +++++++++++++++++++++++++++++++ include/spi.h | 4 ++++ 2 files changed, 35 insertions(+)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index e0f6b25..e5df2c2 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -157,6 +157,7 @@ static int spi_child_pre_probe(struct udevice *dev)
    slave->max_hz = plat->max_hz;
    slave->mode = plat->mode;
  slave->mode_rx = plat->mode_rx;

  return 0;
} @@ -369,6 +370,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, struct dm_spi_slave_platdata *plat) { int mode = 0;
  int value;

  plat->cs = fdtdec_get_int(blob, node, "reg", -1);
  plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
@@ -382,6 +384,35 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, mode |= SPI_3WIRE; if (fdtdec_get_bool(blob, node, "spi-half-duplex")) mode |= SPI_PREAMBLE;
  /* Device DUAL/QUAD mode */
  value = fdtdec_get_uint(blob, node, "spi-tx-bus-width", 1);
  switch (value) {
  case 1:
          break;
I think it missed case 2 for dual

I tried searching spi devices using dual mode for tx in kernel dt files, but I found only single and quad mode, so I dropped dual mode parsing.

It can be added when there is a controller which supports max dual mode.

...

...
  case 4:
          mode |= SPI_TX_QUAD;
          break;
  default:
          error("spi-tx-bus-width %d not supported\n", value);
          break;
  }
  value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
  switch (value) {
  case 1:
          break;
  case 2:
          plat->mode_rx |= SPI_RX_DUAL;
          break;
  case 4:
          plat->mode_rx |= SPI_RX_QUAD;
          break;
  default:
          error("spi-rx-bus-width %d not supported\n", value);
          break;
  }
  plat->mode = mode;

  return 0;
diff --git a/include/spi.h b/include/spi.h index 803fb40..94d8a32 100644 --- a/include/spi.h +++ b/include/spi.h @@ -38,11 +38,15 @@ struct dm_spi_bus {

@cs: Chip select number (0..n-1)

@max_hz: Maximum bus speed that this slave can tolerate

@mode: SPI mode to use for this device (see SPI mode flags)

@mode_rx: SPI RX operation mode.

@mode_tx: SPI TX operation mode.

*/

struct dm_spi_slave_platdata { unsigned int cs; uint max_hz; uint mode;
  u8 mode_rx;
  u8 mode_tx;
mode_tx not required and you defined but not used.

Oops, missed removing this unused. Do you want me to post this patch only as a followup patch or the entire series as v7?

Regards Mugunthan V N

...

...
};

#endif /* CONFIG_DM_SPI */

2.7.0.rc1.5.gf3adf45

thanks!

Mugunthan V N

23 Dec 23 Dec

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 06/17] dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl

Since OMAP's spl doesn't support DM currently, do not define DM_SPI and DM_SPI_FLASH for spl build.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- include/configs/dra7xx_evm.h | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 81070b1..9d62421 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -142,6 +142,11 @@ #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 #define CONFIG_QSPI_QUAD_SUPPORT

+#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#endif + /* * Default to using SPI for environment, etc. * 0x000000 - 0x010000 : QSPI.SPL (64KiB)

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 07/17] dts: dra7: add spi alias for qspi

add spi alias for qspi so that spi probes the device and driver successfully.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org --- arch/arm/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index feb3708..c69c651 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -41,6 +41,7 @@ ethernet1 = &cpsw_emac1; d_can0 = &dcan1; d_can1 = &dcan2; + spi0 = &qspi; };

timer {

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 08/17] drivers: spi: ti_qspi: convert driver to adopt device driver model

adopt ti_qspi driver to device driver model

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com --- drivers/spi/ti_qspi.c | 187 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 187 insertions(+)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 36d3193..78d8b13 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -11,11 +11,14 @@ #include <asm/arch/omap.h> #include <malloc.h> #include <spi.h> +#include <dm.h> #include <asm/gpio.h> #include <asm/omap_gpio.h> #include <asm/omap_common.h> #include <asm/ti-common/ti-edma3.h>

+DECLARE_GLOBAL_DATA_PTR; + /* ti qpsi register bit masks */ #define QSPI_TIMEOUT 2000000 #define QSPI_FCLK 192000000 @@ -48,12 +51,14 @@ #define CORE_CTRL_IO 0x4a002558

#define QSPI_CMD_READ (0x3 << 0) +#define QSPI_CMD_READ_DUAL (0x6b << 0) #define QSPI_CMD_READ_QUAD (0x6b << 0) #define QSPI_CMD_READ_FAST (0x0b << 0) #define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) #define QSPI_SETUP0_READ_NORMAL (0x0 << 12) +#define QSPI_SETUP0_READ_DUAL (0x1 << 12) #define QSPI_SETUP0_READ_QUAD (0x3 << 12) #define QSPI_CMD_WRITE (0x2 << 16) #define QSPI_NUM_DUMMY_BITS (0x0 << 24) @@ -87,7 +92,13 @@ struct ti_qspi_regs {

/* ti qspi priv */ struct ti_qspi_priv { +#ifndef CONFIG_DM_SPI struct spi_slave slave; +#else + void *memory_map; + uint max_hz; + u32 num_cs; +#endif struct ti_qspi_regs *base; void *ctrl_mod_mmap; unsigned int mode; @@ -288,6 +299,8 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len) } #endif

+#ifndef CONFIG_DM_SPI + static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) { return container_of(slave, struct ti_qspi_priv, slave); @@ -401,3 +414,177 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, priv->slave.bus, priv->slave.cs, bitlen, flags); return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs); } + +#else /* CONFIG_DM_SPI */ + +static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, + struct spi_slave *slave, + bool enable) +{ + u32 memval; + u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL); + + if (!enable) { + writel(0, &priv->base->setup0); + return; + } + + memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; + + switch (mode) { + case SPI_RX_QUAD: + memval |= QSPI_CMD_READ_QUAD; + memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; + memval |= QSPI_SETUP0_READ_QUAD; + slave->mode_rx = SPI_RX_QUAD; + break; + case SPI_RX_DUAL: + memval |= QSPI_CMD_READ_DUAL; + memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; + memval |= QSPI_SETUP0_READ_DUAL; + break; + default: + memval |= QSPI_CMD_READ; + memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS; + memval |= QSPI_SETUP0_READ_NORMAL; + break; + } + + writel(memval, &priv->base->setup0); +} + + +static int ti_qspi_set_speed(struct udevice *bus, uint max_hz) +{ + struct ti_qspi_priv *priv = dev_get_priv(bus); + + ti_spi_set_speed(priv, max_hz); + + return 0; +} + +static int ti_qspi_set_mode(struct udevice *bus, uint mode) +{ + struct ti_qspi_priv *priv = dev_get_priv(bus); + return __ti_qspi_set_mode(priv, mode); +} + +static int ti_qspi_claim_bus(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct spi_slave *slave = dev_get_parent_priv(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + if (slave_plat->cs > priv->num_cs) { + debug("invalid qspi chip select\n"); + return -EINVAL; + } + + __ti_qspi_setup_memorymap(priv, slave, true); + + return __ti_qspi_claim_bus(priv, slave_plat->cs); +} + +static int ti_qspi_release_bus(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + __ti_qspi_setup_memorymap(priv, slave, false); + __ti_qspi_release_bus(priv); + + return 0; +} + +static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + struct ti_qspi_priv *priv; + struct udevice *bus; + + bus = dev->parent; + priv = dev_get_priv(bus); + + if (slave->cs > priv->num_cs) { + debug("invalid qspi chip select\n"); + return -EINVAL; + } + + return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs); +} + +static int ti_qspi_probe(struct udevice *bus) +{ + /* Nothing to do in probe */ + return 0; +} + +static int ti_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct ti_qspi_priv *priv = dev_get_priv(bus); + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + fdt_addr_t addr; + + priv->base = (struct ti_qspi_regs *)dev_get_addr(bus); + priv->memory_map = (void *)dev_get_addr_index(bus, 1); + addr = dev_get_addr_index(bus, 2); + priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr; + + priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); + if (priv->max_hz < 0) { + debug("Error: Max frequency missing\n"); + return -ENODEV; + } + priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); + + debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__, + (int)priv->base, priv->max_hz); + + return 0; +} + +static int ti_qspi_child_pre_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + struct udevice *bus = dev_get_parent(dev); + struct ti_qspi_priv *priv = dev_get_priv(bus); + + slave->memory_map = priv->memory_map; + return 0; +} + +static const struct dm_spi_ops ti_qspi_ops = { + .claim_bus = ti_qspi_claim_bus, + .release_bus = ti_qspi_release_bus, + .xfer = ti_qspi_xfer, + .set_speed = ti_qspi_set_speed, + .set_mode = ti_qspi_set_mode, +}; + +static const struct udevice_id ti_qspi_ids[] = { + { .compatible = "ti,dra7xxx-qspi" }, + { .compatible = "ti,am4372-qspi" }, + { } +}; + +U_BOOT_DRIVER(ti_qspi) = { + .name = "ti_qspi", + .id = UCLASS_SPI, + .of_match = ti_qspi_ids, + .ops = &ti_qspi_ops, + .ofdata_to_platdata = ti_qspi_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct ti_qspi_priv), + .probe = ti_qspi_probe, + .child_pre_probe = ti_qspi_child_pre_probe, +}; +#endif /* CONFIG_DM_SPI */

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 09/17] arm: dts: dra7: add qspi register maps for memory map and control module

Add qspi memory map and control module register maps to device tree.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org --- arch/arm/dts/dra7.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index c69c651..e7fecf7 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -1114,8 +1114,11 @@

qspi: qspi@4b300000 { compatible = "ti,dra7xxx-qspi"; - reg = <0x4b300000 0x100>; - reg-names = "qspi_base"; + reg = <0x4b300000 0x100>, + <0x5c000000 0x4000000>, + <0x4a002558 0x4>; + reg-names = "qspi_base", "qspi_mmap", + "qspi_ctrlmod"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi";

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 10/17] arm: dts: am437x-gp-evm: add spi-flash comaptible for flash

In U-Boot most flashes uses "spi-flash" as compatible to bind the device to flash driver, so adding "spi-flash" compatible to m25p80 node.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- arch/arm/dts/am437x-sk-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts index 3f9d808..89feaf3 100644 --- a/arch/arm/dts/am437x-sk-evm.dts +++ b/arch/arm/dts/am437x-sk-evm.dts @@ -567,7 +567,7 @@

spi-max-frequency = <48000000>; m25p80@0 { - compatible = "mx66l51235l"; + compatible = "mx66l51235l","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-cpol;

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 11/17] arm: dts: dra7-evm: add spi-flash comaptible for flash

In U-Boot most flashes uses "spi-flash" as compatible to bind the device to flash driver, so adding "spi-flash" compatible to m25p80 node.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- arch/arm/dts/dra7-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index e4daa99..797d411 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -487,7 +487,7 @@

spi-max-frequency = <48000000>; m25p80@0 { - compatible = "s25fl256s1"; + compatible = "s25fl256s1","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>;

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 12/17] arm: dts: dra72-evm: add spi-flash comaptible for flash

In U-Boot most flashes uses "spi-flash" as compatible to bind the device to flash driver, so adding "spi-flash" compatible to m25p80 node.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com --- arch/arm/dts/dra72-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts index efb544c..a62550f 100644 --- a/arch/arm/dts/dra72-evm.dts +++ b/arch/arm/dts/dra72-evm.dts @@ -604,7 +604,7 @@

spi-max-frequency = <48000000>; m25p80@0 { - compatible = "s25fl256s1"; + compatible = "s25fl256s1","spi-flash"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>;

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 13/17] defconfig: dra72_evm: enable spi driver model

enable mmc driver model for dra72_evm as ti_qspi supports driver model

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com --- configs/dra72_evm_defconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig index 3205bd5..b57ecca 100644 --- a/configs/dra72_evm_defconfig +++ b/configs/dra72_evm_defconfig @@ -20,3 +20,5 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 14/17] defconfig: dra74_evm: enable spi driver model

enable spi driver model for dra74_evm as ti_qspi supports driver model

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com --- configs/dra74_evm_defconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig index 394edbe..6e5a705 100644 --- a/configs/dra74_evm_defconfig +++ b/configs/dra74_evm_defconfig @@ -19,3 +19,5 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 15/17] am43xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl

Since OMAP's spl doesn't support DM currently, do not define DM_SPI and DM_SPI_FLASH for spl build.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- include/configs/am43xx_evm.h | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index aac550a..de7538f 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -142,6 +142,8 @@ */ #ifdef CONFIG_SPL_BUILD #undef CONFIG_DM_MMC +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH #endif

#ifndef CONFIG_SPL_BUILD

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 16/17] arm: dts: am4372: add qspi register maps for memory map

Add qspi memory map address to device tree.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org --- arch/arm/dts/am4372.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index 3fffe1e..c95d1d3 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -25,6 +25,7 @@ serial0 = &uart0; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; + spi0 = &qspi; };

cpus { @@ -908,7 +909,9 @@

qspi: qspi@47900000 { compatible = "ti,am4372-qspi"; - reg = <0x47900000 0x100>; + reg = <0x47900000 0x100>, + <0x30000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi";

-- 2.7.0.rc1.5.gf3adf45

Mugunthan V N

4:09 p.m.

New subject: [U-Boot] [PATCH re-send v6 17/17] defconfig: am437x_sk_evm: enable spi driver model

enable spi driver model for am437x_sk_evm as ti_qspi supports driver model

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Tom Rini trini@konsulko.com --- configs/am437x_sk_evm_defconfig | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig index a9b6f52..8f78eeb 100644 --- a/configs/am437x_sk_evm_defconfig +++ b/configs/am437x_sk_evm_defconfig @@ -18,3 +18,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y

-- 2.7.0.rc1.5.gf3adf45

Jagan Teki

29 Dec 29 Dec

7:45 a.m.

New subject: [U-Boot] [PATCH re-send v6 00/17] device model bring-up of ti-qspi on dra72, dra74 and am437x-sk evm

On 23 December 2015 at 20:39, Mugunthan V N mugunthanvnm@ti.com wrote:

...

Resending the patches as I have missed 01/17 patch while sending v6 series

This patch series enables ti_qspi to adopt driver model. This has been tested on dra72, dra74 and am437x-sk evms (logs [1]). Also pushed a branch for testing [2]

This patch series is based on u-boot-spi/next and a fix for Macronix flash Quad Enable as per the comments in thread [3].

[2]: git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-qspi-v6

Changes from v5->v6:

Removed adding flash compatibles to flash driver and added "spi-flash" compatible to dts as done by other flash devices.

Changes from v4->v5:

Adopt to latest spi framework changes by Jagan [3] and [4]

Changes from v3->v4:

used op_mode_{t/r}x to hold flash tx/rx modes.

Changes from v2->v3:

removed usage of spi_slave structure in driver model and introduced required variables in qspi priv itself.

Used fdt_addr_cells() and fdt_size_cells() instead of hard-coding size of each address-size pair.

Changed qspi dts entries to be same as in kernel qspi dts patch for avoiding future conflicts.

Fixed some typos and added more info in commits.

Added error check on chip select passed from framework.

Removed un-used define QSPI_RD_DUAL.

Changes from Initial version:

Split "prepare driver for DM conversion" for easier review

added memory map mode to the driver

Fixed the cosmetic reviews from Simon

Modified the dev_get_addr_index to adopt OF_TRANSULATE as well and also removed code duplicate.

Added compatibles for spi flashed found in DRA7xx and AM437x SK

Mugunthan V N (17): drivers: spi: ti_qspi: do not hard code chip select for memory map configuration drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model conversion drivers: spi: ti_qspi: prepare driver for DM conversion dm: core: Add a new api to get indexed device address spi: Add support for dual and quad mode dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl dts: dra7: add spi alias for qspi drivers: spi: ti_qspi: convert driver to adopt device driver model arm: dts: dra7: add qspi register maps for memory map and control module arm: dts: am437x-gp-evm: add spi-flash comaptible for flash arm: dts: dra7-evm: add spi-flash comaptible for flash arm: dts: dra72-evm: add spi-flash comaptible for flash defconfig: dra72_evm: enable spi driver model defconfig: dra74_evm: enable spi driver model am43xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl arm: dts: am4372: add qspi register maps for memory map defconfig: am437x_sk_evm: enable spi driver model

Applied to u-boot-spi/master

thanks!

-- Jagan.

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Jagan Teki
Mugunthan V N