[U-Boot] [PATCH 0/6] Updates for atevk1100 support
These patches makes it possible to load code into external SRAM on the atevk1100.
Also included is a patch to use the internal flash. Before this can be done, U-Boot must be relocated to SRAM.
The GPIO implementation is made cpu dependent due to differences between at32uc and ap700x.
Gunnar Rangoy (6): AVR32: Make GPIO implmentation cpu dependent AVR32: Support for external SRAM on at32uc3 AVR32: Use SRAM as main memory on the atevk1100 board AVR32: Enable relocation of code for at32uc3 AVR32: Support for writing to internal flash on at32uc3 AVR32: Set boot parameters for atevk1100
board/atmel/atevk1100/atevk1100.c | 65 +++++++++----- board/atmel/atevk1100/u-boot.lds | 2 - cpu/at32uc/Makefile | 1 + cpu/at32uc/flashc.c | 69 ++++++++++++++- cpu/at32uc/flashc.h | 17 ++++ cpu/at32uc/portmux-gpio.c | 30 ------- cpu/at32uc/smc.c | 61 +++++++++++++ cpu/at32uc/smc.h | 105 +++++++++++++++++++++++ cpu/at32uc/start.S | 15 +--- include/asm-avr32/arch-at32ap700x/gpio-impl.h | 86 ++++++++++++++++++ include/asm-avr32/arch-at32uc3a0xxx/gpio-impl.h | 62 +++++++++++++ include/asm-avr32/arch-common/portmux-gpio.h | 83 +----------------- include/asm-avr32/sram.h | 34 +++++++ include/configs/atevk1100.h | 22 +++-- lib_avr32/board.c | 5 - 15 files changed, 490 insertions(+), 167 deletions(-) create mode 100644 cpu/at32uc/smc.c create mode 100644 cpu/at32uc/smc.h create mode 100644 include/asm-avr32/arch-at32ap700x/gpio-impl.h create mode 100644 include/asm-avr32/arch-at32uc3a0xxx/gpio-impl.h create mode 100644 include/asm-avr32/sram.h
There are some differences in the implementation of GPIO in the at32uc chip compared to the ap700x series.
Signed-off-by: Gunnar Rangoy gunnar@rangoy.com Signed-off-by: Paul Driveklepp pauldriveklepp@gmail.com Signed-off-by: Olav Morken olavmrk@gmail.com --- cpu/at32uc/portmux-gpio.c | 30 -------- include/asm-avr32/arch-at32ap700x/gpio-impl.h | 86 +++++++++++++++++++++++ include/asm-avr32/arch-at32uc3a0xxx/gpio-impl.h | 62 ++++++++++++++++ include/asm-avr32/arch-common/portmux-gpio.h | 83 +--------------------- 4 files changed, 150 insertions(+), 111 deletions(-) create mode 100644 include/asm-avr32/arch-at32ap700x/gpio-impl.h create mode 100644 include/asm-avr32/arch-at32uc3a0xxx/gpio-impl.h
diff --git a/cpu/at32uc/portmux-gpio.c b/cpu/at32uc/portmux-gpio.c index 8ed5659..0b8bae9 100644 --- a/cpu/at32uc/portmux-gpio.c +++ b/cpu/at32uc/portmux-gpio.c @@ -29,26 +29,11 @@ void portmux_select_peripheral(void *port, unsigned long pin_mask, enum portmux_function func, unsigned long flags) { - /* Both pull-up and pull-down set means buskeeper */ - if (flags & PORTMUX_PULL_DOWN) - gpio_writel(port, PDERS, pin_mask); - else - gpio_writel(port, PDERC, pin_mask); if (flags & PORTMUX_PULL_UP) gpio_writel(port, PUERS, pin_mask); else gpio_writel(port, PUERC, pin_mask);
- /* Select drive strength */ - if (flags & PORTMUX_DRIVE_LOW) - gpio_writel(port, ODCR0S, pin_mask); - else - gpio_writel(port, ODCR0C, pin_mask); - if (flags & PORTMUX_DRIVE_HIGH) - gpio_writel(port, ODCR1S, pin_mask); - else - gpio_writel(port, ODCR1C, pin_mask); - /* Select function */ if (func & PORTMUX_FUNC_B) gpio_writel(port, PMR0S, pin_mask); @@ -66,11 +51,6 @@ void portmux_select_peripheral(void *port, unsigned long pin_mask, void portmux_select_gpio(void *port, unsigned long pin_mask, unsigned long flags) { - /* Both pull-up and pull-down set means buskeeper */ - if (flags & PORTMUX_PULL_DOWN) - gpio_writel(port, PDERS, pin_mask); - else - gpio_writel(port, PDERC, pin_mask); if (flags & PORTMUX_PULL_UP) gpio_writel(port, PUERS, pin_mask); else @@ -82,16 +62,6 @@ void portmux_select_gpio(void *port, unsigned long pin_mask, else gpio_writel(port, ODMERC, pin_mask);
- /* Select drive strength */ - if (flags & PORTMUX_DRIVE_LOW) - gpio_writel(port, ODCR0S, pin_mask); - else - gpio_writel(port, ODCR0C, pin_mask); - if (flags & PORTMUX_DRIVE_HIGH) - gpio_writel(port, ODCR1S, pin_mask); - else - gpio_writel(port, ODCR1C, pin_mask); - /* Select direction and initial pin state */ if (flags & PORTMUX_DIR_OUTPUT) { if (flags & PORTMUX_INIT_HIGH) diff --git a/include/asm-avr32/arch-at32ap700x/gpio-impl.h b/include/asm-avr32/arch-at32ap700x/gpio-impl.h new file mode 100644 index 0000000..8801bd0 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/gpio-impl.h @@ -0,0 +1,86 @@ +#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__ +#define __ASM_AVR32_ARCH_GPIO_IMPL_H__ + +/* Register offsets */ +struct gpio_regs { + u32 GPER; + u32 GPERS; + u32 GPERC; + u32 GPERT; + u32 PMR0; + u32 PMR0S; + u32 PMR0C; + u32 PMR0T; + u32 PMR1; + u32 PMR1S; + u32 PMR1C; + u32 PMR1T; + u32 __reserved0[4]; + u32 ODER; + u32 ODERS; + u32 ODERC; + u32 ODERT; + u32 OVR; + u32 OVRS; + u32 OVRC; + u32 OVRT; + u32 PVR; + u32 __reserved_PVRS; + u32 __reserved_PVRC; + u32 __reserved_PVRT; + u32 PUER; + u32 PUERS; + u32 PUERC; + u32 PUERT; + u32 PDER; + u32 PDERS; + u32 PDERC; + u32 PDERT; + u32 IER; + u32 IERS; + u32 IERC; + u32 IERT; + u32 IMR0; + u32 IMR0S; + u32 IMR0C; + u32 IMR0T; + u32 IMR1; + u32 IMR1S; + u32 IMR1C; + u32 IMR1T; + u32 GFER; + u32 GFERS; + u32 GFERC; + u32 GFERT; + u32 IFR; + u32 __reserved_IFRS; + u32 IFRC; + u32 __reserved_IFRT; + u32 ODMER; + u32 ODMERS; + u32 ODMERC; + u32 ODMERT; + u32 __reserved1[4]; + u32 ODCR0; + u32 ODCR0S; + u32 ODCR0C; + u32 ODCR0T; + u32 ODCR1; + u32 ODCR1S; + u32 ODCR1C; + u32 ODCR1T; + u32 __reserved2[4]; + u32 OSRR0; + u32 OSRR0S; + u32 OSRR0C; + u32 OSRR0T; + u32 __reserved3[8]; + u32 STER; + u32 STERS; + u32 STERC; + u32 STERT; + u32 __reserved4[35]; + u32 VERSION; +}; + +#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */ diff --git a/include/asm-avr32/arch-at32uc3a0xxx/gpio-impl.h b/include/asm-avr32/arch-at32uc3a0xxx/gpio-impl.h new file mode 100644 index 0000000..636bd19 --- /dev/null +++ b/include/asm-avr32/arch-at32uc3a0xxx/gpio-impl.h @@ -0,0 +1,62 @@ +#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__ +#define __ASM_AVR32_ARCH_GPIO_IMPL_H__ + +/* Register offsets */ +struct gpio_regs { + u32 GPER; + u32 GPERS; + u32 GPERC; + u32 GPERT; + u32 PMR0; + u32 PMR0S; + u32 PMR0C; + u32 PMR0T; + u32 PMR1; + u32 PMR1S; + u32 PMR1C; + u32 PMR1T; + u32 __reserved0[4]; + u32 ODER; + u32 ODERS; + u32 ODERC; + u32 ODERT; + u32 OVR; + u32 OVRS; + u32 OVRC; + u32 OVRT; + u32 PVR; + u32 __reserved_PVRS; + u32 __reserved_PVRC; + u32 __reserved_PVRT; + u32 PUER; + u32 PUERS; + u32 PUERC; + u32 PUERT; + u32 ODMER; + u32 ODMERS; + u32 ODMERC; + u32 ODMERT; + u32 IER; + u32 IERS; + u32 IERC; + u32 IERT; + u32 IMR0; + u32 IMR0S; + u32 IMR0C; + u32 IMR0T; + u32 IMR1; + u32 IMR1S; + u32 IMR1C; + u32 IMR1T; + u32 GFER; + u32 GFERS; + u32 GFERC; + u32 GFERT; + u32 IFR; + u32 __reserved_IFRS; + u32 IFRC; + u32 __reserved_IFRT; + u32 __reserved1[8]; +}; + +#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */ diff --git a/include/asm-avr32/arch-common/portmux-gpio.h b/include/asm-avr32/arch-common/portmux-gpio.h index 24943ec..1306cbe 100644 --- a/include/asm-avr32/arch-common/portmux-gpio.h +++ b/include/asm-avr32/arch-common/portmux-gpio.h @@ -24,87 +24,8 @@
#include <asm/io.h>
-/* Register offsets */ -struct gpio_regs { - u32 GPER; - u32 GPERS; - u32 GPERC; - u32 GPERT; - u32 PMR0; - u32 PMR0S; - u32 PMR0C; - u32 PMR0T; - u32 PMR1; - u32 PMR1S; - u32 PMR1C; - u32 PMR1T; - u32 __reserved0[4]; - u32 ODER; - u32 ODERS; - u32 ODERC; - u32 ODERT; - u32 OVR; - u32 OVRS; - u32 OVRC; - u32 OVRT; - u32 PVR; - u32 __reserved_PVRS; - u32 __reserved_PVRC; - u32 __reserved_PVRT; - u32 PUER; - u32 PUERS; - u32 PUERC; - u32 PUERT; - u32 PDER; - u32 PDERS; - u32 PDERC; - u32 PDERT; - u32 IER; - u32 IERS; - u32 IERC; - u32 IERT; - u32 IMR0; - u32 IMR0S; - u32 IMR0C; - u32 IMR0T; - u32 IMR1; - u32 IMR1S; - u32 IMR1C; - u32 IMR1T; - u32 GFER; - u32 GFERS; - u32 GFERC; - u32 GFERT; - u32 IFR; - u32 __reserved_IFRS; - u32 IFRC; - u32 __reserved_IFRT; - u32 ODMER; - u32 ODMERS; - u32 ODMERC; - u32 ODMERT; - u32 __reserved1[4]; - u32 ODCR0; - u32 ODCR0S; - u32 ODCR0C; - u32 ODCR0T; - u32 ODCR1; - u32 ODCR1S; - u32 ODCR1C; - u32 ODCR1T; - u32 __reserved2[4]; - u32 OSRR0; - u32 OSRR0S; - u32 OSRR0C; - u32 OSRR0T; - u32 __reserved3[8]; - u32 STER; - u32 STERS; - u32 STERC; - u32 STERT; - u32 __reserved4[35]; - u32 VERSION; -}; +/* Register layout for this specific device */ +#include <asm/arch/gpio-impl.h>
/* Register access macros */ #define gpio_readl(port, reg) \
This patch adds support for external SRAM connected to the EBI bus on the at32uc3a0xxx.
Signed-off-by: Gunnar Rangoy gunnar@rangoy.com Signed-off-by: Paul Driveklepp pauldriveklepp@gmail.com Signed-off-by: Olav Morken olavmrk@gmail.com --- cpu/at32uc/Makefile | 1 + cpu/at32uc/smc.c | 61 ++++++++++++++++++++++++++ cpu/at32uc/smc.h | 105 ++++++++++++++++++++++++++++++++++++++++++++++ include/asm-avr32/sram.h | 34 +++++++++++++++ 4 files changed, 201 insertions(+), 0 deletions(-) create mode 100644 cpu/at32uc/smc.c create mode 100644 cpu/at32uc/smc.h create mode 100644 include/asm-avr32/sram.h
diff --git a/cpu/at32uc/Makefile b/cpu/at32uc/Makefile index cab9bdc..6714d14 100644 --- a/cpu/at32uc/Makefile +++ b/cpu/at32uc/Makefile @@ -36,6 +36,7 @@ COBJS-y += cache.o COBJS-y += interrupts.o COBJS-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o COBJS-y += flashc.o +COBJS-y += smc.o
SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/at32uc/smc.c b/cpu/at32uc/smc.c new file mode 100644 index 0000000..f4bb9fb --- /dev/null +++ b/cpu/at32uc/smc.c @@ -0,0 +1,61 @@ +#include <common.h> +#include <asm/sram.h> +#include "smc.h" + +unsigned long sram_init(const struct sram_config *config) +{ + u32 cfgreg; + u32 dbw; + u32 sram_size; + + cfgreg = SMC_BF(NWE_SETUP, config->nwe_setup) + |SMC_BF(NRD_SETUP, config->nrd_setup) + |SMC_BF(NCS_WR_SETUP, config->ncs_wr_setup) + |SMC_BF(NCS_RD_SETUP, config->ncs_rd_setup); + smc_writel(config->chip_select, SETUP, cfgreg); + + cfgreg = SMC_BF(NWE_PULSE, config->nwe_pulse) + |SMC_BF(NRD_PULSE, config->nrd_pulse) + |SMC_BF(NCS_WR_PULSE, config->ncs_wr_pulse) + |SMC_BF(NCS_RD_PULSE, config->ncs_rd_pulse); + smc_writel(config->chip_select, PULSE, cfgreg); + + cfgreg = SMC_BF(NWE_CYCLE, config->nwe_cycle) + |SMC_BF(NRD_CYCLE, config->nrd_cycle); + smc_writel(config->chip_select, CYCLE, cfgreg); + + switch (config->data_bits) { + case 8: + dbw=0; + break; + case 16: + dbw=1; + break; + case 32: + dbw=2; + break; + default: + panic("Invalid number of databits for SRAM"); + + } + cfgreg = SMC_BF(READ_MODE, config->read_mode) + |SMC_BF(WRITE_MODE, config->write_mode) + |SMC_BF(EXNW_MODE, config->exnw_mode) + |SMC_BF(BAT, config->bat) + |SMC_BF(DBW, dbw) + |SMC_BF(TDF_CYCLES, config->tdf_cycles) + |SMC_BF(TDF_MODE, config->tdf_mode) + |SMC_BF(PMEN, config->pmen) + |SMC_BF(PS, config->ps); + + + + + smc_writel(config->chip_select, MODE, cfgreg); + sram_size= (1<<config->address_bits) * (config->data_bits/8); + + + return sram_size; +} + + diff --git a/cpu/at32uc/smc.h b/cpu/at32uc/smc.h new file mode 100644 index 0000000..ea4d399 --- /dev/null +++ b/cpu/at32uc/smc.h @@ -0,0 +1,105 @@ +/* + * Register definitions for Static Memory Controller + */ +#ifndef __CPU_AT32UC3_SMC_H__ +#define __CPU_AT32UC3_SMC_H__ + +#include <asm/arch/memory-map.h> +#include <asm/io.h> + +/* SMC register offsets */ +#define SMC_SETUP(x) 0x0000+(x)*0x10 +#define SMC_PULSE(x) 0x0004+(x)*0x10 +#define SMC_CYCLE(x) 0x0008+(x)*0x10 +#define SMC_MODE(x) 0x000c+(x)*0x10 + +/* Bitfields in SETUP0..3 */ +#define SMC_NWE_SETUP_OFFSET 0 +#define SMC_NWE_SETUP_SIZE 6 +#define SMC_NCS_WR_SETUP_OFFSET 8 +#define SMC_NCS_WR_SETUP_SIZE 6 +#define SMC_NRD_SETUP_OFFSET 16 +#define SMC_NRD_SETUP_SIZE 6 +#define SMC_NCS_RD_SETUP_OFFSET 24 +#define SMC_NCS_RD_SETUP_SIZE 6 + +/* Bitfields in PULSE0..3 */ +#define SMC_NWE_PULSE_OFFSET 0 +#define SMC_NWE_PULSE_SIZE 7 +#define SMC_NCS_WR_PULSE_OFFSET 8 +#define SMC_NCS_WR_PULSE_SIZE 7 +#define SMC_NRD_PULSE_OFFSET 16 +#define SMC_NRD_PULSE_SIZE 7 +#define SMC_NCS_RD_PULSE_OFFSET 24 +#define SMC_NCS_RD_PULSE_SIZE 7 + +/* Bitfields in CYCLE0..3 */ +#define SMC_NWE_CYCLE_OFFSET 0 +#define SMC_NWE_CYCLE_SIZE 9 +#define SMC_NRD_CYCLE_OFFSET 16 +#define SMC_NRD_CYCLE_SIZE 9 + +/* Bitfields in MODE0..3 */ +#define SMC_READ_MODE_OFFSET 0 +#define SMC_READ_MODE_SIZE 1 +#define SMC_WRITE_MODE_OFFSET 1 +#define SMC_WRITE_MODE_SIZE 1 +#define SMC_EXNW_MODE_OFFSET 4 +#define SMC_EXNW_MODE_SIZE 2 +#define SMC_BAT_OFFSET 8 +#define SMC_BAT_SIZE 1 +#define SMC_DBW_OFFSET 12 +#define SMC_DBW_SIZE 2 +#define SMC_TDF_CYCLES_OFFSET 16 +#define SMC_TDF_CYCLES_SIZE 4 +#define SMC_TDF_MODE_OFFSET 20 +#define SMC_TDF_MODE_SIZE 1 +#define SMC_PMEN_OFFSET 24 +#define SMC_PMEN_SIZE 1 +#define SMC_PS_OFFSET 28 +#define SMC_PS_SIZE 2 + +/* Constants for READ_MODE */ +#define SMC_READ_MODE_NCS_CONTROLLED 0 +#define SMC_READ_MODE_NRD_CONTROLLED 1 + +/* Constants for WRITE_MODE */ +#define SMC_WRITE_MODE_NCS_CONTROLLED 0 +#define SMC_WRITE_MODE_NWE_CONTROLLED 1 + +/* Constants for EXNW_MODE */ +#define SMC_EXNW_MODE_DISABLED 0 +#define SMC_EXNW_MODE_RESERVED 1 +#define SMC_EXNW_MODE_FROZEN 2 +#define SMC_EXNW_MODE_READY 3 + +/* Constants for BAT */ +#define SMC_BAT_BYTE_SELECT 0 +#define SMC_BAT_BYTE_WRITE 1 + +/* Constants for DBW */ +#define SMC_DBW_8_BITS 0 +#define SMC_DBW_16_BITS 1 +#define SMC_DBW_32_BITS 2 + +/* Bit manipulation macros */ +#define SMC_BIT(name) \ + (1 << SMC_##name##_OFFSET) +#define SMC_BF(name,value) \ + (((value) & ((1 << SMC_##name##_SIZE) - 1)) \ + << SMC_##name##_OFFSET) +#define SMC_BFEXT(name,value) \ + (((value) >> SMC_##name##_OFFSET) \ + & ((1 << SMC_##name##_SIZE) - 1)) +#define SMC_BFINS(name,value,old)\ + (((old) & ~(((1 << SMC_##name##_SIZE) - 1) \ + << SMC_##name##_OFFSET)) \ + | SMC_BF(name,value)) + +/* Register access macros */ +#define smc_readl(cs,reg) \ + readl((void *)SMC_BASE + SMC_##reg(cs)) +#define smc_writel(cs,reg,value) \ + writel((value), (void *)SMC_BASE + SMC_##reg(cs)) + +#endif /* __CPU_AT32UC3_SMC_H__ */ diff --git a/include/asm-avr32/sram.h b/include/asm-avr32/sram.h new file mode 100644 index 0000000..3306d0b --- /dev/null +++ b/include/asm-avr32/sram.h @@ -0,0 +1,34 @@ +#ifndef __ASM_AVR32_SRAM_H +#define __ASM_AVR32_SRAM_H +#include <asm/types.h> + +struct sram_config { + /* Number of data bits. */ + u8 data_bits; + + /* Chip select */ + u8 chip_select; + + /* Number of address bits */ + u8 address_bits; + + /* nwe/nrd waveforms */ + u8 nwe_setup, nwe_pulse, nwe_hold; + u8 nrd_setup, nrd_pulse, nrd_hold; + + /* ncs waveforms */ + u8 ncs_wr_setup, ncs_wr_pulse, ncs_wr_hold; + u8 ncs_rd_setup, ncs_rd_pulse, ncs_rd_hold; + + /* Cycle length */ + u16 nwe_cycle, nrd_cycle; + + /* mode */ + u8 read_mode, write_mode, exnw_mode; + u8 bat, dbw, tdf_cycles, tdf_mode, pmen, ps; +}; + + +unsigned long sram_init(const struct sram_config *config); + +#endif /* __ASM_AVR32_SRAM_H */
This patch makes u-boot use SRAM instead of SDRAM as main memory. This is done due to a bug in the current revsions of the at32uc3a0xxx series microcontrollers, which makes it unreliable to run code from SDRAM.
Signed-off-by: Gunnar Rangoy gunnar@rangoy.com Signed-off-by: Paul Driveklepp pauldriveklepp@gmail.com Signed-off-by: Olav Morken olavmrk@gmail.com --- board/atmel/atevk1100/atevk1100.c | 65 ++++++++++++++++++++++++------------ include/configs/atevk1100.h | 12 ++++--- 2 files changed, 50 insertions(+), 27 deletions(-)
diff --git a/board/atmel/atevk1100/atevk1100.c b/board/atmel/atevk1100/atevk1100.c index 105e5c9..a85337e 100644 --- a/board/atmel/atevk1100/atevk1100.c +++ b/board/atmel/atevk1100/atevk1100.c @@ -22,30 +22,51 @@ #include <common.h>
#include <asm/io.h> -#include <asm/sdram.h> +#include <asm/sram.h> #include <asm/arch/clk.h> #include <asm/arch/hmatrix.h> #include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
-static const struct sdram_config sdram_config = { - /* MT48LC16M16A2-7E (32 MB) */ - .data_bits = SDRAM_DATA_16BIT, - .row_bits = 13, - .col_bits = 9, - .bank_bits = 2, - .cas = 2, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 4, - .txsr = 7, - /* 7.81 us */ - .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, -}; +static const struct sram_config sram_config = { + /* 2x16MBit, CY7C1069AV33-10ZXC */ + .data_bits = 16, + .address_bits = 21, + .ncs_rd_setup = 0, + .ncs_wr_setup = 0, + .nwe_setup = 0, + .nrd_setup = 0, + /* + * These settings works when running at 33Mhz, + * but fails at 54MHz + */ + + /* + .ncs_wr_pulse = 1, + .ncs_rd_pulse = 1, + .nwe_pulse = 1, + .nrd_pulse = 1, + .nwe_cycle = 2, + .nrd_cycle = 2, + */ + .ncs_wr_pulse = 2, + .ncs_rd_pulse = 2, + .nwe_pulse = 2, + .nrd_pulse = 2, + .nwe_cycle = 3, + .nrd_cycle = 3, + .chip_select = 2, + .read_mode = 1, + .write_mode = 1, + .exnw_mode = 0, + .bat = 1, + .tdf_cycles = 0, + .tdf_mode = 0, + .pmen = 0, + .ps = 1,
+}; int board_early_init_f(void) { /* Enable SDRAM in the EBI mux according to AP7000 datasheet */ @@ -65,14 +86,14 @@ phys_size_t initdram(int board_type) { unsigned long expected_size; unsigned long actual_size; - void *sdram_base; + void *sram_base;
- sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + sram_base = map_physmem(EBI_SRAM_CS2_BASE, EBI_SRAM_CS2_SIZE, MAP_NOCACHE);
- expected_size = sdram_init(sdram_base, &sdram_config); - actual_size = get_ram_size(sdram_base, expected_size); + expected_size = sram_init(&sram_config); + actual_size = get_ram_size(sram_base, expected_size);
- unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + unmap_physmem(sram_base, EBI_SRAM_CS2_SIZE);
if (expected_size != actual_size) printf("Warning: Only %lu of %lu MiB SDRAM is working\n", diff --git a/include/configs/atevk1100.h b/include/configs/atevk1100.h index db5af37..166027a 100644 --- a/include/configs/atevk1100.h +++ b/include/configs/atevk1100.h @@ -148,7 +148,8 @@ #define CONFIG_ATMEL_SPI 1 #define CONFIG_PORTMUX_GPIO 1 #define CFG_NR_PIOS 5 -#define CFG_SDRAMC 1 +#define CFG_SDRAMC 0 +#define CFG_SMC 1
#define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 @@ -165,7 +166,8 @@
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE #define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CFG_SDRAM_BASE EBI_SDRAM_BASE +/* Not really SDRAM, maybe change to SRAM? */ +#define CFG_SDRAM_BASE EBI_SRAM_CS2_BASE
#define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SIZE 65536 @@ -176,8 +178,8 @@ #define CFG_MALLOC_LEN (256*1024) #define CFG_DMA_ALLOC_LEN (16384)
-/* Allow 4MB for the kernel run-time image */ -#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +/* Allow 3MB(TODO:update) for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00270000) #define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */ @@ -187,7 +189,7 @@ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1
-#define CFG_MEMTEST_START EBI_SDRAM_BASE +#define CFG_MEMTEST_START CFG_SDRAM_BASE #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Since we now have working SRAM, we can relocate the code to SRAM.
Signed-off-by: Gunnar Rangoy gunnar@rangoy.com Signed-off-by: Paul Driveklepp pauldriveklepp@gmail.com Signed-off-by: Olav Morken olavmrk@gmail.com --- board/atmel/atevk1100/u-boot.lds | 2 -- cpu/at32uc/start.S | 15 +-------------- lib_avr32/board.c | 5 ----- 3 files changed, 1 insertions(+), 21 deletions(-)
diff --git a/board/atmel/atevk1100/u-boot.lds b/board/atmel/atevk1100/u-boot.lds index 3c20979..1c09641 100644 --- a/board/atmel/atevk1100/u-boot.lds +++ b/board/atmel/atevk1100/u-boot.lds @@ -40,8 +40,6 @@ SECTIONS *(.rodata.*) }
- _end_noreloc = .; - . = ALIGN(8); _data = .; .data : { diff --git a/cpu/at32uc/start.S b/cpu/at32uc/start.S index e1d44cb..a8798af 100644 --- a/cpu/at32uc/start.S +++ b/cpu/at32uc/start.S @@ -216,44 +216,31 @@ relocate_code: brgt 1b
/* jump to RAM */ - /* we don't want to run from sdram. sub r0, pc, . - in_ram add pc, r0, lr - */
.align 2 in_ram: /* find the new GOT and relocate it */ lddpc r6, got_init_reloc 3: rsub r6, pc - add r6, lr mov r8, r6 lda.w r9, _egot lda.w r10, _got sub r9, r10
- lda.w r1, _end_noreloc - 1: ld.w r0, r8[0] - /* Check if the symbol points to the text-section, and - * skip relocation if they do. - */ - cp.w r0, r1 - brlt 2f - add r0, lr st.w r8, r0 -2: + sub r8, -4 sub r9, 4 brgt 1b
/* Move the exception handlers */ - /* We don't want to run from sdram. mfsr r2, SYSREG_EVBA add r2, lr mtsr SYSREG_EVBA, r2 - */
/* Do the rest of the initialization sequence */ call board_init_r diff --git a/lib_avr32/board.c b/lib_avr32/board.c index 6afa8bd..216ff74 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -294,13 +294,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) cmdtp != &__u_boot_cmd_end; cmdtp++) { unsigned long addr;
- /* We don't relocate code in the at32uc3a0xxx cpu yet due to - * SDRAM bug. See errata 41.4.6.1. - */ -#ifndef CONFIG_AT32UC addr = (unsigned long)cmdtp->cmd + gd->reloc_off; cmdtp->cmd = (typeof(cmdtp->cmd))addr; -#endif
addr = (unsigned long)cmdtp->name + gd->reloc_off; cmdtp->name = (typeof(cmdtp->name))addr;
This patch enables writing (the environment) to the internal flash in the microcontroller.
Signed-off-by: Gunnar Rangoy gunnar@rangoy.com Signed-off-by: Paul Driveklepp pauldriveklepp@gmail.com Signed-off-by: Olav Morken olavmrk@gmail.com --- cpu/at32uc/flashc.c | 69 +++++++++++++++++++++++++++++++++++++++++-- cpu/at32uc/flashc.h | 17 ++++++++++ include/configs/atevk1100.h | 2 +- 3 files changed, 84 insertions(+), 4 deletions(-)
diff --git a/cpu/at32uc/flashc.c b/cpu/at32uc/flashc.c index f33a4bb..e626e1f 100644 --- a/cpu/at32uc/flashc.c +++ b/cpu/at32uc/flashc.c @@ -45,6 +45,7 @@ unsigned long flash_init(void) { unsigned long fsz; unsigned long size; + unsigned int i;
fsz = FLASHC_BFEXT(FSZ, flashc_readl(FSR));
@@ -55,6 +56,10 @@ unsigned long flash_init(void) /* Currently, all interflash have pages which are 128 words. */ flash_info[0].sector_count = size / (128*4);
+ for(i=0; i<flash_info[0].sector_count; i++){ + flash_info[0].start[i] = i*128*4 + CFG_FLASH_BASE; + } + return size; }
@@ -62,19 +67,77 @@ void flash_print_info(flash_info_t *info) { printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n", info->flash_id >> 16, info->flash_id & 0xffff); - printf("Size: %ld MB in %d sectors\n", + printf("Size: %ld kB in %d sectors\n", info->size >> 10, info->sector_count); }
+static void flash_wait_ready(void) +{ + while(! flashc_readl(FSR) & FLASHC_BIT(FRDY) ); +} + int flash_erase(flash_info_t *info, int s_first, int s_last) { - /* TODO */ + int page; + + for(page=s_first;page<s_last; page++){ + flash_wait_ready(); + flashc_writel( + FCMD,FLASHC_BF(CMD, FLASHC_EP) + |FLASHC_BF(PAGEN, page) + |FLASHC_BF(KEY, 0xa5)); + } return ERR_OK; }
+static void write_flash_page(unsigned int pagen, const u32 *data) +{ + unsigned int i; + u32 *dst; + + dst = (u32 *) CFG_FLASH_BASE; + + /* clear page buffer */ + flash_wait_ready(); + flashc_writel(FCMD, + FLASHC_BF(CMD, FLASHC_CPB) | + FLASHC_BF(KEY, 0xa5)); + + /* fill page buffer*/ + flash_wait_ready(); + for(i=0; i<128; i++){ + dst[i]=data[i]; + } + + /* issue write command */ + flashc_writel(FCMD, + FLASHC_BF(CMD, FLASHC_WP)| + FLASHC_BF(PAGEN, pagen)| + FLASHC_BF(KEY, 0xa5)); +} + int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong count) { - /* TODO */ + unsigned int i; + + if (addr % (4*128)) { + printf("flash: write_buff(): ERROR, addr(0x%08lx) not " + "on page boundary", addr); + return ERR_ALIGN; + } + if (count % (4*128)) { + printf("flash: write_buff(): ERROR, count(0x%lu) not " + "a multiple of pagesize", count); + return ERR_ALIGN; + } + + for (i = 0; i < count; i += 128*4) { + unsigned int pagen; + pagen = (addr-CFG_FLASH_BASE+i) / (128*4); + write_flash_page(pagen, (u32*) (src+i)); + } + + return ERR_OK; }
diff --git a/cpu/at32uc/flashc.h b/cpu/at32uc/flashc.h index 23618bc..3e97781 100644 --- a/cpu/at32uc/flashc.h +++ b/cpu/at32uc/flashc.h @@ -43,6 +43,23 @@ #define FLASHC_LOCK_OFFSET 16 #define FLASHC_LOCK_SIZE 16
+#define FLASHC_NOP 0 /*No operation*/ +#define FLASHC_WP 1 /*Write Page*/ +#define FLASHC_EP 2 /*Erase Page*/ +#define FLASHC_CPB 3 /*Clear Page Buffer*/ +#define FLASHC_LP 4 /*Lock region containing given Page*/ +#define FLASHC_UP 5 /*Unlock region containing given Page*/ +#define FLASHC_EA 6 /*Erase All*/ +#define FLASHC_WGPB 7 /*Write General-Purpose Fuse Bit*/ +#define FLASHC_EGPB 8 /*Erase General-Purpose Fuse Bit*/ +#define FLASHC_SSB 9 /*Set Security Bit*/ +#define FLASHC_PGPFB 10 /*Program GP Fuse Byte*/ +#define FLASHC_EAGPF 11 /*Erase All GPFuses*/ +#define FLASHC_QPR 12 /*Quick Page Read*/ +#define FLASHC_WUP 13 /*Write User Page*/ +#define FLASHC_EUP 14 /*Erase User Page*/ +#define FLASHC_QPRUP 15 /*Quick Page Read User Page*/ +
/* Bit manipulation macros */ #define FLASHC_BIT(name) \ diff --git a/include/configs/atevk1100.h b/include/configs/atevk1100.h index 166027a..776a3a1 100644 --- a/include/configs/atevk1100.h +++ b/include/configs/atevk1100.h @@ -160,7 +160,7 @@ #define CFG_FLASH_BASE 0x80000000 #define CFG_FLASH_SIZE 0x80000 #define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 135 +#define CFG_MAX_FLASH_SECT 1024
#define CFG_MONITOR_BASE CFG_FLASH_BASE
This patch sets resonable boot parameters for the atevk1100. (Load kernel via tftp/dhcp and use nfs rootfs.)
Signed-off-by: Gunnar Rangoy gunnar@rangoy.com Signed-off-by: Paul Driveklepp pauldriveklepp@gmail.com Signed-off-by: Olav Morken olavmrk@gmail.com --- include/configs/atevk1100.h | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/atevk1100.h b/include/configs/atevk1100.h index 776a3a1..2a9d91b 100644 --- a/include/configs/atevk1100.h +++ b/include/configs/atevk1100.h @@ -95,17 +95,17 @@
#define CONFIG_BAUDRATE 9600 #define CONFIG_BOOTARGS \ - "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1" + "console=ttyS0 ip=dhcp root=/dev/nfs rootwait=1"
#define CONFIG_BOOTCOMMAND \ - "fsload; bootm $(fileaddr)" + "dhcp; bootm $(fileaddr)"
/* * Only interrupt autoboot if <space> is pressed. Otherwise, garbage * data on the serial line may interrupt the boot sequence. */ -#define CONFIG_BOOTDELAY -1 -#define CONFIG_AUTOBOOT 0 +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 #define CONFIG_AUTOBOOT_PROMPT \ "Press SPACE to abort autoboot in %d seconds\n", bootdelay
participants (1)
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Gunnar Rangoy