If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of ram and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux board ports in arch/powerpc with bootwrapper support, which recalculate the memory size from the SDRAM controller setup, will have to get fixed in Linux additionally.

This patch enables this config option on some PPC440EPx boards as a workaround for the CHIP 11 errata. Here the description from the AMCC documentation:

CHIP_11: End of memory range area restricted access. Category: 3

Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus.

Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU.

Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux.

This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: lwmon5, korat, sequoia

The other remaining 440EPx board were intentionally not included since it is not clear to me, if they use the end of ram for some other purpose. This is unclear, since these boards have CONFIG_PRAM defined and even comments like this:

PMC440.h: /* esd expects pram at end of physical memory. * So no logbuffer at the moment. */

It is strongly recommended to not use the last 256 bytes on those boards too. Patches from the board maintainers are welcome.

Signed-off-by: Stefan Roese sr@denx.de --- Changes in this version v5: - Small changes in the patch description and README

Changes in this version v4: - Add CFG_MEM_TOP_HIDE decription to README

Changes in this version v3: - Changed value of CFG_MEM_TOP_HIDE from 256 to 4k so that memory end location is on a page boundary - Rebased on current git version

Changes in this version v2: - Changed name of define to CFG_MEM_TOP_HIDE

README | 21 +++++++++++++++++++++ include/configs/korat.h | 2 ++ include/configs/lwmon5.h | 2 ++ include/configs/sequoia.h | 4 +++- lib_ppc/board.c | 13 +++++++++++++ 5 files changed, 41 insertions(+), 1 deletions(-)

diff --git a/README b/README index 0e37b8b..4c7bf95 100644 --- a/README +++ b/README @@ -1854,6 +1854,27 @@ Configuration Settings: Scratch address used by the alternate memory test You only need to set this if address zero isn't writeable

+- CFG_MEM_TOP_HIDE (PPC only): + If CFG_MEM_TOP_HIDE is defined in the board config header, + this specified memory area will get subtracted from the top + (end) of ram and won't get "touched" at all by U-Boot. By + fixing up gd->ram_size the Linux kernel should gets passed + the now "corrected" memory size and won't touch it either. + This should work for arch/ppc and arch/powerpc. Only Linux + board ports in arch/powerpc with bootwrapper support, that + recalculate the memory size from the SDRAM controller setup + will have to get fixed. + + This option can be used as a workaround for the 440EPx/GRx + CHIP 11 errata where the last 256 bytes in SDRAM shouldn't + be touched. + + WARNING: Please make sure that this value is a multiple of + the Linux page size (normally 4k). If this is not the case, + then the end address of the Linux memory will be located at a + non page size aligned address and this could cause major + problems. + - CFG_TFTP_LOADADDR: Default load address for network file downloads

diff --git a/include/configs/korat.h b/include/configs/korat.h index dcec9b0..de672ea 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -144,6 +144,8 @@ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB #define CFG_DRAM_TEST +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */

/* * I2C diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index ced7ba6..3056cb0 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -86,6 +86,8 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) /* unused GPT0 COMP reg */ +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */

/* Additional registers for watchdog timer post test */

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index dfa8779..555316f 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -221,6 +221,8 @@ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */

/* * I2C @@ -275,7 +277,7 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ "flash_nfs=run nfsargs addip addtty addmisc;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty addmisc;" \ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 3ab22f8..f0a2c87 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -425,6 +425,7 @@ void board_init_f (ulong bootflag) * relocate the code and continue running from DRAM. * * Reserve memory at end of RAM for (top down in that order): + * - area that won't get touched by U-Boot and Linux (optional) * - kernel log buffer * - protected RAM * - LCD framebuffer @@ -433,6 +434,18 @@ void board_init_f (ulong bootflag) */ len = (ulong)&_end - CFG_MONITOR_BASE;

+ /* + * Subtract specified amount of memory to hide so that it won't + * get "touched" at all by U-Boot. By fixing up gd->ram_size + * the Linux kernel should now get passed the now "corrected" + * memory size and won't touch it either. This should work + * for arch/ppc and arch/powerpc. Only Linux board ports in + * arch/powerpc with bootwrapper support, that recalculate the + * memory size from the SDRAM controller setup will have to + * get fixed. + */ + gd->ram_size -= CFG_MEM_TOP_HIDE; + #ifndef CONFIG_MAX_MEM_MAPPED #define CONFIG_MAX_MEM_MAPPED (256 << 20) #endif