[U-Boot] [PATCH v4 1/4] rtc: ds3232/ds3231: Add support to generate 32KHz output for driver module
This patch add an implementation of the rtc_enable_32khz_output() that uses the driver model i2c APIs.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- depends on: - http://patchwork.ozlabs.org/project/uboot/list/?series=118772 - http://patchwork.ozlabs.org/project/uboot/list/?series=117226
Changes in v4: - No change. Changes in v3: - Delete something about DS3231_BUS_NUM - Modify the interface and definition of rtc_enable_32khz_output function Changes in v2: - No change.
drivers/rtc/Kconfig | 6 ++++++ drivers/rtc/ds3231.c | 17 +++++++++++++++++ include/rtc.h | 6 ++++++ 3 files changed, 29 insertions(+)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index fd0009b..cf15914 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -31,6 +31,12 @@ config TPL_DM_RTC drivers to perform the actual functions. See rtc.h for a description of the API.
+config RTC_ENABLE_32KHZ_OUTPUT + bool "Enable RTC 32Khz output" + help + Some real-time clocks support the output of 32kHz square waves (such as ds3231), + the config symbol choose Real Time Clock device 32Khz output feature. + config RTC_PCF2127 bool "Enable PCF2127 driver" depends on DM_RTC diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index 79b026a..fde4d86 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -148,11 +148,13 @@ void rtc_reset (void) /* * Enable 32KHz output */ +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT void rtc_enable_32khz_output(void) { rtc_write(RTC_STAT_REG_ADDR, RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ); } +#endif
/* * Helper functions @@ -251,6 +253,21 @@ static int ds3231_probe(struct udevice *dev) return 0; }
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT +int rtc_enable_32khz_output(int busnum, int chip_addr) +{ + int ret; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(busnum, chip_addr, 1, &dev); + if (!ret) + ret = dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR, + RTC_STAT_BIT_BB32KHZ | + RTC_STAT_BIT_EN32KHZ); + return ret; +} +#endif + static const struct rtc_ops ds3231_rtc_ops = { .get = ds3231_rtc_get, .set = ds3231_rtc_set, diff --git a/include/rtc.h b/include/rtc.h index b255bdc..7386d52 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -166,11 +166,17 @@ int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep); */ int rtc_write32(struct udevice *dev, unsigned int reg, u32 value);
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT +int rtc_enable_32khz_output(int busnum, int chip_addr); +#endif + #else int rtc_get (struct rtc_time *); int rtc_set (struct rtc_time *); void rtc_reset (void); +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT void rtc_enable_32khz_output(void); +#endif
/** * rtc_read8() - Read an 8-bit register
This patch is updating ls2088aqds board init code to support DM_I2C.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- depends on: - http://patchwork.ozlabs.org/project/uboot/list/?series=118772 - http://patchwork.ozlabs.org/project/uboot/list/?series=117226
Changes in v4: - Simplify i2c_write related function calls and reduce the amount of code by using circular iteration - Place the variable definitions for udevice at the beginning of the function Changes in v3: - Delete something about DS3231_BUS_NUM - Modify the interface and definition of rtc_enable_32khz_output function Changes in v2: - No change.
board/freescale/ls2080aqds/eth.c | 151 ++++++++++++++++++++++---------- board/freescale/ls2080aqds/ls2080aqds.c | 16 ++++ include/configs/ls2080aqds.h | 3 + 3 files changed, 123 insertions(+), 47 deletions(-)
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index f706fd4..baf031a 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -89,11 +89,16 @@ struct ls2080a_qds_mdio { struct mii_dev *realbus; };
+struct reg_pair { + uint addr; + u8 *val; +}; + static void sgmii_configure_repeater(int serdes_port) { struct mii_dev *bus; uint8_t a = 0xf; - int i, j, ret; + int i, j, k, ret; int dpmac_id = 0, dpmac, mii_bus = 0; unsigned short value; char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"}; @@ -104,10 +109,30 @@ static void sgmii_configure_repeater(int serdes_port) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + int *riser_phy_addr = &xqsgii_riser_phy_addr[0]; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif
/* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error;
for (dpmac = 0; dpmac < 8; dpmac++) { /* Check the PHY status */ @@ -120,7 +145,15 @@ static void sgmii_configure_repeater(int serdes_port) mii_bus = 1; dpmac_id = dpmac + 9; a = 0xb; - i2c_write(0x76, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x76, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; break; }
@@ -153,29 +186,29 @@ static void sgmii_configure_repeater(int serdes_port)
for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_addr[dpmac], 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_addr[dpmac], 8, 1, &a, 1); - - i2c_write(i2c_addr[dpmac], 0xf, 1, - &ch_a_eq[i], 1); - i2c_write(i2c_addr[dpmac], 0x11, 1, - &ch_a_ctl2[j], 1); - - i2c_write(i2c_addr[dpmac], 0x16, 1, - &ch_b_eq[i], 1); - i2c_write(i2c_addr[dpmac], 0x18, 1, - &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_addr[dpmac], + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_addr[dpmac], + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], @@ -216,7 +249,7 @@ error: static void qsgmii_configure_repeater(int dpmac) { uint8_t a = 0xf; - int i, j; + int i, j, k; int i2c_phy_addr = 0; int phy_addr = 0; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -226,12 +259,32 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, ®_val[0]}, {4, ®_val[1]}, + {8, ®_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, ®_val[3]}, + {0x2d, ®_val[4]}, {4, ®_val[5]}, + }; + const char *dev = "LS2080A_QDS_MDIO0"; int ret = 0; unsigned short value; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif
/* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error;
switch (dpmac) { case 1: @@ -282,25 +335,29 @@ static void qsgmii_configure_repeater(int dpmac)
for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_phy_addr, + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index a0a3301..b3d120b 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -160,8 +160,16 @@ unsigned long get_board_ddr_clk(void) int select_i2c_ch_pca9547(u8 ch) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev;
+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); + +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -224,7 +232,15 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT +#ifdef CONFIG_DM_I2C + rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR); +#else rtc_enable_32khz_output(); +#endif +#endif + #ifdef CONFIG_FSL_CAAM sec_init(); #endif diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 18f30b5..05ff770 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -16,7 +16,9 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_FSL_QSPI #define CONFIG_QIXIS_I2C_ACCESS +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C_EARLY_INIT +#endif #define CONFIG_SYS_I2C_IFDR_DIV 0x7e #endif
@@ -324,6 +326,7 @@ unsigned long get_board_ddr_clk(void); */ #define RTC #define CONFIG_RTC_DS3231 1 +#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT #define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* EEPROM */
-----Original Message----- From: Chuanhua Han chuanhua.han@nxp.com Sent: Friday, July 26, 2019 4:54 PM To: albert.u.boot@aribaud.net; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Priyanka Jain priyanka.jain@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com Cc: u-boot@lists.denx.de; wd@denx.de; lukma@denx.de; trini@konsulko.com; Chuanhua Han chuanhua.han@nxp.com Subject: [PATCH v4 2/4] armv8: ls2088aqds: The ls2088aqds board supports the I2C driver model.
This patch is updating ls2088aqds board init code to support DM_I2C.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
This patch has been applied to fsl-qoriq master, awaiting upstream.
--pk
Dear Chuanhua Han,
In message 20190726112403.32842-2-chuanhua.han@nxp.com you wrote:
This patch is updating ls2088aqds board init code to support DM_I2C.
...
+struct reg_pair {
- uint addr;
- u8 *val;
+};
static void sgmii_configure_repeater(int serdes_port) { struct mii_dev *bus; uint8_t a = 0xf;
- int i, j, ret;
- int i, j, k, ret; int dpmac_id = 0, dpmac, mii_bus = 0; unsigned short value; char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
@@ -104,10 +109,30 @@ static void sgmii_configure_repeater(int serdes_port) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
- u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
- struct reg_pair reg_pair[10] = {
{6, ®_val[0]}, {4, ®_val[1]},{8, ®_val[2]}, {0xf, NULL},{0x11, NULL}, {0x16, NULL},{0x18, NULL}, {0x23, ®_val[3]},{0x2d, ®_val[4]}, {4, ®_val[5]},- };
Argh... this is pretty much unreadable. Why do you use a pointer for "val" in your struct reg_pair?
Would it not be much simpler to use something like this:
struct reg_pair { uint addr; u8 val; } ... struct reg_pair reg_pair[] = { {0x06, 0x18}, {0x04, 0x38}, {0x08, 0x04}, {0x0F, 0}, {0x11, 0}, {0x16, 0}, {0x18, 0}, {0x23, 0x14}, {0x2D, 0xB5}, {0x04, 0x20}, }} ?
Also, you should add some comments what all these magic numbers mean. As is, nobody is able to understand what you are doing here. This must be explained!
Also, a comment should be added that (and why) some of the values get inserted dynamically later down in the code.
Best regards,
Wolfgang Denk
++ Xiaowei Bao (he is taking over from Chuanhua)
-----Original Message----- From: Wolfgang Denk wd@denx.de Sent: Friday, August 23, 2019 3:05 PM To: Chuanhua Han chuanhua.han@nxp.com Cc: albert.u.boot@aribaud.net; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Priyanka Jain priyanka.jain@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com; u-boot@lists.denx.de; lukma@denx.de; trini@konsulko.com Subject: Re: [PATCH v4 2/4] armv8: ls2088aqds: The ls2088aqds board supports the I2C driver model.
Dear Chuanhua Han,
In message 20190726112403.32842-2-chuanhua.han@nxp.com you wrote:
This patch is updating ls2088aqds board init code to support DM_I2C.
...
+struct reg_pair {
- uint addr;
- u8 *val;
+};
static void sgmii_configure_repeater(int serdes_port) { struct mii_dev *bus; uint8_t a = 0xf;
- int i, j, ret;
- int i, j, k, ret; int dpmac_id = 0, dpmac, mii_bus = 0; unsigned short value; char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
@@
-104,10 +109,30 @@ static void sgmii_configure_repeater(int serdes_port) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
- u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
- struct reg_pair reg_pair[10] = {
{6, ®_val[0]}, {4, ®_val[1]},{8, ®_val[2]}, {0xf, NULL},{0x11, NULL}, {0x16, NULL},{0x18, NULL}, {0x23, ®_val[3]},{0x2d, ®_val[4]}, {4, ®_val[5]},- };
Argh... this is pretty much unreadable. Why do you use a pointer for "val" in your struct reg_pair?
Would it not be much simpler to use something like this:
struct reg_pair { uint addr; u8 val; } ... struct reg_pair reg_pair[] = { {0x06, 0x18}, {0x04, 0x38}, {0x08, 0x04}, {0x0F, 0}, {0x11, 0}, {0x16, 0}, {0x18, 0}, {0x23, 0x14}, {0x2D, 0xB5}, {0x04, 0x20}, }} ?
Also, you should add some comments what all these magic numbers mean. As is, nobody is able to understand what you are doing here. This must be explained!
Also, a comment should be added that (and why) some of the values get inserted dynamically later down in the code.
Dear Wolfgang,
Unfortunately this patch has been merged in main-line.
But I will ask (Xiaowei Bao) to send patch to fix it. I will make sure to get fix in RC3 or RC4.
--pk
This patch adds the ds3232-rtc node under the i2c0->i2c-mux@77->i2c@0 for ls2088aqds boards.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- depends on: - http://patchwork.ozlabs.org/project/uboot/list/?series=118772 - http://patchwork.ozlabs.org/project/uboot/list/?series=117226
Changes in v4: - No change. Changes in v3: - Change the order of the config and device tree patch files Changes in v2: - No change.
arch/arm/dts/fsl-ls2080a-qds.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index 2a0a528..13461b5 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -19,6 +19,25 @@ }; };
+&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + }; +}; + &dspi { bus-num = <0>; status = "okay";
-----Original Message----- From: Chuanhua Han chuanhua.han@nxp.com Sent: Friday, July 26, 2019 4:54 PM To: albert.u.boot@aribaud.net; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Priyanka Jain priyanka.jain@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com Cc: u-boot@lists.denx.de; wd@denx.de; lukma@denx.de; trini@konsulko.com; Chuanhua Han chuanhua.han@nxp.com Subject: [PATCH v4 3/4] armv8: ls2088aqds : Add ds3232 node
This patch adds the ds3232-rtc node under the i2c0->i2c-mux@77->i2c@0 for ls2088aqds boards.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
This patch has been applied to fsl-qoriq master, awaiting upstream.
--pk
Enable related configs on all ls2088aqds boards to support ds3231 rtc DM function.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- depends on: - http://patchwork.ozlabs.org/project/uboot/list/?series=118772 - http://patchwork.ozlabs.org/project/uboot/list/?series=117226
Changes in v4: - No change. Changes in v3: - Change the order of the config and device tree patch files Changes in v2: - No change.
configs/ls2088aqds_tfa_defconfig | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index e798c59..caa3425 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -1,12 +1,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_TFABOOT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -63,3 +63,10 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_DM_GPIO=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_DM_RTC=y
-----Original Message----- From: Chuanhua Han chuanhua.han@nxp.com Sent: Friday, July 26, 2019 4:54 PM To: albert.u.boot@aribaud.net; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Priyanka Jain priyanka.jain@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com Cc: u-boot@lists.denx.de; wd@denx.de; lukma@denx.de; trini@konsulko.com; Chuanhua Han chuanhua.han@nxp.com Subject: [PATCH v4 4/4] configs: ls2088aqds: Enable DM support for ds3231 rtc
Enable related configs on all ls2088aqds boards to support ds3231 rtc DM function.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
This patch has been applied to fsl-qoriq master, awaiting upstream.
--pk
-----Original Message----- From: Chuanhua Han chuanhua.han@nxp.com Sent: Friday, July 26, 2019 4:54 PM To: albert.u.boot@aribaud.net; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Priyanka Jain priyanka.jain@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com Cc: u-boot@lists.denx.de; wd@denx.de; lukma@denx.de; trini@konsulko.com; Chuanhua Han chuanhua.han@nxp.com Subject: [PATCH v4 1/4] rtc: ds3232/ds3231: Add support to generate 32KHz output for driver module
This patch add an implementation of the rtc_enable_32khz_output() that uses the driver model i2c APIs.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
This patch has been applied to fsl-qoriq master, awaiting upstream.
--pk
Dear Chuanhua Han,
In message 20190726112403.32842-1-chuanhua.han@nxp.com you wrote:
This patch add an implementation of the rtc_enable_32khz_output() that uses the driver model i2c APIs.
...
- ret = i2c_get_chip_for_busnum(busnum, chip_addr, 1, &dev);
- if (!ret)
ret = dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR,RTC_STAT_BIT_BB32KHZ |RTC_STAT_BIT_EN32KHZ);
Strictly speaking, this is a multi-line statement following the "if" so braces are required according to the coding style:
if (!ret) { ret = dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR, RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ); }
Best regards,
Wolfgang Denk
++ Xiaowei Bao (he is taking over from Chuanhua)
-----Original Message----- From: Wolfgang Denk wd@denx.de Sent: Friday, August 23, 2019 2:53 PM To: Chuanhua Han chuanhua.han@nxp.com Cc: albert.u.boot@aribaud.net; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Priyanka Jain priyanka.jain@nxp.com; Rajesh Bhagat rajesh.bhagat@nxp.com; u-boot@lists.denx.de; lukma@denx.de; trini@konsulko.com Subject: Re: [PATCH v4 1/4] rtc: ds3232/ds3231: Add support to generate 32KHz output for driver module
Dear Chuanhua Han,
In message 20190726112403.32842-1-chuanhua.han@nxp.com you wrote:
This patch add an implementation of the rtc_enable_32khz_output() that uses the driver model i2c APIs.
...
- ret = i2c_get_chip_for_busnum(busnum, chip_addr, 1, &dev);
- if (!ret)
ret = dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR,RTC_STAT_BIT_BB32KHZ |RTC_STAT_BIT_EN32KHZ);Strictly speaking, this is a multi-line statement following the "if" so braces are required according to the coding style:
if (!ret) { ret = dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR, RTC_STAT_BIT_BB32KHZ |) RTC_STAT_BIT_EN32KHZ); }
Dear Wolfgang,
Unfortunately this patch has been merged in main-line.
But I will ask (Xiaowei Bao) to send patch to fix it. I will make sure to get fix in RC3 or RC4.
--pk
participants (3)
-
Chuanhua Han -
Prabhakar Kushwaha -
Wolfgang Denk