Thanks for this

I checked and rechecked my sequence according to document and I do not see any problem. However, I changed PLPRCR to give me reset if I get checkstop, and that is what is happening i.e. I am getting checkstop exception. Any ideas what could be wrong?

Lokesh

-----Original Message----- From: Sam Song [mailto:samsongshu@yahoo.com.cn] Sent: Wednesday, June 30, 2004 10:22 AM To: Lokesh Kumar Cc: u-boot-users@lists.sourceforge.net Subject: RE: [U-Boot-Users] u-boot and 2.4.18 kernel problem

Lokesh Kumar wrote:

/* perform SDRAM initializsation sequence */

memctl->memc_mar = 0x00000088;

memctl->memc_mcr = 0x80002105; memctl->memc_mcr = 0x80002830; memctl->memc_mcr = 0x80002106;

It seems sth out of place here.But I am not quite sure.At least two cycles before refresh should be safer than one.You could refer to my poor work http://cvs.sourceforge.net/viewcvs.py/*checkout*/u-boot/u-boot/board/RPXlite _dw/RPXlite_dw.c?rev=1.1

udelay (1000);

size10 = dram_size (CFG_MAMR_10COL, (ulong > *)

SDRAM_BASE_PRELIM,

SDRAM_MAX_SIZE);

memctl->memc_mamr |= MAMR_PTAE; return (size10); }

I do not have the upm config tool from motorola to verify these settings. Has anybody used this chip with mpc855T and can help me figure this out?

I tested 2 MT48LC16M16A2-75 in 32-bit mode on 832e RPXlite_DW board.It worked fine.Next,I will also test 2 MT48LC8M16A2 on a 8xx custom board.So please let me know your advancement.I just had a look at the datasheet of MT48LC8M16A2 and MT48LC16M16A2.They have exactly the same timing waveform on initialization.

Hope this help!

Best regards,

Sam

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