[PATCH 00/12] clk: mediatek: add OPs to support OF_UPSTREAM
This series doesn't currently change anything and it does add all the additional OPs to make support of OF_UPSTREAM.
While converting the mt7681/7686/7688/7623/7622 it was notice lots of discrepancy between the downstream dtsi and the upstream one and the clock ID between downstream clock ID and upstream clock ID.
Upstream reference clock by names and clock are handled by the CCF (Common Clock Framework). The same can't be used here as we would quickly reach the max space allocated before relocation.
The current mediatek clock driver reference all the parents and clocks with offset from the clk ID related to the different tables.
Discrepancy between clock ID and the order in the clocks table cause one clock referenced for another or even crash for trying to access a clock at an offset that doesn't exist.
To handle this and permit use of OF_UPSTREAM, various measure and changes are done to the mediatek clock driver to support it.
This series have all the generic clock changes. Once this is merged, series for each SoC will came that will just change files in their dedicated clock driver. This is to prevent massive patch and to permit to split series, one for each SoC.
As said at the start, these changes doesn't cause regression and are just expansion to the current API. Current behaviour is saved in every possible way (aside from the first 2 patch that fixes latent bugs)
World compile tested in Azure Pipeline test
Christian Marangi (12): clk: mediatek: return XTAL rate directly for gates with XTAL parent clk: mediatek: return XTAL rate for infrasys get_mux_rate clk: mediatek: add support for gates in clk_tree for infrasys clk: mediatek: add support for gate ID at offset clk: mediatek: add support for parent mux from different source clk: mediatek: add support for parent mux from different source for topckgen clk: mediatek: add support for gate clock to reference topckgen clock clk: mediatek: provide common clk init function for infrasys clk: mediatek: add support for remapping clock ID clk: mediatek: implement MUX_FLAGS and MUX_MIXED_FLAGS macro clk: mediatek: add support for GATEs for APMIXED OPs clk: mediatek: add support for APMIXED parent in infra MUX
drivers/clk/mediatek/clk-mtk.c | 433 ++++++++++++++++++++++++--------- drivers/clk/mediatek/clk-mtk.h | 74 +++++- 2 files changed, 392 insertions(+), 115 deletions(-)
There is currently a massive bug that makes any gate clk that have CLK_XTAL as parent to return the wrong clock.
Following the code, with CLK_XTAL defined as TOPCKGEN parent, the topckgen get_rate is called. The clk ID (0) is parsed and only in some corner case (scenario where fixed clock are not defined) the correct XTAL rate will be returned as get_factor or get_mux is called (that have correct handling for CLK_XTAL). With fixed clock defined, the rate that will be returned will always be the FIRST ELEMENT of the fixed clock table instead of the hardcoded XTAL rate.
To handle this, add additional logic and if the flag is set to PARENT_XTAL for the gate, return the XTAL rate directly.
We assume the clk_tree to have xtal_rate defined with clk gates that have XTAL as parents.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d2c45be30de..e68beccc060 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -543,6 +543,13 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk) struct mtk_cg_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate = &priv->gates[clk->id];
+ /* + * Assume xtal_rate to be declared if some gates have + * XTAL as parent + */ + if (gate->flags & CLK_PARENT_XTAL) + return priv->tree->xtal_rate; + return mtk_clk_find_parent_rate(clk, gate->parent, priv->parent); }
We currently return 0 if XTAL rate is requested in get_mux_rate. This deviates from what is done in get_factor_rate and is totally wrong as it can cause unwanted results (division by 0 crash)
For infrasys that makes use of CLK_XTAL, assume xtal_rate to be defined in clk_tree and return the rate when BYPASS_XTAL is not enabled with clk ID 0 index parents.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index e68beccc060..555e2220748 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -376,7 +376,7 @@ static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off) break; } } - return 0; + return priv->tree->xtal_rate; }
static ulong mtk_topckgen_get_rate(struct clk *clk)
Add support for gates in clk_tree for infrasys ops.
Infracfg clks can have a sum of gates and muxes, and current solution handle this by duplicating the driver and split clks for mux and clks for gates. Upstream linux kernel handle this differently and doesn't have this distinction.
To be closer to the upstream kernel clock definition, implement additional logic to have gates defined in the clk_tree and implement variant for the infrasys ops to handle gates defined in the tree.
Similar to how it's done with factor and mux, we introduce gates_offs. Upstream kernel follow the similar logic with all the ID defined as FDIVS, MUXES and finally GATES.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 85 ++++++++++++++++++++++++++++------ drivers/clk/mediatek/clk-mtk.h | 2 + 2 files changed, 72 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 555e2220748..c3c50f4c14b 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -404,9 +404,26 @@ static ulong mtk_infrasys_get_rate(struct clk *clk) } else if (clk->id < priv->tree->muxes_offs) { rate = mtk_infrasys_get_factor_rate(clk, clk->id - priv->tree->fdivs_offs); - } else { + /* No gates defined or ID is a MUX */ + } else if (!priv->tree->gates || clk->id < priv->tree->gates_offs) { rate = mtk_infrasys_get_mux_rate(clk, clk->id - priv->tree->muxes_offs); + /* Only valid with muxes + gates implementation */ + } else { + struct udevice *parent = NULL; + const struct mtk_gate *gate; + + gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; + if (gate->flags & CLK_PARENT_TOPCKGEN) + parent = priv->parent; + /* + * Assume xtal_rate to be declared if some gates have + * XTAL as parent + */ + else if (gate->flags & CLK_PARENT_XTAL) + return priv->tree->xtal_rate; + + rate = mtk_clk_find_parent_rate(clk, gate->parent, parent); }
return rate; @@ -484,24 +501,22 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent)
/* CG functions */
-static int mtk_clk_gate_enable(struct clk *clk) +static int mtk_gate_enable(void __iomem *base, const struct mtk_gate *gate) { - struct mtk_cg_priv *priv = dev_get_priv(clk->dev); - const struct mtk_gate *gate = &priv->gates[clk->id]; u32 bit = BIT(gate->shift);
switch (gate->flags & CLK_GATE_MASK) { case CLK_GATE_SETCLR: - writel(bit, priv->base + gate->regs->clr_ofs); + writel(bit, base + gate->regs->clr_ofs); break; case CLK_GATE_SETCLR_INV: - writel(bit, priv->base + gate->regs->set_ofs); + writel(bit, base + gate->regs->set_ofs); break; case CLK_GATE_NO_SETCLR: - clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0); + clrsetbits_le32(base + gate->regs->sta_ofs, bit, 0); break; case CLK_GATE_NO_SETCLR_INV: - clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit); + clrsetbits_le32(base + gate->regs->sta_ofs, bit, bit); break;
default: @@ -511,24 +526,43 @@ static int mtk_clk_gate_enable(struct clk *clk) return 0; }
-static int mtk_clk_gate_disable(struct clk *clk) +static int mtk_clk_gate_enable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate = &priv->gates[clk->id]; + + return mtk_gate_enable(priv->base, gate); +} + +static int mtk_clk_infrasys_enable(struct clk *clk) +{ + struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + const struct mtk_gate *gate; + + /* MUX handling */ + if (!priv->tree->gates || clk->id < priv->tree->gates_offs) + return mtk_clk_mux_enable(clk); + + gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; + return mtk_gate_enable(priv->base, gate); +} + +static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate) +{ u32 bit = BIT(gate->shift);
switch (gate->flags & CLK_GATE_MASK) { case CLK_GATE_SETCLR: - writel(bit, priv->base + gate->regs->set_ofs); + writel(bit, base + gate->regs->set_ofs); break; case CLK_GATE_SETCLR_INV: - writel(bit, priv->base + gate->regs->clr_ofs); + writel(bit, base + gate->regs->clr_ofs); break; case CLK_GATE_NO_SETCLR: - clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit); + clrsetbits_le32(base + gate->regs->sta_ofs, bit, bit); break; case CLK_GATE_NO_SETCLR_INV: - clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0); + clrsetbits_le32(base + gate->regs->sta_ofs, bit, 0); break;
default: @@ -538,6 +572,27 @@ static int mtk_clk_gate_disable(struct clk *clk) return 0; }
+static int mtk_clk_gate_disable(struct clk *clk) +{ + struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + const struct mtk_gate *gate = &priv->gates[clk->id]; + + return mtk_gate_disable(priv->base, gate); +} + +static int mtk_clk_infrasys_disable(struct clk *clk) +{ + struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + const struct mtk_gate *gate; + + /* MUX handling */ + if (!priv->tree->gates || clk->id < priv->tree->gates_offs) + return mtk_clk_mux_disable(clk); + + gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; + return mtk_gate_disable(priv->base, gate); +} + static ulong mtk_clk_gate_get_rate(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); @@ -568,8 +623,8 @@ const struct clk_ops mtk_clk_topckgen_ops = { };
const struct clk_ops mtk_clk_infrasys_ops = { - .enable = mtk_clk_mux_enable, - .disable = mtk_clk_mux_disable, + .enable = mtk_clk_infrasys_enable, + .disable = mtk_clk_infrasys_disable, .get_rate = mtk_infrasys_get_rate, .set_parent = mtk_common_clk_set_parent, }; diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 48ce16484ec..8dde9e56e81 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -200,10 +200,12 @@ struct mtk_clk_tree { unsigned long xtal2_rate; const int fdivs_offs; const int muxes_offs; + const int gates_offs; const struct mtk_pll_data *plls; const struct mtk_fixed_clk *fclks; const struct mtk_fixed_factor *fdivs; const struct mtk_composite *muxes; + const struct mtk_gate *gates; u32 flags; };
Add support to clk_gate ops to reference the clk ID at an offset by using the just introduced gates_offs value from the unified muxes + gates implementation.
Gate clock that doesn't have gates_offs set won't be affected as the offset will simply be 0 and won't be offset of any value.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index c3c50f4c14b..79230fc26e0 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -529,8 +529,12 @@ static int mtk_gate_enable(void __iomem *base, const struct mtk_gate *gate) static int mtk_clk_gate_enable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); - const struct mtk_gate *gate = &priv->gates[clk->id]; + const struct mtk_gate *gate; + + if (clk->id < priv->tree->gates_offs) + return -EINVAL;
+ gate = &priv->gates[clk->id - priv->tree->gates_offs]; return mtk_gate_enable(priv->base, gate); }
@@ -575,8 +579,12 @@ static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate) static int mtk_clk_gate_disable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); - const struct mtk_gate *gate = &priv->gates[clk->id]; + const struct mtk_gate *gate;
+ if (clk->id < priv->tree->gates_offs) + return -EINVAL; + + gate = &priv->gates[clk->id - priv->tree->gates_offs]; return mtk_gate_disable(priv->base, gate); }
@@ -596,8 +604,12 @@ static int mtk_clk_infrasys_disable(struct clk *clk) static ulong mtk_clk_gate_get_rate(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); - const struct mtk_gate *gate = &priv->gates[clk->id]; + const struct mtk_gate *gate; + + if (clk->id < priv->tree->gates_offs) + return -EINVAL;
+ gate = &priv->gates[clk->id - priv->tree->gates_offs]; /* * Assume xtal_rate to be declared if some gates have * XTAL as parent
There is a current limitation where parents for a mux can be all declared as they are from a common source. This is not true as there are some MUX that can have parent from both infracfg or from topckgen.
To handle this, implement a new flag for the mux, CLK_PARENT_MIXED, and a new entry for the mux parent_flags.
To use this, CLK_PARENT_MIXED must be used and parent_flags will be used instead of the parent variable.
Entry in parent_flags are just a struct of ID and flags where it will be defined where that parent comes from with the usage of CLK_PARENT_INFRASYS or CLK_PARENT_TOPCKGEN.
This permits to have MUX with parents from infracfg or topckgen.
Notice that with CLK_PARENT_MIXED applied the CLK_BYPASS_XTAL is ignored. With CLK_PARENT_MIXED declare CLK_PARENT_XTAL for the relevant parent instead.
Also alias for the CLK_PARENT macro are provided to better clear their usage. CLK_PARENT_MIXED require these alias that describe the clk type to be defined in the clk_tree flags to prevent clk ID clash from different subsystem that may have equal clk ID.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 69 +++++++++++++++++++++++++--------- drivers/clk/mediatek/clk-mtk.h | 43 +++++++++++++++++++-- 2 files changed, 91 insertions(+), 21 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 79230fc26e0..4b8a904aa5e 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -54,13 +54,27 @@ static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, }
static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, + u32 parent_type, const struct mtk_composite *mux) { u32 val, index = 0;
- while (mux->parent[index] != parent) - if (++index == mux->num_parents) - return -EINVAL; + if (mux->flags & CLK_PARENT_MIXED) { + /* + * Assume parent_type in clk_tree to be always set with + * CLK_PARENT_MIXED implementation. If it's not, assume + * not parent clk ID clash is possible. + */ + while (mux->parent_flags[index].id != parent || + (parent_type && (mux->parent_flags[index].flags & CLK_PARENT_MASK) != + parent_type)) + if (++index == mux->num_parents) + return -EINVAL; + } else { + while (mux->parent[index] != parent) + if (++index == mux->num_parents) + return -EINVAL; + }
if (mux->flags & CLK_MUX_SETCLR_UPD) { val = (mux->mux_mask << mux->mux_shift); @@ -352,6 +366,19 @@ static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) return priv->tree->xtal_rate; }
+static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, + const int parent, u16 flags) +{ + switch (flags & CLK_PARENT_MASK) { + case CLK_PARENT_XTAL: + return priv->tree->xtal_rate; + case CLK_PARENT_TOPCKGEN: + return mtk_clk_find_parent_rate(clk, parent, priv->parent); + default: + return mtk_clk_find_parent_rate(clk, parent, NULL); + } +} + static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); @@ -362,21 +389,21 @@ static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off) index &= mux->mux_mask << mux->mux_shift; index = index >> mux->mux_shift;
- if (mux->parent[index] > 0 || - (mux->parent[index] == CLK_XTAL && - priv->tree->flags & CLK_BYPASS_XTAL)) { - switch (mux->flags & CLK_PARENT_MASK) { - case CLK_PARENT_TOPCKGEN: - return mtk_clk_find_parent_rate(clk, mux->parent[index], - priv->parent); - break; - default: - return mtk_clk_find_parent_rate(clk, mux->parent[index], - NULL); - break; - } + /* + * Parents can be either from TOPCKGEN or INFRACFG, + * inspect the mtk_parent struct to check the source + */ + if (mux->flags & CLK_PARENT_MIXED) { + const struct mtk_parent *parent = &mux->parent_flags[index]; + + return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); } - return priv->tree->xtal_rate; + + if (mux->parent[index] == CLK_XTAL && + !(priv->tree->flags & CLK_BYPASS_XTAL)) + return priv->tree->xtal_rate; + + return mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags); }
static ulong mtk_topckgen_get_rate(struct clk *clk) @@ -490,12 +517,18 @@ static int mtk_clk_mux_disable(struct clk *clk)
static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent) { + struct mtk_clk_priv *parent_priv = dev_get_priv(parent->dev); struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + u32 parent_type;
if (clk->id < priv->tree->muxes_offs) return 0;
- return mtk_clk_mux_set_parent(priv->base, parent->id, + if (!parent_priv) + return 0; + + parent_type = parent_priv->tree->flags & CLK_PARENT_MASK; + return mtk_clk_mux_set_parent(priv->base, parent->id, parent_type, &priv->tree->muxes[clk->id - priv->tree->muxes_offs]); }
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 8dde9e56e81..4423689803a 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -13,7 +13,11 @@
/* flags in struct mtk_clk_tree */
-/* clk id == 0 doesn't mean it's xtal clk */ +/* clk id == 0 doesn't mean it's xtal clk + * This doesn't apply when CLK_PARENT_MIXED is defined. + * With CLK_PARENT_MIXED declare CLK_PARENT_XTAL for the + * relevant parent. + */ #define CLK_BYPASS_XTAL BIT(0)
#define HAVE_RST_BAR BIT(0) @@ -30,7 +34,17 @@ #define CLK_PARENT_TOPCKGEN BIT(5) #define CLK_PARENT_INFRASYS BIT(6) #define CLK_PARENT_XTAL BIT(7) -#define CLK_PARENT_MASK GENMASK(7, 4) +/* + * For CLK_PARENT_MIXED to correctly work, is required to + * define in clk_tree flags the clk type using the alias. + */ +#define CLK_PARENT_MIXED BIT(8) +#define CLK_PARENT_MASK GENMASK(8, 4) + +/* alias to reference clk type */ +#define CLK_APMIXED CLK_PARENT_APMIXED +#define CLK_TOPCKGEN CLK_PARENT_TOPCKGEN +#define CLK_INFRASYS CLK_PARENT_INFRASYS
#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
@@ -97,11 +111,31 @@ struct mtk_fixed_factor { .flags = _flags, \ }
+/** + * struct mtk_parent - clock parent with flags. Needed for MUX that + * parent with mixed infracfg and topckgen. + * + * @id: index of parent clocks + * @flags: hardware-specific flags (parent location, + * infracfg, topckgen, APMIXED, xtal ...) + */ +struct mtk_parent { + const int id; + u16 flags; +}; + +#define PARENT(_id, _flags) { \ + .id = _id, \ + .flags = _flags, \ + } + /** * struct mtk_composite - aggregate clock of mux, divider and gate clocks * * @id: index of clocks * @parent: index of parnet clocks + * @parent: index of parnet clocks + * @parent_flags: table of parent clocks with flags * @mux_reg: hardware-specific mux register * @gate_reg: hardware-specific gate register * @mux_mask: mask to the mux bit field @@ -112,7 +146,10 @@ struct mtk_fixed_factor { */ struct mtk_composite { const int id; - const int *parent; + union { + const int *parent; + const struct mtk_parent *parent_flags; + }; u32 mux_reg; u32 mux_set_reg; u32 mux_clr_reg;
As done for infracfg, also add support for parent mux from different source for topckgen. This is needed as upstream linux doesn't use 1/1 factor and use directly the APMIXED clocks.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 42 ++++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 4b8a904aa5e..790b92eaf86 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -338,6 +338,19 @@ static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off) return mtk_factor_recalc_rate(fdiv, rate); }
+static ulong mtk_topckgen_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, + const int parent, u16 flags) +{ + switch (flags & CLK_PARENT_MASK) { + case CLK_PARENT_XTAL: + return priv->tree->xtal_rate; + case CLK_PARENT_APMIXED: + return mtk_clk_find_parent_rate(clk, parent, priv->parent); + default: + return mtk_clk_find_parent_rate(clk, parent, NULL); + } +} + static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); @@ -348,22 +361,23 @@ static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) index &= mux->mux_mask << mux->mux_shift; index = index >> mux->mux_shift;
- if (mux->parent[index] > 0 || - (mux->parent[index] == CLK_XTAL && - priv->tree->flags & CLK_BYPASS_XTAL)) { - switch (mux->flags & CLK_PARENT_MASK) { - case CLK_PARENT_APMIXED: - return mtk_clk_find_parent_rate(clk, mux->parent[index], - priv->parent); - break; - default: - return mtk_clk_find_parent_rate(clk, mux->parent[index], - NULL); - break; - } + /* + * Parents can be either from APMIXED or TOPCKGEN, + * inspect the mtk_parent struct to check the source + */ + if (mux->flags & CLK_PARENT_MIXED) { + const struct mtk_parent *parent = &mux->parent_flags[index]; + + return mtk_topckgen_find_parent_rate(priv, clk, parent->id, + parent->flags); }
- return priv->tree->xtal_rate; + if (mux->parent[index] == CLK_XTAL && + !(priv->tree->flags & CLK_BYPASS_XTAL)) + return priv->tree->xtal_rate; + + return mtk_topckgen_find_parent_rate(priv, clk, mux->parent[index], + mux->flags); }
static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk,
Add support for gate clock get_rate to reference topckgen clock for infracfg-ao implementation.
In infracfg-ao implementation topckgen is on second level of parent with infracfg in the middle. To correctly detect this, check the driver of the dev parent and use the second level parent if it's not mtk_clk_topckgen.
Due to all the dependency, parent tree must be filled before a gate is used, hence is safe to assume it will be there.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 790b92eaf86..4a057059407 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -651,20 +651,33 @@ static int mtk_clk_infrasys_disable(struct clk *clk) static ulong mtk_clk_gate_get_rate(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + struct udevice *parent = priv->parent; const struct mtk_gate *gate;
if (clk->id < priv->tree->gates_offs) return -EINVAL;
gate = &priv->gates[clk->id - priv->tree->gates_offs]; + /* + * With requesting a TOPCKGEN parent, make sure the dev parent + * is actually topckgen. This might not be the case for an + * infracfg-ao implementation where: + * parent = infracfg + * parent->parent = topckgen + */ + if (gate->flags & CLK_PARENT_TOPCKGEN && + parent->driver != DM_DRIVER_GET(mtk_clk_topckgen)) { + priv = dev_get_priv(parent); + parent = priv->parent; /* * Assume xtal_rate to be declared if some gates have * XTAL as parent */ - if (gate->flags & CLK_PARENT_XTAL) + } else if (gate->flags & CLK_PARENT_XTAL) { return priv->tree->xtal_rate; + }
- return mtk_clk_find_parent_rate(clk, gate->parent, priv->parent); + return mtk_clk_find_parent_rate(clk, gate->parent, parent); }
const struct clk_ops mtk_clk_apmixedsys_ops = {
Provide common clk init function for infrasys that defaults to topckgen driver if clock-parent is not defined. This is the case for upstream DTSI that doesn't provide this entry.
This is needed for infracfg driver that will make use of the unified gates + muxes implementation.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 22 ++++++++++++++++++---- drivers/clk/mediatek/clk-mtk.h | 2 ++ 2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 4a057059407..8a7a61d6740 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -707,8 +707,9 @@ const struct clk_ops mtk_clk_gate_ops = { .get_rate = mtk_clk_gate_get_rate, };
-int mtk_common_clk_init(struct udevice *dev, - const struct mtk_clk_tree *tree) +static int mtk_common_clk_init_drv(struct udevice *dev, + const struct mtk_clk_tree *tree, + const struct driver *drv) { struct mtk_clk_priv *priv = dev_get_priv(dev); struct udevice *parent; @@ -720,8 +721,7 @@ int mtk_common_clk_init(struct udevice *dev,
ret = uclass_get_device_by_phandle(UCLASS_CLK, dev, "clock-parent", &parent); if (ret || !parent) { - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(mtk_clk_apmixedsys), &parent); + ret = uclass_get_device_by_driver(UCLASS_CLK, drv, &parent); if (ret || !parent) return -ENOENT; } @@ -732,6 +732,20 @@ int mtk_common_clk_init(struct udevice *dev, return 0; }
+int mtk_common_clk_init(struct udevice *dev, + const struct mtk_clk_tree *tree) +{ + return mtk_common_clk_init_drv(dev, tree, + DM_DRIVER_GET(mtk_clk_apmixedsys)); +} + +int mtk_common_clk_infrasys_init(struct udevice *dev, + const struct mtk_clk_tree *tree) +{ + return mtk_common_clk_init_drv(dev, tree, + DM_DRIVER_GET(mtk_clk_topckgen)); +} + int mtk_common_clk_gate_init(struct udevice *dev, const struct mtk_clk_tree *tree, const struct mtk_gate *gates) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 4423689803a..e9c8a52ce8f 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -266,6 +266,8 @@ extern const struct clk_ops mtk_clk_gate_ops;
int mtk_common_clk_init(struct udevice *dev, const struct mtk_clk_tree *tree); +int mtk_common_clk_infrasys_init(struct udevice *dev, + const struct mtk_clk_tree *tree); int mtk_common_clk_gate_init(struct udevice *dev, const struct mtk_clk_tree *tree, const struct mtk_gate *gates);
Upstream kernel linux might have a different clock ID order in their <soc>-clk.h header. This is the case of some clock ID for mt7623 that upstream use the shared header clk-mt7601.h
This header doesn't have a well distincted order and have factor or mux in the middle of the CLK ID list. This is problematic with the mtk clock driver that expect everything well organized in block and apply offset to reference the clk in the different array.
To solve this problem, implement in the mtk_clk_tree an additional option .id_offs_map, an array where each CLK ID can be remapped to what the driver expect permitting to reorganize the clock following the expected logic of fixed, factor, mux and gates.
Each clock function is updated to tranparently handle this by first converting the clk ID to the remapped one.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 107 ++++++++++++++++++++++----------- drivers/clk/mediatek/clk-mtk.h | 8 +++ 2 files changed, 80 insertions(+), 35 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 8a7a61d6740..096f593fc5c 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -35,6 +35,18 @@
/* shared functions */
+static int mtk_clk_get_id(struct clk *clk) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + int id = clk->id; + + /* Remap the clk ID to the one expected by driver */ + if (priv->tree->id_offs_map) + id = priv->tree->id_offs_map[id]; + + return id; +} + /* * In case the rate change propagation to parent clocks is undesirable, * this function is recursively called to find the parent to calculate @@ -134,9 +146,12 @@ static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; + const struct mtk_pll_data *pll; + int id = mtk_clk_get_id(clk); u32 val, chg;
+ pll = &priv->tree->plls[id]; + /* set postdiv */ val = readl(priv->base + pll->pd_reg); val &= ~(POSTDIV_MASK << pll->pd_shift); @@ -176,12 +191,16 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, u32 freq) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; - unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ; + const struct mtk_pll_data *pll; + int id = mtk_clk_get_id(clk); + unsigned long fmin; u64 _pcw; int ibits; u32 val;
+ pll = &priv->tree->plls[id]; + fmin = pll->fmin ? pll->fmin : 1000 * MHZ; + if (freq > pll->fmax) freq = pll->fmax;
@@ -213,10 +232,13 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) static ulong mtk_apmixedsys_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; + const struct mtk_pll_data *pll; + int id = mtk_clk_get_id(clk); u32 postdiv; u32 pcw;
+ pll = &priv->tree->plls[id]; + postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) & POSTDIV_MASK; postdiv = 1 << postdiv; @@ -231,9 +253,12 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk) static int mtk_apmixedsys_enable(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; + const struct mtk_pll_data *pll; + int id = mtk_clk_get_id(clk); u32 r;
+ pll = &priv->tree->plls[id]; + r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON; writel(r, priv->base + pll->pwr_reg); udelay(1); @@ -260,9 +285,12 @@ static int mtk_apmixedsys_enable(struct clk *clk) static int mtk_apmixedsys_disable(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; + const struct mtk_pll_data *pll; + int id = mtk_clk_get_id(clk); u32 r;
+ pll = &priv->tree->plls[id]; + if (pll->flags & HAVE_RST_BAR) { r = readl(priv->base + pll->reg + REG_CON0); r &= ~pll->rst_bar_mask; @@ -423,38 +451,39 @@ static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off) static ulong mtk_topckgen_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + int id = mtk_clk_get_id(clk);
- if (clk->id < priv->tree->fdivs_offs) - return priv->tree->fclks[clk->id].rate; - else if (clk->id < priv->tree->muxes_offs) - return mtk_topckgen_get_factor_rate(clk, clk->id - + if (id < priv->tree->fdivs_offs) + return priv->tree->fclks[id].rate; + else if (id < priv->tree->muxes_offs) + return mtk_topckgen_get_factor_rate(clk, id - priv->tree->fdivs_offs); else - return mtk_topckgen_get_mux_rate(clk, clk->id - + return mtk_topckgen_get_mux_rate(clk, id - priv->tree->muxes_offs); }
static ulong mtk_infrasys_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - + int id = mtk_clk_get_id(clk); ulong rate;
- if (clk->id < priv->tree->fdivs_offs) { - rate = priv->tree->fclks[clk->id].rate; - } else if (clk->id < priv->tree->muxes_offs) { - rate = mtk_infrasys_get_factor_rate(clk, clk->id - + if (id < priv->tree->fdivs_offs) { + rate = priv->tree->fclks[id].rate; + } else if (id < priv->tree->muxes_offs) { + rate = mtk_infrasys_get_factor_rate(clk, id - priv->tree->fdivs_offs); /* No gates defined or ID is a MUX */ - } else if (!priv->tree->gates || clk->id < priv->tree->gates_offs) { - rate = mtk_infrasys_get_mux_rate(clk, clk->id - + } else if (!priv->tree->gates || id < priv->tree->gates_offs) { + rate = mtk_infrasys_get_mux_rate(clk, id - priv->tree->muxes_offs); /* Only valid with muxes + gates implementation */ } else { struct udevice *parent = NULL; const struct mtk_gate *gate;
- gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; + gate = &priv->tree->gates[id - priv->tree->gates_offs]; if (gate->flags & CLK_PARENT_TOPCKGEN) parent = priv->parent; /* @@ -474,12 +503,13 @@ static int mtk_clk_mux_enable(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux; + int id = mtk_clk_get_id(clk); u32 val;
- if (clk->id < priv->tree->muxes_offs) + if (id < priv->tree->muxes_offs) return 0;
- mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; + mux = &priv->tree->muxes[id - priv->tree->muxes_offs]; if (mux->gate_shift < 0) return 0;
@@ -507,12 +537,13 @@ static int mtk_clk_mux_disable(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux; + int id = mtk_clk_get_id(clk); u32 val;
- if (clk->id < priv->tree->muxes_offs) + if (id < priv->tree->muxes_offs) return 0;
- mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; + mux = &priv->tree->muxes[id - priv->tree->muxes_offs]; if (mux->gate_shift < 0) return 0;
@@ -533,9 +564,10 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent) { struct mtk_clk_priv *parent_priv = dev_get_priv(parent->dev); struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + int id = mtk_clk_get_id(clk); u32 parent_type;
- if (clk->id < priv->tree->muxes_offs) + if (id < priv->tree->muxes_offs) return 0;
if (!parent_priv) @@ -543,7 +575,7 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent)
parent_type = parent_priv->tree->flags & CLK_PARENT_MASK; return mtk_clk_mux_set_parent(priv->base, parent->id, parent_type, - &priv->tree->muxes[clk->id - priv->tree->muxes_offs]); + &priv->tree->muxes[id - priv->tree->muxes_offs]); }
/* CG functions */ @@ -576,25 +608,27 @@ static int mtk_gate_enable(void __iomem *base, const struct mtk_gate *gate) static int mtk_clk_gate_enable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + int id = mtk_clk_get_id(clk); const struct mtk_gate *gate;
- if (clk->id < priv->tree->gates_offs) + if (id < priv->tree->gates_offs) return -EINVAL;
- gate = &priv->gates[clk->id - priv->tree->gates_offs]; + gate = &priv->gates[id - priv->tree->gates_offs]; return mtk_gate_enable(priv->base, gate); }
static int mtk_clk_infrasys_enable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + int id = mtk_clk_get_id(clk); const struct mtk_gate *gate;
/* MUX handling */ - if (!priv->tree->gates || clk->id < priv->tree->gates_offs) + if (!priv->tree->gates || id < priv->tree->gates_offs) return mtk_clk_mux_enable(clk);
- gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; + gate = &priv->tree->gates[id - priv->tree->gates_offs]; return mtk_gate_enable(priv->base, gate); }
@@ -626,25 +660,27 @@ static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate) static int mtk_clk_gate_disable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + int id = mtk_clk_get_id(clk); const struct mtk_gate *gate;
- if (clk->id < priv->tree->gates_offs) + if (id < priv->tree->gates_offs) return -EINVAL;
- gate = &priv->gates[clk->id - priv->tree->gates_offs]; + gate = &priv->gates[id - priv->tree->gates_offs]; return mtk_gate_disable(priv->base, gate); }
static int mtk_clk_infrasys_disable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + int id = mtk_clk_get_id(clk); const struct mtk_gate *gate;
/* MUX handling */ - if (!priv->tree->gates || clk->id < priv->tree->gates_offs) + if (!priv->tree->gates || id < priv->tree->gates_offs) return mtk_clk_mux_disable(clk);
- gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; + gate = &priv->tree->gates[id - priv->tree->gates_offs]; return mtk_gate_disable(priv->base, gate); }
@@ -652,12 +688,13 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); struct udevice *parent = priv->parent; + int id = mtk_clk_get_id(clk); const struct mtk_gate *gate;
- if (clk->id < priv->tree->gates_offs) + if (id < priv->tree->gates_offs) return -EINVAL;
- gate = &priv->gates[clk->id - priv->tree->gates_offs]; + gate = &priv->gates[id - priv->tree->gates_offs]; /* * With requesting a TOPCKGEN parent, make sure the dev parent * is actually topckgen. This might not be the case for an diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index e9c8a52ce8f..c448ed024aa 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -235,6 +235,14 @@ struct mtk_gate { struct mtk_clk_tree { unsigned long xtal_rate; unsigned long xtal2_rate; + /* + * Clock ID offset are remapped with an auxiliary table. + * Enable this by defining .id_offs_map. + * This is needed for upstream linux kernel <soc>-clk.h that + * have mixed clk ID and doesn't have clear distinction between + * ID for factor, mux and gates. + */ + const int *id_offs_map; /* optional, table clk.h to driver ID */ const int fdivs_offs; const int muxes_offs; const int gates_offs;
Some simple MUX might require flags to specify the parent source. Implement MUX_FLAGS as a variant of the MUX macro that takes custom flags as last arg. Also implement MUX_MIXED_FLAGS for PARENT_MIXED implementation and MUX_MIXED with no additional flags.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index c448ed024aa..c1d9901c10b 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -179,7 +179,20 @@ struct mtk_composite { #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
-#define MUX(_id, _parents, _reg, _shift, _width) { \ +#define MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ + .id = _id, \ + .mux_reg = _reg, \ + .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, \ + .gate_shift = -1, \ + .parent_flags = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_PARENT_MIXED | (_flags), \ + } +#define MUX_MIXED(_id, _parents, _reg, _shift, _width) \ + MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, 0) + +#define MUX_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ .id = _id, \ .mux_reg = _reg, \ .mux_shift = _shift, \ @@ -187,8 +200,10 @@ struct mtk_composite { .gate_shift = -1, \ .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = 0, \ + .flags = _flags, \ } +#define MUX(_id, _parents, _reg, _shift, _width) \ + MUX_FLAGS(_id, _parents, _reg, _shift, _width, 0)
#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\ _mux_clr_ofs, _shift, _width, _gate, \
Add support for GATEs for APMIXED OPs. It's possible that some APMIXED have also gates on top of PLL. This is the case for mt7622. Add support for this.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 144 +++++++++++++++++++-------------- 1 file changed, 84 insertions(+), 60 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 096f593fc5c..c1d171624b9 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -47,6 +47,56 @@ static int mtk_clk_get_id(struct clk *clk) return id; }
+static int mtk_gate_enable(void __iomem *base, const struct mtk_gate *gate) +{ + u32 bit = BIT(gate->shift); + + switch (gate->flags & CLK_GATE_MASK) { + case CLK_GATE_SETCLR: + writel(bit, base + gate->regs->clr_ofs); + break; + case CLK_GATE_SETCLR_INV: + writel(bit, base + gate->regs->set_ofs); + break; + case CLK_GATE_NO_SETCLR: + clrsetbits_le32(base + gate->regs->sta_ofs, bit, 0); + break; + case CLK_GATE_NO_SETCLR_INV: + clrsetbits_le32(base + gate->regs->sta_ofs, bit, bit); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate) +{ + u32 bit = BIT(gate->shift); + + switch (gate->flags & CLK_GATE_MASK) { + case CLK_GATE_SETCLR: + writel(bit, base + gate->regs->set_ofs); + break; + case CLK_GATE_SETCLR_INV: + writel(bit, base + gate->regs->clr_ofs); + break; + case CLK_GATE_NO_SETCLR: + clrsetbits_le32(base + gate->regs->sta_ofs, bit, bit); + break; + case CLK_GATE_NO_SETCLR_INV: + clrsetbits_le32(base + gate->regs->sta_ofs, bit, 0); + break; + + default: + return -EINVAL; + } + + return 0; +} + /* * In case the rate change propagation to parent clocks is undesirable, * this function is recursively called to find the parent to calculate @@ -143,11 +193,10 @@ static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, * for the integer part and the remaining bits (if present) for the * fractional part. Also they have a 3 bit power-of-two post divider. */ -static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) +static void mtk_pll_set_rate_regs(struct mtk_clk_priv *priv, u32 id, + u32 pcw, int postdiv) { - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll; - int id = mtk_clk_get_id(clk); u32 val, chg;
pll = &priv->tree->plls[id]; @@ -182,17 +231,16 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv)
/** * mtk_pll_calc_values - calculate good values for a given input frequency. - * @clk: The clk + * @priv: The mtk priv struct + * @id: The clk id * @pcw: The pcw value (output) * @postdiv: The post divider (output) * @freq: The desired target frequency */ -static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, - u32 freq) +static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id, + u32 *pcw, u32 *postdiv, u32 freq) { - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll; - int id = mtk_clk_get_id(clk); unsigned long fmin; u64 _pcw; int ibits; @@ -220,11 +268,16 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv,
static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) { + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + int id = mtk_clk_get_id(clk); u32 pcw = 0; u32 postdiv;
- mtk_pll_calc_values(clk, &pcw, &postdiv, rate); - mtk_pll_set_rate_regs(clk, pcw, postdiv); + if (priv->tree->gates && id >= priv->tree->gates_offs) + return -EINVAL; + + mtk_pll_calc_values(priv, id, &pcw, &postdiv, rate); + mtk_pll_set_rate_regs(priv, id, pcw, postdiv);
return 0; } @@ -234,9 +287,16 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll; int id = mtk_clk_get_id(clk); + const struct mtk_gate *gate; u32 postdiv; u32 pcw;
+ /* GATE handling */ + if (priv->tree->gates && id >= priv->tree->gates_offs) { + gate = &priv->tree->gates[id - priv->tree->gates_offs]; + return mtk_clk_find_parent_rate(clk, gate->parent, NULL); + } + pll = &priv->tree->plls[id];
postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) & @@ -255,8 +315,15 @@ static int mtk_apmixedsys_enable(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll; int id = mtk_clk_get_id(clk); + const struct mtk_gate *gate; u32 r;
+ /* GATE handling */ + if (priv->tree->gates && id >= priv->tree->gates_offs) { + gate = &priv->tree->gates[id - priv->tree->gates_offs]; + return mtk_gate_enable(priv->base, gate); + } + pll = &priv->tree->plls[id];
r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON; @@ -287,8 +354,15 @@ static int mtk_apmixedsys_disable(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll; int id = mtk_clk_get_id(clk); + const struct mtk_gate *gate; u32 r;
+ /* GATE handling */ + if (priv->tree->gates && id >= priv->tree->gates_offs) { + gate = &priv->tree->gates[id - priv->tree->gates_offs]; + return mtk_gate_disable(priv->base, gate); + } + pll = &priv->tree->plls[id];
if (pll->flags & HAVE_RST_BAR) { @@ -580,31 +654,6 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent)
/* CG functions */
-static int mtk_gate_enable(void __iomem *base, const struct mtk_gate *gate) -{ - u32 bit = BIT(gate->shift); - - switch (gate->flags & CLK_GATE_MASK) { - case CLK_GATE_SETCLR: - writel(bit, base + gate->regs->clr_ofs); - break; - case CLK_GATE_SETCLR_INV: - writel(bit, base + gate->regs->set_ofs); - break; - case CLK_GATE_NO_SETCLR: - clrsetbits_le32(base + gate->regs->sta_ofs, bit, 0); - break; - case CLK_GATE_NO_SETCLR_INV: - clrsetbits_le32(base + gate->regs->sta_ofs, bit, bit); - break; - - default: - return -EINVAL; - } - - return 0; -} - static int mtk_clk_gate_enable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); @@ -632,31 +681,6 @@ static int mtk_clk_infrasys_enable(struct clk *clk) return mtk_gate_enable(priv->base, gate); }
-static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate) -{ - u32 bit = BIT(gate->shift); - - switch (gate->flags & CLK_GATE_MASK) { - case CLK_GATE_SETCLR: - writel(bit, base + gate->regs->set_ofs); - break; - case CLK_GATE_SETCLR_INV: - writel(bit, base + gate->regs->clr_ofs); - break; - case CLK_GATE_NO_SETCLR: - clrsetbits_le32(base + gate->regs->sta_ofs, bit, bit); - break; - case CLK_GATE_NO_SETCLR_INV: - clrsetbits_le32(base + gate->regs->sta_ofs, bit, 0); - break; - - default: - return -EINVAL; - } - - return 0; -} - static int mtk_clk_gate_disable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
Add support for APMIXED parent in infra MUX. This is the case for mt7622 that reference APMIXED parents for the MUX1_SEL clock.
We assume the second level parent is always APMIXED.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index c1d171624b9..66683aeb2d7 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -488,6 +488,10 @@ static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, switch (flags & CLK_PARENT_MASK) { case CLK_PARENT_XTAL: return priv->tree->xtal_rate; + /* Assume the second level parent is always APMIXED */ + case CLK_PARENT_APMIXED: + priv = dev_get_priv(priv->parent); + fallthrough; case CLK_PARENT_TOPCKGEN: return mtk_clk_find_parent_rate(clk, parent, priv->parent); default:
On Fri, Jun 28, 2024 at 07:40:45PM +0200, Christian Marangi wrote:
This series doesn't currently change anything and it does add all the additional OPs to make support of OF_UPSTREAM.
While converting the mt7681/7686/7688/7623/7622 it was notice lots of discrepancy between the downstream dtsi and the upstream one and the clock ID between downstream clock ID and upstream clock ID.
Upstream reference clock by names and clock are handled by the CCF (Common Clock Framework). The same can't be used here as we would quickly reach the max space allocated before relocation.
The current mediatek clock driver reference all the parents and clocks with offset from the clk ID related to the different tables.
Discrepancy between clock ID and the order in the clocks table cause one clock referenced for another or even crash for trying to access a clock at an offset that doesn't exist.
To handle this and permit use of OF_UPSTREAM, various measure and changes are done to the mediatek clock driver to support it.
This series have all the generic clock changes. Once this is merged, series for each SoC will came that will just change files in their dedicated clock driver. This is to prevent massive patch and to permit to split series, one for each SoC.
As said at the start, these changes doesn't cause regression and are just expansion to the current API. Current behaviour is saved in every possible way (aside from the first 2 patch that fixes latent bugs)
World compile tested in Azure Pipeline test
Christian Marangi (12): clk: mediatek: return XTAL rate directly for gates with XTAL parent clk: mediatek: return XTAL rate for infrasys get_mux_rate clk: mediatek: add support for gates in clk_tree for infrasys clk: mediatek: add support for gate ID at offset clk: mediatek: add support for parent mux from different source clk: mediatek: add support for parent mux from different source for topckgen clk: mediatek: add support for gate clock to reference topckgen clock clk: mediatek: provide common clk init function for infrasys clk: mediatek: add support for remapping clock ID clk: mediatek: implement MUX_FLAGS and MUX_MIXED_FLAGS macro clk: mediatek: add support for GATEs for APMIXED OPs clk: mediatek: add support for APMIXED parent in infra MUX
drivers/clk/mediatek/clk-mtk.c | 433 ++++++++++++++++++++++++--------- drivers/clk/mediatek/clk-mtk.h | 74 +++++- 2 files changed, 392 insertions(+), 115 deletions(-)
Any news for this? Notice the driver changes got merged. This is currently blocking 4 more series to convert all the mediatek soc to of upstream.
On Fri, 28 Jun 2024 19:40:45 +0200, Christian Marangi wrote:
This series doesn't currently change anything and it does add all the additional OPs to make support of OF_UPSTREAM.
While converting the mt7681/7686/7688/7623/7622 it was notice lots of discrepancy between the downstream dtsi and the upstream one and the clock ID between downstream clock ID and upstream clock ID.
[...]
Applied to u-boot/master, thanks!
participants (2)
-
Christian Marangi -
Tom Rini