1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case and check the min tRTP. 3. wr_to_rd add the check the min requirement for tWTR.

Reported-by: Joakim Tjernlund Joakim.Tjernlund@transmode.se Signed-off-by: Dave Liu daveliu@freescale.com --- cpu/mpc8xxx/ddr/ctrl_regs.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 292980d..5c3e383 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -253,6 +253,10 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps); acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps); wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps); +#if defined(CONFIG_FSL_DDR2) + if (wrtord_mclk < 2) + wrtord_mclk = 2; +#endif

ddr->timing_cfg_1 = (0 | ((pretoact_mclk & 0x0F) << 28) @@ -302,12 +306,17 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, */ wr_lat = 0; #elif defined(CONFIG_FSL_DDR2) - wr_lat = cas_latency + additive_latency - 1; + wr_lat = cas_latency - 1; #else #error "Fix WR_LAT for DDR3" #endif

rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps); +#if defined(CONFIG_FSL_DDR2) + if (rd_to_pre < 2) + rd_to_pre = 2; + rd_to_pre += additive_latency; +#endif wr_data_delay = popts->write_data_delay; cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps); four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);