[U-Boot] [PATCH v1 0/4] sf: add ADDR_4B for 4byte address support
From: Yuan Yao yao.yuan@nxp.com
Some new flash don't support bar but use 4bytes address to direct support exceed 16MB flash size. So add flash flag: ADDR_4B for some flash which support 4bytes address.
Yuan Yao (4): sf: add ADDR_4B for 4byte address support spi: fsl_qspi: Add 4bytes address support armv8: ls1012a: update the flash size to 64M. armv8: ls1046a: update the flash size to 64M.
drivers/mtd/spi/sf_internal.h | 4 +++- drivers/mtd/spi/sf_params.c | 2 +- drivers/mtd/spi/spi_flash.c | 38 +++++++++++++++++++++++++------------- drivers/spi/fsl_qspi.c | 8 ++++++-- include/configs/ls1012a_common.h | 3 +-- include/configs/ls1046ardb.h | 3 +-- include/spi_flash.h | 1 + 7 files changed, 38 insertions(+), 21 deletions(-)
From: Yuan Yao yao.yuan@nxp.com
Some new flash don't support bar register but use 4bytes address to support exceed 16MB flash size. So add flash flag: ADDR_4B for some flash which support 4bytes address.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- drivers/mtd/spi/sf_internal.h | 4 +++- drivers/mtd/spi/sf_params.c | 2 +- drivers/mtd/spi/spi_flash.c | 38 +++++++++++++++++++++++++------------- include/spi_flash.h | 1 + 4 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index cde4cfb..9ae1549 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -26,7 +26,8 @@ enum spi_nor_option_flags { };
#define SPI_FLASH_3B_ADDR_LEN 3 -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) +#define SPI_FLASH_4B_ADDR_LEN 4 +#define SPI_FLASH_CMD_MAX_LEN (1 + SPI_FLASH_4B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000
/* CFI Manufacture ID's */ @@ -130,6 +131,7 @@ struct spi_flash_params { #define RD_DUAL BIT(5) #define RD_QUADIO BIT(6) #define RD_DUALIO BIT(7) +#define ADDR_4B BIT(8) #define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO) };
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 5b50114..9c26cc8 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -68,7 +68,7 @@ const struct spi_flash_params spi_flash_params_table[] = { {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP}, {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP}, {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP}, - {"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL | WR_QPP}, + {"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL | WR_QPP | ADDR_4B}, {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP}, {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP}, {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP}, diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 7f6e9ae..487488f 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -22,12 +22,15 @@
DECLARE_GLOBAL_DATA_PTR;
-static void spi_flash_addr(u32 addr, u8 *cmd) +static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd) { /* cmd[0] is actual command */ - cmd[1] = addr >> 16; - cmd[2] = addr >> 8; - cmd[3] = addr >> 0; + int i; + + for (i = flash->cmd_len - 1; i > 0; i--) { + cmd[i] = addr; + addr = addr >> 8; + } }
static int read_sr(struct spi_flash *flash, u8 *rs) @@ -327,7 +330,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { u32 erase_size, erase_addr; - u8 cmd[SPI_FLASH_CMD_LEN]; + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; int ret = -1;
erase_size = flash->erase_size; @@ -357,7 +360,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) if (ret < 0) return ret; #endif - spi_flash_addr(erase_addr, cmd); + spi_flash_addr(flash, erase_addr, cmd);
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], erase_addr); @@ -382,7 +385,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, unsigned long byte_addr, page_size; u32 write_addr; size_t chunk_len, actual; - u8 cmd[SPI_FLASH_CMD_LEN]; + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; int ret = -1;
page_size = flash->page_size; @@ -415,7 +418,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, chunk_len = min(chunk_len, (size_t)spi->max_write_size);
- spi_flash_addr(write_addr, cmd); + spi_flash_addr(flash, write_addr, cmd);
debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); @@ -492,7 +495,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return 0; }
- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; + cmdsz = flash->cmd_len + flash->dummy_byte; cmd = calloc(1, cmdsz); if (!cmd) { debug("SF: Failed to allocate cmd\n"); @@ -513,14 +516,18 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return ret; bank_sel = flash->bank_curr; #endif - remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * - (bank_sel + 1)) - offset; + if (flash->cmd_len == 1 + SPI_FLASH_4B_ADDR_LEN) + remain_len = flash->size - offset; + else + remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * + (bank_sel + 1)) - offset; + if (len < remain_len) read_len = len; else read_len = remain_len;
- spi_flash_addr(read_addr, cmd); + spi_flash_addr(flash, read_addr, cmd);
ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); if (ret < 0) { @@ -974,7 +981,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) #ifdef CONFIG_SPI_FLASH_SPANSION static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi) { - u8 cmd[4]; + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; u32 offset = 0x800004; /* CR3V register offset */ u8 cr3v; int ret; @@ -1246,6 +1253,10 @@ int spi_flash_scan(struct spi_flash *flash) puts("\n"); #endif
+ if (params->flags & ADDR_4B) { + flash->cmd_len = 1 + SPI_FLASH_4B_ADDR_LEN; + } else { + flash->cmd_len = 1 + SPI_FLASH_3B_ADDR_LEN; #ifndef CONFIG_SPI_FLASH_BAR if (((flash->dual_flash == SF_SINGLE_FLASH) && (flash->size > SPI_FLASH_16MB_BOUN)) || @@ -1255,6 +1266,7 @@ int spi_flash_scan(struct spi_flash *flash) puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); } #endif + }
return ret; } diff --git a/include/spi_flash.h b/include/spi_flash.h index d0ce9e7..56b3252 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -83,6 +83,7 @@ struct spi_flash { u8 read_cmd; u8 write_cmd; u8 dummy_byte; + u8 cmd_len;
void *memory_map;
On 09/28/2016 04:21 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
Some new flash don't support bar register but use 4bytes address to support exceed 16MB flash size. So add flash flag: ADDR_4B for some flash which support 4bytes address.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
drivers/mtd/spi/sf_internal.h | 4 +++- drivers/mtd/spi/sf_params.c | 2 +- drivers/mtd/spi/spi_flash.c | 38 +++++++++++++++++++++++++------------- include/spi_flash.h | 1 + 4 files changed, 30 insertions(+), 15 deletions(-)
Jagan,
Please review and give your comment. Thanks.
York
On 09/28/2016 06:21 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
Some new flash don't support bar register but use 4bytes address to support exceed 16MB flash size. So add flash flag: ADDR_4B for some flash which support 4bytes address.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
Jagan,
Your comment, please?
York
On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao yao.yuan@freescale.com wrote:
From: Yuan Yao yao.yuan@nxp.com
Some new flash don't support bar register but use 4bytes address to support exceed 16MB flash size. So add flash flag: ADDR_4B for some flash which support 4bytes address.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
drivers/mtd/spi/sf_internal.h | 4 +++- drivers/mtd/spi/sf_params.c | 2 +- drivers/mtd/spi/spi_flash.c | 38 +++++++++++++++++++++++++------------- include/spi_flash.h | 1 + 4 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index cde4cfb..9ae1549 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -26,7 +26,8 @@ enum spi_nor_option_flags { };
#define SPI_FLASH_3B_ADDR_LEN 3 -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) +#define SPI_FLASH_4B_ADDR_LEN 4 +#define SPI_FLASH_CMD_MAX_LEN (1 + SPI_FLASH_4B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000
/* CFI Manufacture ID's */ @@ -130,6 +131,7 @@ struct spi_flash_params { #define RD_DUAL BIT(5) #define RD_QUADIO BIT(6) #define RD_DUALIO BIT(7) +#define ADDR_4B BIT(8) #define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO) };
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 5b50114..9c26cc8 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -68,7 +68,7 @@ const struct spi_flash_params spi_flash_params_table[] = { {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP}, {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP}, {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP},
{"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL | WR_QPP},
{"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL | WR_QPP | ADDR_4B},
Sorry for the late, It's better to not relay on specific flash and do the 4-byte addressing. So, I've sent some patches based on this [1] and will send the next version to wind-up all these changes. Please wait some time.
thanks!
On Wed, Oct 26, 2016 at 3:39 PM, Jagan Teki wrote:
On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao yao.yuan@freescale.com wrote:
From: Yuan Yao yao.yuan@nxp.com
Some new flash don't support bar register but use 4bytes address to support exceed 16MB flash size. So add flash flag: ADDR_4B for some flash which support 4bytes address.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
drivers/mtd/spi/sf_internal.h | 4 +++- drivers/mtd/spi/sf_params.c | 2 +- drivers/mtd/spi/spi_flash.c | 38 +++++++++++++++++++++++++------------- include/spi_flash.h | 1 + 4 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index cde4cfb..9ae1549 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -26,7 +26,8 @@ enum spi_nor_option_flags { };
#define SPI_FLASH_3B_ADDR_LEN 3 -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) +#define SPI_FLASH_4B_ADDR_LEN 4 +#define SPI_FLASH_CMD_MAX_LEN (1 + SPI_FLASH_4B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000
/* CFI Manufacture ID's */ @@ -130,6 +131,7 @@ struct spi_flash_params { #define RD_DUAL BIT(5) #define RD_QUADIO BIT(6) #define RD_DUALIO BIT(7) +#define ADDR_4B BIT(8) #define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO |
RD_DUALIO)
};
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 5b50114..9c26cc8 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -68,7 +68,7 @@ const struct spi_flash_params spi_flash_params_table[]
= {
{"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL |WR_QPP},
{"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL |WR_QPP},
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL |WR_QPP},
{"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL |WR_QPP},
{"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL |WR_QPP | ADDR_4B},
Sorry for the late, It's better to not relay on specific flash and do the 4-byte addressing. So, I've sent some patches based on this [1] and will send the next version to wind-up all these changes. Please wait some time.
Ok, hope for it. We need change a lot and prepare for embrace more. BTW, I'm working on a QSPI NAND flash support, a lot of the differences with NOR flash.
Do you think is it better to have a drivers/mtd/spi/spi_nand_flash.c ?
On Wed, Oct 26, 2016 at 4:39 PM, Jagan Teki wrote:
On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao yao.yuan@freescale.com wrote:
From: Yuan Yao yao.yuan@nxp.com
Some new flash don't support bar register but use 4bytes address to support exceed 16MB flash size. So add flash flag: ADDR_4B for some flash which support 4bytes address.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
drivers/mtd/spi/sf_internal.h | 4 +++- drivers/mtd/spi/sf_params.c | 2 +- drivers/mtd/spi/spi_flash.c | 38 +++++++++++++++++++++++++------------- include/spi_flash.h | 1 + 4 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index cde4cfb..9ae1549 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -26,7 +26,8 @@ enum spi_nor_option_flags { };
#define SPI_FLASH_3B_ADDR_LEN 3 -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) +#define SPI_FLASH_4B_ADDR_LEN 4 +#define SPI_FLASH_CMD_MAX_LEN (1 + SPI_FLASH_4B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000
/* CFI Manufacture ID's */ @@ -130,6 +131,7 @@ struct spi_flash_params { #define RD_DUAL BIT(5) #define RD_QUADIO BIT(6) #define RD_DUALIO BIT(7) +#define ADDR_4B BIT(8) #define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO |
RD_DUALIO)
};
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 5b50114..9c26cc8 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -68,7 +68,7 @@ const struct spi_flash_params spi_flash_params_table[]
= {
{"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL |WR_QPP},
{"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL |WR_QPP},
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL |WR_QPP},
{"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL |WR_QPP},
{"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL |WR_QPP | ADDR_4B},
Sorry for the late, It's better to not relay on specific flash and do the 4-byte addressing. So, I've sent some patches based on this [1] and will send the next version to wind-up all these changes. Please wait some time.
Hi Jagan,
May I know is there any update for those 4-bytes addressing support in uboot? If your patch is ready, Can I get the patch set and then working for my QSPI 64M flash support?
I think it will be very helpful. The 64MB flash support for our QSPI is very needed.
Thanks.
Yao.
Hello Jagan,
[snip]
Sorry for the late, It's better to not relay on specific flash and do the 4-byte addressing. So, I've sent some patches based on this [1] and will send the next version to wind-up all these changes. Please wait some
time.
Any update on supporting 4-byte addressing for flash with size of 16M+
Hi Jagan,
May I know is there any update for those 4-bytes addressing support in uboot? If your patch is ready, Can I get the patch set and then working for my QSPI 64M flash support?
I think it will be very helpful. The 64MB flash support for our QSPI is very needed.
Thanks.
Yao.
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
From: Yuan Yao yao.yuan@nxp.com
The QSPI support the direct 4bytes address command for flash read/write/erase. And the address can cover the whole QSPI memory space.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- drivers/spi/fsl_qspi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 2144fca..119b782 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUFFER_SIZE 0x40 #endif
-#define OFFSET_BITS_MASK GENMASK(23, 0) +#define OFFSET_BITS_MASK ((FSL_QSPI_FLASH_SIZE > SZ_16M) ? \ + GENMASK(27, 0) : GENMASK(23, 0))
#define FLASH_STATUS_WEL 0x02
@@ -760,7 +761,10 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, if (dout) { if (flags & SPI_XFER_BEGIN) { priv->cur_seqid = *(u8 *)dout; - memcpy(&txbuf, dout, 4); + if (FSL_QSPI_FLASH_SIZE > SZ_16M) + memcpy(&txbuf, dout + 1, 4); + else + memcpy(&txbuf, dout, 4); }
if (flags == SPI_XFER_END) {
On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao yao.yuan@freescale.com wrote:
From: Yuan Yao yao.yuan@nxp.com
The QSPI support the direct 4bytes address command for flash read/write/erase. And the address can cover the whole QSPI memory space.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
drivers/spi/fsl_qspi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 2144fca..119b782 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUFFER_SIZE 0x40 #endif
-#define OFFSET_BITS_MASK GENMASK(23, 0) +#define OFFSET_BITS_MASK ((FSL_QSPI_FLASH_SIZE > SZ_16M) ? \
GENMASK(27, 0) : GENMASK(23, 0))#define FLASH_STATUS_WEL 0x02
@@ -760,7 +761,10 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, if (dout) { if (flags & SPI_XFER_BEGIN) { priv->cur_seqid = *(u8 *)dout;
memcpy(&txbuf, dout, 4);
if (FSL_QSPI_FLASH_SIZE > SZ_16M)memcpy(&txbuf, dout + 1, 4);elsememcpy(&txbuf, dout, 4);
This driver has lot of flash hacks, and I am completely unhappy about this please try to write new driver on flash side (mtd/spi).
thanks!
On Wed, Oct 26, 2016 at 3:39 PM, Jagan Teki wrote:
On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao yao.yuan@freescale.com wrote:
From: Yuan Yao yao.yuan@nxp.com
The QSPI support the direct 4bytes address command for flash read/write/erase. And the address can cover the whole QSPI memory space.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
drivers/spi/fsl_qspi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 2144fca..119b782 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUFFER_SIZE 0x40 #endif
-#define OFFSET_BITS_MASK GENMASK(23, 0) +#define OFFSET_BITS_MASK ((FSL_QSPI_FLASH_SIZE > SZ_16M) ? \
GENMASK(27, 0) : GENMASK(23,+0))
#define FLASH_STATUS_WEL 0x02
@@ -760,7 +761,10 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int
bitlen,
if (dout) { if (flags & SPI_XFER_BEGIN) { priv->cur_seqid = *(u8 *)dout;
memcpy(&txbuf, dout, 4);
if (FSL_QSPI_FLASH_SIZE > SZ_16M)memcpy(&txbuf, dout + 1, 4);elsememcpy(&txbuf, dout, 4);This driver has lot of flash hacks, and I am completely unhappy about this please try to write new driver on flash side (mtd/spi).
Hi Jagan,
Yes, I think so, I also think I need rewrite this driver now. In fact, I'm working on this. But need more time, So I have to send those patch set to support 16M+ support.
Thanks for your support.
From: Yuan Yao yao.yuan@nxp.com
The QSPI flash on LS1012A is 64MB, and don't support BAR.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- include/configs/ls1012a_common.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 5fb6c47..4a900bf 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -60,9 +60,8 @@ #define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_BAR
-#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_SIZE SZ_64M #define FSL_QSPI_FLASH_NUM 2
/*
From: Yuan Yao yao.yuan@nxp.com
The QSPI flash on LS1046A is 64MB, and don't support BAR.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- include/configs/ls1046ardb.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 693cc8d..3322953 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -209,9 +209,8 @@ /* QSPI device */ #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION -#define FSL_QSPI_FLASH_SIZE (1 << 26) +#define FSL_QSPI_FLASH_SIZE SZ_64M #define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SPI_FLASH_BAR #endif
/* SATA */
participants (5)
-
Jagan Teki -
Suresh Gupta -
Yao Yuan -
york sun -
Yuan Yao