This patch adds codes to enable FIFO and disable flow control taken from ns16550 driver.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/serial/serial_mtk.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)

diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index bce1be8227..11892a8740 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -46,6 +46,22 @@ struct mtk_serial_regs {

#define UART_LSR_DR 0x01 /* Data ready */ #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ + +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ + +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define UART_MCRVAL (UART_MCR_DTR | \ + UART_MCR_RTS) + +/* Clear & enable FIFOs */ +#define UART_FCRVAL (UART_FCR_FIFO_EN | \ + UART_FCR_RXSR | \ + UART_FCR_TXSR)

/* the data is correct if the real baud is within 3%. */ #define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100) @@ -175,6 +191,9 @@ static int mtk_serial_probe(struct udevice *dev) /* Disable interrupt */ writel(0, &priv->regs->ier);

+ writel(UART_MCRVAL, &priv->regs->mcr); + writel(UART_FCRVAL, &priv->regs->fcr); + return 0; }

@@ -248,6 +267,8 @@ static inline void _debug_uart_init(void) priv.clock = CONFIG_DEBUG_UART_CLOCK;

writel(0, &priv.regs->ier); + writel(UART_MCRVAL, &priv.regs->mcr); + writel(UART_FCRVAL, &priv.regs->fcr);

_mtk_serial_setbrg(&priv, CONFIG_BAUDRATE); }

The UART of MT7628 has fixed 40MHz input clock so there is no need to put clock-frequency in every dts files. Just put it into the common dtsi file.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- arch/mips/dts/gardena-smart-gateway-mt7688.dts | 1 - arch/mips/dts/linkit-smart-7688.dts | 1 - arch/mips/dts/mt7628a.dtsi | 6 ++++++ 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/arch/mips/dts/gardena-smart-gateway-mt7688.dts index eedde89dfd..95675a3947 100644 --- a/arch/mips/dts/gardena-smart-gateway-mt7688.dts +++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts @@ -87,7 +87,6 @@

&uart0 { status = "okay"; - clock-frequency = <40000000>; };

&spi0 { diff --git a/arch/mips/dts/linkit-smart-7688.dts b/arch/mips/dts/linkit-smart-7688.dts index bb10402174..935315743c 100644 --- a/arch/mips/dts/linkit-smart-7688.dts +++ b/arch/mips/dts/linkit-smart-7688.dts @@ -28,7 +28,6 @@

&uart2 { status = "okay"; - clock-frequency = <40000000>; };

&spi0 { diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 1e7d0a6ec5..6bc0722b07 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -127,6 +127,8 @@ compatible = "ns16550a"; reg = <0xc00 0x100>;

+ clock-frequency = <40000000>; + resets = <&resetc 12>; reset-names = "uart0";

@@ -140,6 +142,8 @@ compatible = "ns16550a"; reg = <0xd00 0x100>;

+ clock-frequency = <40000000>; + resets = <&resetc 19>; reset-names = "uart1";

@@ -153,6 +157,8 @@ compatible = "ns16550a"; reg = <0xe00 0x100>;

+ clock-frequency = <40000000>; + resets = <&resetc 20>; reset-names = "uart2";

All three UARTs of mt7628 are actually MediaTek's high-speed UARTs which support baudrate up to 921600. The high-speed UART is compatible with ns16550 when baudrate <= 115200.

Add compatible string to dtsi file so u-boot can use it when serial_mtk driver is built in.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- arch/mips/dts/mt7628a.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 6bc0722b07..e9241a0737 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -124,7 +124,7 @@ };

uart0: uartlite@c00 { - compatible = "ns16550a"; + compatible = "mediatek,hsuart", "ns16550a"; reg = <0xc00 0x100>;

clock-frequency = <40000000>; @@ -139,7 +139,7 @@ };

uart1: uart1@d00 { - compatible = "ns16550a"; + compatible = "mediatek,hsuart", "ns16550a"; reg = <0xd00 0x100>;

clock-frequency = <40000000>; @@ -154,7 +154,7 @@ };

uart2: uart2@e00 { - compatible = "ns16550a"; + compatible = "mediatek,hsuart", "ns16550a"; reg = <0xe00 0x100>;

clock-frequency = <40000000>;

The mt7621 spi controller supports continuous generic half-duplex spi transaction. There is no need to cache xfer data at all.

To achieve this goal, the OPADDR register must be used as the first data to be sent. And follows the eight generic DIDO registers. But one thing different between OPADDR and DIDO registers is OPADDR has a reversed byte order.

With this patch, any amount of data can be read/written in a single xfer function call.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/spi/mt7621_spi.c | 197 ++++++++++++++++++--------------------- 1 file changed, 91 insertions(+), 106 deletions(-)

diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c index 107e58f657..20fe93d416 100644 --- a/drivers/spi/mt7621_spi.c +++ b/drivers/spi/mt7621_spi.c @@ -14,9 +14,8 @@ #include <wait_bit.h> #include <linux/io.h>

-#define SPI_MSG_SIZE_MAX 32 /* SPI message chunk size */ -/* Enough for SPI NAND page read / write with page size 2048 bytes */ -#define SPI_MSG_SIZE_OVERALL (2048 + 16) +#define MT7621_RX_FIFO_LEN 32 +#define MT7621_TX_FIFO_LEN 36

#define MT7621_SPI_TRANS 0x00 #define MT7621_SPI_TRANS_START BIT(8) @@ -38,11 +37,16 @@ #define MASTER_RS_CLK_SEL_SHIFT 16 #define MASTER_RS_SLAVE_SEL GENMASK(31, 29)

+#define MOREBUF_CMD_CNT GENMASK(29, 24) +#define MOREBUF_CMD_CNT_SHIFT 24 +#define MOREBUF_MISO_CNT GENMASK(20, 12) +#define MOREBUF_MISO_CNT_SHIFT 12 +#define MOREBUF_MOSI_CNT GENMASK(8, 0) +#define MOREBUF_MOSI_CNT_SHIFT 0 + struct mt7621_spi { void __iomem *base; unsigned int sys_freq; - u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1]; - int tx_len; };

static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) @@ -128,20 +132,89 @@ static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs) return ret; }

+static int mt7621_spi_read(struct mt7621_spi *rs, u8 *buf, size_t len) +{ + size_t rx_len; + int i, ret; + u32 val = 0; + + while (len) { + rx_len = min_t(size_t, len, MT7621_RX_FIFO_LEN); + + iowrite32((rx_len * 8) << MOREBUF_MISO_CNT_SHIFT, + rs->base + MT7621_SPI_MOREBUF); + iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS); + + ret = mt7621_spi_wait_till_ready(rs); + if (ret) + return ret; + + for (i = 0; i < rx_len; i++) { + if ((i % 4) == 0) + val = ioread32(rs->base + MT7621_SPI_DATA0 + i); + *buf++ = val & 0xff; + val >>= 8; + } + + len -= rx_len; + } + + return ret; +} + +static int mt7621_spi_write(struct mt7621_spi *rs, const u8 *buf, size_t len) +{ + size_t tx_len, opcode_len, dido_len; + int i, ret; + u32 val; + + while (len) { + tx_len = min_t(size_t, len, MT7621_TX_FIFO_LEN); + + opcode_len = min_t(size_t, tx_len, 4); + dido_len = tx_len - opcode_len; + + val = 0; + for (i = 0; i < opcode_len; i++) { + val <<= 8; + val |= *buf++; + } + + iowrite32(val, rs->base + MT7621_SPI_OPCODE); + + val = 0; + for (i = 0; i < dido_len; i++) { + val |= (*buf++) << ((i % 4) * 8); + + if ((i % 4 == 3) || (i == dido_len - 1)) { + iowrite32(val, rs->base + MT7621_SPI_DATA0 + + (i & ~3)); + val = 0; + } + } + + iowrite32(((opcode_len * 8) << MOREBUF_CMD_CNT_SHIFT) | + ((dido_len * 8) << MOREBUF_MOSI_CNT_SHIFT), + rs->base + MT7621_SPI_MOREBUF); + iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS); + + ret = mt7621_spi_wait_till_ready(rs); + if (ret) + return ret; + + len -= tx_len; + } + + return 0; +} + static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct udevice *bus = dev->parent; struct mt7621_spi *rs = dev_get_priv(bus); - const u8 *tx_buf = dout; - u8 *ptr = (u8 *)dout; - u8 *rx_buf = din; int total_size = bitlen >> 3; - int chunk_size; - int rx_len = 0; - u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 }; - u32 val; - int i; + int ret = 0;

debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, total_size, flags); @@ -155,13 +228,6 @@ static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen, return -EIO; }

- if (dout) { - debug("TX-DATA: "); - for (i = 0; i < total_size; i++) - debug("%02x ", *ptr++); - debug("\n"); - } - mt7621_spi_wait_till_ready(rs);

/* @@ -171,96 +237,15 @@ static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen, if (flags & SPI_XFER_BEGIN) mt7621_spi_set_cs(rs, spi_chip_select(dev), 1);

- while (total_size > 0) { - /* Don't exceed the max xfer size */ - chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX); - - /* - * We might have some TX data buffered from the last xfer - * message. Make sure, that this does not exceed the max - * xfer size - */ - if (rs->tx_len > 4) - chunk_size -= rs->tx_len; - if (din) - rx_len = chunk_size; - - if (tx_buf) { - /* Check if this message does not exceed the buffer */ - if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) { - printf("TX message size too big (%d)\n", - chunk_size + rs->tx_len); - return -EMSGSIZE; - } - - /* - * Write all TX data into internal buffer to collect - * all TX messages into one buffer (might be split into - * multiple calls to this function) - */ - for (i = 0; i < chunk_size; i++, rs->tx_len++) { - rs->data[rs->tx_len / 4] |= - tx_buf[i] << (8 * (rs->tx_len & 3)); - } - } - - if (flags & SPI_XFER_END) { - /* Write TX data into controller */ - if (rs->tx_len) { - rs->data[0] = swab32(rs->data[0]); - if (rs->tx_len < 4) - rs->data[0] >>= (4 - rs->tx_len) * 8; - - for (i = 0; i < rs->tx_len; i += 4) { - iowrite32(rs->data[i / 4], rs->base + - MT7621_SPI_OPCODE + i); - } - } - - /* Write length into controller */ - val = (min_t(int, rs->tx_len, 4) * 8) << 24; - if (rs->tx_len > 4) - val |= (rs->tx_len - 4) * 8; - val |= (rx_len * 8) << 12; - iowrite32(val, rs->base + MT7621_SPI_MOREBUF); - - /* Start the xfer */ - setbits_le32(rs->base + MT7621_SPI_TRANS, - MT7621_SPI_TRANS_START); - - /* Wait until xfer is finished on bus */ - mt7621_spi_wait_till_ready(rs); - - /* Reset TX length and TX buffer for next xfer */ - rs->tx_len = 0; - memset(rs->data, 0, sizeof(rs->data)); - } - - for (i = 0; i < rx_len; i += 4) - data[i / 4] = ioread32(rs->base + MT7621_SPI_DATA0 + i); - - if (rx_len) { - debug("RX-DATA: "); - for (i = 0; i < rx_len; i++) { - rx_buf[i] = data[i / 4] >> (8 * (i & 3)); - debug("%02x ", rx_buf[i]); - } - debug("\n"); - } - - if (tx_buf) - tx_buf += chunk_size; - if (rx_buf) - rx_buf += chunk_size; - total_size -= chunk_size; - } + if (din) + ret = mt7621_spi_read(rs, din, total_size); + else if (dout) + ret = mt7621_spi_write(rs, dout, total_size);

- /* Wait until xfer is finished on bus and de-assert CS */ - mt7621_spi_wait_till_ready(rs); if (flags & SPI_XFER_END) mt7621_spi_set_cs(rs, spi_chip_select(dev), 0);

- return 0; + return ret; }

static int mt7621_spi_probe(struct udevice *dev)

Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver.

This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/spi/mt7621_spi.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c index 20fe93d416..06484e7abe 100644 --- a/drivers/spi/mt7621_spi.c +++ b/drivers/spi/mt7621_spi.c @@ -20,6 +20,10 @@ #define MT7621_SPI_TRANS 0x00 #define MT7621_SPI_TRANS_START BIT(8) #define MT7621_SPI_TRANS_BUSY BIT(16) +#define TRANS_ADDR_SZ GENMASK(20, 19) +#define TRANS_ADDR_SZ_SHIFT 19 +#define TRANS_MOSI_BCNT GENMASK(3, 0) +#define TRANS_MOSI_BCNT_SHIFT 0

#define MT7621_SPI_OPCODE 0x04 #define MT7621_SPI_DATA0 0x08 @@ -49,20 +53,22 @@ struct mt7621_spi { unsigned int sys_freq; };

-static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) -{ - setbits_le32(rs->base + MT7621_SPI_MASTER, - MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); -} - static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable) { - u32 val = 0; - debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable"); - if (enable) - val = BIT(cs); - iowrite32(val, rs->base + MT7621_SPI_POLAR); + + if (enable) { + setbits_le32(rs->base + MT7621_SPI_MASTER, + MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); + iowrite32(BIT(cs), rs->base + MT7621_SPI_POLAR); + } else { + iowrite32(0, rs->base + MT7621_SPI_POLAR); + iowrite32((2 << TRANS_ADDR_SZ_SHIFT) | + (1 << TRANS_MOSI_BCNT_SHIFT), + rs->base + MT7621_SPI_TRANS); + clrbits_le32(rs->base + MT7621_SPI_MASTER, + MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); + } }

static int mt7621_spi_set_mode(struct udevice *bus, uint mode) @@ -267,8 +273,6 @@ static int mt7621_spi_probe(struct udevice *dev) return -EINVAL; }

- mt7621_spi_reset(rs, 0); - return 0; }

This patch adds pinctrl support for mt7628, with a file for common pinmux functions and a file for mt7628 which has additional support for pinconf.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/mtmips/Kconfig | 13 + drivers/pinctrl/mtmips/Makefile | 7 + drivers/pinctrl/mtmips/pinctrl-mt7628.c | 585 ++++++++++++++++++ .../pinctrl/mtmips/pinctrl-mtmips-common.c | 87 +++ .../pinctrl/mtmips/pinctrl-mtmips-common.h | 53 ++ 7 files changed, 747 insertions(+) create mode 100644 drivers/pinctrl/mtmips/Kconfig create mode 100644 drivers/pinctrl/mtmips/Makefile create mode 100644 drivers/pinctrl/mtmips/pinctrl-mt7628.c create mode 100644 drivers/pinctrl/mtmips/pinctrl-mtmips-common.c create mode 100644 drivers/pinctrl/mtmips/pinctrl-mtmips-common.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index a0ac167d14..1634dffb35 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -244,6 +244,7 @@ source "drivers/pinctrl/exynos/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/meson/Kconfig" source "drivers/pinctrl/mscc/Kconfig" +source "drivers/pinctrl/mtmips/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/renesas/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 4b080b74dc..ce0879a2b7 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -9,6 +9,7 @@ obj-y += nxp/ obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ATH79) += ath79/ +obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o

diff --git a/drivers/pinctrl/mtmips/Kconfig b/drivers/pinctrl/mtmips/Kconfig new file mode 100644 index 0000000000..8482a38ebc --- /dev/null +++ b/drivers/pinctrl/mtmips/Kconfig @@ -0,0 +1,13 @@ + +config PINCTRL_MTMIPS + depends on ARCH_MTMIPS + bool + +config PINCTRL_MT7628 + bool "MediaTek MT7628 pin control driver" + select PINCTRL_MTMIPS + depends on SOC_MT7628 && PINCTRL_GENERIC + help + Support pin multiplexing control on MediaTek MT7628. + The driver is controlled by a device tree node which contains + the pin mux functions for each available pin groups. diff --git a/drivers/pinctrl/mtmips/Makefile b/drivers/pinctrl/mtmips/Makefile new file mode 100644 index 0000000000..3ba5c0c66d --- /dev/null +++ b/drivers/pinctrl/mtmips/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +# Core +obj-$(CONFIG_PINCTRL_MTMIPS) += pinctrl-mtmips-common.o + +# SoC Drivers +obj-$(CONFIG_PINCTRL_MT7628) += pinctrl-mt7628.o diff --git a/drivers/pinctrl/mtmips/pinctrl-mt7628.c b/drivers/pinctrl/mtmips/pinctrl-mt7628.c new file mode 100644 index 0000000000..6883450a09 --- /dev/null +++ b/drivers/pinctrl/mtmips/pinctrl-mt7628.c @@ -0,0 +1,585 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao weijie.gao@mediatek.com + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <linux/bitops.h> +#include <linux/io.h> + +#include "pinctrl-mtmips-common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define AGPIO_OFS 0 +#define GPIOMODE1_OFS 0x24 +#define GPIOMODE2_OFS 0x28 + +#define EPHY4_1_PAD_SHIFT 17 +#define EPHY4_1_PAD_MASK 0x0f +#define EPHY0_SHIFT 16 +#define RF_OLT_MODE_SHIFT 12 +#define N9_EINT_SRC_SHIFT 9 +#define WLED_OD_SHIFT 8 +#define REF_CLKO_PAD_SHIFT 4 +#define I2S_CLK_PAD_SHIFT 3 +#define I2S_WS_PAD_SHIFT 2 +#define I2S_SDO_PAD_SHIFT 1 +#define I2S_SDI_PAD_SHIFT 0 + +#define GM4_MASK 3 + +#define P4LED_K_SHIFT 26 +#define P3LED_K_SHIFT 24 +#define P2LED_K_SHIFT 22 +#define P1LED_K_SHIFT 20 +#define P0LED_K_SHIFT 18 +#define WLED_K_SHIFT 16 +#define P4LED_A_SHIFT 10 +#define P3LED_A_SHIFT 8 +#define P2LED_A_SHIFT 6 +#define P1LED_A_SHIFT 4 +#define P0LED_A_SHIFT 2 +#define WLED_A_SHIFT 0 + +#define PWM1_SHIFT 30 +#define PWM0_SHIFT 28 +#define UART2_SHIFT 26 +#define UART1_SHIFT 24 +#define I2C_SHIFT 20 +#define REFCLK_SHIFT 18 +#define PERST_SHIFT 16 +#define ESD_SHIFT 15 +#define WDT_SHIFT 14 +#define SPI_SHIFT 12 +#define SDMODE_SHIFT 10 +#define UART0_SHIFT 8 +#define I2S_SHIFT 6 +#define SPI_CS1_SHIFT 4 +#define SPIS_SHIFT 2 +#define GPIO0_SHIFT 0 + +#define PAD_PU_G0_REG 0x00 +#define PAD_PU_G1_REG 0x04 +#define PAD_PD_G0_REG 0x10 +#define PAD_PD_G1_REG 0x14 +#define PAD_SR_G0_REG 0x20 +#define PAD_SR_G1_REG 0x24 +#define PAD_SMT_G0_REG 0x30 +#define PAD_SMT_G1_REG 0x34 +#define PAD_E2_G0_REG 0x40 +#define PAD_E2_G1_REG 0x44 +#define PAD_E4_G0_REG 0x50 +#define PAD_E4_G1_REG 0x54 +#define PAD_E8_G0_REG 0x60 +#define PAD_E8_G1_REG 0x64 + +#define PIN_CONFIG_DRIVE_STRENGTH_28 (PIN_CONFIG_END + 1) +#define PIN_CONFIG_DRIVE_STRENGTH_4G (PIN_CONFIG_END + 2) + +struct mt7628_pinctrl_priv { + struct mtmips_pinctrl_priv mp; + + void __iomem *pcbase; +}; + +#if CONFIG_IS_ENABLED(PINMUX) +static struct mtmips_pmx_func ephy4_1_pad_grp[] = { + FUNC("digital", 0xf), + FUNC("analog", 0), +}; + +static struct mtmips_pmx_func ephy0_grp[] = { + FUNC("disable", 1), + FUNC("enable", 0), +}; + +static struct mtmips_pmx_func rf_olt_grp[] = { + FUNC("enable", 1), + FUNC("disable", 0), +}; + +static struct mtmips_pmx_func n9_eint_src_grp[] = { + FUNC("gpio", 1), + FUNC("utif", 0), +}; + +static struct mtmips_pmx_func wlen_od_grp[] = { + FUNC("enable", 1), + FUNC("disable", 0), +}; + +static struct mtmips_pmx_func ref_clko_grp[] = { + FUNC("digital", 1), + FUNC("analog", 0), +}; + +static struct mtmips_pmx_func i2s_clk_grp[] = { + FUNC("digital", 1), + FUNC("analog", 0), +}; + +static struct mtmips_pmx_func i2s_ws_grp[] = { + FUNC("digital", 1), + FUNC("analog", 0), +}; + +static struct mtmips_pmx_func i2s_sdo_grp[] = { + FUNC("digital", 1), + FUNC("analog", 0), +}; + +static struct mtmips_pmx_func i2s_sdi_grp[] = { + FUNC("digital", 1), + FUNC("analog", 0), +}; + +static struct mtmips_pmx_func pwm1_grp[] = { + FUNC("sdxc d6", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("pwm1", 0), +}; + +static struct mtmips_pmx_func pwm0_grp[] = { + FUNC("sdxc d7", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("pwm0", 0), +}; + +static struct mtmips_pmx_func uart2_grp[] = { + FUNC("sdxc d5 d4", 3), + FUNC("pwm", 2), + FUNC("gpio", 1), + FUNC("uart2", 0), +}; + +static struct mtmips_pmx_func uart1_grp[] = { + FUNC("sw_r", 3), + FUNC("pwm", 2), + FUNC("gpio", 1), + FUNC("uart1", 0), +}; + +static struct mtmips_pmx_func i2c_grp[] = { + FUNC("-", 3), + FUNC("debug", 2), + FUNC("gpio", 1), + FUNC("i2c", 0), +}; + +static struct mtmips_pmx_func refclk_grp[] = { + FUNC("gpio", 1), + FUNC("refclk", 0), +}; + +static struct mtmips_pmx_func perst_grp[] = { + FUNC("gpio", 1), + FUNC("perst", 0), +}; + +static struct mtmips_pmx_func esd_grp[] = { + FUNC("router", 1), + FUNC("iot", 0), +}; + +static struct mtmips_pmx_func wdt_grp[] = { + FUNC("gpio", 1), + FUNC("wdt", 0), +}; + +static struct mtmips_pmx_func spi_grp[] = { + FUNC("gpio", 1), + FUNC("spi", 0), +}; + +static struct mtmips_pmx_func sd_mode_grp[] = { + FUNC("n9 jtag", 3), + FUNC("utif1", 2), + FUNC("gpio", 1), + FUNC("sdxc", 0), +}; + +static struct mtmips_pmx_func uart0_grp[] = { + FUNC("-", 3), + FUNC("-", 2), + FUNC("gpio", 1), + FUNC("uart0", 0), +}; + +static struct mtmips_pmx_func i2s_grp[] = { + FUNC("antenna", 3), + FUNC("pcm", 2), + FUNC("gpio", 1), + FUNC("i2s", 0), +}; + +static struct mtmips_pmx_func spi_cs1_grp[] = { + FUNC("-", 3), + FUNC("refclk", 2), + FUNC("gpio", 1), + FUNC("spi cs1", 0), +}; + +static struct mtmips_pmx_func spis_grp[] = { + FUNC("pwm_uart2", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("spis", 0), +}; + +static struct mtmips_pmx_func gpio0_grp[] = { + FUNC("perst", 3), + FUNC("refclk", 2), + FUNC("gpio", 1), + FUNC("gpio0", 0), +}; + +static struct mtmips_pmx_func wled_a_grp[] = { + FUNC("-", 3), + FUNC("-", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func p0led_a_grp[] = { + FUNC("jtag", 3), + FUNC("rsvd", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func p1led_a_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func p2led_a_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func p3led_a_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func p4led_a_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func wled_k_grp[] = { + FUNC("-", 3), + FUNC("-", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func p0led_k_grp[] = { + FUNC("jtag", 3), + FUNC("rsvd", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func p1led_k_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func p2led_k_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func p3led_k_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_func p4led_k_grp[] = { + FUNC("jtag", 3), + FUNC("utif", 2), + FUNC("gpio", 1), + FUNC("led", 0), +}; + +static struct mtmips_pmx_group mt7628_pinmux_data[] = { + GRP("ephy4_1_pad", ephy4_1_pad_grp, AGPIO_OFS, EPHY4_1_PAD_SHIFT, + EPHY4_1_PAD_MASK), + GRP("ephy0", ephy0_grp, AGPIO_OFS, EPHY0_SHIFT, 1), + GRP("rf_olt", rf_olt_grp, AGPIO_OFS, RF_OLT_MODE_SHIFT, 1), + GRP("n9_eint_src", n9_eint_src_grp, AGPIO_OFS, N9_EINT_SRC_SHIFT, 1), + GRP("wlen_od", wlen_od_grp, AGPIO_OFS, WLED_OD_SHIFT, 1), + GRP("ref_clko_pad", ref_clko_grp, AGPIO_OFS, REF_CLKO_PAD_SHIFT, 1), + GRP("i2s_clk_pad", i2s_clk_grp, AGPIO_OFS, I2S_CLK_PAD_SHIFT, 1), + GRP("i2s_ws_pad", i2s_ws_grp, AGPIO_OFS, I2S_WS_PAD_SHIFT, 1), + GRP("i2s_sdo_pad", i2s_sdo_grp, AGPIO_OFS, I2S_SDO_PAD_SHIFT, 1), + GRP("i2s_sdi_pad", i2s_sdi_grp, AGPIO_OFS, I2S_SDI_PAD_SHIFT, 1), + GRP("pwm1", pwm1_grp, GPIOMODE1_OFS, PWM1_SHIFT, GM4_MASK), + GRP("pwm0", pwm0_grp, GPIOMODE1_OFS, PWM0_SHIFT, GM4_MASK), + GRP("uart2", uart2_grp, GPIOMODE1_OFS, UART2_SHIFT, GM4_MASK), + GRP("uart1", uart1_grp, GPIOMODE1_OFS, UART1_SHIFT, GM4_MASK), + GRP("i2c", i2c_grp, GPIOMODE1_OFS, I2C_SHIFT, GM4_MASK), + GRP("refclk", refclk_grp, GPIOMODE1_OFS, REFCLK_SHIFT, 1), + GRP("perst", perst_grp, GPIOMODE1_OFS, PERST_SHIFT, 1), + GRP("sd router", esd_grp, GPIOMODE1_OFS, ESD_SHIFT, 1), + GRP("wdt", wdt_grp, GPIOMODE1_OFS, WDT_SHIFT, 1), + GRP("spi", spi_grp, GPIOMODE1_OFS, SPI_SHIFT, 1), + GRP("sdmode", sd_mode_grp, GPIOMODE1_OFS, SDMODE_SHIFT, GM4_MASK), + GRP("uart0", uart0_grp, GPIOMODE1_OFS, UART0_SHIFT, GM4_MASK), + GRP("i2s", i2s_grp, GPIOMODE1_OFS, I2S_SHIFT, GM4_MASK), + GRP("spi cs1", spi_cs1_grp, GPIOMODE1_OFS, SPI_CS1_SHIFT, GM4_MASK), + GRP("spis", spis_grp, GPIOMODE1_OFS, SPIS_SHIFT, GM4_MASK), + GRP("gpio0", gpio0_grp, GPIOMODE1_OFS, GPIO0_SHIFT, GM4_MASK), + GRP("wled_a", wled_a_grp, GPIOMODE2_OFS, WLED_A_SHIFT, GM4_MASK), + GRP("p0led_a", p0led_a_grp, GPIOMODE2_OFS, P0LED_A_SHIFT, GM4_MASK), + GRP("p1led_a", p1led_a_grp, GPIOMODE2_OFS, P1LED_A_SHIFT, GM4_MASK), + GRP("p2led_a", p2led_a_grp, GPIOMODE2_OFS, P2LED_A_SHIFT, GM4_MASK), + GRP("p3led_a", p3led_a_grp, GPIOMODE2_OFS, P3LED_A_SHIFT, GM4_MASK), + GRP("p4led_a", p4led_a_grp, GPIOMODE2_OFS, P4LED_A_SHIFT, GM4_MASK), + GRP("wled_k", wled_k_grp, GPIOMODE2_OFS, WLED_K_SHIFT, GM4_MASK), + GRP("p0led_k", p0led_k_grp, GPIOMODE2_OFS, P0LED_K_SHIFT, GM4_MASK), + GRP("p1led_k", p1led_k_grp, GPIOMODE2_OFS, P1LED_K_SHIFT, GM4_MASK), + GRP("p2led_k", p2led_k_grp, GPIOMODE2_OFS, P2LED_K_SHIFT, GM4_MASK), + GRP("p3led_k", p3led_k_grp, GPIOMODE2_OFS, P3LED_K_SHIFT, GM4_MASK), + GRP("p4led_k", p4led_k_grp, GPIOMODE2_OFS, P4LED_K_SHIFT, GM4_MASK), +}; + +static int mt7628_get_groups_count(struct udevice *dev) +{ + return ARRAY_SIZE(mt7628_pinmux_data); +} + +static const char *mt7628_get_group_name(struct udevice *dev, + unsigned int selector) +{ + return mt7628_pinmux_data[selector].name; +} +#endif /* CONFIG_IS_ENABLED(PINMUX) */ + +#if CONFIG_IS_ENABLED(PINCONF) +static const struct pinconf_param mt7628_conf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "drive-strength-28", PIN_CONFIG_DRIVE_STRENGTH_28, 0 }, + { "drive-strength-4g", PIN_CONFIG_DRIVE_STRENGTH_4G, 0 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, +}; + +static const char *const mt7628_pins[] = { + "i2s_sdi", + "i2s_sdo", + "i2s_ws", + "i2s_clk", + "i2s_sclk", + "i2c_sd", + "spi_cs1", + "spi_clk", + "spi_mosi", + "spi_miso", + "spi_cs0", + "gpio0", + "uart0_txd", + "uart0_rxd", + "spis_cs", + "spis_clk", + "spis_miso", + "spis_mosi", + "pwm_ch0", + "pwm_ch1", + "uart2_txd", + "uart2_rxd", + "sd_wp", + "sd_cd", + "sd_d1", + "sd_d0", + "sd_clk", + "sd_cmd", + "sd_d3", + "sd_d2", + "ephy_led4_k", + "ephy_led3_k", + "ephy_led2_k", + "ephy_led1_k", + "ephy_led0_k", + "wled_k", + "perst_n", + "co_clko", + "wdt", + "ephy_led4_a", + "ephy_led3_a", + "ephy_led2_a", + "ephy_led1_a", + "ephy_led0_a", + "wled_a", + "uart1_txd", + "uart1_rxd", +}; + +static const u32 mt7628_drv_strength_28_tbl[] = {2, 4, 6, 8}; +static const u32 mt7628_drv_strength_4g_tbl[] = {4, 8, 12, 16}; + +static int mt7628_set_drv_strength(void __iomem *base, u32 val, u32 bit, + const u32 tbl[], u32 reg_lo, u32 reg_hi) +{ + int i; + + for (i = 0; i < 4; i++) + if (tbl[i] == val) + break; + + if (i >= 4) + return -EINVAL; + + clrsetbits_32(base + reg_lo, BIT(bit), (i & 1) << bit); + clrsetbits_32(base + reg_hi, BIT(bit), ((i >> 1) & 1) << bit); + + return 0; +} + +static int mt7628_get_pins_count(struct udevice *dev) +{ + return ARRAY_SIZE(mt7628_pins); +} + +static const char *mt7628_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + return mt7628_pins[selector]; +} + +static int mt7628_pinconf_set(struct udevice *dev, unsigned int pin_selector, + unsigned int param, unsigned int argument) +{ + struct mt7628_pinctrl_priv *priv = dev_get_priv(dev); + u32 offs, bit; + int ret = 0; + + offs = (pin_selector / 32) * 4; + bit = pin_selector % 32; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit)); + clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit)); + break; + case PIN_CONFIG_BIAS_PULL_UP: + setbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit)); + clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit)); + setbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit)); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + clrsetbits_32(priv->pcbase + offs + PAD_SMT_G0_REG, + BIT(bit), (!!argument) << bit); + break; + case PIN_CONFIG_DRIVE_STRENGTH_28: + ret = mt7628_set_drv_strength(priv->pcbase + offs, argument, + bit, mt7628_drv_strength_28_tbl, + PAD_E2_G0_REG, PAD_E4_G0_REG); + break; + case PIN_CONFIG_DRIVE_STRENGTH_4G: + ret = mt7628_set_drv_strength(priv->pcbase + offs, argument, + bit, mt7628_drv_strength_4g_tbl, + PAD_E4_G0_REG, PAD_E8_G0_REG); + break; + case PIN_CONFIG_SLEW_RATE: + clrsetbits_32(priv->pcbase + offs + PAD_SR_G0_REG, + BIT(bit), (!!argument) << bit); + break; + default: + ret = -EINVAL; + } + + return ret; +} +#endif + +static int mt7628_pinctrl_probe(struct udevice *dev) +{ + struct mt7628_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; + +#if CONFIG_IS_ENABLED(PINMUX) + ret = mtmips_pinctrl_probe(&priv->mp, ARRAY_SIZE(mt7628_pinmux_data), + mt7628_pinmux_data); +#endif /* CONFIG_IS_ENABLED(PINMUX) */ + + return ret; +} + +static int mt7628_pinctrl_ofdata_to_platdata(struct udevice *dev) +{ + struct mt7628_pinctrl_priv *priv = dev_get_priv(dev); + + priv->mp.base = (void __iomem *)dev_remap_addr_index(dev, 0); + + if (!priv->mp.base) + return -EINVAL; + + priv->pcbase = (void __iomem *)dev_remap_addr_index(dev, 1); + + if (!priv->pcbase) + return -EINVAL; + + return 0; +} + +static struct pinctrl_ops mt7628_pinctrl_ops = { +#if CONFIG_IS_ENABLED(PINMUX) + .get_groups_count = mt7628_get_groups_count, + .get_group_name = mt7628_get_group_name, + .get_functions_count = mtmips_get_functions_count, + .get_function_name = mtmips_get_function_name, + .pinmux_group_set = mtmips_pinmux_group_set, +#endif /* CONFIG_IS_ENABLED(PINMUX) */ +#if CONFIG_IS_ENABLED(PINCONF) + .pinconf_num_params = ARRAY_SIZE(mt7628_conf_params), + .pinconf_params = mt7628_conf_params, + .get_pins_count = mt7628_get_pins_count, + .get_pin_name = mt7628_get_pin_name, + .pinconf_set = mt7628_pinconf_set, +#endif /* CONFIG_IS_ENABLED(PINCONF) */ + .set_state = pinctrl_generic_set_state, +}; + +static const struct udevice_id mt7628_pinctrl_ids[] = { + { .compatible = "mediatek,mt7628-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(mt7628_pinctrl) = { + .name = "mt7628-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7628_pinctrl_ids, + .ofdata_to_platdata = mt7628_pinctrl_ofdata_to_platdata, + .ops = &mt7628_pinctrl_ops, + .probe = mt7628_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct mt7628_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c new file mode 100644 index 0000000000..ee6a9d1fc8 --- /dev/null +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao weijie.gao@mediatek.com + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <linux/io.h> + +#include "pinctrl-mtmips-common.h" + +static void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv, + u32 reg, u32 shift, u32 mask, u32 value) +{ + u32 val; + + val = readl(priv->base + reg); + val &= ~(mask << shift); + val |= value << shift; + writel(val, priv->base + reg); +} + +int mtmips_get_functions_count(struct udevice *dev) +{ + struct mtmips_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->nfuncs; +} + +const char *mtmips_get_function_name(struct udevice *dev, unsigned int selector) +{ + struct mtmips_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->funcs[selector]->name; +} + +int mtmips_pinmux_group_set(struct udevice *dev, unsigned int group_selector, + unsigned int func_selector) +{ + struct mtmips_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtmips_pmx_group *grp = &priv->groups[group_selector]; + const struct mtmips_pmx_func *func = priv->funcs[func_selector]; + int i; + + if (!grp->nfuncs) + return 0; + + for (i = 0; i < grp->nfuncs; i++) { + if (!strcmp(grp->funcs[i].name, func->name)) { + mtmips_pinctrl_reg_set(priv, grp->reg, grp->shift, + grp->mask, grp->funcs[i].value); + return 0; + } + } + + return -EINVAL; +} + +int mtmips_pinctrl_probe(struct mtmips_pinctrl_priv *priv, u32 ngroups, + const struct mtmips_pmx_group *groups) +{ + int i, j, n; + + priv->ngroups = ngroups; + priv->groups = groups; + + priv->nfuncs = 0; + + for (i = 0; i < ngroups; i++) + priv->nfuncs += groups[i].nfuncs; + + priv->funcs = malloc(priv->nfuncs * sizeof(*priv->funcs)); + if (!priv->funcs) + return -ENOMEM; + + n = 0; + + for (i = 0; i < ngroups; i++) { + for (j = 0; j < groups[i].nfuncs; j++) + priv->funcs[n++] = &groups[i].funcs[j]; + } + + return 0; +} diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h new file mode 100644 index 0000000000..b51d8f009c --- /dev/null +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao weijie.gao@mediatek.com + */ + +#ifndef _PINCTRL_MTMIPS_COMMON_H_ +#define _PINCTRL_MTMIPS_COMMON_H_ + +#include <common.h> + +struct mtmips_pmx_func { + const char *name; + int value; +}; + +struct mtmips_pmx_group { + const char *name; + + u32 reg; + u32 shift; + char mask; + + int nfuncs; + const struct mtmips_pmx_func *funcs; +}; + +struct mtmips_pinctrl_priv { + void __iomem *base; + + u32 ngroups; + const struct mtmips_pmx_group *groups; + + u32 nfuncs; + const struct mtmips_pmx_func **funcs; +}; + +#define FUNC(name, value) { name, value } + +#define GRP(_name, _funcs, _reg, _shift, _mask) \ + { .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \ + .funcs = (_funcs), .nfuncs = ARRAY_SIZE(_funcs) } + +int mtmips_get_functions_count(struct udevice *dev); +const char *mtmips_get_function_name(struct udevice *dev, + unsigned int selector); +int mtmips_pinmux_group_set(struct udevice *dev, unsigned int group_selector, + unsigned int func_selector); +int mtmips_pinctrl_probe(struct mtmips_pinctrl_priv *priv, u32 ngroups, + const struct mtmips_pmx_group *groups); + +#endif /* _PINCTRL_MTMIPS_COMMON_H_ */

This patch adds pinctrl node with default pin state for mt7628an.dtsi.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- arch/mips/dts/mt7628a.dtsi | 150 +++++++++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+)

diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index e9241a0737..be9ab50931 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -48,6 +48,156 @@ mask = <0x1>; };

+ pinctrl: pinctrl@60 { + compatible = "mediatek,mt7628-pinctrl"; + reg = <0x3c 0x2c>, <0x1300 0x100>; + reg-names = "gpiomode", "padconf"; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pin_state { + }; + + spi_single_pins: spi_single_pins { + groups = "spi"; + function = "spi"; + }; + + spi_dual_pins: spi_dual_pins { + spi_master_pins { + groups = "spi"; + function = "spi"; + }; + + spi_cs1_pin { + groups = "spi cs1"; + function = "spi cs1"; + }; + }; + + uart0_pins: uart0_pins { + groups = "uart0"; + function = "uart0"; + }; + + uart1_pins: uart1_pins { + groups = "uart1"; + function = "uart1"; + }; + + uart2_pins: uart2_pins { + groups = "uart2"; + function = "uart2"; + }; + + i2c_pins: i2c_pins { + groups = "i2c"; + function = "i2c"; + }; + + ephy_iot_mode: ephy_iot_mode { + ephy4_1_dis { + groups = "ephy4_1_pad"; + function = "digital"; + }; + + ephy0_en { + groups = "ephy0"; + function = "enable"; + }; + }; + + ephy_router_mode: ephy_router_mode { + ephy4_1_en { + groups = "ephy4_1_pad"; + function = "analog"; + }; + + ephy0_en { + groups = "ephy0"; + function = "enable"; + }; + }; + + sd_iot_mode: sd_iot_mode { + ephy4_1_dis { + groups = "ephy4_1_pad"; + function = "digital"; + }; + + sdxc_en { + groups = "sdmode"; + function = "sdxc"; + }; + + sdxc_iot_mode { + groups = "sd router"; + function = "iot"; + }; + + sd_clk_pad { + pins = "sd_clk"; + drive-strength-4g = <8>; + }; + }; + + sd_router_mode: sd_router_mode { + sdxc_router_mode { + groups = "sd router"; + function = "router"; + }; + + sdxc_map_pins { + groups = "gpio0", "i2s", "sdmode", \ + "i2c", "uart1"; + function = "gpio"; + }; + + sd_clk_pad { + pins = "gpio0"; + drive-strength-28 = <8>; + }; + }; + + emmc_iot_8bit_mode: emmc_iot_8bit_mode { + ephy4_1_dis { + groups = "ephy4_1_pad"; + function = "digital"; + }; + + emmc_en { + groups = "sdmode"; + function = "sdxc"; + }; + + emmc_iot_mode { + groups = "sd router"; + function = "iot"; + }; + + emmc_d4_d5 { + groups = "uart2"; + function = "sdxc d5 d4"; + }; + + emmc_d6 { + groups = "pwm1"; + function = "sdxc d6"; + }; + + emmc_d7 { + groups = "pwm0"; + function = "sdxc d7"; + }; + + sd_clk_pad { + pins = "sd_clk"; + drive-strength-4g = <8>; + }; + }; + }; + watchdog: watchdog@100 { compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt"; reg = <0x100 0x30>;

This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/reset/Kconfig | 7 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-mtmips.c | 82 ++++++++++++++++++++++++ include/dt-bindings/reset/mt7628-reset.h | 36 +++++++++++ 4 files changed, 126 insertions(+) create mode 100644 drivers/reset/reset-mtmips.c create mode 100644 include/dt-bindings/reset/mt7628-reset.h

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6ec6f39c85..76866a2e90 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -113,6 +113,13 @@ config RESET_MEDIATEK help Support for reset controller on MediaTek SoCs.

+config RESET_MTMIPS + bool "Reset controller driver for MediaTek MIPS platform" + depends on DM_RESET && ARCH_MTMIPS + default y + help + Support for reset controller on MediaTek MIPS platform. + config RESET_SUNXI bool "RESET support for Allwinner SoCs" depends on DM_RESET && ARCH_SUNXI diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 7fec75bb49..87d2bc4f18 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -18,5 +18,6 @@ obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o +obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o diff --git a/drivers/reset/reset-mtmips.c b/drivers/reset/reset-mtmips.c new file mode 100644 index 0000000000..59734565d7 --- /dev/null +++ b/drivers/reset/reset-mtmips.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao weijie.gao@mediatek.com + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <reset-uclass.h> +#include <linux/io.h> + +struct mtmips_reset_priv { + void __iomem *base; +}; + +static int mtmips_reset_request(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int mtmips_reset_free(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int mtmips_reset_assert(struct reset_ctl *reset_ctl) +{ + struct mtmips_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + setbits_32(priv->base, BIT(reset_ctl->id)); + + return 0; +} + +static int mtmips_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct mtmips_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + clrbits_32(priv->base, BIT(reset_ctl->id)); + + return 0; +} + +static const struct reset_ops mtmips_reset_ops = { + .request = mtmips_reset_request, + .free = mtmips_reset_free, + .rst_assert = mtmips_reset_assert, + .rst_deassert = mtmips_reset_deassert, +}; + +static int mtmips_reset_probe(struct udevice *dev) +{ + return 0; +} + +static int mtmips_reset_ofdata_to_platdata(struct udevice *dev) +{ + struct mtmips_reset_priv *priv = dev_get_priv(dev); + + priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id mtmips_reset_ids[] = { + { .compatible = "mediatek,mtmips-reset" }, + { } +}; + +U_BOOT_DRIVER(mtmips_reset) = { + .name = "mtmips-reset", + .id = UCLASS_RESET, + .of_match = mtmips_reset_ids, + .ofdata_to_platdata = mtmips_reset_ofdata_to_platdata, + .probe = mtmips_reset_probe, + .priv_auto_alloc_size = sizeof(struct mtmips_reset_priv), + .ops = &mtmips_reset_ops, +}; diff --git a/include/dt-bindings/reset/mt7628-reset.h b/include/dt-bindings/reset/mt7628-reset.h new file mode 100644 index 0000000000..2a674c1ea7 --- /dev/null +++ b/include/dt-bindings/reset/mt7628-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao weijie.gao@mediatek.com + */ + +#ifndef _DT_BINDINGS_MT7628_RESET_H_ +#define _DT_BINDINGS_MT7628_RESET_H_ + +#define MT7628_PWM_RST 31 +#define MT7628_SDXC_RST 30 +#define MT7628_CRYPTO_RST 29 +#define MT7628_AUX_STCK_RST 28 +#define MT7628_PCIE_RST 26 +#define MT7628_EPHY_RST 24 +#define MT7628_ETH_RST 23 +#define MT7628_UPHY_RST 22 +#define MT7628_UART2_RST 20 +#define MT7628_UART1_RST 19 +#define MT7628_SPI_RST 18 +#define MT7628_I2S_RST 17 +#define MT7628_I2C_RST 16 +#define MT7628_GDMA_RST 14 +#define MT7628_PIO_RST 13 +#define MT7628_UART0_RST 12 +#define MT7628_PCM_RST 11 +#define MT7628_MC_RST 10 +#define MT7628_INT_RST 9 +#define MT7628_TIMER_RST 8 +#define MT7628_HIF_RST 5 +#define MT7628_WIFI_RST 4 +#define MT7628_SPIS_RST 3 +#define MT7628_SYS_RST 0 + +#endif /* _DT_BINDINGS_MT7628_RESET_H_ */

This patch adds clock gating driver for MediaTek MIPS platform

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/clk/Kconfig | 8 ++++ drivers/clk/Makefile | 1 + drivers/clk/clk-mtmips-cg.c | 63 ++++++++++++++++++++++++++++ include/dt-bindings/clk/mt7628-clk.h | 31 ++++++++++++++ 4 files changed, 103 insertions(+) create mode 100644 drivers/clk/clk-mtmips-cg.c create mode 100644 include/dt-bindings/clk/mt7628-clk.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 95fe0aea2c..0762a42476 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -160,4 +160,12 @@ config SANDBOX_CLK_CCF Enable this option if you want to test the Linux kernel's Common Clock Framework [CCF] code in U-Boot's Sandbox clock driver.

+config CLK_MTMIPS_GATE + bool "Enable clock gating driver for MediaTek MIPS platform" + depends on CLK && ARCH_MTMIPS + default y + help + Enable clock gating driver for MediaTek MIPS platform. + This driver supports only clock enable and disable. + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 68aabe1ca9..353974d784 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o +obj-$(CONFIG_CLK_MTMIPS_GATE) += clk-mtmips-cg.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ diff --git a/drivers/clk/clk-mtmips-cg.c b/drivers/clk/clk-mtmips-cg.c new file mode 100644 index 0000000000..0221d95aed --- /dev/null +++ b/drivers/clk/clk-mtmips-cg.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao weijie.gao@mediatek.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/io.h> + +struct mtmips_clk_gate_priv { + void __iomem *base; +}; + +static int mtmips_clk_gate_enable(struct clk *clk) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev); + + setbits_32(priv->base, BIT(clk->id)); + + return 0; +} + +static int mtmips_clk_gate_disable(struct clk *clk) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev); + + clrbits_32(priv->base, BIT(clk->id)); + + return 0; +} + +const struct clk_ops mtmips_clk_gate_ops = { + .enable = mtmips_clk_gate_enable, + .disable = mtmips_clk_gate_disable, +}; + +static int mtmips_clk_gate_probe(struct udevice *dev) +{ + struct mtmips_clk_gate_priv *priv = dev_get_priv(dev); + + priv->base = (void __iomem *)dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id mtmips_clk_gate_ids[] = { + { .compatible = "mediatek,mtmips-clk-gate" }, + { } +}; + +U_BOOT_DRIVER(mtmips_clk_gate) = { + .name = "mtmips-clk-gate", + .id = UCLASS_CLK, + .of_match = mtmips_clk_gate_ids, + .probe = mtmips_clk_gate_probe, + .priv_auto_alloc_size = sizeof(struct mtmips_clk_gate_priv), + .ops = &mtmips_clk_gate_ops, +}; diff --git a/include/dt-bindings/clk/mt7628-clk.h b/include/dt-bindings/clk/mt7628-clk.h new file mode 100644 index 0000000000..6784d6e50b --- /dev/null +++ b/include/dt-bindings/clk/mt7628-clk.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao weijie.gao@mediatek.com + */ + +#ifndef _DT_BINDINGS_MT7628_CLK_H_ +#define _DT_BINDINGS_MT7628_CLK_H_ + +#define MT7628_PWM_CLK 31 +#define MT7628_SDXC_CLK 30 +#define MT7628_CRYPTO_CLK 29 +#define MT7628_MIPS_CNT_CLK 28 +#define MT7628_PCIE_CLK 26 +#define MT7628_UPHY_CLK 25 +#define MT7628_ETH_CLK 23 +#define MT7628_UART2_CLK 20 +#define MT7628_UART1_CLK 19 +#define MT7628_SPI_CLK 18 +#define MT7628_I2S_CLK 17 +#define MT7628_I2C_CLK 16 +#define MT7628_GDMA_CLK 14 +#define MT7628_PIO_CLK 13 +#define MT7628_UART0_CLK 12 +#define MT7628_PCM_CLK 11 +#define MT7628_MC_CLK 10 +#define MT7628_INT_CLK 9 +#define MT7628_TIMER_CLK 8 + +#endif /* _DT_BINDINGS_MT7628_CLK_H_ */

This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/phy/Kconfig | 2 + drivers/phy/mt76x8-usb-phy.c | 225 ++++++++++++++++++++++++----------- 2 files changed, 159 insertions(+), 68 deletions(-)

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 02312273e2..5c7b221431 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -200,6 +200,8 @@ config KEYSTONE_USB_PHY config MT76X8_USB_PHY bool "MediaTek MT76x8 (7628/88) USB PHY support" depends on PHY + select CLK + select DM_RESET help Support the USB PHY in MT76x8 SoCs

diff --git a/drivers/phy/mt76x8-usb-phy.c b/drivers/phy/mt76x8-usb-phy.c index 268da8ef6c..1e7c5f334b 100644 --- a/drivers/phy/mt76x8-usb-phy.c +++ b/drivers/phy/mt76x8-usb-phy.c @@ -6,93 +6,185 @@ * Copyright (C) 2017 John Crispin john@phrozen.org */

+#include <clk.h> #include <common.h> #include <dm.h> #include <generic-phy.h> -#include <regmap.h> -#include <reset-uclass.h> -#include <syscon.h> +#include <reset.h> #include <asm/io.h> - -#define RT_SYSC_REG_SYSCFG1 0x014 -#define RT_SYSC_REG_CLKCFG1 0x030 -#define RT_SYSC_REG_USB_PHY_CFG 0x05c +#include <linux/bitops.h>

#define OFS_U2_PHY_AC0 0x800 +#define USBPLL_FBDIV_S 16 +#define USBPLL_FBDIV_M GENMASK(22, 16) +#define BG_TRIM_S 8 +#define BG_TRIM_M GENMASK(11, 8) +#define BG_RBSEL_S 6 +#define BG_RBSEL_M GENMASK(7, 6) +#define BG_RASEL_S 4 +#define BG_RASEL_M GENMASK(5, 4) +#define BGR_DIV_S 2 +#define BGR_DIV_M GENMASK(3, 2) +#define CHP_EN BIT(1) + #define OFS_U2_PHY_AC1 0x804 +#define VRT_VREF_SEL_S 28 +#define VRT_VREF_SEL_M GENMASK(30, 28) +#define TERM_VREF_SEL_S 24 +#define TERM_VREF_SEL_M GENMASK(26, 24) +#define USBPLL_RSVD BIT(4) +#define USBPLL_ACCEN BIT(3) +#define USBPLL_LF BIT(2) + #define OFS_U2_PHY_AC2 0x808 + #define OFS_U2_PHY_ACR0 0x810 -#define OFS_U2_PHY_ACR1 0x814 -#define OFS_U2_PHY_ACR2 0x818 +#define HSTX_SRCAL_EN BIT(23) +#define HSTX_SRCTRL_S 16 +#define HSTX_SRCTRL_M GENMASK(18, 16) + #define OFS_U2_PHY_ACR3 0x81C -#define OFS_U2_PHY_ACR4 0x820 -#define OFS_U2_PHY_AMON0 0x824 +#define HSTX_DBIST_S 28 +#define HSTX_DBIST_M GENMASK(31, 28) +#define HSRX_BIAS_EN_SEL_S 20 +#define HSRX_BIAS_EN_SEL_M GENMASK(21, 20) + #define OFS_U2_PHY_DCR0 0x860 -#define OFS_U2_PHY_DCR1 0x864 +#define PHYD_RESERVE_S 8 +#define PHYD_RESERVE_M GENMASK(23, 8) +#define CDR_FILT_S 0 +#define CDR_FILT_M GENMASK(3, 0) + #define OFS_U2_PHY_DTM0 0x868 -#define OFS_U2_PHY_DTM1 0x86C +#define FORCE_USB_CLKEN BIT(25) + +#define OFS_FM_CR0 0xf00 +#define FREQDET_EN BIT(24) +#define CYCLECNT_S 0 +#define CYCLECNT_M GENMASK(23, 0)

-#define RT_RSTCTRL_UDEV BIT(25) -#define RT_RSTCTRL_UHST BIT(22) -#define RT_SYSCFG1_USB0_HOST_MODE BIT(10) +#define OFS_FM_MONR0 0xf0c

-#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25) -#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22) -#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20) -#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18) +#define OFS_FM_MONR1 0xf10 +#define FRCK_EN BIT(8)

-#define USB_PHY_UTMI_8B60M BIT(1) -#define UDEV_WAKEUP BIT(0) +#define U2_SR_COEF_7628 32

struct mt76x8_usb_phy { - u32 clk; void __iomem *base; - struct regmap *sysctl; + struct clk cg; /* for clock gating */ + struct reset_ctl rst_phy; };

-static void u2_phy_w32(struct mt76x8_usb_phy *phy, u32 val, u32 reg) +static void phy_w32(struct mt76x8_usb_phy *phy, u32 reg, u32 val) { writel(val, phy->base + reg); }

-static u32 u2_phy_r32(struct mt76x8_usb_phy *phy, u32 reg) +static u32 phy_r32(struct mt76x8_usb_phy *phy, u32 reg) { return readl(phy->base + reg); }

+static void phy_rmw32(struct mt76x8_usb_phy *phy, u32 reg, u32 clr, u32 set) +{ + clrsetbits_32(phy->base + reg, clr, set); +} + static void mt76x8_usb_phy_init(struct mt76x8_usb_phy *phy) { - u2_phy_r32(phy, OFS_U2_PHY_AC2); - u2_phy_r32(phy, OFS_U2_PHY_ACR0); - u2_phy_r32(phy, OFS_U2_PHY_DCR0); - - u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0); - u2_phy_r32(phy, OFS_U2_PHY_DCR0); - u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0); - u2_phy_r32(phy, OFS_U2_PHY_DCR0); - u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0); - u2_phy_r32(phy, OFS_U2_PHY_DCR0); - u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0); - u2_phy_r32(phy, OFS_U2_PHY_DCR0); - u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0); - u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1); - u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3); - u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0); + phy_r32(phy, OFS_U2_PHY_AC2); + phy_r32(phy, OFS_U2_PHY_ACR0); + phy_r32(phy, OFS_U2_PHY_DCR0); + + phy_w32(phy, OFS_U2_PHY_DCR0, + (0xffff << PHYD_RESERVE_S) | (2 << CDR_FILT_S)); + phy_r32(phy, OFS_U2_PHY_DCR0); + + phy_w32(phy, OFS_U2_PHY_DCR0, + (0x5555 << PHYD_RESERVE_S) | (2 << CDR_FILT_S)); + phy_r32(phy, OFS_U2_PHY_DCR0); + + phy_w32(phy, OFS_U2_PHY_DCR0, + (0xaaaa << PHYD_RESERVE_S) | (2 << CDR_FILT_S)); + phy_r32(phy, OFS_U2_PHY_DCR0); + + phy_w32(phy, OFS_U2_PHY_DCR0, + (4 << PHYD_RESERVE_S) | (2 << CDR_FILT_S)); + phy_r32(phy, OFS_U2_PHY_DCR0); + + phy_w32(phy, OFS_U2_PHY_AC0, + (0x48 << USBPLL_FBDIV_S) | (8 << BG_TRIM_S) | + (1 << BG_RBSEL_S) | (2 << BG_RASEL_S) | (2 << BGR_DIV_S) | + CHP_EN); + + phy_w32(phy, OFS_U2_PHY_AC1, + (4 << VRT_VREF_SEL_S) | (4 << TERM_VREF_SEL_S) | USBPLL_RSVD | + USBPLL_ACCEN | USBPLL_LF); + + phy_w32(phy, OFS_U2_PHY_ACR3, + (12 << HSTX_DBIST_S) | (2 << HSRX_BIAS_EN_SEL_S)); + + phy_w32(phy, OFS_U2_PHY_DTM0, FORCE_USB_CLKEN); +} + +static void mt76x8_usb_phy_sr_calibrate(struct mt76x8_usb_phy *phy) +{ + u32 fmout, tmp = 4; + int i; + + /* Enable HS TX SR calibration */ + phy_rmw32(phy, OFS_U2_PHY_ACR0, 0, HSTX_SRCAL_EN); + mdelay(1); + + /* Enable free run clock */ + phy_rmw32(phy, OFS_FM_MONR1, 0, FRCK_EN); + + /* Set cycle count = 0x400 */ + phy_rmw32(phy, OFS_FM_CR0, CYCLECNT_M, 0x400 << CYCLECNT_S); + + /* Enable frequency meter */ + phy_rmw32(phy, OFS_FM_CR0, 0, FREQDET_EN); + + /* Wait for FM detection done, set timeout to 10ms */ + for (i = 0; i < 10; i++) { + fmout = phy_r32(phy, OFS_FM_MONR0); + + if (fmout) + break; + + mdelay(1); + } + + /* Disable frequency meter */ + phy_rmw32(phy, OFS_FM_CR0, FREQDET_EN, 0); + + /* Disable free run clock */ + phy_rmw32(phy, OFS_FM_MONR1, FRCK_EN, 0); + + /* Disable HS TX SR calibration */ + phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCAL_EN, 0); + mdelay(1); + + if (fmout) { + /* + * set reg = (1024 / FM_OUT) * 25 * 0.028 + * (round to the nearest digits) + */ + tmp = (((1024 * 25 * U2_SR_COEF_7628) / fmout) + 500) / 1000; + } + + phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCTRL_M, + (tmp << HSTX_SRCTRL_S) & HSTX_SRCTRL_M); }

static int mt76x8_usb_phy_power_on(struct phy *_phy) { struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev); - u32 t;

- /* enable the phy */ - regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, - phy->clk, phy->clk); + clk_enable(&phy->cg);

- /* setup host mode */ - regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1, - RT_SYSCFG1_USB0_HOST_MODE, - RT_SYSCFG1_USB0_HOST_MODE); + reset_deassert(&phy->rst_phy);

/* * The SDK kernel had a delay of 100ms. however on device @@ -100,17 +192,8 @@ static int mt76x8_usb_phy_power_on(struct phy *_phy) */ mdelay(10);

- if (phy->base) - mt76x8_usb_phy_init(phy); - - /* print some status info */ - regmap_read(phy->sysctl, RT_SYSC_REG_USB_PHY_CFG, &t); - printf("remote usb device wakeup %s\n", - (t & UDEV_WAKEUP) ? "enabled" : "disabled"); - if (t & USB_PHY_UTMI_8B60M) - printf("UTMI 8bit 60MHz\n"); - else - printf("UTMI 16bit 30MHz\n"); + mt76x8_usb_phy_init(phy); + mt76x8_usb_phy_sr_calibrate(phy);

return 0; } @@ -119,9 +202,9 @@ static int mt76x8_usb_phy_power_off(struct phy *_phy) { struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);

- /* disable the phy */ - regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, - phy->clk, 0); + clk_disable(&phy->cg); + + reset_assert(&phy->rst_phy);

return 0; } @@ -129,15 +212,21 @@ static int mt76x8_usb_phy_power_off(struct phy *_phy) static int mt76x8_usb_phy_probe(struct udevice *dev) { struct mt76x8_usb_phy *phy = dev_get_priv(dev); - - phy->sysctl = syscon_regmap_lookup_by_phandle(dev, "ralink,sysctl"); - if (IS_ERR(phy->sysctl)) - return PTR_ERR(phy->sysctl); + int ret;

phy->base = dev_read_addr_ptr(dev); if (!phy->base) return -EINVAL;

+ /* clock gate */ + ret = clk_get_by_name(dev, "cg", &phy->cg); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "phy", &phy->rst_phy); + if (ret) + return ret; + return 0; }

When received a packet with an invalid length recorded in rx descriptor, we should free this rx descriptor to allow us to continue to receive following packets. Without doing so, u-boot will stuck in a dead loop trying to process this invalid rx descriptor.

This patch adds a call to mt7628_eth_free_pkt() after received an invalid packet length.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/net/mt7628-eth.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c index eef25da8a8..8ca2c66edb 100644 --- a/drivers/net/mt7628-eth.c +++ b/drivers/net/mt7628-eth.c @@ -139,6 +139,8 @@ struct mt7628_eth_dev { struct reset_ctl rst_ephy; };

+static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length); + static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set) { void __iomem *base = priv->eth_sw_base; @@ -400,6 +402,7 @@ static int mt7628_eth_recv(struct udevice *dev, int flags, uchar **packetp) length = FIELD_GET(RX_DMA_PLEN0, priv->rx_ring[idx].rxd2); if (length == 0 || length > MTK_QDMA_PAGE_SIZE) { printf("%s: invalid length (%d bytes)\n", __func__, length); + mt7628_eth_free_pkt(dev, NULL, 0); return -EIO; }

This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to prevent LAN devices from getting IP address from WAN.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/net/mt7628-eth.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)

diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c index 8ca2c66edb..1215b24eaf 100644 --- a/drivers/net/mt7628-eth.c +++ b/drivers/net/mt7628-eth.c @@ -57,6 +57,11 @@ /* Ethernet switch register */ #define MT7628_SWITCH_FCT0 0x0008 #define MT7628_SWITCH_PFC1 0x0014 +#define MT7628_SWITCH_PVIDC0 0x0040 +#define MT7628_SWITCH_PVIDC1 0x0044 +#define MT7628_SWITCH_PVIDC2 0x0048 +#define MT7628_SWITCH_PVIDC3 0x004c +#define MT7628_SWITCH_VMSC0 0x0070 #define MT7628_SWITCH_FPA 0x0084 #define MT7628_SWITCH_SOCPC 0x008c #define MT7628_SWITCH_POC0 0x0090 @@ -137,6 +142,8 @@ struct mt7628_eth_dev { int tx_dma_idx;

struct reset_ctl rst_ephy; + + int wan_port; };

static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length); @@ -269,6 +276,9 @@ static void mt7628_ephy_init(struct mt7628_eth_dev *priv) static void rt305x_esw_init(struct mt7628_eth_dev *priv) { void __iomem *base = priv->eth_sw_base; + void __iomem *reg; + u32 val = 0, pvid; + int i;

/* * FC_RLS_TH=200, FC_SET_TH=160 @@ -290,6 +300,25 @@ static void rt305x_esw_init(struct mt7628_eth_dev *priv) /* 1us cycle number=125 (FE's clock=125Mhz) */ writel(0x7d000000, base + MT7628_SWITCH_BMU_CTRL);

+ /* LAN/WAN partition, WAN port will be unusable in u-boot network */ + if (priv->wan_port >= 0 && priv->wan_port < 6) { + for (i = 0; i < 8; i++) { + pvid = i == priv->wan_port ? 2 : 1; + reg = base + MT7628_SWITCH_PVIDC0 + (i / 2) * 4; + if (i % 2 == 0) { + val = pvid; + } else { + val |= (pvid << 12); + writel(val, reg); + } + } + + val = 0xffff407f; + val |= 1 << (8 + priv->wan_port); + val &= ~(1 << priv->wan_port); + writel(val, base + MT7628_SWITCH_VMSC0); + } + /* Reset PHY */ reset_assert(&priv->rst_ephy); reset_deassert(&priv->rst_ephy); @@ -529,6 +558,9 @@ static int mt7628_eth_probe(struct udevice *dev) return ret; }

+ /* WAN port will be isolated from LAN ports */ + priv->wan_port = dev_read_u32_default(dev, "mediatek,wan-port", -1); + /* Put rx and tx rings into KSEG1 area (uncached) */ priv->tx_ring = (struct fe_tx_dma *) KSEG1ADDR(memalign(ARCH_DMA_MINALIGN,

This patch adds a dts property cd-active-high for builtin-cd mode to make it configurable instead of using hardcoded active-low.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- drivers/mmc/mtk-sd.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 7069fe8948..814a1b5fe9 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -270,6 +270,7 @@ struct msdc_host {

/* whether to use gpio detection or built-in hw detection */ bool builtin_cd; + bool cd_active_high;

/* card detection / write protection GPIOs */ #if CONFIG_IS_ENABLED(DM_GPIO) @@ -852,7 +853,12 @@ static int msdc_ops_get_cd(struct udevice *dev)

if (host->builtin_cd) { val = readl(&host->base->msdc_ps); - return !(val & MSDC_PS_CDSTS); + val &= MSDC_PS_CDSTS; + + if (!host->cd_active_high) + val = !val; + + return val; }

#if CONFIG_IS_ENABLED(DM_GPIO) @@ -1355,6 +1361,7 @@ static int msdc_ofdata_to_platdata(struct udevice *dev) host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0); host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0); host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0); + host->cd_active_high = dev_read_bool(dev, "cd-active-high");

return 0; }

This adds default pinctrl (dual SPI chip select) for gardena smart gateway

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- arch/mips/dts/gardena-smart-gateway-mt7688.dts | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/arch/mips/dts/gardena-smart-gateway-mt7688.dts index 821e5bcdf8..8a9b8227b7 100644 --- a/arch/mips/dts/gardena-smart-gateway-mt7688.dts +++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts @@ -102,6 +102,9 @@ status = "okay"; num-cs = <2>;

+ pinctrl-names = "default"; + pinctrl-0 = <&spi_dual_pins>; + spi-flash@0 { #address-cells = <1>; #size-cells = <1>;

This patch adds a referenceable name to eth node, and adds default pinctrl for all boards.

There are two pinctrl nodes used for two scenarios: ephy_iot_mode - for IOT boards which have only one port (PHY0) ephy_router_mode - For routers which have more than one ports

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- arch/mips/dts/gardena-smart-gateway-mt7688.dts | 5 +++++ arch/mips/dts/linkit-smart-7688.dts | 5 +++++ arch/mips/dts/mt7628a.dtsi | 2 +- 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/arch/mips/dts/gardena-smart-gateway-mt7688.dts index 8a9b8227b7..1a2629ad9d 100644 --- a/arch/mips/dts/gardena-smart-gateway-mt7688.dts +++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts @@ -121,3 +121,8 @@ reg = <1>; }; }; + +&eth { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_iot_mode>; +}; diff --git a/arch/mips/dts/linkit-smart-7688.dts b/arch/mips/dts/linkit-smart-7688.dts index 7dbd909d00..aca1ec8c70 100644 --- a/arch/mips/dts/linkit-smart-7688.dts +++ b/arch/mips/dts/linkit-smart-7688.dts @@ -51,3 +51,8 @@ reg = <0>; }; }; + +&eth { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_iot_mode>; +}; diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 929397c729..f13b539242 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -352,7 +352,7 @@ }; };

- eth@10110000 { + eth: eth@10110000 { compatible = "mediatek,mt7628-eth"; reg = <0x10100000 0x10000 0x10110000 0x8000>;

This patch changes all defconfig files of mtmips to use mtk high-speed uart driver.

This driver is compatible with ns16550a when baudrate <= 115200.

Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- configs/gardena-smart-gateway-mt7688-ram_defconfig | 2 +- configs/gardena-smart-gateway-mt7688_defconfig | 2 +- configs/linkit-smart-7688-ram_defconfig | 2 +- configs/linkit-smart-7688_defconfig | 2 +- include/configs/gardena-smart-gateway-mt7688.h | 2 +- include/configs/linkit-smart-7688.h | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig index 1a1167b2a6..99010289e9 100644 --- a/configs/gardena-smart-gateway-mt7688-ram_defconfig +++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig @@ -68,7 +68,7 @@ CONFIG_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_RESET=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_SYS_NS16550=y +CONFIG_MTK_SERIAL=y CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index a456e3b575..1e270cb61d 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -71,7 +71,7 @@ CONFIG_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_RESET=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_SYS_NS16550=y +CONFIG_MTK_SERIAL=y CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig index aa76633802..1e9cac5596 100644 --- a/configs/linkit-smart-7688-ram_defconfig +++ b/configs/linkit-smart-7688-ram_defconfig @@ -55,7 +55,7 @@ CONFIG_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_RESET=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_SYS_NS16550=y +CONFIG_MTK_SERIAL=y CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index 3750e59a4b..743cc48166 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -59,7 +59,7 @@ CONFIG_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_RESET=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_SYS_NS16550=y +CONFIG_MTK_SERIAL=y CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index b3b89d2ab9..e83a96ad5e 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -22,7 +22,7 @@

/* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 500000, 1500000 } + 230400, 460800, 921600 }

/* RAM */ #define CONFIG_SYS_MEMTEST_START 0x80100000 diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 2adf38545a..4d30d98abf 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -22,7 +22,7 @@

/* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 500000, 1500000 } + 230400, 460800, 921600 }

/* RAM */ #define CONFIG_SYS_MEMTEST_START 0x80100000