[U-Boot] [PATCH 07/19] ColdFire: Modules header files cleanup - 6 - U-Boot

22 Oct 2008

From: TsiChung Liew Tsi-Chung.Liew@freescale.com
Consolidate FlexBus structures and definitions
in immap_5xxx.h and m5xxx.h to more unify modules
header files. Apply changes to mcf52x2's cpu_init.c
Signed-off-by: TsiChung Liew Tsi-Chung.Liew@freescale.com
---
 cpu/mcf52x2/cpu_init.c              |  271 ++++++++++------------------------
 include/asm-m68k/coldfire/flexbus.h |   96 ++++++++-----
 include/asm-m68k/immap_5235.h       |   52 +-------
 include/asm-m68k/immap_5249.h       |    2 +
 include/asm-m68k/immap_5253.h       |    2 +
 include/asm-m68k/immap_5271.h       |    1 +
 include/asm-m68k/immap_5275.h       |   46 +------
 include/asm-m68k/immap_5282.h       |   52 +-------
 include/asm-m68k/m5235.h            |   40 -----
 include/asm-m68k/m5249.h            |   13 --
 include/asm-m68k/m5282.h            |   23 ---
 include/asm-m68k/m5329.h            |   59 --------
 include/configs/EB+MCF-EV123.h      |   16 +--
 include/configs/M5235EVB.h          |   10 +-
 include/configs/M5249EVB.h          |   14 +-
 include/configs/M5253DEMO.h         |   24 +--
 include/configs/M5253EVBE.h         |   20 +--
 include/configs/M5275EVB.h          |   14 +-
 include/configs/M5282EVB.h          |   18 +--
 include/configs/TASREG.h            |   14 +-
 20 files changed, 196 insertions(+), 591 deletions(-)

diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 7bb358e..32ad6cd 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -36,6 +36,65 @@
 #include <watchdog.h>
 #include <asm/immap.h>
+#ifndef CONFIG_M5272
+/* Only 5272 Flexbus chipselect is different from the rest */
+void init_fbcs(void)
+{
+	volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
+	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
+	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
+	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
+	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
+	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
+	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
+     && defined(CONFIG_SYS_CS6_CTRL))
+	fbcs->csar6 = CONFIG_SYS_CS6_BASE;
+	fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
+	fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
+     && defined(CONFIG_SYS_CS7_CTRL))
+	fbcs->csar7 = CONFIG_SYS_CS7_BASE;
+	fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
+	fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+#endif
+}
+#endif
+
 #if defined(CONFIG_M5253)
 /*
  * Breath some life into the CPU...
@@ -66,22 +125,14 @@ void cpu_init_f(void)
    mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
    mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
-	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
-
-	/*
-	 *  Setup chip selects...
-	 */
-
-	mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
-	mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
-	mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
+	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */
-	mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
-	mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
-	mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
+	/* FlexBus Chipselect */
+	init_fbcs();
#ifdef CONFIG_FSL_I2C
-	CONFIG_SYS_I2C_PINMUX_REG = CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
+	CONFIG_SYS_I2C_PINMUX_REG =
+	    CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
    CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 #ifdef CONFIG_SYS_I2C2_OFFSET
    CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
@@ -121,6 +172,9 @@ void cpu_init_f(void)
    mbar_writeShort(MCF_WTM_WCR, 0);
 #endif
+	/* FlexBus Chipselect */
+	init_fbcs();
+
    /* Set clockspeed to 100MHz */
    mbar_writeShort(MCF_FMPLL_SYNCR,
    		MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
@@ -268,66 +322,20 @@ void uart_port_conf(void)
  */
 void cpu_init_f(void)
 {
-	/* if we come from RAM we assume the CPU is
+	/*
+	 * if we come from RAM we assume the CPU is
     * already initialized.
     */
#ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
-	volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
-	volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
+	volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+	volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
/* Kill watchdog so we can initialize the PLL */
    wdog_reg->wcr = 0;
-	/* Memory Controller: */
-	/* Flash */
-	csctrl_reg->ar0 = CONFIG_SYS_AR0_PRELIM;
-	csctrl_reg->cr0 = CONFIG_SYS_CR0_PRELIM;
-	csctrl_reg->mr0 = CONFIG_SYS_MR0_PRELIM;
-
-#if (defined(CONFIG_SYS_AR1_PRELIM) && defined(CONFIG_SYS_CR1_PRELIM) && defined(CONFIG_SYS_MR1_PRELIM))
-	csctrl_reg->ar1 = CONFIG_SYS_AR1_PRELIM;
-	csctrl_reg->cr1 = CONFIG_SYS_CR1_PRELIM;
-	csctrl_reg->mr1 = CONFIG_SYS_MR1_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR2_PRELIM) && defined(CONFIG_SYS_CR2_PRELIM) && defined(CONFIG_SYS_MR2_PRELIM))
-	csctrl_reg->ar2 = CONFIG_SYS_AR2_PRELIM;
-	csctrl_reg->cr2 = CONFIG_SYS_CR2_PRELIM;
-	csctrl_reg->mr2 = CONFIG_SYS_MR2_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR3_PRELIM) && defined(CONFIG_SYS_CR3_PRELIM) && defined(CONFIG_SYS_MR3_PRELIM))
-	csctrl_reg->ar3 = CONFIG_SYS_AR3_PRELIM;
-	csctrl_reg->cr3 = CONFIG_SYS_CR3_PRELIM;
-	csctrl_reg->mr3 = CONFIG_SYS_MR3_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR4_PRELIM) && defined(CONFIG_SYS_CR4_PRELIM) && defined(CONFIG_SYS_MR4_PRELIM))
-	csctrl_reg->ar4 = CONFIG_SYS_AR4_PRELIM;
-	csctrl_reg->cr4 = CONFIG_SYS_CR4_PRELIM;
-	csctrl_reg->mr4 = CONFIG_SYS_MR4_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR5_PRELIM) && defined(CONFIG_SYS_CR5_PRELIM) && defined(CONFIG_SYS_MR5_PRELIM))
-	csctrl_reg->ar5 = CONFIG_SYS_AR5_PRELIM;
-	csctrl_reg->cr5 = CONFIG_SYS_CR5_PRELIM;
-	csctrl_reg->mr5 = CONFIG_SYS_MR5_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR6_PRELIM) && defined(CONFIG_SYS_CR6_PRELIM) && defined(CONFIG_SYS_MR6_PRELIM))
-	csctrl_reg->ar6 = CONFIG_SYS_AR6_PRELIM;
-	csctrl_reg->cr6 = CONFIG_SYS_CR6_PRELIM;
-	csctrl_reg->mr6 = CONFIG_SYS_MR6_PRELIM;
-#endif
-
-#if (defined(CONFIG_SYS_AR7_PRELIM) && defined(CONFIG_SYS_CR7_PRELIM) && defined(CONFIG_SYS_MR7_PRELIM))
-	csctrl_reg->ar7 = CONFIG_SYS_AR7_PRELIM;
-	csctrl_reg->cr7 = CONFIG_SYS_CR7_PRELIM;
-	csctrl_reg->mr7 = CONFIG_SYS_MR7_PRELIM;
-#endif
-
+	/* FlexBus Chipselect */
+	init_fbcs();
 #endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
@@ -349,7 +357,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
 {
-	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
    switch (CONFIG_SYS_UART_PORT) {
@@ -384,7 +392,8 @@ void cpu_init_f(void)
 #ifndef CONFIG_MONITOR_IS_IN_RAM
    /* Set speed /PLL */
    MCFCLOCK_SYNCR =
-	    MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
+	    MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
+	    MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
    while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
@@ -425,119 +434,8 @@ void cpu_init_f(void)
    MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
 #endif
-	/* This is probably a bad place to setup chip selects, but everyone
-	   else is doing it! */
-
-#if defined(CONFIG_SYS_CS0_BASE) & defined(CONFIG_SYS_CS0_SIZE) & \
-    defined(CONFIG_SYS_CS0_WIDTH) & defined(CONFIG_SYS_CS0_WS)
-
-	MCFCSM_CSAR0 = (CONFIG_SYS_CS0_BASE >> 16) & 0xFFFF;
-
-#if (CONFIG_SYS_CS0_WIDTH == 8)
-#define	 CONFIG_SYS_CS0_PS  MCFCSM_CSCR_PS_8
-#elif (CONFIG_SYS_CS0_WIDTH == 16)
-#define	 CONFIG_SYS_CS0_PS  MCFCSM_CSCR_PS_16
-#elif (CONFIG_SYS_CS0_WIDTH == 32)
-#define	 CONFIG_SYS_CS0_PS  MCFCSM_CSCR_PS_32
-#else
-#error	"CONFIG_SYS_CS0_WIDTH: Fault - wrong bus with for CS0"
-#endif
-	MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CONFIG_SYS_CS0_WS)
-	    | CONFIG_SYS_CS0_PS | MCFCSM_CSCR_AA;
-
-#if (CONFIG_SYS_CS0_RO != 0)
-	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1)
-	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
-	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1) | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 0 are not initialized/used"
-#endif
-
-#if defined(CONFIG_SYS_CS1_BASE) & defined(CONFIG_SYS_CS1_SIZE) & \
-    defined(CONFIG_SYS_CS1_WIDTH) & defined(CONFIG_SYS_CS1_WS)
-
-	MCFCSM_CSAR1 = (CONFIG_SYS_CS1_BASE >> 16) & 0xFFFF;
-
-#if (CONFIG_SYS_CS1_WIDTH == 8)
-#define	 CONFIG_SYS_CS1_PS  MCFCSM_CSCR_PS_8
-#elif (CONFIG_SYS_CS1_WIDTH == 16)
-#define	 CONFIG_SYS_CS1_PS  MCFCSM_CSCR_PS_16
-#elif (CONFIG_SYS_CS1_WIDTH == 32)
-#define	 CONFIG_SYS_CS1_PS  MCFCSM_CSCR_PS_32
-#else
-#error	"CONFIG_SYS_CS1_WIDTH: Fault - wrong bus with for CS1"
-#endif
-	MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CONFIG_SYS_CS1_WS)
-	    | CONFIG_SYS_CS1_PS | MCFCSM_CSCR_AA;
-
-#if (CONFIG_SYS_CS1_RO != 0)
-	MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
-	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
-	MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
-	    | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 1 are not initialized/used"
-#endif
-
-#if defined(CONFIG_SYS_CS2_BASE) & defined(CONFIG_SYS_CS2_SIZE) & \
-    defined(CONFIG_SYS_CS2_WIDTH) & defined(CONFIG_SYS_CS2_WS)
-
-	MCFCSM_CSAR2 = (CONFIG_SYS_CS2_BASE >> 16) & 0xFFFF;
-
-#if (CONFIG_SYS_CS2_WIDTH == 8)
-#define	 CONFIG_SYS_CS2_PS  MCFCSM_CSCR_PS_8
-#elif (CONFIG_SYS_CS2_WIDTH == 16)
-#define	 CONFIG_SYS_CS2_PS  MCFCSM_CSCR_PS_16
-#elif (CONFIG_SYS_CS2_WIDTH == 32)
-#define	 CONFIG_SYS_CS2_PS  MCFCSM_CSCR_PS_32
-#else
-#error	"CONFIG_SYS_CS2_WIDTH: Fault - wrong bus with for CS2"
-#endif
-	MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CONFIG_SYS_CS2_WS)
-	    | CONFIG_SYS_CS2_PS | MCFCSM_CSCR_AA;
-
-#if (CONFIG_SYS_CS2_RO != 0)
-	MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
-	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
-	MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
-	    | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 2 are not initialized/used"
-#endif
-
-#if defined(CONFIG_SYS_CS3_BASE) & defined(CONFIG_SYS_CS3_SIZE) & \
-    defined(CONFIG_SYS_CS3_WIDTH) & defined(CONFIG_SYS_CS3_WS)
-
-	MCFCSM_CSAR3 = (CONFIG_SYS_CS3_BASE >> 16) & 0xFFFF;
-
-#if (CONFIG_SYS_CS3_WIDTH == 8)
-#define	 CONFIG_SYS_CS3_PS  MCFCSM_CSCR_PS_8
-#elif (CONFIG_SYS_CS3_WIDTH == 16)
-#define	 CONFIG_SYS_CS3_PS  MCFCSM_CSCR_PS_16
-#elif (CONFIG_SYS_CS3_WIDTH == 32)
-#define	 CONFIG_SYS_CS3_PS  MCFCSM_CSCR_PS_32
-#else
-#error	"CONFIG_SYS_CS3_WIDTH: Fault - wrong bus with for CS1"
-#endif
-	MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CONFIG_SYS_CS3_WS)
-	    | CONFIG_SYS_CS3_PS | MCFCSM_CSCR_AA;
-
-#if (CONFIG_SYS_CS3_RO != 0)
-	MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
-	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
-	MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
-	    | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 3 are not initialized/used"
-#endif
+	/* FlexBus Chipselect */
+	init_fbcs();
#endif				/* CONFIG_MONITOR_IS_IN_RAM */
@@ -632,17 +530,8 @@ void cpu_init_f(void)
    mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
    mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
-	/*
-	 *  Setup chip selects...
-	 */
-
-	mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
-	mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
-	mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
-
-	mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
-	mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
-	mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
+	/* FlexBus Chipselect */
+	init_fbcs();
/* enable instruction cache now */
    icache_enable();
diff --git a/include/asm-m68k/coldfire/flexbus.h b/include/asm-m68k/coldfire/flexbus.h
index 1d902c0..51cbbd8 100644
--- a/include/asm-m68k/coldfire/flexbus.h
+++ b/include/asm-m68k/coldfire/flexbus.h
@@ -31,33 +31,36 @@
 *********************************************************************/
typedef struct fbcs {
-	u32 csar0;		/* Chip-select Address Register */
-	u32 csmr0;		/* Chip-select Mask Register */
-	u32 cscr0;		/* Chip-select Control Register */
-	u32 csar1;		/* Chip-select Address Register */
-	u32 csmr1;		/* Chip-select Mask Register */
-	u32 cscr1;		/* Chip-select Control Register */
-	u32 csar2;		/* Chip-select Address Register */
-	u32 csmr2;		/* Chip-select Mask Register */
-	u32 cscr2;		/* Chip-select Control Register */
-	u32 csar3;		/* Chip-select Address Register */
-	u32 csmr3;		/* Chip-select Mask Register */
-	u32 cscr3;		/* Chip-select Control Register */
-	u32 csar4;		/* Chip-select Address Register */
-	u32 csmr4;		/* Chip-select Mask Register */
-	u32 cscr4;		/* Chip-select Control Register */
-	u32 csar5;		/* Chip-select Address Register */
-	u32 csmr5;		/* Chip-select Mask Register */
-	u32 cscr5;		/* Chip-select Control Register */
+	u32 csar0;		/* Chip-select Address */
+	u32 csmr0;		/* Chip-select Mask */
+	u32 cscr0;		/* Chip-select Control */
+	u32 csar1;
+	u32 csmr1;
+	u32 cscr1;
+	u32 csar2;
+	u32 csmr2;
+	u32 cscr2;
+	u32 csar3;
+	u32 csmr3;
+	u32 cscr3;
+	u32 csar4;
+	u32 csmr4;
+	u32 cscr4;
+	u32 csar5;
+	u32 csmr5;
+	u32 cscr5;
+	u32 csar6;
+	u32 csmr6;
+	u32 cscr6;
+	u32 csar7;
+	u32 csmr7;
+	u32 cscr7;
 } fbcs_t;
-/* Bit definitions and macros for CSAR group */
-#define FBCS_CSAR_BA(x)			((x)&0xFFFF0000)
+#define FBCS_CSAR_BA(x)			((x) & 0xFFFF0000)
-/* Bit definitions and macros for CSMR group */
-#define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
-#define FBCS_CSMR_WP			(0x00000100)	/* Write protect */
-#define FBCS_CSMR_BAM(x)		(((x)&0x0000FFFF)<<16)	/* Base address mask */
+#define FBCS_CSMR_BAM(x)		(((x) & 0xFFFF) << 16)
+#define FBCS_CSMR_BAM_MASK		(0x0000FFFF)
 #define FBCS_CSMR_BAM_4G		(0xFFFF0000)
 #define FBCS_CSMR_BAM_2G		(0x7FFF0000)
 #define FBCS_CSMR_BAM_1G		(0x3FFF0000)
@@ -78,21 +81,40 @@ typedef struct fbcs {
 #define FBCS_CSMR_BAM_128K		(0x00010000)
 #define FBCS_CSMR_BAM_64K		(0x00000000)
-/* Bit definitions and macros for CSCR group */
-#define FBCS_CSCR_BSTW			(0x00000008)	/* Burst-write enable */
-#define FBCS_CSCR_BSTR			(0x00000010)	/* Burst-read enable */
-#define FBCS_CSCR_BEM			(0x00000020)	/* Byte-enable mode */
-#define FBCS_CSCR_PS(x)			(((x)&0x00000003)<<6)	/* Port size */
-#define FBCS_CSCR_AA			(0x00000100)	/* Auto-acknowledge */
-#define FBCS_CSCR_WS(x)			(((x)&0x0000003F)<<10)	/* Wait states */
-#define FBCS_CSCR_WRAH(x)		(((x)&0x00000003)<<16)	/* Write address hold or deselect */
-#define FBCS_CSCR_RDAH(x)		(((x)&0x00000003)<<18)	/* Read address hold or deselect */
-#define FBCS_CSCR_ASET(x)		(((x)&0x00000003)<<20)	/* Address setup */
-#define FBCS_CSCR_SWSEN			(0x00800000)	/* Secondary wait state enable */
-#define FBCS_CSCR_SWS(x)		(((x)&0x0000003F)<<26)	/* Secondary wait states */
+#ifdef CONFIG_M5249
+#define FBCS_CSMR_WP			(0x00000080)
+#define FBCS_CSMR_AM			(0x00000040)
+#define FBCS_CSMR_CI			(0x00000020)
+#define FBCS_CSMR_SC			(0x00000010)
+#define FBCS_CSMR_SD			(0x00000008)
+#define FBCS_CSMR_UC			(0x00000004)
+#define FBCS_CSMR_UD			(0x00000002)
+#else
+#define FBCS_CSMR_WP			(0x00000100)
+#endif
+#define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
+
+#define FBCS_CSCR_SWS(x)		(((x) & 0x3F) << 26)
+#define FBCS_CSCR_SWS_MASK		(0x03FFFFFF)
+#define FBCS_CSCR_SWSEN			(0x00800000)
+#define FBCS_CSCR_ASET(x)		(((x) & 0x03) << 20)
+#define FBCS_CSCR_ASET_MASK		(0xFFCFFFFF)
+#define FBCS_CSCR_RDAH(x)		(((x) & 0x03) << 18)
+#define FBCS_CSCR_RDAH_MASK		(0xFFF3FFFF)
+#define FBCS_CSCR_WRAH(x)		(((x) & 0x03) << 16)
+#define FBCS_CSCR_WRAH_MASK		(0xFFFCFFFF)
+#define FBCS_CSCR_WS(x)			(((x) & 0x3F) << 10)
+#define FBCS_CSCR_WS_MASK		(0xFFFF03FF)
+#define FBCS_CSCR_SBM			(0x00000200)
+#define FBCS_CSCR_AA			(0x00000100)
+#define FBCS_CSCR_PS(x)			(((x) & 0x03) << 6)
+#define FBCS_CSCR_PS_MASK		(0xFFFFFF3F)
+#define FBCS_CSCR_BEM			(0x00000020)
+#define FBCS_CSCR_BSTR			(0x00000010)
+#define FBCS_CSCR_BSTW			(0x00000008)
-#define FBCS_CSCR_PS_8			(0x00000040)
 #define FBCS_CSCR_PS_16			(0x00000080)
+#define FBCS_CSCR_PS_8			(0x00000040)
 #define FBCS_CSCR_PS_32			(0x00000000)
#endif				/* __FLEXBUS_H */
diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h
index a987121..f7f35fc 100644
--- a/include/asm-m68k/immap_5235.h
+++ b/include/asm-m68k/immap_5235.h
@@ -64,6 +64,7 @@
 #define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
 #include <asm/coldfire/flexcan.h>
 #include <asm/coldfire/intctrl.h>
 #include <asm/coldfire/mdha.h>
@@ -112,57 +113,6 @@ typedef struct sdram_ctrl {
    u32 dmr1;		/* 0x14 mask register block 1 */
 } sdram_t;
-/* Flexbus module Chip select registers */
-typedef struct fbcs_ctrl {
-	u16 csar0;		/* 0x00 Chip-Select Address Register 0 */
-	u16 res0;
-	u32 csmr0;		/* 0x04 Chip-Select Mask Register 0 */
-	u16 res1;		/* 0x08 */
-	u16 cscr0;		/* 0x0A Chip-Select Control Register 0 */
-
-	u16 csar1;		/* 0x0C Chip-Select Address Register 1 */
-	u16 res2;
-	u32 csmr1;		/* 0x10 Chip-Select Mask Register 1 */
-	u16 res3;		/* 0x14 */
-	u16 cscr1;		/* 0x16 Chip-Select Control Register 1 */
-
-	u16 csar2;		/* 0x18 Chip-Select Address Register 2 */
-	u16 res4;
-	u32 csmr2;		/* 0x1C Chip-Select Mask Register 2 */
-	u16 res5;		/* 0x20 */
-	u16 cscr2;		/* 0x22 Chip-Select Control Register 2 */
-
-	u16 csar3;		/* 0x24 Chip-Select Address Register 3 */
-	u16 res6;
-	u32 csmr3;		/* 0x28 Chip-Select Mask Register 3 */
-	u16 res7;		/* 0x2C */
-	u16 cscr3;		/* 0x2E Chip-Select Control Register 3 */
-
-	u16 csar4;		/* 0x30 Chip-Select Address Register 4 */
-	u16 res8;
-	u32 csmr4;		/* 0x34 Chip-Select Mask Register 4 */
-	u16 res9;		/* 0x38 */
-	u16 cscr4;		/* 0x3A Chip-Select Control Register 4 */
-
-	u16 csar5;		/* 0x3C Chip-Select Address Register 5 */
-	u16 res10;
-	u32 csmr5;		/* 0x40 Chip-Select Mask Register 5 */
-	u16 res11;		/* 0x44 */
-	u16 cscr5;		/* 0x46 Chip-Select Control Register 5 */
-
-	u16 csar6;		/* 0x48 Chip-Select Address Register 5 */
-	u16 res12;
-	u32 csmr6;		/* 0x4C Chip-Select Mask Register 5 */
-	u16 res13;		/* 0x50 */
-	u16 cscr6;		/* 0x52 Chip-Select Control Register 5 */
-
-	u16 csar7;		/* 0x54 Chip-Select Address Register 5 */
-	u16 res14;
-	u32 csmr7;		/* 0x58 Chip-Select Mask Register 5 */
-	u16 res15;		/* 0x5C */
-	u16 cscr7;		/* 0x5E Chip-Select Control Register 5 */
-} fbcs_t;
-
 typedef struct canex_ctrl {
    can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
 } canex_t;
diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h
index f4fedfd..0242086 100644
--- a/include/asm-m68k/immap_5249.h
+++ b/include/asm-m68k/immap_5249.h
@@ -26,12 +26,14 @@
 #define __IMMAP_5249__
#define MMAP_INTC		(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS		(CONFIG_SYS_MBAR + 0x00000080)
 #define MMAP_DTMR0		(CONFIG_SYS_MBAR + 0x00000140)
 #define MMAP_DTMR1		(CONFIG_SYS_MBAR + 0x00000180)
 #define MMAP_UART0		(CONFIG_SYS_MBAR + 0x000001C0)
 #define MMAP_UART1		(CONFIG_SYS_MBAR + 0x00000200)
 #define MMAP_QSPI		(CONFIG_SYS_MBAR + 0x00000400)
+#include <asm/coldfire/flexbus.h>
 #include <asm/coldfire/qspi.h>
#endif				/* __IMMAP_5249__ */
diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h
index bf30189..b5a4cb5 100644
--- a/include/asm-m68k/immap_5253.h
+++ b/include/asm-m68k/immap_5253.h
@@ -27,6 +27,7 @@
 #define __IMMAP_5253__
#define MMAP_INTC		(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS		(CONFIG_SYS_MBAR + 0x00000080)
 #define MMAP_DTMR0		(CONFIG_SYS_MBAR + 0x00000140)
 #define MMAP_DTMR1		(CONFIG_SYS_MBAR + 0x00000180)
 #define MMAP_UART0		(CONFIG_SYS_MBAR + 0x000001C0)
@@ -40,6 +41,7 @@
 #define MMAP_UART2		(CONFIG_SYS_MBAR2 + 0x00000C00)
#include <asm/coldfire/ata.h>
+#include <asm/coldfire/flexbus.h>
 #include <asm/coldfire/flexcan.h>
 #include <asm/coldfire/qspi.h>
diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h
index 3576656..8ddec5c 100644
--- a/include/asm-m68k/immap_5271.h
+++ b/include/asm-m68k/immap_5271.h
@@ -64,6 +64,7 @@
 #define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
 #include <asm/coldfire/intctrl.h>
 #include <asm/coldfire/mdha.h>
 #include <asm/coldfire/qspi.h>
diff --git a/include/asm-m68k/immap_5275.h b/include/asm-m68k/immap_5275.h
index e04dd4e..46426a3 100644
--- a/include/asm-m68k/immap_5275.h
+++ b/include/asm-m68k/immap_5275.h
@@ -67,6 +67,7 @@
 #define MMAP_PWM0	(CONFIG_SYS_MBAR + 0x001D0000)
#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
 #include <asm/coldfire/intctrl.h>
 #include <asm/coldfire/mdha.h>
 #include <asm/coldfire/pwm.h>
@@ -117,51 +118,6 @@ typedef struct sdram_ctrl {
    u32 sdbmr1;
 } sdramctrl_t;
-/* Chip select module registers, offset: 0x080
-*/
-typedef struct	cs_ctlr {
-	u16 ar0;
-	u16 res1;
-	u32 mr0;
-	u16 res2;
-	u16 cr0;
-	u16 ar1;
-	u16 res3;
-	u32 mr1;
-	u16 res4;
-	u16 cr1;
-	u16 ar2;
-	u16 res5;
-	u32 mr2;
-	u16 res6;
-	u16 cr2;
-	u16 ar3;
-	u16 res7;
-	u32 mr3;
-	u16 res8;
-	u16 cr3;
-	u16 ar4;
-	u16 res9;
-	u32 mr4;
-	u16 res10;
-	u16 cr4;
-	u16 ar5;
-	u16 res11;
-	u32 mr5;
-	u16 res12;
-	u16 cr5;
-	u16 ar6;
-	u16 res13;
-	u32 mr6;
-	u16 res14;
-	u16 cr6;
-	u16 ar7;
-	u16 res15;
-	u32 mr7;
-	u16 res16;
-	u16 cr7;
-} csctrl_t;
-
 /* DMA module registers, offset 0x100
  */
 typedef struct	dma_ctrl {
diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h
index f0ae599..dd526a1 100644
--- a/include/asm-m68k/immap_5282.h
+++ b/include/asm-m68k/immap_5282.h
@@ -63,6 +63,7 @@
 #define MMAP_CFMMEM	(CONFIG_SYS_MBAR + 0x04000000)
#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
 #include <asm/coldfire/flexcan.h>
 #include <asm/coldfire/intctrl.h>
 #include <asm/coldfire/qspi.h>
@@ -101,57 +102,6 @@ typedef struct canex_ctrl {
    can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
 } canex_t;
-/* Flexbus module Chip select registers */
-typedef struct fbcs_ctrl {
-	u16 csar0;		/* 0x00 Chip-Select Address Register 0 */
-	u16 res0;
-	u32 csmr0;		/* 0x04 Chip-Select Mask Register 0 */
-	u16 res1;		/* 0x08 */
-	u16 cscr0;		/* 0x0A Chip-Select Control Register 0 */
-
-	u16 csar1;		/* 0x0C Chip-Select Address Register 1 */
-	u16 res2;
-	u32 csmr1;		/* 0x10 Chip-Select Mask Register 1 */
-	u16 res3;		/* 0x14 */
-	u16 cscr1;		/* 0x16 Chip-Select Control Register 1 */
-
-	u16 csar2;		/* 0x18 Chip-Select Address Register 2 */
-	u16 res4;
-	u32 csmr2;		/* 0x1C Chip-Select Mask Register 2 */
-	u16 res5;		/* 0x20 */
-	u16 cscr2;		/* 0x22 Chip-Select Control Register 2 */
-
-	u16 csar3;		/* 0x24 Chip-Select Address Register 3 */
-	u16 res6;
-	u32 csmr3;		/* 0x28 Chip-Select Mask Register 3 */
-	u16 res7;		/* 0x2C */
-	u16 cscr3;		/* 0x2E Chip-Select Control Register 3 */
-
-	u16 csar4;		/* 0x30 Chip-Select Address Register 4 */
-	u16 res8;
-	u32 csmr4;		/* 0x34 Chip-Select Mask Register 4 */
-	u16 res9;		/* 0x38 */
-	u16 cscr4;		/* 0x3A Chip-Select Control Register 4 */
-
-	u16 csar5;		/* 0x3C Chip-Select Address Register 5 */
-	u16 res10;
-	u32 csmr5;		/* 0x40 Chip-Select Mask Register 5 */
-	u16 res11;		/* 0x44 */
-	u16 cscr5;		/* 0x46 Chip-Select Control Register 5 */
-
-	u16 csar6;		/* 0x48 Chip-Select Address Register 5 */
-	u16 res12;
-	u32 csmr6;		/* 0x4C Chip-Select Mask Register 5 */
-	u16 res13;		/* 0x50 */
-	u16 cscr6;		/* 0x52 Chip-Select Control Register 5 */
-
-	u16 csar7;		/* 0x54 Chip-Select Address Register 5 */
-	u16 res14;
-	u32 csmr7;		/* 0x58 Chip-Select Mask Register 5 */
-	u16 res15;		/* 0x5C */
-	u16 cscr7;		/* 0x5E Chip-Select Control Register 5 */
-} fbcs_t;
-
 /* Clock Module registers */
 typedef struct pll_ctrl {
    u16 syncr;		/* 0x00 synthesizer control register */
diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h
index 1733be6..22987ac 100644
--- a/include/asm-m68k/m5235.h
+++ b/include/asm-m68k/m5235.h
@@ -163,46 +163,6 @@
 #define SDRAMC_DMRn_V			(0x00000001)
/*********************************************************************
-* FlexBus Chip Selects (FBCS)
-*********************************************************************/
-/* Bit definitions and macros for FBCS_CSMR */
-#define FBCS_CSMR_BAM(x)		(((x)&0xFFFF)<<16)
-#define FBCS_CSMR_BAM_4G		(0xFFFF0000)
-#define FBCS_CSMR_BAM_2G		(0x7FFF0000)
-#define FBCS_CSMR_BAM_1G		(0x3FFF0000)
-#define FBCS_CSMR_BAM_1024M		(0x3FFF0000)
-#define FBCS_CSMR_BAM_512M		(0x1FFF0000)
-#define FBCS_CSMR_BAM_256M		(0x0FFF0000)
-#define FBCS_CSMR_BAM_128M		(0x07FF0000)
-#define FBCS_CSMR_BAM_64M		(0x03FF0000)
-#define FBCS_CSMR_BAM_32M		(0x01FF0000)
-#define FBCS_CSMR_BAM_16M		(0x00FF0000)
-#define FBCS_CSMR_BAM_8M		(0x007F0000)
-#define FBCS_CSMR_BAM_4M		(0x003F0000)
-#define FBCS_CSMR_BAM_2M		(0x001F0000)
-#define FBCS_CSMR_BAM_1M		(0x000F0000)
-#define FBCS_CSMR_BAM_1024K		(0x000F0000)
-#define FBCS_CSMR_BAM_512K		(0x00070000)
-#define FBCS_CSMR_BAM_256K		(0x00030000)
-#define FBCS_CSMR_BAM_128K		(0x00010000)
-#define FBCS_CSMR_BAM_64K		(0x00000000)
-#define FBCS_CSMR_WP			(0x00000100)
-#define FBCS_CSMR_V			(0x00000001)
-
-/* Bit definitions and macros for FBCS_CSCR */
-#define FBCS_CSCR_SRWS(x)		(((x)&0x03)<<14)
-#define FBCS_CSCR_IWS(x)		(((x)&0x0F)<<10)
-#define FBCS_CSCR_AA			(0x0100)
-#define FBCS_CSCR_PS_MASK		(0x00C0)
-#define FBCS_CSCR_PS_32			(0x0000)
-#define FBCS_CSCR_PS_16			(0x0080)
-#define FBCS_CSCR_PS_8			(0x0040)
-#define FBCS_CSCR_BEM			(0x0020)
-#define FBCS_CSCR_BSTR			(0x0010)
-#define FBCS_CSCR_BSTW			(0x0008)
-#define FBCS_CSCR_SWWS(x)		((x)&0x07)
-
-/*********************************************************************
 * Interrupt Controller (INTC)
 *********************************************************************/
 #define INT0_LO_RSVD0			(0)
diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h
index feb675c..fa0cb14 100644
--- a/include/asm-m68k/m5249.h
+++ b/include/asm-m68k/m5249.h
@@ -77,19 +77,6 @@
 #define MCFSIM_IPR		0x40	/* Interrupt Pend reg (r/w) */
 #define MCFSIM_IMR		0x44	/* Interrupt Mask reg (r/w) */
-#define MCFSIM_CSAR0		0x80	/* CS 0 Address 0 reg (r/w) */
-#define MCFSIM_CSMR0		0x84	/* CS 0 Mask 0 reg (r/w) */
-#define MCFSIM_CSCR0		0x8a	/* CS 0 Control reg (r/w) */
-#define MCFSIM_CSAR1		0x8c	/* CS 1 Address reg (r/w) */
-#define MCFSIM_CSMR1		0x90	/* CS 1 Mask reg (r/w) */
-#define MCFSIM_CSCR1		0x96	/* CS 1 Control reg (r/w) */
-#define MCFSIM_CSAR2		0x98	/* CS 2 Address reg (r/w) */
-#define MCFSIM_CSMR2		0x9c	/* CS 2 Mask reg (r/w) */
-#define MCFSIM_CSCR2		0xa2	/* CS 2 Control reg (r/w) */
-#define MCFSIM_CSAR3		0xa4	/* CS 3 Address reg (r/w) */
-#define MCFSIM_CSMR3		0xa8	/* CS 3 Mask reg (r/w) */
-#define MCFSIM_CSCR3		0xae	/* CS 3 Control reg (r/w) */
-
 #define MCFSIM_DCR		0x100	/* DRAM Control reg (r/w) */
 #define MCFSIM_DACR0		0x108	/* DRAM 0 Addr and Ctrl (r/w) */
 #define MCFSIM_DMR0		0x10c	/* DRAM 0 Mask reg (r/w) */
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
index 772c7e0..d59a8b2 100644
--- a/include/asm-m68k/m5282.h
+++ b/include/asm-m68k/m5282.h
@@ -440,29 +440,6 @@
 #define MCFWTM_WCNTR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
 #define MCFWTM_WSR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
-/*  Chip SELECT Module CSM */
-#define MCFCSM_CSAR0		(*(vu_short *)(CONFIG_SYS_MBAR+0x00000080))
-#define MCFCSM_CSMR0		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000084))
-#define MCFCSM_CSCR0		(*(vu_short *)(CONFIG_SYS_MBAR+0x0000008a))
-#define MCFCSM_CSAR1		(*(vu_short *)(CONFIG_SYS_MBAR+0x0000008C))
-#define MCFCSM_CSMR1		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000090))
-#define MCFCSM_CSCR1		(*(vu_short *)(CONFIG_SYS_MBAR+0x00000096))
-#define MCFCSM_CSAR2		(*(vu_short *)(CONFIG_SYS_MBAR+0x00000098))
-#define MCFCSM_CSMR2		(*(vu_long *) (CONFIG_SYS_MBAR+0x0000009C))
-#define MCFCSM_CSCR2		(*(vu_short *)(CONFIG_SYS_MBAR+0x000000A2))
-#define MCFCSM_CSAR3		(*(vu_short *)(CONFIG_SYS_MBAR+0x000000A4))
-#define MCFCSM_CSMR3		(*(vu_long *) (CONFIG_SYS_MBAR+0x000000A8))
-#define MCFCSM_CSCR3		(*(vu_short *)(CONFIG_SYS_MBAR+0x000000AE))
-
-#define MCFCSM_CSMR_BAM(x)	((x) & 0xFFFF0000)
-#define MCFCSM_CSMR_WP		(1<<8)
-#define MCFCSM_CSMR_V		(0x01)
-#define MCFCSM_CSCR_WS(x)	((x & 0x0F)<<10)
-#define MCFCSM_CSCR_AA		(0x0100)
-#define MCFCSM_CSCR_PS_32	(0x0000)
-#define MCFCSM_CSCR_PS_8	(0x0040)
-#define MCFCSM_CSCR_PS_16	(0x0080)
-
 /*********************************************************************
 * General Purpose Timer (GPT) Module
 *********************************************************************/
diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
index 0aa50f1..c7ebed1 100644
--- a/include/asm-m68k/m5329.h
+++ b/include/asm-m68k/m5329.h
@@ -187,65 +187,6 @@
 #define CFATR_TYPE			(0x01)
/*********************************************************************
-* FlexBus Chip Selects (FBCS)
-*********************************************************************/
-/* Bit definitions and macros for FBCS_CSAR */
-#define CSAR_BA(x)			(((x)&0xFFFF)<<16)
-
-/* Bit definitions and macros for FBCS_CSMR */
-#define CSMR_BAM(x)			(((x)&0xFFFF)<<16)
-#define CSMR_BAM_4G			(0xFFFF0000)
-#define CSMR_BAM_2G			(0x7FFF0000)
-#define CSMR_BAM_1G			(0x3FFF0000)
-#define CSMR_BAM_1024M			(0x3FFF0000)
-#define CSMR_BAM_512M			(0x1FFF0000)
-#define CSMR_BAM_256M			(0x0FFF0000)
-#define CSMR_BAM_128M			(0x07FF0000)
-#define CSMR_BAM_64M			(0x03FF0000)
-#define CSMR_BAM_32M			(0x01FF0000)
-#define CSMR_BAM_16M			(0x00FF0000)
-#define CSMR_BAM_8M			(0x007F0000)
-#define CSMR_BAM_4M			(0x003F0000)
-#define CSMR_BAM_2M			(0x001F0000)
-#define CSMR_BAM_1M			(0x000F0000)
-#define CSMR_BAM_1024K			(0x000F0000)
-#define CSMR_BAM_512K			(0x00070000)
-#define CSMR_BAM_256K			(0x00030000)
-#define CSMR_BAM_128K			(0x00010000)
-#define CSMR_BAM_64K			(0x00000000)
-#define CSMR_WP				(0x00000100)
-#define CSMR_V				(0x00000001)
-
-/* Bit definitions and macros for FBCS_CSCR */
-#define CSCR_SWS(x)			(((x)&0x3F)<<26)
-#define CSCR_ASET(x)			(((x)&0x03)<<20)
-#define CSCR_SWSEN			(0x00800000)
-#define CSCR_ASET_4CLK			(0x00300000)
-#define CSCR_ASET_3CLK			(0x00200000)
-#define CSCR_ASET_2CLK			(0x00100000)
-#define CSCR_ASET_1CLK			(0x00000000)
-#define CSCR_RDAH(x)			(((x)&0x03)<<18)
-#define CSCR_RDAH_4CYC			(0x000C0000)
-#define CSCR_RDAH_3CYC			(0x00080000)
-#define CSCR_RDAH_2CYC			(0x00040000)
-#define CSCR_RDAH_1CYC			(0x00000000)
-#define CSCR_WRAH(x)			(((x)&0x03)<<16)
-#define CSCR_WDAH_4CYC			(0x00003000)
-#define CSCR_WDAH_3CYC			(0x00002000)
-#define CSCR_WDAH_2CYC			(0x00001000)
-#define CSCR_WDAH_1CYC			(0x00000000)
-#define CSCR_WS(x)			(((x)&0x3F)<<10)
-#define CSCR_SBM			(0x00000200)
-#define CSCR_AA				(0x00000100)
-#define CSCR_PS_MASK			(0x000000C0)
-#define CSCR_PS_32			(0x00000000)
-#define CSCR_PS_16			(0x00000080)
-#define CSCR_PS_8			(0x00000040)
-#define CSCR_BEM			(0x00000020)
-#define CSCR_BSTR			(0x00000010)
-#define CSCR_BSTW			(0x00000008)
-
-/*********************************************************************
 * Reset Controller Module (RCM)
 *********************************************************************/
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index 876ec20..a13db7c 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -178,7 +178,7 @@
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_SDRAM_BASE1
 #define	CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_SDRAM_SIZE1
-#define CONFIG_SYS_FLASH_BASE		0xFFE00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 #define	CONFIG_SYS_INT_FLASH_BASE	0xF0000000
 #define CONFIG_SYS_INT_FLASH_ENABLE	0x21
@@ -218,17 +218,13 @@
  * Memory bank definitions
  */
-#define CONFIG_SYS_CS0_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		2*1024*1024
-#define CONFIG_SYS_CS0_WIDTH		16
-#define CONFIG_SYS_CS0_RO		0
-#define CONFIG_SYS_CS0_WS		6
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
#define CONFIG_SYS_CS3_BASE		0xE0000000
-#define CONFIG_SYS_CS3_SIZE		1*1024*1024
-#define CONFIG_SYS_CS3_WIDTH		16
-#define CONFIG_SYS_CS3_RO		0
-#define CONFIG_SYS_CS3_WS		6
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS3_MASK		0x000F0001
/*-----------------------------------------------------------------------
  * Port configuration
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index e6c87ef..8c66f87 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -215,7 +215,7 @@
 #	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 #endif
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
/* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -251,13 +251,13 @@
  * CS7 - Available
  */
 #ifdef NORFLASH_PS32BIT
-#	define CONFIG_SYS_CS0_BASE	0xFFC0
+#	define CONFIG_SYS_CS0_BASE	0xFFC00000
 #	define CONFIG_SYS_CS0_MASK	0x003f0001
-#	define CONFIG_SYS_CS0_CTRL	0x1D00
+#	define CONFIG_SYS_CS0_CTRL	0x00001D00
 #else
-#	define CONFIG_SYS_CS0_BASE	0xFFE0
+#	define CONFIG_SYS_CS0_BASE	0xFFE00000
 #	define CONFIG_SYS_CS0_MASK	0x001f0001
-#	define CONFIG_SYS_CS0_CTRL	0x1D80
+#	define CONFIG_SYS_CS0_CTRL	0x00001D80
 #endif
#endif				/* _M5329EVB_H */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 8699ef9..e3830e5 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -125,7 +125,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CSAR0 << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
#if 0 /* test-only */
 #define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@@ -170,15 +170,15 @@
  */
/* CS0 - AMD Flash, address 0xffc00000 */
-#define	CONFIG_SYS_CSAR0		0xffe0
-#define	CONFIG_SYS_CSCR0		0x1980		/* WS=0110, AA=1, PS=10         */
+#define	CONFIG_SYS_CS0_BASE		0xffe00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CONFIG_SYS_CSMR0		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
/* CS1 - FPGA, address 0xe0000000 */
-#define	CONFIG_SYS_CSAR1		0xe000
-#define	CONFIG_SYS_CSCR1		0x0d80		/* WS=0011, AA=1, PS=10         */
-#define	CONFIG_SYS_CSMR1		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
  * Port configuration
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 3a5c12f..378e45a 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -90,7 +90,7 @@
#define CONFIG_DRIVER_DM9000
 #ifdef CONFIG_DRIVER_DM9000
-#	define CONFIG_DM9000_BASE	((CONFIG_SYS_CSAR1 << 16) | 0x300)
+#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
 #	define DM9000_IO		CONFIG_DM9000_BASE
 #	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
 #	undef CONFIG_DM9000_DEBUG
@@ -202,7 +202,7 @@
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CSAR0 << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	1000
@@ -233,21 +233,13 @@
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
-#define CONFIG_SYS_CSAR0		0xFF80
-#define CONFIG_SYS_CSMR0		0x007F0021
-#define CONFIG_SYS_CSCR0		0x1D80
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		0x007F0021
+#define CONFIG_SYS_CS0_CTRL		0x00001D80
-#define CONFIG_SYS_CSAR1               0xE000
-#define CONFIG_SYS_CSMR1               0x00000001
-#define CONFIG_SYS_CSCR1               0x3DD8
-
-#define CONFIG_SYS_CSAR2		0
-#define CONFIG_SYS_CSMR2		0
-#define CONFIG_SYS_CSCR2		0
-
-#define CONFIG_SYS_CSAR3		0
-#define CONFIG_SYS_CSMR3		0
-#define CONFIG_SYS_CSCR3		0
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		0x00000001
+#define CONFIG_SYS_CS1_CTRL		0x00003DD8
/*-----------------------------------------------------------------------
  * Port configuration
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index c2cd62b..86de97d 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -166,7 +166,7 @@
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	1000
@@ -182,21 +182,9 @@
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
-#define CONFIG_SYS_CSAR0		0xFFE0
-#define CONFIG_SYS_CSMR0		0x001F0021
-#define CONFIG_SYS_CSCR0		0x1D80
-
-#define CONFIG_SYS_CSAR1		0
-#define CONFIG_SYS_CSMR1		0
-#define CONFIG_SYS_CSCR1		0
-
-#define CONFIG_SYS_CSAR2		0
-#define CONFIG_SYS_CSMR2		0
-#define CONFIG_SYS_CSCR2		0
-
-#define CONFIG_SYS_CSAR3		0
-#define CONFIG_SYS_CSMR3		0
-#define CONFIG_SYS_CSCR3		0
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_MASK		0x001F0021
+#define CONFIG_SYS_CS0_CTRL		0x00001D80
/*-----------------------------------------------------------------------
  * Port configuration
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 1f3539e..db48d76 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -173,7 +173,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#ifdef CONFIG_MONITOR_IS_IN_RAM
 #define CONFIG_SYS_MONITOR_BASE	0x20000
@@ -211,13 +211,13 @@
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CONFIG_SYS_AR0_PRELIM		(CONFIG_SYS_FLASH_BASE >> 16)
-#define CONFIG_SYS_CR0_PRELIM		0x1980
-#define CONFIG_SYS_MR0_PRELIM		0x001F0001
+#define CONFIG_SYS_CS0_BASE		0xffe00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
-#define CONFIG_SYS_AR1_PRELIM		0x3000
-#define CONFIG_SYS_CR1_PRELIM		0x1900
-#define CONFIG_SYS_MR1_PRELIM		0x00070001
+#define CONFIG_SYS_CS1_BASE		0x30000000
+#define CONFIG_SYS_CS1_CTRL		0x00001900
+#define CONFIG_SYS_CS1_MASK		0x00070001
/*-----------------------------------------------------------------------
  * Port configuration
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index a8a2655..15590cf 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -165,7 +165,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define	CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 #define	CONFIG_SYS_INT_FLASH_BASE	0xf0000000
 #define CONFIG_SYS_INT_FLASH_ENABLE	0x21
@@ -212,18 +212,10 @@
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CONFIG_SYS_CS0_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		2*1024*1024
-#define CONFIG_SYS_CS0_WIDTH		16
-#define CONFIG_SYS_CS0_RO		0
-#define CONFIG_SYS_CS0_WS		6
-/*
-#define CONFIG_SYS_CS3_BASE		0xE0000000
-#define CONFIG_SYS_CS3_SIZE		1*1024*1024
-#define CONFIG_SYS_CS3_WIDTH		16
-#define CONFIG_SYS_CS3_RO		0
-#define CONFIG_SYS_CS3_WS		6
-*/
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
+
 /*-----------------------------------------------------------------------
  * Port configuration
  */
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 18ffbfd..25f3a26 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -206,7 +206,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xffc00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#if 0 /* test-only */
 #define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@@ -257,15 +257,15 @@
  */
/* CS0 - AMD Flash, address 0xffc00000 */
-#define	CONFIG_SYS_CSAR0               0xffc0
-#define	CONFIG_SYS_CSCR0               0x1980          /* WS=0110, AA=1, PS=10         */
+#define	CONFIG_SYS_CS0_BASE		0xffc00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CONFIG_SYS_CSMR0               0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
/* CS1 - FPGA, address 0xe0000000 */
-#define	CONFIG_SYS_CSAR1               0xe000
-#define	CONFIG_SYS_CSCR1               0x0d80          /* WS=0011, AA=1, PS=10         */
-#define	CONFIG_SYS_CSMR1               0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
  * Port configuration
-- 
1.5.6.4


    

[U-Boot] [PATCH 07/19] ColdFire: Modules header files cleanup - 6

Tsi-Chung Liew

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