[U-Boot] [PATCH 00/24] Lift mpc85xx config options to Kconfig
In this set, more mpc85xx config options are moved into Kconfig, including some shared configuration for DDR, crypto, mmc, etc.
York Sun (24): powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 powerpc: T1023RDB: Remove macro CONFIG_T1023RDB powerpc: T1024RDB: Remove macro CONFIG_T1024RDB powerpc: T1040QDS: Remove macro CONFIG_T1040QDS powerpc: T2080QDS: Remove macro T2080QDS powerpc: T2080RDB: Remove macro CONFIG_T2080RDB powerpc: T2081QDS: Remove macro T2081QDS powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS fsl_ddr: Move DDR config options to driver Kconfig arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig powerpc: mpc85xx: Remove unused ifdef in config header powerpc: E6500: Move macro CONFIG_E6500 to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to Kconfig powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 to Kconfig
README | 9 - arch/arm/Kconfig | 14 + arch/arm/cpu/armv7/ls102xa/Kconfig | 61 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 87 ++- arch/arm/include/asm/arch-fsl-layerscape/config.h | 30 +- arch/arm/include/asm/arch-ls102xa/config.h | 6 - arch/powerpc/Kconfig | 7 + arch/powerpc/cpu/mpc83xx/Kconfig | 6 + arch/powerpc/cpu/mpc85xx/Kconfig | 648 +++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/Makefile | 4 - arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 22 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 18 +- arch/powerpc/cpu/mpc86xx/Kconfig | 4 + arch/powerpc/include/asm/config.h | 11 - arch/powerpc/include/asm/config_mpc85xx.h | 331 +---------- arch/powerpc/include/asm/config_mpc86xx.h | 2 - arch/powerpc/include/asm/fsl_secure_boot.h | 7 +- arch/powerpc/include/asm/immap_85xx.h | 6 +- board/freescale/b4860qds/ddr.c | 4 +- board/freescale/corenet_ds/ddr.c | 6 +- board/freescale/t102xrdb/Makefile | 2 +- board/freescale/t102xrdb/ddr.c | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 10 +- board/freescale/t102xrdb/t102xrdb.c | 22 +- board/freescale/t102xrdb/t102xrdb.h | 2 +- board/freescale/t208xqds/Makefile | 4 +- board/freescale/t208xqds/eth_t208xqds.c | 32 +- board/freescale/t208xqds/t208xqds.c | 8 +- board/freescale/t208xrdb/Makefile | 2 +- configs/MPC8349EMDS_defconfig | 1 + configs/MPC8536DS_36BIT_defconfig | 1 + configs/MPC8536DS_SDCARD_defconfig | 1 + configs/MPC8536DS_SPIFLASH_defconfig | 1 + configs/MPC8536DS_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/MPC8572DS_36BIT_defconfig | 1 + configs/MPC8572DS_defconfig | 1 + configs/MPC8610HPCD_defconfig | 1 + configs/MPC8641HPCN_36BIT_defconfig | 1 + configs/MPC8641HPCN_defconfig | 1 + configs/T1023RDB_NAND_defconfig | 3 +- configs/T1023RDB_SDCARD_defconfig | 3 +- configs/T1023RDB_SECURE_BOOT_defconfig | 2 +- configs/T1023RDB_SPIFLASH_defconfig | 3 +- configs/T1023RDB_defconfig | 2 +- configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 2 +- configs/T1024QDS_DDR4_defconfig | 2 +- configs/T1024QDS_NAND_defconfig | 1 + configs/T1024QDS_SDCARD_defconfig | 1 + configs/T1024QDS_SECURE_BOOT_defconfig | 1 + configs/T1024QDS_SPIFLASH_defconfig | 1 + configs/T1024QDS_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 3 +- configs/T1024RDB_SDCARD_defconfig | 3 +- configs/T1024RDB_SECURE_BOOT_defconfig | 2 +- configs/T1024RDB_SPIFLASH_defconfig | 3 +- configs/T1024RDB_defconfig | 2 +- configs/T1040D4RDB_NAND_defconfig | 3 +- configs/T1040D4RDB_SDCARD_defconfig | 3 +- configs/T1040D4RDB_SECURE_BOOT_defconfig | 2 +- configs/T1040D4RDB_SPIFLASH_defconfig | 3 +- configs/T1040D4RDB_defconfig | 2 +- configs/T1040QDS_DDR4_defconfig | 2 +- configs/T1040QDS_SECURE_BOOT_defconfig | 1 + configs/T1040QDS_defconfig | 1 + configs/T1040RDB_NAND_defconfig | 1 + configs/T1040RDB_SDCARD_defconfig | 1 + configs/T1040RDB_SECURE_BOOT_defconfig | 1 + configs/T1040RDB_SPIFLASH_defconfig | 1 + configs/T1040RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 3 +- configs/T1042D4RDB_SDCARD_defconfig | 3 +- configs/T1042D4RDB_SECURE_BOOT_defconfig | 2 +- configs/T1042D4RDB_SPIFLASH_defconfig | 3 +- configs/T1042D4RDB_defconfig | 2 +- configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 1 + configs/T1042RDB_PI_NAND_defconfig | 1 + configs/T1042RDB_PI_SDCARD_defconfig | 1 + configs/T1042RDB_PI_SPIFLASH_defconfig | 1 + configs/T1042RDB_PI_defconfig | 1 + configs/T1042RDB_SECURE_BOOT_defconfig | 1 + configs/T1042RDB_defconfig | 1 + configs/ls1046aqds_defconfig | 1 - configs/ls1046aqds_nand_defconfig | 2 +- configs/ls1046aqds_qspi_defconfig | 1 - configs/ls1046aqds_sdcard_ifc_defconfig | 2 +- configs/ls1046aqds_sdcard_qspi_defconfig | 2 +- configs/ls1046ardb_emmc_defconfig | 2 +- configs/ls1046ardb_qspi_defconfig | 1 - configs/ls1046ardb_sdcard_defconfig | 2 +- configs/ls2080a_emu_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080aqds_qspi_defconfig | 2 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +- configs/ls2080ardb_defconfig | 3 +- configs/ls2080ardb_nand_defconfig | 2 +- configs/sbc8548_PCI_33_PCIE_defconfig | 1 + configs/sbc8548_PCI_33_defconfig | 1 + configs/sbc8548_PCI_66_PCIE_defconfig | 1 + configs/sbc8548_PCI_66_defconfig | 1 + configs/sbc8548_defconfig | 1 + configs/xpedite517x_defconfig | 1 + configs/xpedite520x_defconfig | 1 + configs/xpedite537x_defconfig | 1 + drivers/Kconfig | 2 + drivers/crypto/fsl/Kconfig | 39 ++ drivers/ddr/fsl/Kconfig | 172 ++++++ drivers/ddr/fsl/Makefile | 2 +- drivers/ddr/fsl/arm_ddr_gen3.c | 6 +- drivers/ddr/fsl/ctrl_regs.c | 6 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 6 +- drivers/ddr/fsl/interactive.c | 14 +- drivers/ddr/fsl/main.c | 30 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 6 +- drivers/ddr/fsl/options.c | 30 +- drivers/ddr/fsl/util.c | 28 +- drivers/mmc/Kconfig | 12 + drivers/net/fm/Makefile | 2 - include/configs/B4860QDS.h | 7 +- include/configs/BSC9131RDB.h | 4 - include/configs/BSC9132QDS.h | 4 - include/configs/C29XPCIE.h | 3 - include/configs/MPC8308RDB.h | 1 - include/configs/MPC8349EMDS.h | 9 +- include/configs/MPC8536DS.h | 6 - include/configs/MPC8540ADS.h | 6 - include/configs/MPC8541CDS.h | 4 - include/configs/MPC8544DS.h | 6 - include/configs/MPC8548CDS.h | 6 - include/configs/MPC8555CDS.h | 4 - include/configs/MPC8560ADS.h | 4 - include/configs/MPC8568MDS.h | 6 - include/configs/MPC8569MDS.h | 6 - include/configs/MPC8572DS.h | 4 - include/configs/MPC8610HPCD.h | 2 - include/configs/MPC8641HPCN.h | 2 - include/configs/P1010RDB.h | 4 - include/configs/P1022DS.h | 4 - include/configs/P1023RDB.h | 3 - include/configs/P2041RDB.h | 6 +- include/configs/T102xQDS.h | 8 +- include/configs/T102xRDB.h | 51 +- include/configs/T1040QDS.h | 10 +- include/configs/T104xRDB.h | 9 +- include/configs/T208xQDS.h | 8 +- include/configs/T208xRDB.h | 7 +- include/configs/T4240RDB.h | 7 +- include/configs/UCP1020.h | 7 - include/configs/colibri_vf.h | 2 - include/configs/controlcenterd.h | 4 - include/configs/corenet_ds.h | 6 +- include/configs/cyrus.h | 6 +- include/configs/hrcon.h | 1 - include/configs/km/kmp204x-common.h | 6 +- include/configs/mx6_common.h | 2 - include/configs/mx7_common.h | 2 - include/configs/p1_p2_rdb_pc.h | 6 - include/configs/p1_twr.h | 6 - include/configs/pcm052.h | 3 - include/configs/qemu-ppce500.h | 4 - include/configs/s32v234evb.h | 2 - include/configs/sbc8548.h | 4 - include/configs/sbc8641d.h | 2 - include/configs/socrates.h | 4 - include/configs/strider.h | 1 - include/configs/t4qds.h | 7 +- include/configs/ts4800.h | 2 - include/configs/vf610twr.h | 2 - include/configs/xpedite517x.h | 2 - include/configs/xpedite520x.h | 4 - include/configs/xpedite537x.h | 4 - include/configs/xpedite550x.h | 4 - include/fsl_ddr.h | 3 +- include/fsl_sec.h | 2 +- scripts/config_whitelist.txt | 85 --- 180 files changed, 1220 insertions(+), 1016 deletions(-) create mode 100644 drivers/ddr/fsl/Kconfig
Use Kconfig option for E500 and E500MC macros.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 30 ++++++++++++++++++++++++++++++ include/configs/B4860QDS.h | 3 --- include/configs/BSC9131RDB.h | 2 -- include/configs/BSC9132QDS.h | 2 -- include/configs/C29XPCIE.h | 2 -- include/configs/MPC8536DS.h | 4 ---- include/configs/MPC8540ADS.h | 4 ---- include/configs/MPC8541CDS.h | 2 -- include/configs/MPC8544DS.h | 4 ---- include/configs/MPC8548CDS.h | 4 ---- include/configs/MPC8555CDS.h | 2 -- include/configs/MPC8560ADS.h | 2 -- include/configs/MPC8568MDS.h | 4 ---- include/configs/MPC8569MDS.h | 4 ---- include/configs/MPC8572DS.h | 2 -- include/configs/P1010RDB.h | 3 --- include/configs/P1022DS.h | 2 -- include/configs/P1023RDB.h | 2 -- include/configs/P2041RDB.h | 3 --- include/configs/T102xQDS.h | 3 --- include/configs/T102xRDB.h | 3 --- include/configs/T1040QDS.h | 3 --- include/configs/T104xRDB.h | 3 --- include/configs/T208xQDS.h | 3 --- include/configs/T208xRDB.h | 3 --- include/configs/T4240RDB.h | 3 --- include/configs/UCP1020.h | 5 ----- include/configs/controlcenterd.h | 2 -- include/configs/corenet_ds.h | 3 --- include/configs/cyrus.h | 3 --- include/configs/km/kmp204x-common.h | 3 --- include/configs/p1_p2_rdb_pc.h | 4 ---- include/configs/p1_twr.h | 4 ---- include/configs/qemu-ppce500.h | 4 ---- include/configs/sbc8548.h | 2 -- include/configs/socrates.h | 2 -- include/configs/t4qds.h | 3 --- include/configs/xpedite520x.h | 2 -- include/configs/xpedite537x.h | 2 -- include/configs/xpedite550x.h | 2 -- scripts/config_whitelist.txt | 2 -- 41 files changed, 30 insertions(+), 115 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index e4873f5..6d8709e 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -323,10 +323,12 @@ endchoice
config ARCH_B4420 bool + select E500MC select FSL_LAW
config ARCH_B4860 bool + select E500MC select FSL_LAW
config ARCH_BSC9131 @@ -419,22 +421,27 @@ config ARCH_P2020
config ARCH_P2041 bool + select E500MC select FSL_LAW
config ARCH_P3041 bool + select E500MC select FSL_LAW
config ARCH_P4080 bool + select E500MC select FSL_LAW
config ARCH_P5020 bool + select E500MC select FSL_LAW
config ARCH_P5040 bool + select E500MC select FSL_LAW
config ARCH_QEMU_E500 @@ -442,36 +449,59 @@ config ARCH_QEMU_E500
config ARCH_T1023 bool + select E500MC select FSL_LAW
config ARCH_T1024 bool + select E500MC select FSL_LAW
config ARCH_T1040 bool + select E500MC select FSL_LAW
config ARCH_T1042 bool + select E500MC select FSL_LAW
config ARCH_T2080 bool + select E500MC select FSL_LAW
config ARCH_T2081 bool + select E500MC select FSL_LAW
config ARCH_T4160 bool + select E500MC select FSL_LAW
config ARCH_T4240 bool + select E500MC select FSL_LAW
+config BOOKE + bool + default y + +config E500 + bool + default y + help + Enable PowerPC E500 cores, including e500v1, e500v2, e500mc + +config E500MC + bool + help + Enble PowerPC E500MC core + config FSL_LAW bool help diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 7d3ebf3..e3ed317 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -50,9 +50,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index eecbd75..33c015a 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -46,8 +46,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 5cfdbb2..b59a7cf 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -69,8 +69,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 79cf09e..a47d23c 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -68,8 +68,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index d8f7961..d43c429 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -37,10 +37,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif
-/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ - #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 9fd7109..02ad0b0 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -18,10 +18,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ - /* * default CCARBAR is at 0xff700000 * assume U-Boot is less than 0.5MB diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 2dad188..0d850fe 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -14,8 +14,6 @@ #define __CONFIG_H
/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 4bab893..96c0b11 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -11,10 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ - #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 41ba9e7..7ffacf8 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -13,10 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ - #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 #endif diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 0f035dd..9f75f9b 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -14,8 +14,6 @@ #define __CONFIG_H
/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 343287e..871d14e 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -19,8 +19,6 @@ #define __CONFIG_H
/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_CPM2 1 /* has CPM2 */
/* diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 3cddb5f..84fea61 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -10,10 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ - #define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_SYS_SRIO diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index bd52054..ded22b7 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -10,10 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ - #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
#define CONFIG_SYS_SRIO diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index bffcad1..1c7dbc8 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -26,8 +26,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 78e0064..a01a739 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -11,7 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> #define CONFIG_NAND_FSL_IFC
@@ -131,8 +130,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 81e8c29..18ea9ac 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -86,8 +86,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index d5728a1..1ebe836 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -23,8 +23,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_MP /* support multiple processors */
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 91e5f8b..551200b 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -28,9 +28,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index fda83d2..4bf4ac4 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -12,9 +12,6 @@ #define __T1024QDS_H
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ #define CONFIG_ENABLE_36BIT_PHYS diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 054b323..f3ba0cd 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -12,9 +12,6 @@ #define __T1024RDB_H
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ #define CONFIG_ENABLE_36BIT_PHYS diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 00676dd..8e13f3b 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -36,9 +36,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 7521dd0..7f2de86 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -10,7 +10,6 @@ /* * T104x RDB board configuration file */ -#define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h>
#ifdef CONFIG_RAMBOOT_PBL @@ -147,8 +146,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index b984fcd..3e01ae7 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -25,9 +25,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ #define CONFIG_ENABLE_36BIT_PHYS diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index e013e72..fbdb0bd 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -18,9 +18,6 @@ #define CONFIG_FSL_SATA_V2
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ #define CONFIG_ENABLE_36BIT_PHYS diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index fd5dbc5..b890c10 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -60,9 +60,6 @@ #define CONFIG_CMD_REGINFO
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index c194ec7..e931f38 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -117,11 +117,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif
-/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 -/* #define CONFIG_MPC85xx */ - #define CONFIG_MP
#define CONFIG_ENV_OVERWRITE diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 971549e..744ff50 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -35,8 +35,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_CONTROLCENTERD #define CONFIG_MP /* support multiple processors */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c4d172d..5720386 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -46,9 +46,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 45caf9f..00dc58b 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -39,9 +39,6 @@ #endif
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index affcb48..87f1932 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -29,9 +29,6 @@ #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c20ef5e..b95be2a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -258,10 +258,6 @@ #endif #endif
-/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 - #define CONFIG_MP
#define CONFIG_FSL_ELBC diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 5ff2e35..f7ec5a2 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -38,10 +38,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif
-/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 - #define CONFIG_MP
#define CONFIG_FSL_ELBC diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 2c85f65..9517674 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -12,10 +12,6 @@
#define CONFIG_CMD_REGINFO
-/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ - #undef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 617be27..b81ff75 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -36,8 +36,6 @@ /* * High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */
/* diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 81afed0..d148f87 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -18,8 +18,6 @@ #define __CONFIG_H
/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_SOCRATES 1
#define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index e2b1171..91982a4 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -13,9 +13,6 @@ #define CONFIG_CMD_REGINFO
/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index fee8c34..22ada4c 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -14,8 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_XPEDITE5200 1 #define CONFIG_SYS_BOARD_NAME "XPedite5200" #define CONFIG_SYS_FORM_PMC_XMC 1 diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 7e811d5..73a8a20 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -14,8 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_SYS_BOARD_NAME "XPedite5370" #define CONFIG_SYS_FORM_3U_VPX 1 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 4dfb79d..7582813 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -14,8 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_XPEDITE550X 1 #define CONFIG_SYS_BOARD_NAME "XPedite5500" #define CONFIG_SYS_FORM_PMC_XMC 1 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8814841..da10149 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -958,8 +958,6 @@ CONFIG_DW_WDT_CLOCK_KHZ CONFIG_DYNAMIC_MMC_DEVNO CONFIG_E1000_NO_NVM CONFIG_E300 -CONFIG_E500 -CONFIG_E500MC CONFIG_E5500 CONFIG_E6500 CONFIG_EBCAW_VAL
On Wed, Dec 28, 2016 at 08:43:27AM -0800, York Sun wrote:
Use Kconfig option for E500 and E500MC macros.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use Kconfig option for SYS_NUM_TLBCAMS and clean up existing macros.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 8 ++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 7 ------- 2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 6d8709e..2b1d0f6 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -647,6 +647,14 @@ config SYS_FSL_NUM_LAWS Number of local access windows. This is fixed per SoC. If not sure, do not change.
+config SYS_NUM_TLBCAMS + int "Number of TLB CAM entries" + default 64 if E500MC + default 16 + help + Number of TLB CAM entries for Book-E chips. 64 for E500MC, + 16 for other E500 SoCs. + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8cfc612..5761218 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -24,13 +24,6 @@ #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SEC_MON_BE
-/* Number of TLB CAM entries we have on FSL Book-E chips */ -#if defined(CONFIG_E500MC) -#define CONFIG_SYS_NUM_TLBCAMS 64 -#elif defined(CONFIG_E500) -#define CONFIG_SYS_NUM_TLBCAMS 16 -#endif - #if defined(CONFIG_ARCH_MPC8536) #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2
On Wed, Dec 28, 2016 at 08:43:28AM -0800, York Sun wrote:
Use Kconfig option for SYS_NUM_TLBCAMS and clean up existing macros.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.
Signed-off-by: York Sun york.sun@nxp.com ---
README | 9 ------- arch/powerpc/cpu/mpc85xx/Kconfig | 40 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 14 ----------- scripts/config_whitelist.txt | 1 - 4 files changed, 40 insertions(+), 24 deletions(-)
diff --git a/README b/README index 25cad2f..f6d3781 100644 --- a/README +++ b/README @@ -376,15 +376,6 @@ The following options need to be configured: Defines the string to utilize when trying to match PCIe device tree nodes for the given platform.
- CONFIG_SYS_PPC_E500_DEBUG_TLB - - Enables a temporary TLB entry to be used during boot to work - around limitations in e500v1 and e500v2 external debugger - support. This reduces the portions of the boot code where - breakpoints and single stepping do not work. The value of this - symbol should be set to the TLB1 entry to be used for this - purpose. - CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set, diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 2b1d0f6..7f04a09 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -338,14 +338,17 @@ config ARCH_BSC9131 config ARCH_BSC9132 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_C29X bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8536 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8540 bool @@ -358,10 +361,12 @@ config ARCH_MPC8541 config ARCH_MPC8544 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8548 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8555 bool @@ -386,22 +391,27 @@ config ARCH_MPC8572 config ARCH_P1010 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1011 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1020 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1021 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1022 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1023 bool @@ -410,14 +420,17 @@ config ARCH_P1023 config ARCH_P1024 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1025 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2020 bool select FSL_LAW + select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2041 bool @@ -655,6 +668,33 @@ config SYS_NUM_TLBCAMS Number of TLB CAM entries for Book-E chips. 64 for E500MC, 16 for other E500 SoCs.
+config SYS_PPC_E500_USE_DEBUG_TLB + bool + +config SYS_PPC_E500_DEBUG_TLB + int "Temporary TLB entry for external debugger" + depends on SYS_PPC_E500_USE_DEBUG_TLB + default 0 if ARCH_MPC8544 || ARCH_MPC8548 + default 1 if ARCH_MPC8536 + default 2 if ARCH_MPC8572 || \ + ARCH_P1011 || \ + ARCH_P1020 || \ + ARCH_P1021 || \ + ARCH_P1022 || \ + ARCH_P1024 || \ + ARCH_P1025 || \ + ARCH_P2020 + default 3 if ARCH_P1010 || \ + ARCH_BSC9132 || \ + ARCH_C29X + help + Select a temporary TLB entry to be used during boot to work + around limitations in e500v1 and e500v2 external debugger + support. This reduces the portions of the boot code where + breakpoints and single stepping do not work. The value of this + symbol should be set to the TLB1 entry to be used for this + purpose. If unsure, do not change. + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 5761218..cbaba36 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_FSL_SEC_MON_BE
#if defined(CONFIG_ARCH_MPC8536) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 @@ -39,13 +38,11 @@
#elif defined(CONFIG_ARCH_MPC8544) #define CONFIG_SYS_FSL_DDRC_GEN2 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8548) #define CONFIG_SYS_FSL_DDRC_GEN2 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 @@ -92,7 +89,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8572) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 @@ -101,7 +97,6 @@
#elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -126,7 +121,6 @@
/* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -137,7 +131,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1020) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -150,7 +143,6 @@ #endif
#elif defined(CONFIG_ARCH_P1021) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -164,7 +156,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 @@ -192,7 +183,6 @@
/* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -205,7 +195,6 @@ /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -218,7 +207,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -433,7 +421,6 @@ #define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_BSC9132) -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -721,7 +708,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2_1 #define CONFIG_SYS_FSL_SEC_COMPAT 6 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index da10149..2f33c2e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7211,7 +7211,6 @@ CONFIG_SYS_POWER_MANAGER CONFIG_SYS_PPC4XX_USB_ADDR CONFIG_SYS_PPC64 CONFIG_SYS_PPC_DDR_WIMGE -CONFIG_SYS_PPC_E500_DEBUG_TLB CONFIG_SYS_PQSPAR CONFIG_SYS_PRELIM_OR_AM CONFIG_SYS_PROMPT_HUSH_PS2
On Wed, Dec 28, 2016 at 08:43:29AM -0800, York Sun wrote:
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/arm/Kconfig | 4 ++ arch/arm/cpu/armv7/ls102xa/Kconfig | 2 + arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 - arch/arm/include/asm/arch-ls102xa/config.h | 1 - arch/powerpc/Kconfig | 2 + arch/powerpc/cpu/mpc85xx/Kconfig | 70 +++++++++++++++++++++++ arch/powerpc/include/asm/config.h | 1 - arch/powerpc/include/asm/config_mpc85xx.h | 30 ---------- drivers/crypto/fsl/Kconfig | 33 +++++++++++ include/configs/mx6_common.h | 1 - include/configs/mx7_common.h | 1 - scripts/config_whitelist.txt | 1 - 13 files changed, 115 insertions(+), 37 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 587f288..ff601ea 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -464,10 +464,14 @@ config ARCH_MESON config ARCH_MX7 bool "Freescale MX7" select CPU_V7 + select SYS_FSL_HAS_SEC if SECURE_BOOT + select SYS_FSL_SEC_COMPAT_4
config ARCH_MX6 bool "Freescale MX6" select CPU_V7 + select SYS_FSL_HAS_SEC if SECURE_BOOT + select SYS_FSL_SEC_COMPAT_4
config ARCH_MX5 bool "Freescale MX5" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index f94568a..e233aa4 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,6 +5,8 @@ config ARCH_LS1021A select SYS_HAS_SERDES select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5
menu "LS102xA architecture" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index cc0dc88..17b470d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -29,10 +29,14 @@ config ARCH_LS2080A select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 select SYS_FSL_HAS_DP_DDR + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SRDS_2
config FSL_LSCH2 bool + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index c50894a..f4f9eaa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -57,7 +57,6 @@
/* SEC */ #define CONFIG_SYS_FSL_SEC_LE -#define CONFIG_SYS_FSL_SEC_COMPAT 5
/* Security Monitor */ #define CONFIG_SYS_FSL_SEC_MON_LE @@ -135,7 +134,6 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ec65cc0..97c69e9 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -114,7 +114,6 @@ #define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_LS102XA -#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 18451d3..9fc1d5c 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -23,6 +23,8 @@ config MPC8260 config MPC83xx bool "MPC83xx" select CREATE_ARCH_SYMLINK + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2
config MPC85xx bool "MPC85xx" diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 7f04a09..1287ab6 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -325,29 +325,41 @@ config ARCH_B4420 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_B4860 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_BSC9131 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_BSC9132 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_C29X bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_6 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8536 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8540 @@ -357,20 +369,28 @@ config ARCH_MPC8540 config ARCH_MPC8541 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8544 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8548 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8555 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8560 bool @@ -379,83 +399,117 @@ config ARCH_MPC8560 config ARCH_MPC8568 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8569 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8572 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2
config ARCH_P1010 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1011 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1020 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1021 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1022 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1023 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_P1024 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1025 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2020 bool select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2041 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_P3041 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_P4080 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_P5020 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_P5040 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_QEMU_E500 bool @@ -464,41 +518,57 @@ config ARCH_T1023 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5
config ARCH_T1024 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5
config ARCH_T1040 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5
config ARCH_T1042 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5
config ARCH_T2080 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_T2081 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_T4160 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config ARCH_T4240 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4
config BOOKE bool diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 9d3a3b4..9b7bcb0 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -72,7 +72,6 @@ */ #if defined(CONFIG_MPC83xx) #define CONFIG_SYS_FSL_SEC_BE -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #endif
/* Since so many PPC SOCs have a semi-common LBC, define this here */ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index cbaba36..7131b61 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_FSL_SEC_MON_BE
#if defined(CONFIG_ARCH_MPC8536) -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125
@@ -34,16 +33,13 @@
#elif defined(CONFIG_ARCH_MPC8541) #define CONFIG_SYS_FSL_DDRC_GEN1 -#define CONFIG_SYS_FSL_SEC_COMPAT 2
#elif defined(CONFIG_ARCH_MPC8544) #define CONFIG_SYS_FSL_DDRC_GEN2 -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8548) #define CONFIG_SYS_FSL_DDRC_GEN2 -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 @@ -58,14 +54,12 @@
#elif defined(CONFIG_ARCH_MPC8555) #define CONFIG_SYS_FSL_DDRC_GEN1 -#define CONFIG_SYS_FSL_SEC_COMPAT 2
#elif defined(CONFIG_ARCH_MPC8560) #define CONFIG_SYS_FSL_DDRC_GEN1
#elif defined(CONFIG_ARCH_MPC8568) #define CONFIG_SYS_FSL_DDRC_GEN2 -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 @@ -76,7 +70,6 @@ #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_MPC8569) -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define QE_MURAM_SIZE 0x20000UL #define MAX_QE_RISC 4 #define QE_NUM_OF_SNUM 46 @@ -89,7 +82,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8572) -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 #define CONFIG_SYS_FSL_ERRATUM_A004508 @@ -98,7 +90,6 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 @@ -123,7 +114,6 @@ #elif defined(CONFIG_ARCH_P1011) #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -133,7 +123,6 @@ #elif defined(CONFIG_ARCH_P1020) #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A004508 @@ -145,7 +134,6 @@ #elif defined(CONFIG_ARCH_P1021) #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -157,7 +145,6 @@
#elif defined(CONFIG_ARCH_P1022) #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -167,7 +154,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_ARCH_P1023) -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 1 @@ -185,7 +171,6 @@ #elif defined(CONFIG_ARCH_P1024) #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -197,7 +182,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -207,7 +191,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020) -#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 @@ -224,7 +207,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -259,7 +241,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -296,7 +277,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM2_DTSEC 4 @@ -345,7 +325,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -378,7 +357,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -407,7 +385,6 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 @@ -423,7 +400,6 @@ #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 @@ -473,7 +449,6 @@ #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_SRDS_3 #define CONFIG_SYS_FSL_SRDS_4 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PME_CLK 0 @@ -515,7 +490,6 @@ #define CONFIG_SYS_MAPLE #define CONFIG_SYS_CPRI #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FM1_CLK 0 @@ -578,7 +552,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 @@ -624,7 +597,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_NUM_CC_PLL 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -661,7 +633,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_QMAN_V3 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 @@ -709,7 +680,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2_1 -#define CONFIG_SYS_FSL_SEC_COMPAT 6 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 86b2f2f..510a108 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -4,3 +4,36 @@ config FSL_CAAM Enables the Freescale's Cryptographic Accelerator and Assurance Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses Job Ring as interface to communicate with CAAM. + +config SYS_FSL_HAS_SEC + bool + help + Enable Freescale Secure Boot and Trusted Architecture + +config SYS_FSL_SEC_COMPAT_2 + bool + help + Secure boot and trust architecture compatible version 2 + +config SYS_FSL_SEC_COMPAT_4 + bool + help + Secure boot and trust architecture compatible version 4 + +config SYS_FSL_SEC_COMPAT_5 + bool + help + Secure boot and trust architecture compatible version 5 + +config SYS_FSL_SEC_COMPAT_6 + bool + help + Secure boot and trust architecture compatible version 6 + +config SYS_FSL_SEC_COMPAT + int "Freescale Secure Boot compatibility" + depends on SYS_FSL_HAS_SEC + default 2 if SYS_FSL_SEC_COMPAT_2 + default 4 if SYS_FSL_SEC_COMPAT_4 + default 5 if SYS_FSL_SEC_COMPAT_5 + default 6 if SYS_FSL_SEC_COMPAT_6 diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index d28654b..8ee7aaf 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -94,7 +94,6 @@ /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CSF_SIZE 0x2000 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_FSL_CAAM #define CONFIG_CMD_DEKBLOB #define CONFIG_SYS_FSL_SEC_LE diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 0645228..bd98925 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -75,7 +75,6 @@ /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CSF_SIZE 0x2000 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_FSL_CAAM #define CONFIG_CMD_DEKBLOB #define CONFIG_SYS_FSL_SEC_LE diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2f33c2e..fa54921 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -5548,7 +5548,6 @@ CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SEC_ADDR CONFIG_SYS_FSL_SEC_BE -CONFIG_SYS_FSL_SEC_COMPAT CONFIG_SYS_FSL_SEC_IDX_OFFSET CONFIG_SYS_FSL_SEC_LE CONFIG_SYS_FSL_SEC_MON_BE
On Wed, Dec 28, 2016 at 08:43:30AM -0800, York Sun wrote:
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use Kconfig option to set little- or big-endian access to secure boot and trust architecture.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/arm/Kconfig | 2 ++ arch/arm/cpu/armv7/ls102xa/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 ++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 --- arch/arm/include/asm/arch-ls102xa/config.h | 1 - arch/powerpc/Kconfig | 1 + arch/powerpc/cpu/mpc85xx/Kconfig | 35 +++++++++++++++++++++++ arch/powerpc/include/asm/config.h | 7 ----- arch/powerpc/include/asm/config_mpc85xx.h | 1 - drivers/crypto/fsl/Kconfig | 6 ++++ include/configs/mx6_common.h | 1 - include/configs/mx7_common.h | 1 - include/fsl_sec.h | 2 +- scripts/config_whitelist.txt | 2 -- 14 files changed, 48 insertions(+), 18 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ff601ea..15a6233 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -466,12 +466,14 @@ config ARCH_MX7 select CPU_V7 select SYS_FSL_HAS_SEC if SECURE_BOOT select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE
config ARCH_MX6 bool "Freescale MX6" select CPU_V7 select SYS_FSL_HAS_SEC if SECURE_BOOT select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE
config ARCH_MX5 bool "Freescale MX5" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index e233aa4..d154f7b 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -7,6 +7,7 @@ config ARCH_LS1021A select SYS_FSL_DDR_VER_50 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE
menu "LS102xA architecture" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 17b470d..a1f781e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -31,12 +31,14 @@ config ARCH_LS2080A select SYS_FSL_HAS_DP_DDR select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2
config FSL_LSCH2 bool select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_BE select SYS_FSL_SRDS_1 select SYS_HAS_SERDES
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index f4f9eaa..29fc33d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -55,9 +55,6 @@ #define CONFIG_SYS_FSL_SFP_LE #define CONFIG_SYS_FSL_SRK_LE
-/* SEC */ -#define CONFIG_SYS_FSL_SEC_LE - /* Security Monitor */ #define CONFIG_SYS_FSL_SEC_MON_LE
@@ -144,7 +141,6 @@ #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_CCSR_GUR_BE #define CONFIG_SYS_FSL_PEX_LUT_BE -#define CONFIG_SYS_FSL_SEC_BE
/* SoC related */ #ifdef CONFIG_LS1043A diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 97c69e9..1c5158b 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -106,7 +106,6 @@ #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE #define CONFIG_SYS_FSL_SEC_MON_LE -#define CONFIG_SYS_FSL_SEC_LE #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 9fc1d5c..853e265 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -24,6 +24,7 @@ config MPC83xx bool "MPC83xx" select CREATE_ARCH_SYMLINK select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2
config MPC85xx diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 1287ab6..f36114a 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -326,6 +326,7 @@ config ARCH_B4420 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_B4860 @@ -333,18 +334,21 @@ config ARCH_B4860 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_BSC9131 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_BSC9132 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -352,6 +356,7 @@ config ARCH_C29X bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_6 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -359,6 +364,7 @@ config ARCH_MPC8536 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -370,12 +376,14 @@ config ARCH_MPC8541 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8544 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -383,6 +391,7 @@ config ARCH_MPC8548 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -390,6 +399,7 @@ config ARCH_MPC8555 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8560 @@ -400,24 +410,28 @@ config ARCH_MPC8568 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8569 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8572 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2
config ARCH_P1010 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -425,6 +439,7 @@ config ARCH_P1011 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -432,6 +447,7 @@ config ARCH_P1020 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -439,6 +455,7 @@ config ARCH_P1021 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -446,6 +463,7 @@ config ARCH_P1022 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -453,12 +471,14 @@ config ARCH_P1023 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_P1024 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -466,6 +486,7 @@ config ARCH_P1025 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -473,6 +494,7 @@ config ARCH_P2020 bool select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB
@@ -481,6 +503,7 @@ config ARCH_P2041 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_P3041 @@ -488,6 +511,7 @@ config ARCH_P3041 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_P4080 @@ -495,6 +519,7 @@ config ARCH_P4080 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_P5020 @@ -502,6 +527,7 @@ config ARCH_P5020 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_P5040 @@ -509,6 +535,7 @@ config ARCH_P5040 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_QEMU_E500 @@ -519,6 +546,7 @@ config ARCH_T1023 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
config ARCH_T1024 @@ -526,6 +554,7 @@ config ARCH_T1024 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
config ARCH_T1040 @@ -533,6 +562,7 @@ config ARCH_T1040 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
config ARCH_T1042 @@ -540,6 +570,7 @@ config ARCH_T1042 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
config ARCH_T2080 @@ -547,6 +578,7 @@ config ARCH_T2080 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_T2081 @@ -554,6 +586,7 @@ config ARCH_T2081 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_T4160 @@ -561,6 +594,7 @@ config ARCH_T4160 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config ARCH_T4240 @@ -568,6 +602,7 @@ config ARCH_T4240 select E500MC select FSL_LAW select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
config BOOKE diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 9b7bcb0..d4f05d1 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -67,13 +67,6 @@ #endif #endif
-/* - * SEC (crypto unit) major compatible version determination - */ -#if defined(CONFIG_MPC83xx) -#define CONFIG_SYS_FSL_SEC_BE -#endif - /* Since so many PPC SOCs have a semi-common LBC, define this here */ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ defined(CONFIG_MPC83xx) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7131b61..8bae577 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -20,7 +20,6 @@
/* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE -#define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SEC_MON_BE
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 510a108..3188959 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -30,6 +30,9 @@ config SYS_FSL_SEC_COMPAT_6 help Secure boot and trust architecture compatible version 6
+config SYS_FSL_SEC_BE + bool "Big-endian access to Freescale Secure Boot" + config SYS_FSL_SEC_COMPAT int "Freescale Secure Boot compatibility" depends on SYS_FSL_HAS_SEC @@ -37,3 +40,6 @@ config SYS_FSL_SEC_COMPAT default 4 if SYS_FSL_SEC_COMPAT_4 default 5 if SYS_FSL_SEC_COMPAT_5 default 6 if SYS_FSL_SEC_COMPAT_6 + +config SYS_FSL_SEC_LE + bool "Little-endian access to Freescale Secure Boot" diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 8ee7aaf..74b0a97 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -96,7 +96,6 @@ #define CONFIG_CSF_SIZE 0x2000 #define CONFIG_FSL_CAAM #define CONFIG_CMD_DEKBLOB -#define CONFIG_SYS_FSL_SEC_LE #endif
#endif diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index bd98925..f111fc5 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -77,7 +77,6 @@ #define CONFIG_CSF_SIZE 0x2000 #define CONFIG_FSL_CAAM #define CONFIG_CMD_DEKBLOB -#define CONFIG_SYS_FSL_SEC_LE #endif
#endif diff --git a/include/fsl_sec.h b/include/fsl_sec.h index e6080d4..61c671d 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -24,7 +24,7 @@ #define sec_in16(a) in_be16(a) #define sec_clrbits32 clrbits_be32 #define sec_setbits32 setbits_be32 -#else +#elif defined(CONFIG_SYS_FSL_HAS_SEC) #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined #endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index fa54921..fcae43a 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -5547,9 +5547,7 @@ CONFIG_SYS_FSL_SCFG_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SEC_ADDR -CONFIG_SYS_FSL_SEC_BE CONFIG_SYS_FSL_SEC_IDX_OFFSET -CONFIG_SYS_FSL_SEC_LE CONFIG_SYS_FSL_SEC_MON_BE CONFIG_SYS_FSL_SEC_MON_LE CONFIG_SYS_FSL_SEC_OFFSET
On Wed, Dec 28, 2016 at 08:43:31AM -0800, York Sun wrote:
Use Kconfig option to set little- or big-endian access to secure boot and trust architecture.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 12 +----------- arch/powerpc/cpu/mpc85xx/Makefile | 4 ---- arch/powerpc/include/asm/config_mpc85xx.h | 6 ++---- arch/powerpc/include/asm/immap_85xx.h | 6 ++---- drivers/net/fm/Makefile | 2 -- 5 files changed, 5 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index f36114a..f27ade2 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -655,8 +655,6 @@ config MAX_CPUS ARCH_P1025 || \ ARCH_P2020 || \ ARCH_P5020 || \ - ARCH_T1020 || \ - ARCH_T1022 || \ ARCH_T1023 || \ ARCH_T1024 default 1 @@ -698,10 +696,6 @@ config SYS_CCSRBAR_DEFAULT ARCH_P4080 || \ ARCH_P5020 || \ ARCH_P5040 || \ - ARCH_T1013 || \ - ARCH_T1014 || \ - ARCH_T1020 || \ - ARCH_T1022 || \ ARCH_T1023 || \ ARCH_T1024 || \ ARCH_T1040 || \ @@ -731,11 +725,7 @@ config SYS_FSL_NUM_LAWS ARCH_T2081 || \ ARCH_T4160 || \ ARCH_T4240 - default 16 if ARCH_T1013 || \ - ARCH_T1014 || \ - ARCH_T1020 || \ - ARCH_T1022 || \ - ARCH_T1023 || \ + default 16 if ARCH_T1023 || \ ARCH_T1024 || \ ARCH_T1040 || \ ARCH_T1042 diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 46ed22c..04585d0 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -50,8 +50,6 @@ obj-$(CONFIG_ARCH_B4420) += b4860_ids.o obj-$(CONFIG_ARCH_B4860) += b4860_ids.o obj-$(CONFIG_ARCH_T1040) += t1040_ids.o obj-$(CONFIG_ARCH_T1042) += t1040_ids.o -obj-$(CONFIG_PPC_T1020) += t1040_ids.o -obj-$(CONFIG_PPC_T1022) += t1040_ids.o obj-$(CONFIG_ARCH_T1023) += t1024_ids.o obj-$(CONFIG_ARCH_T1024) += t1024_ids.o obj-$(CONFIG_ARCH_T2080) += t2080_ids.o @@ -92,8 +90,6 @@ obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o -obj-$(CONFIG_PPC_T1020) += t1040_serdes.o -obj-$(CONFIG_PPC_T1022) += t1040_serdes.o obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8bae577..4e9fcc8 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -538,8 +538,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #endif
-#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\ -defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) +#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ @@ -582,8 +581,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009942
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\ -defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 786e4f6..762b174 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1775,8 +1775,7 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\ -defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) +#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1796,8 +1795,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) || \ - defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 08b3f27..fa96bad 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -26,8 +26,6 @@ obj-$(CONFIG_ARCH_P5020) += p5020.o obj-$(CONFIG_ARCH_P5040) += p5040.o obj-$(CONFIG_ARCH_T1040) += t1040.o obj-$(CONFIG_ARCH_T1042) += t1040.o -obj-$(CONFIG_PPC_T1020) += t1040.o -obj-$(CONFIG_PPC_T1022) += t1040.o obj-$(CONFIG_ARCH_T1023) += t1024.o obj-$(CONFIG_ARCH_T1024) += t1024.o obj-$(CONFIG_ARCH_T2080) += t2080.o
On Wed, Dec 28, 2016 at 08:43:32AM -0800, York Sun wrote:
Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use TARGET_T1023RDB from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com ---
board/freescale/t102xrdb/ddr.c | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 4 ++-- board/freescale/t102xrdb/t102xrdb.c | 12 ++++++------ board/freescale/t102xrdb/t102xrdb.h | 2 +- configs/T1023RDB_NAND_defconfig | 2 +- configs/T1023RDB_SDCARD_defconfig | 2 +- configs/T1023RDB_SECURE_BOOT_defconfig | 1 - configs/T1023RDB_SPIFLASH_defconfig | 2 +- configs/T1023RDB_defconfig | 1 - include/configs/T102xRDB.h | 20 ++++++++++---------- scripts/config_whitelist.txt | 1 - 11 files changed, 23 insertions(+), 26 deletions(-)
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index 9e1b16b..c09199f 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -136,7 +136,7 @@ found: popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; #endif
-#ifdef CONFIG_T1023RDB +#ifdef CONFIG_TARGET_T1023RDB popts->wrlvl_ctl_2 = 0x07070606; popts->half_strength_driver_enable = 1; popts->cpo_sample = 0x43; diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index 02b283d..dadfaf1 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -73,7 +73,7 @@ int board_eth_init(bd_t *bis) case 0x135: /* set the on-board 2.5G SGMII AQR105 PHY */ fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); -#ifdef CONFIG_T1023RDB +#ifdef CONFIG_TARGET_T1023RDB /* set the on-board 1G SGMII RTL8211F PHY */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); #endif @@ -92,7 +92,7 @@ int board_eth_init(bd_t *bis) fm_info_set_mdio(i, dev); break; case PHY_INTERFACE_MODE_SGMII: -#if defined(CONFIG_T1023RDB) +#if defined(CONFIG_TARGET_T1023RDB) dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); #elif defined(CONFIG_T1024RDB) dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 24df4b4..3174726 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -19,7 +19,7 @@ #include "t102xrdb.h" #ifdef CONFIG_T1024RDB #include "cpld.h" -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #include <i2c.h> #include <mmc.h> #endif @@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_T1023RDB +#ifdef CONFIG_TARGET_T1023RDB enum { GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */ GPIO1_EMMC_SEL, @@ -54,7 +54,7 @@ int checkboard(void) #if defined(CONFIG_T1024RDB) printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", CPLD_READ(hw_ver), CPLD_READ(sw_ver)); -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B'); #endif printf("boot from "); @@ -74,7 +74,7 @@ int checkboard(void) reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); printf("NOR vBank%d\n", reg); } -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #ifdef CONFIG_NAND puts("NAND\n"); #else @@ -196,7 +196,7 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_board_enet(blob); #endif
-#ifdef CONFIG_T1023RDB +#ifdef CONFIG_TARGET_T1023RDB if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0) fdt_enable_nor(blob); #endif @@ -204,7 +204,7 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; }
-#ifdef CONFIG_T1023RDB +#ifdef CONFIG_TARGET_T1023RDB /* Enable NOR flash for RevC */ static void fdt_enable_nor(void *blob) { diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h index ae5c60f..6634e7a 100644 --- a/board/freescale/t102xrdb/t102xrdb.h +++ b/board/freescale/t102xrdb/t102xrdb.h @@ -9,7 +9,7 @@
void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); -#ifdef CONFIG_T1023RDB +#ifdef CONFIG_TARGET_T1023RDB static u32 t1023rdb_ctrl(u32 ctrl_type); static void fdt_enable_nor(void *blob); #endif diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index 5649652..71de2a5 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index cc15635..dee5690 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index 1b474d3..d76c3b9 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -6,7 +6,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="T1023RDB" CONFIG_SECURE_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index 28350ad..5fd23e8 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -13,7 +13,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index ef0005e..255da1b 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -5,7 +5,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="T1023RDB" CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index f3ba0cd..24eca18 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -62,7 +62,7 @@ #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #if defined(CONFIG_T1024RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg #endif #define CONFIG_SPL_NAND_BOOT @@ -81,7 +81,7 @@ #endif #if defined(CONFIG_T1024RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg #endif #define CONFIG_SPL_SPI_BOOT @@ -100,7 +100,7 @@ #endif #if defined(CONFIG_T1024RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg #endif #define CONFIG_SPL_MMC_BOOT @@ -177,7 +177,7 @@ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #if defined(CONFIG_T1024RDB) #define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_ENV_SECT_SIZE 0x40000 #endif #elif defined(CONFIG_SDCARD) @@ -192,7 +192,7 @@ #define CONFIG_ENV_SIZE 0x2000 #if defined(CONFIG_T1024RDB) #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #endif #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) @@ -277,7 +277,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_SDRAM_SIZE 2048 @@ -303,7 +303,7 @@ unsigned long get_board_ddr_clk(void); /* NOR Flash Timing Params */ #if defined(CONFIG_T1024RDB) #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) #endif @@ -378,7 +378,7 @@ unsigned long get_board_ddr_clk(void); | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -734,7 +734,7 @@ unsigned long get_board_ddr_clk(void); #if defined(CONFIG_T1024RDB) #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) #endif @@ -767,7 +767,7 @@ unsigned long get_board_ddr_clk(void); #define RGMII_PHY2_ADDR 0x6 #define SGMII_AQR_PHY_ADDR 0x2 #define FM1_10GEC1_PHY_ADDR 0x1 -#elif defined(CONFIG_T1023RDB) +#elif defined(CONFIG_TARGET_T1023RDB) #define RGMII_PHY1_ADDR 0x1 #define SGMII_RTK_PHY_ADDR 0x3 #define SGMII_AQR_PHY_ADDR 0x2 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index fcae43a..30519ae 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7794,7 +7794,6 @@ CONFIG_SYS_XWAY_EBU_BOOTCFG CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL -CONFIG_T1023RDB CONFIG_T1024RDB CONFIG_T1040QDS CONFIG_T2080QDS
On Wed, Dec 28, 2016 at 08:43:33AM -0800, York Sun wrote:
Use TARGET_T1023RDB from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use TARGET_T1024RDB from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com ---
board/freescale/t102xrdb/Makefile | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 6 +++--- board/freescale/t102xrdb/t102xrdb.c | 10 +++++----- configs/T1024RDB_NAND_defconfig | 2 +- configs/T1024RDB_SDCARD_defconfig | 2 +- configs/T1024RDB_SECURE_BOOT_defconfig | 1 - configs/T1024RDB_SPIFLASH_defconfig | 2 +- configs/T1024RDB_defconfig | 1 - include/configs/T102xRDB.h | 24 ++++++++++++------------ scripts/config_whitelist.txt | 1 - 10 files changed, 24 insertions(+), 27 deletions(-)
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile index 6452865..ddeb44f 100644 --- a/board/freescale/t102xrdb/Makefile +++ b/board/freescale/t102xrdb/Makefile @@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-y += t102xrdb.o -obj-$(CONFIG_T1024RDB) += cpld.o +obj-$(CONFIG_TARGET_T1024RDB) += cpld.o obj-y += eth_t102xrdb.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index dadfaf1..c06d1b8 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -58,7 +58,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) { -#ifdef CONFIG_T1024RDB +#ifdef CONFIG_TARGET_T1024RDB case 0x95: /* set the on-board RGMII2 PHY */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); @@ -94,7 +94,7 @@ int board_eth_init(bd_t *bis) case PHY_INTERFACE_MODE_SGMII: #if defined(CONFIG_TARGET_T1023RDB) dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); -#elif defined(CONFIG_T1024RDB) +#elif defined(CONFIG_TARGET_T1024RDB) dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); #endif fm_info_set_mdio(i, dev); @@ -128,7 +128,7 @@ int board_eth_init(bd_t *bis) void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) || (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && (port == FM1_DTSEC3)) { diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 3174726..56f7c1a 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -17,7 +17,7 @@ #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t102xrdb.h" -#ifdef CONFIG_T1024RDB +#ifdef CONFIG_TARGET_T1024RDB #include "cpld.h" #elif defined(CONFIG_TARGET_T1023RDB) #include <i2c.h> @@ -51,7 +51,7 @@ int checkboard(void) srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
printf("Board: %sRDB, ", cpu->name); -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", CPLD_READ(hw_ver), CPLD_READ(sw_ver)); #elif defined(CONFIG_TARGET_T1023RDB) @@ -63,7 +63,7 @@ int checkboard(void) puts("SD/MMC\n"); #elif CONFIG_SPIFLASH puts("SPI\n"); -#elif defined(CONFIG_T1024RDB) +#elif defined(CONFIG_TARGET_T1024RDB) u8 reg;
reg = CPLD_READ(flash_csr); @@ -91,7 +91,7 @@ int checkboard(void) return 0; }
-#ifdef CONFIG_T1024RDB +#ifdef CONFIG_TARGET_T1024RDB static void board_mux_lane(void) { ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -150,7 +150,7 @@ int board_early_init_r(void) 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif
-#ifdef CONFIG_T1024RDB +#ifdef CONFIG_TARGET_T1024RDB board_mux_lane(); #endif
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 96a6b65..d6ad422 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index c6fdb22..8ef312f 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index 9d082f7..7434ebc 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -6,7 +6,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="T1024RDB" CONFIG_SECURE_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index bce2a59..b8dc316 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -13,7 +13,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 0aef757..3ba1e35 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -5,7 +5,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="T1024RDB" CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 24eca18..96bf4b9 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -60,7 +60,7 @@ #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg #elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg @@ -79,7 +79,7 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg #elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg @@ -98,7 +98,7 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg #elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg @@ -175,7 +175,7 @@ #define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_ENV_SECT_SIZE 0x40000 @@ -190,7 +190,7 @@ #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -271,7 +271,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_FSL_DDR_INTERACTIVE -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 @@ -301,7 +301,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */ -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 #elif defined(CONFIG_TARGET_T1023RDB) #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ @@ -330,7 +330,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#ifdef CONFIG_T1024RDB +#ifdef CONFIG_TARGET_T1024RDB /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) @@ -369,7 +369,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -707,7 +707,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_DPAA_FMAN
-#ifdef CONFIG_T1024RDB +#ifdef CONFIG_TARGET_T1024RDB #define CONFIG_QE #define CONFIG_U_QE #endif @@ -731,7 +731,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_TARGET_T1023RDB) @@ -762,7 +762,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHYLIB_10G #define CONFIG_PHY_REALTEK #define CONFIG_PHY_AQUANTIA -#if defined(CONFIG_T1024RDB) +#if defined(CONFIG_TARGET_T1024RDB) #define RGMII_PHY1_ADDR 0x2 #define RGMII_PHY2_ADDR 0x6 #define SGMII_AQR_PHY_ADDR 0x2 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 30519ae..ff7f3d1 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7794,7 +7794,6 @@ CONFIG_SYS_XWAY_EBU_BOOTCFG CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL -CONFIG_T1024RDB CONFIG_T1040QDS CONFIG_T2080QDS CONFIG_T2080RDB
On Wed, Dec 28, 2016 at 08:43:34AM -0800, York Sun wrote:
Use TARGET_T1024RDB from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use TARGET_T1040QDS from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/include/asm/fsl_secure_boot.h | 2 +- include/configs/T1040QDS.h | 1 - scripts/config_whitelist.txt | 1 - 3 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 808adae..6949ee8 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -31,7 +31,7 @@ defined(CONFIG_TARGET_T4240QDS) || \ defined(CONFIG_T2080QDS) || \ defined(CONFIG_T2080RDB) || \ - defined(CONFIG_T1040QDS) || \ + defined(CONFIG_TARGET_T1040QDS) || \ defined(CONFIG_T104xD4QDS) || \ defined(CONFIG_TARGET_T1040RDB) || \ defined(CONFIG_TARGET_T1040D4RDB) || \ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8e13f3b..dc8d86a 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -26,7 +26,6 @@ /* * T1040 QDS board configuration file */ -#define CONFIG_T1040QDS
#ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ff7f3d1..304a341 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7794,7 +7794,6 @@ CONFIG_SYS_XWAY_EBU_BOOTCFG CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL -CONFIG_T1040QDS CONFIG_T2080QDS CONFIG_T2080RDB CONFIG_T2081QDS
On Wed, Dec 28, 2016 at 08:43:35AM -0800, York Sun wrote:
Use TARGET_T1040QDS from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use TARGET_T2080QDS from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/include/asm/fsl_secure_boot.h | 2 +- board/freescale/t208xqds/Makefile | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 16 ++++++++-------- board/freescale/t208xqds/t208xqds.c | 6 +++--- include/configs/T208xQDS.h | 1 - scripts/config_whitelist.txt | 1 - 6 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 6949ee8..95569a1 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -29,7 +29,7 @@ defined(CONFIG_TARGET_B4420QDS) || \ defined(CONFIG_TARGET_T4160QDS) || \ defined(CONFIG_TARGET_T4240QDS) || \ - defined(CONFIG_T2080QDS) || \ + defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_T2080RDB) || \ defined(CONFIG_TARGET_T1040QDS) || \ defined(CONFIG_T104xD4QDS) || \ diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index ef04a26..3a6d030 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -7,7 +7,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else -obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o +obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index e92b5d3..59480a3 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -32,7 +32,7 @@ #define EMI1_RGMII1 0 #define EMI1_RGMII2 1 #define EMI1_SLOT1 2 -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) #define EMI1_SLOT2 6 #define EMI1_SLOT3 3 #define EMI1_SLOT4 4 @@ -59,7 +59,7 @@ static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = { -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) "T2080QDS_MDIO_RGMII1", "T2080QDS_MDIO_RGMII2", "T2080QDS_MDIO_SLOT1", @@ -82,7 +82,7 @@ static const char * const mdio_names[] = { };
/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; #elif defined(CONFIG_T2081QDS) static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1}; @@ -204,7 +204,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, int off;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_T2080QDS +#ifdef CONFIG_TARGET_T2080QDS serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); @@ -217,7 +217,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { phy = fm_info_get_phy_address(port); switch (port) { -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) case FM1_DTSEC1: if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { media_type = 1; @@ -454,7 +454,7 @@ static void initialize_lane_to_slot(void) srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_s1) { -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) case 0x51: case 0x5f: case 0x65: @@ -552,7 +552,7 @@ int board_eth_init(bd_t *bis) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); #endif t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); @@ -663,7 +663,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) case 0xd9: case 0xd3: case 0xcb: diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index d016329..e307ccb 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -99,7 +99,7 @@ int brd_mux_lane_to_slot(void) srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; @@ -109,7 +109,7 @@ int brd_mux_lane_to_slot(void) case 0: /* SerDes1 is not enabled */ break; -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) case 0x1b: case 0x1c: case 0xa2: @@ -268,7 +268,7 @@ int brd_mux_lane_to_slot(void) return -1; }
-#ifdef CONFIG_T2080QDS +#ifdef CONFIG_TARGET_T2080QDS switch (srds_prtcl_s2) { case 0: /* SerDes2 is not enabled */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 3e01ae7..15da358 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -15,7 +15,6 @@ #define CONFIG_MMC #define CONFIG_USB_EHCI #if defined(CONFIG_ARCH_T2080) -#define CONFIG_T2080QDS #define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ #define CONFIG_SRIO1 /* SRIO port 1 */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 304a341..4d9514f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7794,7 +7794,6 @@ CONFIG_SYS_XWAY_EBU_BOOTCFG CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL -CONFIG_T2080QDS CONFIG_T2080RDB CONFIG_T2081QDS CONFIG_TAM3517_SETTINGS
On Wed, Dec 28, 2016 at 08:43:36AM -0800, York Sun wrote:
Use TARGET_T2080QDS from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use TARGET_T2080RDB from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/include/asm/fsl_secure_boot.h | 2 +- board/freescale/t208xrdb/Makefile | 2 +- include/configs/T208xRDB.h | 1 - scripts/config_whitelist.txt | 1 - 4 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 95569a1..89ca45c 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -30,7 +30,7 @@ defined(CONFIG_TARGET_T4160QDS) || \ defined(CONFIG_TARGET_T4240QDS) || \ defined(CONFIG_TARGET_T2080QDS) || \ - defined(CONFIG_T2080RDB) || \ + defined(CONFIG_TARGET_T2080RDB) || \ defined(CONFIG_TARGET_T1040QDS) || \ defined(CONFIG_T104xD4QDS) || \ defined(CONFIG_TARGET_T1040RDB) || \ diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile index cd8fe09..25ea66a 100644 --- a/board/freescale/t208xrdb/Makefile +++ b/board/freescale/t208xrdb/Makefile @@ -7,7 +7,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else -obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o +obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o obj-$(CONFIG_PCI) += pci.o endif
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index fbdb0bd..42261ed 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -11,7 +11,6 @@ #ifndef __T2080RDB_H #define __T2080RDB_H
-#define CONFIG_T2080RDB #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_MMC #define CONFIG_USB_EHCI diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 4d9514f..161096b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7794,7 +7794,6 @@ CONFIG_SYS_XWAY_EBU_BOOTCFG CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL -CONFIG_T2080RDB CONFIG_T2081QDS CONFIG_TAM3517_SETTINGS CONFIG_TAM3517_SW3_SETTINGS
On Wed, Dec 28, 2016 at 08:43:37AM -0800, York Sun wrote:
Use TARGET_T2080RDB from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use TARGET_T2081QDS from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com ---
board/freescale/t208xqds/Makefile | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 16 ++++++++-------- board/freescale/t208xqds/t208xqds.c | 2 +- include/configs/T208xQDS.h | 1 - scripts/config_whitelist.txt | 1 - 5 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index 3a6d030..587903a 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o -obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o +obj-$(CONFIG_TARGET_T2081QDS) += t208xqds.o eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o endif
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 59480a3..c880294 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -38,7 +38,7 @@ #define EMI1_SLOT4 4 #define EMI1_SLOT5 5 #define EMI2 7 -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) #define EMI1_SLOT2 3 #define EMI1_SLOT3 4 #define EMI1_SLOT5 5 @@ -68,7 +68,7 @@ static const char * const mdio_names[] = { "T2080QDS_MDIO_SLOT5", "T2080QDS_MDIO_SLOT2", "T2080QDS_MDIO_10GC", -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) "T2081QDS_MDIO_RGMII1", "T2081QDS_MDIO_RGMII2", "T2081QDS_MDIO_SLOT1", @@ -84,7 +84,7 @@ static const char * const mdio_names[] = { /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ #if defined(CONFIG_TARGET_T2080QDS) static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1}; #endif
@@ -311,7 +311,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_status_okay_by_alias(fdt, "emi1_slot2"); } break; -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) case FM1_DTSEC1: case FM1_DTSEC2: case FM1_DTSEC5: @@ -481,7 +481,7 @@ static void initialize_lane_to_slot(void) lane_to_slot[6] = 3; lane_to_slot[7] = 3; break; -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) case 0x6b: lane_to_slot[4] = 1; lane_to_slot[5] = 3; @@ -556,7 +556,7 @@ int board_eth_init(bd_t *bis) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); #endif t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); -#if defined(CONFIG_T2081QDS) +#if defined(CONFIG_TARGET_T2081QDS) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); #endif @@ -675,7 +675,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) case 0xca: case 0xcb: /* SGMII in Slot3 */ @@ -731,7 +731,7 @@ int board_eth_init(bd_t *bis) fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; -#if defined(CONFIG_T2081QDS) +#if defined(CONFIG_TARGET_T2081QDS) case 5: mdio_mux[i] = EMI1_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval( diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index e307ccb..26093ea 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -191,7 +191,7 @@ int brd_mux_lane_to_slot(void) */ QIXIS_WRITE(brdcfg[12], 0x1a); break; -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) case 0x50: case 0x51: /* SD1(A:D) => SLOT2 XAUI diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 15da358..fd5cb72 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -20,7 +20,6 @@ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ #elif defined(CONFIG_ARCH_T2081) -#define CONFIG_T2081QDS #endif
/* High Level Configuration Options */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 161096b..99a6d25 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7794,7 +7794,6 @@ CONFIG_SYS_XWAY_EBU_BOOTCFG CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL -CONFIG_T2081QDS CONFIG_TAM3517_SETTINGS CONFIG_TAM3517_SW3_SETTINGS CONFIG_TCA642X
On Wed, Dec 28, 2016 at 08:43:38AM -0800, York Sun wrote:
Use TARGET_T2081QDS from Kconfig instead.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Remove this macro. It was added by e622d9ed but actually wasn't used.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/include/asm/fsl_secure_boot.h | 1 - 1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 89ca45c..10e26d6 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -32,7 +32,6 @@ defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ defined(CONFIG_TARGET_T1040QDS) || \ - defined(CONFIG_T104xD4QDS) || \ defined(CONFIG_TARGET_T1040RDB) || \ defined(CONFIG_TARGET_T1040D4RDB) || \ defined(CONFIG_TARGET_T1042RDB) || \
On Wed, Dec 28, 2016 at 08:43:39AM -0800, York Sun wrote:
Remove this macro. It was added by e622d9ed but actually wasn't used.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/arm/Kconfig | 1 + arch/arm/cpu/armv7/ls102xa/Kconfig | 47 +-------- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 57 ++-------- arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +- arch/powerpc/Kconfig | 4 + arch/powerpc/cpu/mpc83xx/Kconfig | 3 + arch/powerpc/cpu/mpc85xx/Kconfig | 46 ++++++++ arch/powerpc/cpu/mpc86xx/Kconfig | 4 + arch/powerpc/include/asm/config.h | 3 - arch/powerpc/include/asm/config_mpc85xx.h | 21 ---- arch/powerpc/include/asm/config_mpc86xx.h | 2 - configs/MPC8349EMDS_defconfig | 1 + configs/MPC8536DS_36BIT_defconfig | 1 + configs/MPC8536DS_SDCARD_defconfig | 1 + configs/MPC8536DS_SPIFLASH_defconfig | 1 + configs/MPC8536DS_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/MPC8572DS_36BIT_defconfig | 1 + configs/MPC8572DS_defconfig | 1 + configs/MPC8610HPCD_defconfig | 1 + configs/MPC8641HPCN_36BIT_defconfig | 1 + configs/MPC8641HPCN_defconfig | 1 + configs/T1023RDB_NAND_defconfig | 1 + configs/T1023RDB_SDCARD_defconfig | 1 + configs/T1023RDB_SECURE_BOOT_defconfig | 1 + configs/T1023RDB_SPIFLASH_defconfig | 1 + configs/T1023RDB_defconfig | 1 + configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 2 +- configs/T1024QDS_DDR4_defconfig | 2 +- configs/T1024QDS_NAND_defconfig | 1 + configs/T1024QDS_SDCARD_defconfig | 1 + configs/T1024QDS_SECURE_BOOT_defconfig | 1 + configs/T1024QDS_SPIFLASH_defconfig | 1 + configs/T1024QDS_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 1 + configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SECURE_BOOT_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1024RDB_defconfig | 1 + configs/T1040D4RDB_NAND_defconfig | 3 +- configs/T1040D4RDB_SDCARD_defconfig | 3 +- configs/T1040D4RDB_SECURE_BOOT_defconfig | 2 +- configs/T1040D4RDB_SPIFLASH_defconfig | 3 +- configs/T1040D4RDB_defconfig | 2 +- configs/T1040QDS_DDR4_defconfig | 2 +- configs/T1040QDS_SECURE_BOOT_defconfig | 1 + configs/T1040QDS_defconfig | 1 + configs/T1040RDB_NAND_defconfig | 1 + configs/T1040RDB_SDCARD_defconfig | 1 + configs/T1040RDB_SECURE_BOOT_defconfig | 1 + configs/T1040RDB_SPIFLASH_defconfig | 1 + configs/T1040RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 3 +- configs/T1042D4RDB_SDCARD_defconfig | 3 +- configs/T1042D4RDB_SECURE_BOOT_defconfig | 2 +- configs/T1042D4RDB_SPIFLASH_defconfig | 3 +- configs/T1042D4RDB_defconfig | 2 +- configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 1 + configs/T1042RDB_PI_NAND_defconfig | 1 + configs/T1042RDB_PI_SDCARD_defconfig | 1 + configs/T1042RDB_PI_SPIFLASH_defconfig | 1 + configs/T1042RDB_PI_defconfig | 1 + configs/T1042RDB_SECURE_BOOT_defconfig | 1 + configs/T1042RDB_defconfig | 1 + configs/ls1046aqds_defconfig | 1 - configs/ls1046aqds_nand_defconfig | 2 +- configs/ls1046aqds_qspi_defconfig | 1 - configs/ls1046aqds_sdcard_ifc_defconfig | 2 +- configs/ls1046aqds_sdcard_qspi_defconfig | 2 +- configs/ls1046ardb_emmc_defconfig | 2 +- configs/ls1046ardb_qspi_defconfig | 1 - configs/ls1046ardb_sdcard_defconfig | 2 +- configs/ls2080a_emu_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080aqds_qspi_defconfig | 2 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +- configs/ls2080ardb_defconfig | 3 +- configs/ls2080ardb_nand_defconfig | 2 +- configs/sbc8548_PCI_33_PCIE_defconfig | 1 + configs/sbc8548_PCI_33_defconfig | 1 + configs/sbc8548_PCI_66_PCIE_defconfig | 1 + configs/sbc8548_PCI_66_defconfig | 1 + configs/sbc8548_defconfig | 1 + configs/xpedite517x_defconfig | 1 + configs/xpedite520x_defconfig | 1 + configs/xpedite537x_defconfig | 1 + drivers/Kconfig | 2 + drivers/ddr/fsl/Kconfig | 122 ++++++++++++++++++++++ drivers/ddr/fsl/Makefile | 2 +- include/configs/B4860QDS.h | 1 - include/configs/BSC9131RDB.h | 1 - include/configs/BSC9132QDS.h | 1 - include/configs/C29XPCIE.h | 1 - include/configs/MPC8349EMDS.h | 8 +- include/configs/MPC8536DS.h | 1 - include/configs/MPC8540ADS.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 1 - include/configs/MPC8548CDS.h | 1 - include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/P1022DS.h | 1 - include/configs/P1023RDB.h | 1 - include/configs/P2041RDB.h | 1 - include/configs/T102xQDS.h | 3 - include/configs/T102xRDB.h | 2 - include/configs/T1040QDS.h | 3 - include/configs/T104xRDB.h | 3 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/UCP1020.h | 1 - include/configs/controlcenterd.h | 1 - include/configs/corenet_ds.h | 1 - include/configs/cyrus.h | 1 - include/configs/km/kmp204x-common.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/p1_twr.h | 1 - include/configs/sbc8548.h | 1 - include/configs/socrates.h | 1 - include/configs/t4qds.h | 1 - include/configs/xpedite517x.h | 1 - include/configs/xpedite520x.h | 1 - include/configs/xpedite537x.h | 1 - include/configs/xpedite550x.h | 1 - scripts/config_whitelist.txt | 11 -- 136 files changed, 281 insertions(+), 216 deletions(-) create mode 100644 drivers/ddr/fsl/Kconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 15a6233..d6a0a23 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -770,6 +770,7 @@ config TARGET_LS1021AQDS select ARCH_LS1021A select ARCH_SUPPORT_PSCI select LS1_DEEP_SLEEP + select SYS_FSL_DDR
config TARGET_LS1021ATWR bool "Support ls1021atwr" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index d154f7b..eca1d06 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -3,8 +3,10 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES - select SYS_FSL_DDR_BE - select SYS_FSL_DDR_VER_50 + select SYS_FSL_DDR_BE if SYS_FSL_DDR + select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR + select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR + select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE @@ -49,47 +51,6 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool
-config SYS_FSL_DDR - bool "Freescale DDR driver" - help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). - -config SYS_FSL_DDR_BE - bool - default y - help - Access DDR registers in big-endian. - -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 - -config SYS_FSL_DDR_VER_50 - bool - -config SYS_FSL_DDRC_ARM_GEN3 - bool - -config SYS_FSL_DDRC_GEN4 - bool - -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. - -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. - config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a1f781e..bee7d15 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -8,28 +8,33 @@ config ARCH_LS1012A config ARCH_LS1043A bool select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4
config ARCH_LS1046A bool select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE - select SYS_FSL_DDR4 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2
config ARCH_LS2080A bool select FSL_LSCH3 - select SYS_FSL_DDR4 + select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 select SYS_FSL_HAS_DP_DDR select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_DDR4 select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 @@ -71,9 +76,6 @@ config FSL_PPA_ARMV8_PSCI implemented under the common ARMv8 PSCI framework. endmenu
-config SYS_FSL_MMDC - bool - config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315"
@@ -129,49 +131,4 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool
-config SYS_FSL_DDR - bool "Freescale DDR driver" - help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). - -config SYS_FSL_DDR_BE - bool - help - Access DDR registers in big-endian. - -config SYS_FSL_DDR_LE - bool - help - Access DDR registers in little-endian. - -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 - -config SYS_FSL_DDR_VER_50 - bool - -config SYS_FSL_DDRC_ARM_GEN3 - bool - -config SYS_FSL_DDRC_GEN4 - bool - -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. - -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. - endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 29fc33d..db40669 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -175,11 +175,11 @@ #define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_ERRATUM_A009660 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#elif defined(CONFIG_ARCH_LS1012A) -#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
+#elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 + #elif defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 853e265..0033c35 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -30,9 +30,13 @@ config MPC83xx config MPC85xx bool "MPC85xx" select CREATE_ARCH_SYMLINK + select SYS_FSL_DDR + select SYS_FSL_DDR_BE
config MPC86xx bool "MPC86xx" + select SYS_FSL_DDR + select SYS_FSL_DDR_BE
config 8xx bool "MPC8xx" diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 3ea62ca..6e4a931 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -38,6 +38,9 @@ config TARGET_MPC832XEMDS
config TARGET_MPC8349EMDS bool "Support MPC8349EMDS" + select SYS_FSL_DDR + select SYS_FSL_HAS_DDR2 + select SYS_FSL_DDR_BE
config TARGET_MPC8349ITX bool "Support MPC8349ITX" diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index f27ade2..3e90c70 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -104,6 +104,8 @@ config TARGET_MPC8569MDS config TARGET_MPC8572DS bool "Support MPC8572DS" select ARCH_MPC8572 +# Use DDR3 controller with DDR2 DIMMs on this board + select SYS_FSL_DDRC_GEN3
config TARGET_P1010RDB_PA bool "Support P1010RDB_PA" @@ -325,6 +327,7 @@ config ARCH_B4420 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -333,6 +336,7 @@ config ARCH_B4860 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -340,6 +344,7 @@ config ARCH_B4860 config ARCH_BSC9131 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -347,6 +352,7 @@ config ARCH_BSC9131 config ARCH_BSC9132 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -355,6 +361,7 @@ config ARCH_BSC9132 config ARCH_C29X bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_6 @@ -363,6 +370,8 @@ config ARCH_C29X config ARCH_MPC8536 bool select FSL_LAW + select SYS_FSL_HAS_DDR2 + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -371,10 +380,12 @@ config ARCH_MPC8536 config ARCH_MPC8540 bool select FSL_LAW + select SYS_FSL_HAS_DDR1
config ARCH_MPC8541 bool select FSL_LAW + select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -382,6 +393,7 @@ config ARCH_MPC8541 config ARCH_MPC8544 bool select FSL_LAW + select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -390,6 +402,8 @@ config ARCH_MPC8544 config ARCH_MPC8548 bool select FSL_LAW + select SYS_FSL_HAS_DDR2 + select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -398,6 +412,7 @@ config ARCH_MPC8548 config ARCH_MPC8555 bool select FSL_LAW + select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -405,10 +420,12 @@ config ARCH_MPC8555 config ARCH_MPC8560 bool select FSL_LAW + select SYS_FSL_HAS_DDR1
config ARCH_MPC8568 bool select FSL_LAW + select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -416,6 +433,7 @@ config ARCH_MPC8568 config ARCH_MPC8569 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -423,6 +441,8 @@ config ARCH_MPC8569 config ARCH_MPC8572 bool select FSL_LAW + select SYS_FSL_HAS_DDR2 + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -430,6 +450,7 @@ config ARCH_MPC8572 config ARCH_P1010 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -438,6 +459,7 @@ config ARCH_P1010 config ARCH_P1011 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -446,6 +468,7 @@ config ARCH_P1011 config ARCH_P1020 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -454,6 +477,7 @@ config ARCH_P1020 config ARCH_P1021 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -462,6 +486,7 @@ config ARCH_P1021 config ARCH_P1022 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -470,6 +495,7 @@ config ARCH_P1022 config ARCH_P1023 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -477,6 +503,7 @@ config ARCH_P1023 config ARCH_P1024 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -485,6 +512,7 @@ config ARCH_P1024 config ARCH_P1025 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -493,6 +521,7 @@ config ARCH_P1025 config ARCH_P2020 bool select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 @@ -502,6 +531,7 @@ config ARCH_P2041 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -510,6 +540,7 @@ config ARCH_P3041 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -518,6 +549,7 @@ config ARCH_P4080 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -526,6 +558,7 @@ config ARCH_P5020 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -534,6 +567,7 @@ config ARCH_P5040 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -545,6 +579,8 @@ config ARCH_T1023 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 @@ -553,6 +589,8 @@ config ARCH_T1024 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 @@ -561,6 +599,8 @@ config ARCH_T1040 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 @@ -569,6 +609,8 @@ config ARCH_T1042 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 @@ -577,6 +619,7 @@ config ARCH_T2080 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -585,6 +628,7 @@ config ARCH_T2081 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -593,6 +637,7 @@ config ARCH_T4160 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 @@ -601,6 +646,7 @@ config ARCH_T4240 bool select E500MC select FSL_LAW + select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index 11afffa..ff21c48 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -29,10 +29,14 @@ endchoice config ARCH_MPC8610 bool select FSL_LAW + select SYS_FSL_HAS_DDR1 + select SYS_FSL_HAS_DDR2
config ARCH_MPC8641 bool select FSL_LAW + select SYS_FSL_HAS_DDR1 + select SYS_FSL_HAS_DDR2
config FSL_LAW bool diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index d4f05d1..55686a1 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -9,16 +9,13 @@
#ifdef CONFIG_MPC85xx #include <asm/config_mpc85xx.h> -#define CONFIG_SYS_FSL_DDR #endif
#ifdef CONFIG_MPC86xx #include <asm/config_mpc86xx.h> -#define CONFIG_SYS_FSL_DDR #endif
#ifdef CONFIG_MPC83xx -#define CONFIG_SYS_FSL_DDR #endif
#ifndef HWCONFIG_BUFFER_SIZE diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4e9fcc8..6aee5bc 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -16,7 +16,6 @@ #define CONFIG_PPC_SPINTABLE_COMPATIBLE
#include <fsl_ddrc_version.h> -#define CONFIG_SYS_FSL_DDR_BE
/* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE @@ -28,17 +27,13 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8540) -#define CONFIG_SYS_FSL_DDRC_GEN1
#elif defined(CONFIG_ARCH_MPC8541) -#define CONFIG_SYS_FSL_DDRC_GEN1
#elif defined(CONFIG_ARCH_MPC8544) -#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8548) -#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 @@ -52,13 +47,10 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
#elif defined(CONFIG_ARCH_MPC8555) -#define CONFIG_SYS_FSL_DDRC_GEN1
#elif defined(CONFIG_ARCH_MPC8560) -#define CONFIG_SYS_FSL_DDRC_GEN1
#elif defined(CONFIG_ARCH_MPC8568) -#define CONFIG_SYS_FSL_DDRC_GEN2 #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 @@ -544,9 +536,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 @@ -588,9 +577,6 @@ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FMAN_V3 -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#endif #define CONFIG_SYS_FSL_NUM_CC_PLL 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 @@ -697,13 +683,6 @@ #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 #endif
-#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ - !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ - !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ - !defined(CONFIG_SYS_FSL_DDRC_GEN4) -#define CONFIG_SYS_FSL_DDRC_GEN3 -#endif - #if !defined(CONFIG_ARCH_C29X) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #endif diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h index f053b9c..5eabe6d 100644 --- a/arch/powerpc/include/asm/config_mpc86xx.h +++ b/arch/powerpc/include/asm/config_mpc86xx.h @@ -7,6 +7,4 @@ #ifndef _ASM_MPC86xx_CONFIG_H_ #define _ASM_MPC86xx_CONFIG_H_
-#define CONFIG_SYS_FSL_DDR_86XX - #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 28945a6..fe72000 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig index 3361dbc..1f0a463 100644 --- a/configs/MPC8536DS_36BIT_defconfig +++ b/configs/MPC8536DS_36BIT_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_MPC8536DS=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_CONSOLE_MUX is not set CONFIG_HUSH_PARSER=y diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig index 2e84b3f..0bdb25b 100644 --- a/configs/MPC8536DS_SDCARD_defconfig +++ b/configs/MPC8536DS_SDCARD_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_MPC8536DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_CONSOLE_MUX is not set CONFIG_HUSH_PARSER=y diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig index 3ec85ac..9754418 100644 --- a/configs/MPC8536DS_SPIFLASH_defconfig +++ b/configs/MPC8536DS_SPIFLASH_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_MPC8536DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_CONSOLE_MUX is not set CONFIG_HUSH_PARSER=y diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig index fd83da1..5b99be5 100644 --- a/configs/MPC8536DS_defconfig +++ b/configs/MPC8536DS_defconfig @@ -4,6 +4,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_CONSOLE_MUX is not set CONFIG_HUSH_PARSER=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 5d834e6..9b4dafd 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8548CDS=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index ee400a3..9991f5c 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8548CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index b733461..381978b 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8548CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY" +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig index 1239d08..cca88d7 100644 --- a/configs/MPC8572DS_36BIT_defconfig +++ b/configs/MPC8572DS_36BIT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_CONSOLE_MUX is not set CONFIG_HUSH_PARSER=y diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig index 13df52e..361e6fc 100644 --- a/configs/MPC8572DS_defconfig +++ b/configs/MPC8572DS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_CONSOLE_MUX is not set CONFIG_HUSH_PARSER=y diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig index b4e053a..d3d4930 100644 --- a/configs/MPC8610HPCD_defconfig +++ b/configs/MPC8610HPCD_defconfig @@ -4,6 +4,7 @@ CONFIG_MPC86xx=y CONFIG_TARGET_MPC8610HPCD=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig index 8ffa5e9..e9a6387 100644 --- a/configs/MPC8641HPCN_36BIT_defconfig +++ b/configs/MPC8641HPCN_36BIT_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_MPC8641HPCN=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig index 6f9bf01..5265564 100644 --- a/configs/MPC8641HPCN_defconfig +++ b/configs/MPC8641HPCN_defconfig @@ -4,6 +4,7 @@ CONFIG_MPC86xx=y CONFIG_TARGET_MPC8641HPCN=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index 71de2a5..3c89695 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index dee5690..88eedeb 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index d76c3b9..177bb93 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index 5fd23e8..33cf11c 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index 255da1b..8f40401 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -7,6 +7,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_FSL_DDR4=y CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig index bdc0a9d..8081a22 100644 --- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig @@ -7,7 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_FSL_DDR4=y CONFIG_SECURE_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig index bd2b438..d8f5616 100644 --- a/configs/T1024QDS_DDR4_defconfig +++ b/configs/T1024QDS_DDR4_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig index 1563609..ea31072 100644 --- a/configs/T1024QDS_NAND_defconfig +++ b/configs/T1024QDS_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig index a86657d..b88afb9 100644 --- a/configs/T1024QDS_SDCARD_defconfig +++ b/configs/T1024QDS_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig index b092068..f8a2e6f 100644 --- a/configs/T1024QDS_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_SECURE_BOOT_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig index 2ab4752..c3d3573 100644 --- a/configs/T1024QDS_SPIFLASH_defconfig +++ b/configs/T1024QDS_SPIFLASH_defconfig @@ -15,6 +15,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig index e45baef..db3e96f 100644 --- a/configs/T1024QDS_defconfig +++ b/configs/T1024QDS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index d6ad422..1d551d2 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 8ef312f..985b446 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index 7434ebc..18f6948 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index b8dc316..1e8ef9a 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 3ba1e35..14884ef 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig index c5ab87b..15eed53 100644 --- a/configs/T1040D4RDB_NAND_defconfig +++ b/configs/T1040D4RDB_NAND_defconfig @@ -12,7 +12,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig index 63af509..d982154 100644 --- a/configs/T1040D4RDB_SDCARD_defconfig +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -12,7 +12,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig index 6f948a1..3d22cb7 100644 --- a/configs/T1040D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_FSL_DDR4=y CONFIG_SECURE_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig index 587cca1..c9ef5d6 100644 --- a/configs/T1040D4RDB_SPIFLASH_defconfig +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -13,7 +13,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig index 87be2b5..fe76c16 100644 --- a/configs/T1040D4RDB_defconfig +++ b/configs/T1040D4RDB_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig index 0af3b36..b5f2717 100644 --- a/configs/T1040QDS_DDR4_defconfig +++ b/configs/T1040QDS_DDR4_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig index 3f15b09..15ee872 100644 --- a/configs/T1040QDS_SECURE_BOOT_defconfig +++ b/configs/T1040QDS_SECURE_BOOT_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig index 1c183f4..b24f305 100644 --- a/configs/T1040QDS_defconfig +++ b/configs/T1040QDS_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig index 2129bf4..a201bbd 100644 --- a/configs/T1040RDB_NAND_defconfig +++ b/configs/T1040RDB_NAND_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig index fc74dec..2153664 100644 --- a/configs/T1040RDB_SDCARD_defconfig +++ b/configs/T1040RDB_SDCARD_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig index a9b61a8..9703895 100644 --- a/configs/T1040RDB_SECURE_BOOT_defconfig +++ b/configs/T1040RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig index 9f05ac3..80d1402 100644 --- a/configs/T1040RDB_SPIFLASH_defconfig +++ b/configs/T1040RDB_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig index e246c43..a005d06 100644 --- a/configs/T1040RDB_defconfig +++ b/configs/T1040RDB_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 4c6b918..fdde0a3 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -13,7 +13,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index c2c03ee..b1e3f8d 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -13,7 +13,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index e20d412..b5732ea 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -7,7 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_FSL_DDR4=y CONFIG_SECURE_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 0a2f379..2e0ae73 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -14,7 +14,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index ef68c5f..b5b7a8c 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig index 26db750..7126adc 100644 --- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_FSL_DDR3=y CONFIG_SECURE_BOOT=y CONFIG_BOOTDELAY=0 CONFIG_SILENT_CONSOLE=y diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig index d8aa1f7..ba68f7d 100644 --- a/configs/T1042RDB_PI_NAND_defconfig +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig index af98400..3d43a90 100644 --- a/configs/T1042RDB_PI_SDCARD_defconfig +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig index 369944d..60b95b9 100644 --- a/configs/T1042RDB_PI_SPIFLASH_defconfig +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -15,6 +15,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig index 4a9bd3a..da43d35 100644 --- a/configs/T1042RDB_PI_defconfig +++ b/configs/T1042RDB_PI_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig index edd1ff6..17cc4d0 100644 --- a/configs/T1042RDB_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_SECURE_BOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig index 2223e6d..7e3ff05 100644 --- a/configs/T1042RDB_defconfig +++ b/configs/T1042RDB_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=10 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 2cc1a0b..5636885 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 74fcd4a..ebb1b5e 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index c8a68fa..bdb8433 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index fe9ad0e..9995047 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 1700082..4fccce4 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT_QSPI" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT_QSPI" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index fd21959..38117f2 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SYS_FSL_DDR4,EMMC_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index fa17373..2992fe8 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 0b810d3..c74e007 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig index 760557a..15aaa9c 100644 --- a/configs/ls2080a_emu_defconfig +++ b/configs/ls2080a_emu_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="EMU,LS2080A" CONFIG_BOOTDELAY=10 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 0c70f92..c1ffe9d 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="LS2080A" CONFIG_SECURE_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 63a15ee..d26f1b6 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="LS2080A" CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 4500c13..91b3b57 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 0e92ad4..803d3bb 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,LS2080A" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 1d20175..d8619a3 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -6,7 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="LS2080A" CONFIG_SECURE_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 4718ab3..e931684 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -6,7 +6,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="LS2080A" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index b79e4e4..f42f00a 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig index b7eae97..dfc85a6 100644 --- a/configs/sbc8548_PCI_33_PCIE_defconfig +++ b/configs/sbc8548_PCI_33_PCIE_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="33,PCIE" +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig index dd974e8..509ccf6 100644 --- a/configs/sbc8548_PCI_33_defconfig +++ b/configs/sbc8548_PCI_33_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="33" +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig index c20021b..f39aba0 100644 --- a/configs/sbc8548_PCI_66_PCIE_defconfig +++ b/configs/sbc8548_PCI_66_PCIE_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="66,PCIE" +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig index 53f6022..d8784a9 100644 --- a/configs/sbc8548_PCI_66_defconfig +++ b/configs/sbc8548_PCI_66_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="66" +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig index 3efb720..4b15a04 100644 --- a/configs/sbc8548_defconfig +++ b/configs/sbc8548_defconfig @@ -3,6 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=10 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig index 2839bc6..27f59f4 100644 --- a/configs/xpedite517x_defconfig +++ b/configs/xpedite517x_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig index c3b91f4..b605366 100644 --- a/configs/xpedite520x_defconfig +++ b/configs/xpedite520x_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig index 5ababef..def754a 100644 --- a/configs/xpedite537x_defconfig +++ b/configs/xpedite537x_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_FSL_DDR2=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y diff --git a/drivers/Kconfig b/drivers/Kconfig index e8c9e0a..0e5d97d 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -16,6 +16,8 @@ source "drivers/crypto/Kconfig"
source "drivers/demo/Kconfig"
+source "drivers/ddr/fsl/Kconfig" + source "drivers/dfu/Kconfig"
source "drivers/dma/Kconfig" diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig new file mode 100644 index 0000000..ad5858d --- /dev/null +++ b/drivers/ddr/fsl/Kconfig @@ -0,0 +1,122 @@ +config SYS_FSL_DDR + bool + help + Select Freescale General DDR driver, shared between most Freescale + PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- + based Layerscape SoCs (such as ls2080a). + +config SYS_FSL_MMDC + bool + help + Select Freescale Multi Mode DDR controller (MMDC). + +config SYS_FSL_DDR_BE + bool + help + Access DDR registers in big-endian + +config SYS_FSL_DDR_LE + bool + help + Access DDR registers in little-endian + +menu "Freescale DDR controllers" + depends on SYS_FSL_DDR + +config SYS_FSL_DDR_VER + int + default 50 if SYS_FSL_DDR_VER_50 + default 47 if SYS_FSL_DDR_VER_47 + default 46 if SYS_FSL_DDR_VER_46 + default 44 if SYS_FSL_DDR_VER_44 + +config SYS_FSL_DDR_VER_50 + bool + +config SYS_FSL_DDR_VER_47 + bool + +config SYS_FSL_DDR_VER_46 + bool + +config SYS_FSL_DDR_VER_44 + bool + +config SYS_FSL_DDRC_GEN1 + bool + help + Enable Freescale DDR controller. + +config SYS_FSL_DDRC_GEN2 + bool + depends on !MPC86xx + help + Enable Freescale DDR2 controller. + +config SYS_FSL_DDRC_86XX_GEN2 + bool + depends on MPC86xx + help + Enable Freescale DDR2 controller for MPC86xx SoCs. + +config SYS_FSL_DDRC_GEN3 + bool + depends on PPC + help + Enable Freescale DDR3 controller for PowerPC SoCs. + +config SYS_FSL_DDRC_ARM_GEN3 + bool + depends on ARM + help + Enable Freescale DDR3 controller for ARM SoCs. + +config SYS_FSL_DDRC_GEN4 + bool + help + Enable Freescale DDR4 controller. + +config SYS_FSL_HAS_DDR4 + bool + +config SYS_FSL_HAS_DDR3 + bool + +config SYS_FSL_HAS_DDR2 + bool + +config SYS_FSL_HAS_DDR1 + bool + +choice + prompt "DDR technology" + default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4 + default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3 + default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2 + default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1 + +config SYS_FSL_DDR4 + bool "Freescale DDR4 controller" + depends on SYS_FSL_HAS_DDR4 + select SYS_FSL_DDRC_GEN4 + +config SYS_FSL_DDR3 + bool "Freescale DDR3 controller" + depends on SYS_FSL_HAS_DDR3 + select SYS_FSL_DDRC_GEN3 if PPC + select SYS_FSL_DDRC_ARM_GEN3 if ARM + +config SYS_FSL_DDR2 + bool "Freescale DDR2 controller" + depends on SYS_FSL_HAS_DDR2 + select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) + select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx + +config SYS_FSL_DDR1 + bool "Freescale DDR1 controller" + depends on SYS_FSL_HAS_DDR1 + select SYS_FSL_DDRC_GEN1 + +endchoice + +endmenu diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile index 00dea42..7935f7d 100644 --- a/drivers/ddr/fsl/Makefile +++ b/drivers/ddr/fsl/Makefile @@ -30,7 +30,7 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o -obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o +obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2) += mpc86xx_ddr.o obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index e3ed317..101a398 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -228,7 +228,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_FSL_DDR3 #ifndef CONFIG_SPL_BUILD #define CONFIG_FSL_DDR_INTERACTIVE #endif diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 33c015a..7864936 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -70,7 +70,6 @@ #define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 #undef CONFIG_SYS_DDR_RAW_TIMING #undef CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index b59a7cf..ac0490d 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index a47d23c..53ee98c 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -126,7 +126,6 @@ #define CONFIG_PANIC_HANG
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x50 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 12b1ce5..d289bf4 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -60,12 +60,9 @@ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/* - * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver - * undefine it to use old spd_sdram.c + * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver + * unselect it to use old spd_sdram.c */ -#define CONFIG_SYS_FSL_DDR2 -#ifdef CONFIG_SYS_FSL_DDR2 -#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x51 @@ -74,7 +71,6 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#endif
/* * 32-bit data path mode. diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index d43c429..8075085 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -95,7 +95,6 @@
/* DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 02ad0b0..c0d74fa 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -68,7 +68,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 0d850fe..f2618a0 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -43,7 +43,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 96c0b11..406ac5a 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -52,7 +52,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 7ffacf8..84292b4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -62,7 +62,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 9f75f9b..7058b85 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -43,7 +43,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 871d14e..218d77d 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -67,7 +67,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 84fea61..3573ef4 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -50,7 +50,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index ded22b7..1b61197 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -77,7 +77,6 @@ extern unsigned long get_clock_freq(void); #endif
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 1c7dbc8..c91e032 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -82,7 +82,6 @@
/* DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 761032e..48eada5 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -79,7 +79,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 8845ea9..d413f21 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -101,7 +101,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index a01a739..ead88e7 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -224,7 +224,6 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 18ea9ac..949bdef 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -136,7 +136,6 @@ /* DDR Setup */ #define CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_FSL_DDR3
#ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 1ebe836..d8ff10e 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -68,7 +68,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 551200b..6575aca 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -165,7 +165,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 4bf4ac4..33a16d2 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -248,9 +248,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDR3 -#endif
#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 96bf4b9..6522bbf 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -273,12 +273,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_DDR_INTERACTIVE #if defined(CONFIG_TARGET_T1024RDB) #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_SDRAM_SIZE 2048 #endif diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index dc8d86a..00539ee 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -168,9 +168,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDR3 -#endif #define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 7f2de86..8debccb 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -273,9 +273,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDR3 -#endif
#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index fd5cb72..18143e5 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -221,7 +221,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 42261ed..36474e3 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -206,7 +206,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b890c10..c3c187f 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -133,7 +133,6 @@ #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3
/* * IFC Definitions diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index e931f38..3fc326b 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -178,7 +178,6 @@
/* DDR Setup */ #define CONFIG_DDR_ECC_ENABLE -#define CONFIG_SYS_FSL_DDR3 #ifndef CONFIG_DDR_ECC_ENABLE #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 744ff50..988b96d 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -122,7 +122,6 @@ #define CONFIG_SYS_SDRAM_SIZE 1024 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_FSL_DDR3 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 5720386..115df2a 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -176,7 +176,6 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 00dc58b..6f04325 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -124,7 +124,6 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 87f1932..22194f9 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -101,7 +101,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index b95be2a..a167bae 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -314,7 +314,6 @@ #endif
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index f7ec5a2..94556a7 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -81,7 +81,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M #define CONFIG_CHIP_SELECTS_PER_CTRL 1 diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index b81ff75..7c5961a 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -96,7 +96,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_DDR_ECC /* only for ECC DDR module */ /* diff --git a/include/configs/socrates.h b/include/configs/socrates.h index d148f87..806fc27 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -68,7 +68,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 91982a4..4fd6f4d 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -89,7 +89,6 @@ #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3
/* * IFC Definitions diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index df36ad7..49c485e 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -35,7 +35,6 @@ /* * DDR config */ -#define CONFIG_SYS_FSL_DDR2 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index 22ada4c..cc8b794 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -32,7 +32,6 @@ /* * DDR config */ -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 73a8a20..f37cf88 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -41,7 +41,6 @@ /* * DDR config */ -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 7582813..6203142 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -42,7 +42,6 @@ /* * DDR config */ -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 99a6d25..3c8845d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -5329,20 +5329,9 @@ CONFIG_SYS_FSL_DCSR_DDR_ADDR CONFIG_SYS_FSL_DCSR_SIZE CONFIG_SYS_FSL_DCU_BE CONFIG_SYS_FSL_DCU_LE -CONFIG_SYS_FSL_DDR -CONFIG_SYS_FSL_DDR1 -CONFIG_SYS_FSL_DDR2 CONFIG_SYS_FSL_DDR2_ADDR -CONFIG_SYS_FSL_DDR3 CONFIG_SYS_FSL_DDR3L CONFIG_SYS_FSL_DDR3_ADDR -CONFIG_SYS_FSL_DDR4 -CONFIG_SYS_FSL_DDRC_ARM_GEN3 -CONFIG_SYS_FSL_DDRC_GEN1 -CONFIG_SYS_FSL_DDRC_GEN2 -CONFIG_SYS_FSL_DDRC_GEN3 -CONFIG_SYS_FSL_DDRC_GEN4 -CONFIG_SYS_FSL_DDR_86XX CONFIG_SYS_FSL_DDR_ADDR CONFIG_SYS_FSL_DDR_BE CONFIG_SYS_FSL_DDR_EMU
On Wed, Dec 28, 2016 at 08:43:40AM -0800, York Sun wrote:
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use Kconfig to select errata workaround.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/arm/cpu/armv7/ls102xa/Kconfig | 7 ++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 41 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 20 ----------- arch/arm/include/asm/arch-ls102xa/config.h | 4 --- drivers/ddr/fsl/Kconfig | 21 ++++++++++++ 5 files changed, 69 insertions(+), 24 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index eca1d06..4b904f3 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,5 +1,9 @@ config ARCH_LS1021A bool + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A008407 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -56,4 +60,7 @@ config SYS_FSL_IFC_BANK_COUNT depends on ARCH_LS1021A default 8
+config SYS_FSL_ERRATUM_A008407 + bool + endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index bee7d15..af84e40 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -11,6 +11,11 @@ config ARCH_LS1043A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A009660 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009929 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 @@ -22,6 +27,11 @@ config ARCH_LS1046A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A009801 + select SYS_FSL_ERRATUM_A009803 + select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 @@ -38,6 +48,16 @@ config ARCH_LS2080A select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 + select SYS_FSL_ERRATUM_A008336 + select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A008514 + select SYS_FSL_ERRATUM_A008585 + select SYS_FSL_ERRATUM_A009635 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009801 + select SYS_FSL_ERRATUM_A009803 + select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A010165
config FSL_LSCH2 bool @@ -132,3 +152,24 @@ config SYS_HAS_SERDES bool
endmenu + +config SYS_FSL_ERRATUM_A008336 + bool + +config SYS_FSL_ERRATUM_A008514 + bool + +config SYS_FSL_ERRATUM_A008585 + bool + +config SYS_FSL_ERRATUM_A008850 + bool + +config SYS_FSL_ERRATUM_A009635 + bool + +config SYS_FSL_ERRATUM_A009660 + bool + +config SYS_FSL_ERRATUM_A009929 + bool diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index db40669..6073d44 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -111,17 +111,7 @@ #define EPU_EPCTR5 0x700060a14ULL #define EPU_EPGCR 0x700060000ULL
-#define CONFIG_SYS_FSL_ERRATUM_A008336 -#define CONFIG_SYS_FSL_ERRATUM_A008511 -#define CONFIG_SYS_FSL_ERRATUM_A008514 -#define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 -#define CONFIG_SYS_FSL_ERRATUM_A009635 -#define CONFIG_SYS_FSL_ERRATUM_A009663 -#define CONFIG_SYS_FSL_ERRATUM_A009801 -#define CONFIG_SYS_FSL_ERRATUM_A009803 -#define CONFIG_SYS_FSL_ERRATUM_A009942 -#define CONFIG_SYS_FSL_ERRATUM_A010165
/* ARM A57 CORE ERRATA */ #define CONFIG_ARM_ERRATA_826974 @@ -169,11 +159,6 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000
-#define CONFIG_SYS_FSL_ERRATUM_A008850 -#define CONFIG_SYS_FSL_ERRATUM_A009663 -#define CONFIG_SYS_FSL_ERRATUM_A009929 -#define CONFIG_SYS_FSL_ERRATUM_A009942 -#define CONFIG_SYS_FSL_ERRATUM_A009660 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_ARCH_LS1012A) @@ -204,11 +189,6 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-#define CONFIG_SYS_FSL_ERRATUM_A008511 -#define CONFIG_SYS_FSL_ERRATUM_A009801 -#define CONFIG_SYS_FSL_ERRATUM_A009803 -#define CONFIG_SYS_FSL_ERRATUM_A009942 -#define CONFIG_SYS_FSL_ERRATUM_A010165 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 1c5158b..fccd4ff 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -91,7 +91,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_DOS_PARTITION -#define CONFIG_SYS_FSL_ERRATUM_A008407
#ifdef CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM @@ -114,9 +113,6 @@
#ifdef CONFIG_LS102XA #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_FSL_ERRATUM_A008378 -#define CONFIG_SYS_FSL_ERRATUM_A009663 -#define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index ad5858d..50adca5 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -120,3 +120,24 @@ config SYS_FSL_DDR1 endchoice
endmenu + +config SYS_FSL_ERRATUM_A008378 + bool + +config SYS_FSL_ERRATUM_A008511 + bool + +config SYS_FSL_ERRATUM_A009663 + bool + +config SYS_FSL_ERRATUM_A009801 + bool + +config SYS_FSL_ERRATUM_A009803 + bool + +config SYS_FSL_ERRATUM_A009942 + bool + +config SYS_FSL_ERRATUM_A010165 + bool
On Wed, Dec 28, 2016 at 08:43:41AM -0800, York Sun wrote:
Use Kconfig to select errata workaround.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13, SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig. Move existing macros to related Kconfig.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/arm/Kconfig | 7 +++++++ arch/powerpc/cpu/mpc83xx/Kconfig | 3 +++ arch/powerpc/cpu/mpc85xx/Kconfig | 25 +++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 22 ---------------------- drivers/mmc/Kconfig | 12 ++++++++++++ include/configs/MPC8308RDB.h | 1 - include/configs/colibri_vf.h | 2 -- include/configs/hrcon.h | 1 - include/configs/pcm052.h | 3 --- include/configs/s32v234evb.h | 2 -- include/configs/strider.h | 1 - include/configs/ts4800.h | 2 -- include/configs/vf610twr.h | 2 -- scripts/config_whitelist.txt | 4 ---- 14 files changed, 47 insertions(+), 40 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d6a0a23..6a312bd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -546,6 +546,7 @@ config ARCH_RMOBILE config TARGET_S32V234EVB bool "Support s32v234evb" select ARM64 + select SYS_FSL_ERRATUM_ESDHC111
config ARCH_SNAPDRAGON bool "Qualcomm Snapdragon SoCs" @@ -602,18 +603,24 @@ config TARGET_TS4600 config TARGET_TS4800 bool "Support TS4800" select CPU_V7 + select SYS_FSL_ERRATUM_ESDHC_A001
config TARGET_VF610TWR bool "Support vf610twr" select CPU_V7 + select SYS_FSL_ERRATUM_ESDHC111
config TARGET_COLIBRI_VF bool "Support Colibri VF50/61" select CPU_V7 + select SYS_FSL_ERRATUM_ESDHC111
config TARGET_PCM052 bool "Support pcm-052" select CPU_V7 + select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_ESDHC135 + select SYS_FSL_ERRATUM_ESDHC_A001
config TARGET_BK4R1 bool "Support BK4r1" diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 6e4a931..184063c 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -22,6 +22,7 @@ config TARGET_VME8349
config TARGET_MPC8308RDB bool "Support MPC8308RDB" + select SYS_FSL_ERRATUM_ESDHC111
config TARGET_MPC8313ERDB bool "Support MPC8313ERDB" @@ -69,9 +70,11 @@ config TARGET_TQM834X
config TARGET_HRCON bool "Support hrcon" + select SYS_FSL_ERRATUM_ESDHC111
config TARGET_STRIDER bool "Support strider" + select SYS_FSL_ERRATUM_ESDHC111
endchoice
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 3e90c70..dc81a3b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -344,6 +344,7 @@ config ARCH_B4860 config ARCH_BSC9131 bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -352,6 +353,7 @@ config ARCH_BSC9131 config ARCH_BSC9132 bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -361,6 +363,7 @@ config ARCH_BSC9132 config ARCH_C29X bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -450,6 +453,7 @@ config ARCH_MPC8572 config ARCH_P1010 bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -459,6 +463,7 @@ config ARCH_P1010 config ARCH_P1011 bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -468,6 +473,7 @@ config ARCH_P1011 config ARCH_P1020 bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -477,6 +483,7 @@ config ARCH_P1020 config ARCH_P1021 bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -486,6 +493,7 @@ config ARCH_P1021 config ARCH_P1022 bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -503,6 +511,7 @@ config ARCH_P1023 config ARCH_P1024 bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -512,6 +521,7 @@ config ARCH_P1024 config ARCH_P1025 bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -521,6 +531,8 @@ config ARCH_P1025 config ARCH_P2020 bool select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_ESDHC_A001 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -531,6 +543,7 @@ config ARCH_P2041 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -540,6 +553,7 @@ config ARCH_P3041 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -549,6 +563,9 @@ config ARCH_P4080 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_ESDHC13 + select SYS_FSL_ERRATUM_ESDHC135 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -558,6 +575,7 @@ config ARCH_P5020 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -567,6 +585,7 @@ config ARCH_P5040 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -579,6 +598,7 @@ config ARCH_T1023 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC @@ -589,6 +609,7 @@ config ARCH_T1024 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC @@ -599,6 +620,7 @@ config ARCH_T1040 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC @@ -609,6 +631,7 @@ config ARCH_T1042 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC @@ -619,6 +642,7 @@ config ARCH_T2080 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -628,6 +652,7 @@ config ARCH_T2081 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6aee5bc..aa06e64 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -81,7 +81,6 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 @@ -107,7 +106,6 @@ #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125
@@ -115,7 +113,6 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT @@ -126,7 +123,6 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -138,7 +134,6 @@ #define CONFIG_TSECV2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 @@ -164,7 +159,6 @@ #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125
@@ -174,7 +168,6 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -182,8 +175,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020) -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -209,7 +200,6 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 @@ -244,7 +234,6 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 @@ -283,9 +272,6 @@ #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC13 #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 @@ -328,7 +314,6 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 @@ -362,7 +347,6 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 @@ -383,7 +367,6 @@ #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_ESDHC_HC_BLK_ADDR @@ -400,7 +383,6 @@ #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_ERRATUM_A005125 @@ -560,7 +542,6 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -598,7 +579,6 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -651,7 +631,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A007212 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006379 @@ -663,7 +642,6 @@ #elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2_1 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 5e84a41..abe6d17 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -111,3 +111,15 @@ config SANDBOX_MMC MMC build errors with sandbox.
endmenu + +config SYS_FSL_ERRATUM_ESDHC111 + bool + +config SYS_FSL_ERRATUM_ESDHC13 + bool + +config SYS_FSL_ERRATUM_ESDHC135 + bool + +config SYS_FSL_ERRATUM_ESDHC_A001 + bool diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 6335c55..47b180b 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -26,7 +26,6 @@ #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
#define CONFIG_GENERIC_MMC diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 47dea62..97db83e 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -61,8 +61,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 - #define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 9677aab..a1d9121 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -27,7 +27,6 @@ #define CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index e70c3f0..934deb0 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -71,9 +71,6 @@ #define CONFIG_SYS_FSL_ESDHC_NUM 1
/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ -#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h index 9f85fdc..291af06 100644 --- a/include/configs/s32v234evb.h +++ b/include/configs/s32v234evb.h @@ -83,8 +83,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 - #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC /* #define CONFIG_CMD_EXT2 EXT2 Support */ diff --git a/include/configs/strider.h b/include/configs/strider.h index 6604cec..fe7b25b 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -27,7 +27,6 @@ #define CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h index 2e5f38d..6053990 100644 --- a/include/configs/ts4800.h +++ b/include/configs/ts4800.h @@ -59,8 +59,6 @@ #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 - #define CONFIG_MMC
#define CONFIG_GENERIC_MMC diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 6aeb078..59a2012 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -69,8 +69,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 - #define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3c8845d..b83626d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -5403,10 +5403,6 @@ CONFIG_SYS_FSL_ERRATUM_DDR_115 CONFIG_SYS_FSL_ERRATUM_DDR_A003 CONFIG_SYS_FSL_ERRATUM_DDR_A003474 CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -CONFIG_SYS_FSL_ERRATUM_ESDHC111 -CONFIG_SYS_FSL_ERRATUM_ESDHC13 -CONFIG_SYS_FSL_ERRATUM_ESDHC135 -CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 CONFIG_SYS_FSL_ERRATUM_I2C_A004447 CONFIG_SYS_FSL_ERRATUM_IFC_A002769 CONFIG_SYS_FSL_ERRATUM_IFC_A003399
On Wed, Dec 28, 2016 at 08:43:42AM -0800, York Sun wrote:
Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13, SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig. Move existing macros to related Kconfig.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use Kconfig to select errata workaround.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 317 ++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/include/asm/config_mpc85xx.h | 157 --------------- drivers/ddr/fsl/Kconfig | 15 ++ include/configs/BSC9132QDS.h | 1 - scripts/config_whitelist.txt | 52 ----- 7 files changed, 334 insertions(+), 212 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index dc81a3b..9154168 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -327,6 +327,16 @@ config ARCH_B4420 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A005871 + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006384 + select SYS_FSL_ERRATUM_A006475 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007075 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -336,6 +346,16 @@ config ARCH_B4860 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A005871 + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006384 + select SYS_FSL_ERRATUM_A006475 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007075 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -344,6 +364,8 @@ config ARCH_B4860 config ARCH_BSC9131 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -353,7 +375,12 @@ config ARCH_BSC9131 config ARCH_BSC9132 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_A005434 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_IFC_A002769 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -363,6 +390,7 @@ config ARCH_BSC9132 config ARCH_C29X bool select FSL_LAW + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -373,6 +401,8 @@ config ARCH_C29X config ARCH_MPC8536 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -396,6 +426,7 @@ config ARCH_MPC8541 config ARCH_MPC8544 bool select FSL_LAW + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -405,6 +436,11 @@ config ARCH_MPC8544 config ARCH_MPC8548 bool select FSL_LAW + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_NMG_DDR120 + select SYS_FSL_ERRATUM_NMG_LBC103 + select SYS_FSL_ERRATUM_NMG_ETSEC129 + select SYS_FSL_ERRATUM_I2C_A004447 select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_SEC @@ -436,6 +472,8 @@ config ARCH_MPC8568 config ARCH_MPC8569 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -444,6 +482,10 @@ config ARCH_MPC8569 config ARCH_MPC8572 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_DDR_115 + select SYS_FSL_ERRATUM_DDR111_DDR134 select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -453,7 +495,17 @@ config ARCH_MPC8572 config ARCH_P1010 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_A007075 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_IFC_A002769 + select SYS_FSL_ERRATUM_P1010_A003549 + select SYS_FSL_ERRATUM_SEC_A003571 + select SYS_FSL_ERRATUM_IFC_A003399 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -463,6 +515,9 @@ config ARCH_P1010 config ARCH_P1011 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -473,6 +528,9 @@ config ARCH_P1011 config ARCH_P1020 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -483,6 +541,9 @@ config ARCH_P1020 config ARCH_P1021 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -493,7 +554,12 @@ config ARCH_P1021 config ARCH_P1022 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_SATA_A001 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -503,6 +569,9 @@ config ARCH_P1022 config ARCH_P1023 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_I2C_A004447 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -511,6 +580,9 @@ config ARCH_P1023 config ARCH_P1024 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -521,6 +593,9 @@ config ARCH_P1024 config ARCH_P1025 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -531,6 +606,9 @@ config ARCH_P1025 config ARCH_P2020 bool select FSL_LAW + select SYS_FSL_ERRATUM_A004477 + select SYS_FSL_ERRATUM_A004508 + select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_ESDHC_A001 select SYS_FSL_HAS_DDR3 @@ -543,7 +621,17 @@ config ARCH_P2041 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_CPU_A003999 + select SYS_FSL_ERRATUM_DDR_A003 + select SYS_FSL_ERRATUM_DDR_A003474 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_NMG_CPU_A011 + select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -553,7 +641,18 @@ config ARCH_P3041 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A005812 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_CPU_A003999 + select SYS_FSL_ERRATUM_DDR_A003 + select SYS_FSL_ERRATUM_DDR_A003474 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_NMG_CPU_A011 + select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -563,9 +662,29 @@ config ARCH_P4080 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004580 + select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A005812 + select SYS_FSL_ERRATUM_A007075 + select SYS_FSL_ERRATUM_CPC_A002 + select SYS_FSL_ERRATUM_CPC_A003 + select SYS_FSL_ERRATUM_CPU_A003999 + select SYS_FSL_ERRATUM_DDR_A003 + select SYS_FSL_ERRATUM_DDR_A003474 + select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_ESDHC13 select SYS_FSL_ERRATUM_ESDHC135 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_NMG_CPU_A011 + select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_P4080_ERRATUM_CPU22 + select SYS_P4080_ERRATUM_PCIE_A003 + select SYS_P4080_ERRATUM_SERDES8 + select SYS_P4080_ERRATUM_SERDES9 + select SYS_P4080_ERRATUM_SERDES_A001 + select SYS_P4080_ERRATUM_SERDES_A005 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -575,7 +694,14 @@ config ARCH_P5020 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_DDR_A003 + select SYS_FSL_ERRATUM_DDR_A003474 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_I2C_A004447 + select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -585,7 +711,14 @@ config ARCH_P5040 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A004699 + select SYS_FSL_ERRATUM_A005812 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_DDR_A003 + select SYS_FSL_ERRATUM_DDR_A003474 select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -598,6 +731,9 @@ config ARCH_T1023 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 @@ -609,6 +745,9 @@ config ARCH_T1024 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 @@ -620,6 +759,10 @@ config ARCH_T1040 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A008044 + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 @@ -631,6 +774,10 @@ config ARCH_T1042 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A008044 + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 @@ -642,6 +789,11 @@ config ARCH_T2080 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -652,6 +804,11 @@ config ARCH_T2081 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007212 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -662,6 +819,13 @@ config ARCH_T4160 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004468 + select SYS_FSL_ERRATUM_A005871 + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007798 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -671,6 +835,14 @@ config ARCH_T4240 bool select E500MC select FSL_LAW + select SYS_FSL_ERRATUM_A004468 + select SYS_FSL_ERRATUM_A005871 + select SYS_FSL_ERRATUM_A006261 + select SYS_FSL_ERRATUM_A006379 + select SYS_FSL_ERRATUM_A006593 + select SYS_FSL_ERRATUM_A007186 + select SYS_FSL_ERRATUM_A007798 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -782,6 +954,151 @@ config SYS_CCSRBAR_DEFAULT if changed by pre-boot regime. The value here must match the current value in SoC. If not sure, do not change.
+config SYS_FSL_ERRATUM_A004468 + bool + +config SYS_FSL_ERRATUM_A004477 + bool + +config SYS_FSL_ERRATUM_A004508 + bool + +config SYS_FSL_ERRATUM_A004580 + bool + +config SYS_FSL_ERRATUM_A004699 + bool + +config SYS_FSL_ERRATUM_A004849 + bool + +config SYS_FSL_ERRATUM_A004510 + bool + +config SYS_FSL_ERRATUM_A004510_SVR_REV + hex + depends on SYS_FSL_ERRATUM_A004510 + default 0x20 if ARCH_P4080 + default 0x10 + +config SYS_FSL_ERRATUM_A004510_SVR_REV2 + hex + depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) + default 0x11 + +config SYS_FSL_ERRATUM_A005125 + bool + +config SYS_FSL_ERRATUM_A005434 + bool + +config SYS_FSL_ERRATUM_A005812 + bool + +config SYS_FSL_ERRATUM_A005871 + bool + +config SYS_FSL_ERRATUM_A006261 + bool + +config SYS_FSL_ERRATUM_A006379 + bool + +config SYS_FSL_ERRATUM_A006384 + bool + +config SYS_FSL_ERRATUM_A006475 + bool + +config SYS_FSL_ERRATUM_A006593 + bool + +config SYS_FSL_ERRATUM_A007075 + bool + +config SYS_FSL_ERRATUM_A007186 + bool + +config SYS_FSL_ERRATUM_A007212 + bool + +config SYS_FSL_ERRATUM_A007798 + bool + +config SYS_FSL_ERRATUM_A008044 + bool + +config SYS_FSL_ERRATUM_CPC_A002 + bool + +config SYS_FSL_ERRATUM_CPC_A003 + bool + +config SYS_FSL_ERRATUM_CPU_A003999 + bool + +config SYS_FSL_ERRATUM_ELBC_A001 + bool + +config SYS_FSL_ERRATUM_I2C_A004447 + bool + +config SYS_FSL_A004447_SVR_REV + hex + depends on SYS_FSL_ERRATUM_I2C_A004447 + default 0x00 if ARCH_MPC8548 + default 0x10 if ARCH_P1010 + default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 + default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 + +config SYS_FSL_ERRATUM_IFC_A002769 + bool + +config SYS_FSL_ERRATUM_IFC_A003399 + bool + +config SYS_FSL_ERRATUM_NMG_CPU_A011 + bool + +config SYS_FSL_ERRATUM_NMG_ETSEC129 + bool + +config SYS_FSL_ERRATUM_NMG_LBC103 + bool + +config SYS_FSL_ERRATUM_P1010_A003549 + bool + +config SYS_FSL_ERRATUM_SATA_A001 + bool + +config SYS_FSL_ERRATUM_SEC_A003571 + bool + +config SYS_FSL_ERRATUM_SRIO_A004034 + bool + +config SYS_FSL_ERRATUM_USB14 + bool + +config SYS_P4080_ERRATUM_CPU22 + bool + +config SYS_P4080_ERRATUM_PCIE_A003 + bool + +config SYS_P4080_ERRATUM_SERDES8 + bool + +config SYS_P4080_ERRATUM_SERDES9 + bool + +config SYS_P4080_ERRATUM_SERDES_A001 + bool + +config SYS_P4080_ERRATUM_SERDES_A005 + bool + config SYS_FSL_NUM_LAWS int "Number of local access windows" depends on FSL_LAW diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 402a1ff..54b5b33 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -136,7 +136,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif __maybe_unused u32 svr = get_svr();
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001) if (IS_SVR_REV(svr, 1, 0)) { switch (SVR_SOC_VER(svr)) { case SVR_P1013: diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index d1b6699..4dff5c8 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -975,7 +975,7 @@ int cpu_init_r(void) #endif #endif
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001) /* * For P1022/1013 Rev1.0 silicon, after power on SATA host * controller is configured in legacy mode instead of the diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index aa06e64..0eaa944 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -23,28 +23,19 @@ #define CONFIG_SYS_FSL_SEC_MON_BE
#if defined(CONFIG_ARCH_MPC8536) -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8540)
#elif defined(CONFIG_ARCH_MPC8541)
#elif defined(CONFIG_ARCH_MPC8544) -#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8548) -#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 -#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 -#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#define CONFIG_SYS_FSL_ERRATUM_A005125 -#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 -#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
#elif defined(CONFIG_ARCH_MPC8555)
@@ -69,14 +60,8 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8572) -#define CONFIG_SYS_FSL_ERRATUM_DDR_115 -#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 @@ -86,18 +71,7 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 -#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 -#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 -#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#define CONFIG_SYS_FSL_ERRATUM_A005125 -#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_ERRATUM_A006261 -#define CONFIG_SYS_FSL_ERRATUM_A004477 -#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 #define CONFIG_ESDHC_HC_BLK_ADDR
/* P1011 is single core version of P1020 */ @@ -105,16 +79,10 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1020) #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif @@ -122,22 +90,14 @@ #elif defined(CONFIG_ARCH_P1021) #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022) #define CONFIG_TSECV2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_FSL_SATA_ERRATUM_A001 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 -#define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_ARCH_P1023) #define CONFIG_SYS_NUM_FMAN 1 @@ -148,31 +108,21 @@ #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 -#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 -#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
/* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020) #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 @@ -180,9 +130,6 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 -#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ @@ -200,23 +147,10 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 -#define CONFIG_SYS_FSL_ERRATUM_USB14 -#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_ERRATUM_A004510 -#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 -#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 -#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 -#define CONFIG_SYS_FSL_ERRATUM_A004849 -#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 -#define CONFIG_SYS_FSL_ERRATUM_A006261 -#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#elif defined(CONFIG_ARCH_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -234,24 +168,10 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 -#define CONFIG_SYS_FSL_ERRATUM_USB14 -#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_ERRATUM_A004510 -#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 -#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 -#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 -#define CONFIG_SYS_FSL_ERRATUM_A004849 -#define CONFIG_SYS_FSL_ERRATUM_A005812 -#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 -#define CONFIG_SYS_FSL_ERRATUM_A006261 -#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -268,34 +188,12 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" -#define CONFIG_SYS_FSL_ERRATUM_CPC_A002 -#define CONFIG_SYS_FSL_ERRATUM_CPC_A003 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_P4080_ERRATUM_CPU22 -#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 -#define CONFIG_SYS_P4080_ERRATUM_SERDES8 -#define CONFIG_SYS_P4080_ERRATUM_SERDES9 -#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 -#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 -#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#define CONFIG_SYS_FSL_ERRATUM_A004510 -#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 -#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 -#define CONFIG_SYS_FSL_ERRATUM_A004849 -#define CONFIG_SYS_FSL_ERRATUM_A004580 -#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 -#define CONFIG_SYS_FSL_ERRATUM_A005812 -#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 -#define CONFIG_SYS_FSL_ERRATUM_A007075 -#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ @@ -314,19 +212,10 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_USB14 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_ERRATUM_A004510 -#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 -#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 -#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 -#define CONFIG_SYS_FSL_ERRATUM_A006261 -#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_PPC64 @@ -347,15 +236,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_USB14 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_ERRATUM_A004699 -#define CONFIG_SYS_FSL_ERRATUM_A004510 -#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 -#define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 -#define CONFIG_SYS_FSL_ERRATUM_A005812
#elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 @@ -367,8 +248,6 @@ #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_FSL_ERRATUM_A005125 -#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_BSC9132) @@ -385,11 +264,6 @@ #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_FSL_ERRATUM_A005125 -#define CONFIG_SYS_FSL_ERRATUM_A005434 -#define CONFIG_SYS_FSL_ERRATUM_A004477 -#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 -#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) @@ -406,7 +280,6 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_ERRATUM_A006261 #else #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -439,13 +312,6 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_A004468 -#define CONFIG_SYS_FSL_ERRATUM_A005871 -#define CONFIG_SYS_FSL_ERRATUM_A006379 -#define CONFIG_SYS_FSL_ERRATUM_A007186 -#define CONFIG_SYS_FSL_ERRATUM_A006593 -#define CONFIG_SYS_FSL_ERRATUM_A007798 -#define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -476,16 +342,6 @@ #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_ERRATUM_A005871 -#define CONFIG_SYS_FSL_ERRATUM_A006379 -#define CONFIG_SYS_FSL_ERRATUM_A007186 -#define CONFIG_SYS_FSL_ERRATUM_A006593 -#define CONFIG_SYS_FSL_ERRATUM_A007075 -#define CONFIG_SYS_FSL_ERRATUM_A006475 -#define CONFIG_SYS_FSL_ERRATUM_A006384 -#define CONFIG_SYS_FSL_ERRATUM_A007212 -#define CONFIG_SYS_FSL_ERRATUM_A004477 -#define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_ARCH_B4860 @@ -529,7 +385,6 @@ #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FSL_ERRATUM_A008044 #define CONFIG_SYS_FMAN_V3 #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV @@ -547,9 +402,6 @@ #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 -#define CONFIG_SYS_FSL_ERRATUM_A008378 -#define CONFIG_SYS_FSL_ERRATUM_A009663 -#define CONFIG_SYS_FSL_ERRATUM_A009942
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) #define CONFIG_E5500 @@ -584,9 +436,6 @@ #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 -#define CONFIG_SYS_FSL_ERRATUM_A008378 -#define CONFIG_SYS_FSL_ERRATUM_A009663 -#define CONFIG_SYS_FSL_ERRATUM_A009942
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define CONFIG_E6500 @@ -628,13 +477,8 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_A007212 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 -#define CONFIG_SYS_FSL_ERRATUM_A006593 -#define CONFIG_SYS_FSL_ERRATUM_A007186 -#define CONFIG_SYS_FSL_ERRATUM_A006379 -#define CONFIG_SYS_FSL_ERRATUM_A009942 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define CONFIG_SYS_FSL_SFP_VER_3_0
@@ -645,7 +489,6 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 50adca5..7b7e4f2 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -141,3 +141,18 @@ config SYS_FSL_ERRATUM_A009942
config SYS_FSL_ERRATUM_A010165 bool + +config SYS_FSL_ERRATUM_NMG_DDR120 + bool + +config SYS_FSL_ERRATUM_DDR_115 + bool + +config SYS_FSL_ERRATUM_DDR111_DDR134 + bool + +config SYS_FSL_ERRATUM_DDR_A003 + bool + +config SYS_FSL_ERRATUM_DDR_A003474 + bool diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index ac0490d..fcd8620 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -20,7 +20,6 @@ #define CONFIG_SYS_TEXT_BASE 0x11000000 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif -#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_RAMBOOT diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b83626d..2d5d30d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1296,7 +1296,6 @@ CONFIG_FSL_QIXIS CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT CONFIG_FSL_QIXIS_V2 CONFIG_FSL_SATA -CONFIG_FSL_SATA_ERRATUM_A001 CONFIG_FSL_SATA_V2 CONFIG_FSL_SDHC_V2_3 CONFIG_FSL_SDRAM_TYPE @@ -5355,31 +5354,7 @@ CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR -CONFIG_SYS_FSL_ERRATUM_A004468 -CONFIG_SYS_FSL_ERRATUM_A004477 -CONFIG_SYS_FSL_ERRATUM_A004508 -CONFIG_SYS_FSL_ERRATUM_A004510 -CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV -CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 -CONFIG_SYS_FSL_ERRATUM_A004580 -CONFIG_SYS_FSL_ERRATUM_A004699 -CONFIG_SYS_FSL_ERRATUM_A004849 -CONFIG_SYS_FSL_ERRATUM_A005125 -CONFIG_SYS_FSL_ERRATUM_A005434 -CONFIG_SYS_FSL_ERRATUM_A005812 -CONFIG_SYS_FSL_ERRATUM_A005871 -CONFIG_SYS_FSL_ERRATUM_A006261 -CONFIG_SYS_FSL_ERRATUM_A006379 -CONFIG_SYS_FSL_ERRATUM_A006384 -CONFIG_SYS_FSL_ERRATUM_A006475 -CONFIG_SYS_FSL_ERRATUM_A006593 -CONFIG_SYS_FSL_ERRATUM_A007075 -CONFIG_SYS_FSL_ERRATUM_A007186 -CONFIG_SYS_FSL_ERRATUM_A007212 -CONFIG_SYS_FSL_ERRATUM_A007798 -CONFIG_SYS_FSL_ERRATUM_A008044 CONFIG_SYS_FSL_ERRATUM_A008336 -CONFIG_SYS_FSL_ERRATUM_A008378 CONFIG_SYS_FSL_ERRATUM_A008407 CONFIG_SYS_FSL_ERRATUM_A008511 CONFIG_SYS_FSL_ERRATUM_A008514 @@ -5388,32 +5363,11 @@ CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ERRATUM_A008850 CONFIG_SYS_FSL_ERRATUM_A009635 CONFIG_SYS_FSL_ERRATUM_A009660 -CONFIG_SYS_FSL_ERRATUM_A009663 CONFIG_SYS_FSL_ERRATUM_A009801 CONFIG_SYS_FSL_ERRATUM_A009803 CONFIG_SYS_FSL_ERRATUM_A009929 -CONFIG_SYS_FSL_ERRATUM_A009942 CONFIG_SYS_FSL_ERRATUM_A010165 CONFIG_SYS_FSL_ERRATUM_A_004934 -CONFIG_SYS_FSL_ERRATUM_CPC_A002 -CONFIG_SYS_FSL_ERRATUM_CPC_A003 -CONFIG_SYS_FSL_ERRATUM_CPU_A003999 -CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 -CONFIG_SYS_FSL_ERRATUM_DDR_115 -CONFIG_SYS_FSL_ERRATUM_DDR_A003 -CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -CONFIG_SYS_FSL_ERRATUM_I2C_A004447 -CONFIG_SYS_FSL_ERRATUM_IFC_A002769 -CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 -CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 -CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 -CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 -CONFIG_SYS_FSL_ERRATUM_P1010_A003549 -CONFIG_SYS_FSL_ERRATUM_SEC_A003571 -CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 -CONFIG_SYS_FSL_ERRATUM_USB14 CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_FSL_ESDHC_BE CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT @@ -6753,12 +6707,6 @@ CONFIG_SYS_OSD_DH CONFIG_SYS_OSD_SCREENS CONFIG_SYS_OSPR_OFFSET CONFIG_SYS_OS_BASE -CONFIG_SYS_P4080_ERRATUM_CPU22 -CONFIG_SYS_P4080_ERRATUM_PCIE_A003 -CONFIG_SYS_P4080_ERRATUM_SERDES8 -CONFIG_SYS_P4080_ERRATUM_SERDES9 -CONFIG_SYS_P4080_ERRATUM_SERDES_A001 -CONFIG_SYS_P4080_ERRATUM_SERDES_A005 CONFIG_SYS_PACNT CONFIG_SYS_PADAT CONFIG_SYS_PADDR
On Wed, Dec 28, 2016 at 08:43:43AM -0800, York Sun wrote:
Use Kconfig to select errata workaround.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ---- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 5 ----- arch/powerpc/include/asm/config_mpc85xx.h | 17 ----------------- drivers/ddr/fsl/Kconfig | 14 ++++++++++++++ include/configs/B4860QDS.h | 1 - include/configs/BSC9131RDB.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8540ADS.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 1 - include/configs/MPC8548CDS.h | 1 - include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/P1022DS.h | 1 - include/configs/T1040QDS.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/UCP1020.h | 1 - include/configs/controlcenterd.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/p1_twr.h | 1 - include/configs/sbc8548.h | 1 - include/configs/sbc8641d.h | 2 -- include/configs/socrates.h | 1 - include/configs/t4qds.h | 1 - include/configs/xpedite517x.h | 1 - include/configs/xpedite520x.h | 1 - include/configs/xpedite537x.h | 1 - include/configs/xpedite550x.h | 1 - scripts/config_whitelist.txt | 1 - 36 files changed, 14 insertions(+), 59 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 4b904f3..9ffb90e 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -33,10 +33,6 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores.
-config NUM_DDR_CONTROLLERS - int "Maximum DDR controllers" - default 1 - config SECURE_BOOT bool "Secure Boot" help diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index af84e40..de0b580 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -115,11 +115,6 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores.
-config NUM_DDR_CONTROLLERS - int "Maximum DDR controllers" - default 3 if ARCH_LS2080A - default 1 - config SECURE_BOOT bool help diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0eaa944..dbc8d7a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -66,7 +66,6 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -102,7 +101,6 @@ #elif defined(CONFIG_ARCH_P1023) #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 @@ -139,7 +137,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 @@ -159,7 +156,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 @@ -182,7 +178,6 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 @@ -203,7 +198,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 @@ -227,7 +221,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 @@ -241,7 +234,6 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 @@ -253,7 +245,6 @@ #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 @@ -279,13 +270,11 @@ #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 2 -#define CONFIG_NUM_DDR_CONTROLLERS 3 #else #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 2 #if defined(CONFIG_ARCH_T4160) #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #endif @@ -352,7 +341,6 @@ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 @@ -365,7 +353,6 @@ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) @@ -379,7 +366,6 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV @@ -417,7 +403,6 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -462,7 +447,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 2 #endif #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FM1_CLK 0 @@ -486,7 +470,6 @@ #elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2_1 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 7b7e4f2..b035502 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -23,6 +23,20 @@ config SYS_FSL_DDR_LE menu "Freescale DDR controllers" depends on SYS_FSL_DDR
+config NUM_DDR_CONTROLLERS + int "Maximum DDR controllers" + default 3 if ARCH_LS2080A || \ + ARCH_T4240 + default 2 if ARCH_B4860 || \ + ARCH_BSC9132 || \ + ARCH_MPC8572 || \ + ARCH_MPC8641 || \ + ARCH_P4080 || \ + ARCH_P5020 || \ + ARCH_P5040 || \ + ARCH_T4160 + default 1 + config SYS_FSL_DDR_VER int default 50 if SYS_FSL_DDR_VER_50 diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 101a398..e5c220e 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -222,7 +222,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 7864936..a6f73f2 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -84,7 +84,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index d289bf4..3d3eeb5 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -66,7 +66,6 @@ #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x51 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8075085..a64f0de 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -105,7 +105,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index c0d74fa..3389a77 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -77,7 +77,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index f2618a0..00a18b5 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -52,7 +52,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 406ac5a..b9c62e1 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -63,7 +63,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 84292b4..c241b51 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -73,7 +73,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 7058b85..6faa230 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -52,7 +52,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 218d77d..e0d010a 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -76,7 +76,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 3573ef4..0d3707f 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -60,7 +60,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 1b61197..ce389ad 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -88,7 +88,6 @@ extern unsigned long get_clock_freq(void); /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index c91e032..5ca01e8 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -93,7 +93,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 48eada5..c5f3634 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -91,7 +91,6 @@ #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d413f21..fb66bb6 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -113,7 +113,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 949bdef..7a83c56 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -145,7 +145,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 00539ee..8393619 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -163,7 +163,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8debccb..4ee17f9 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -268,7 +268,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index c3c187f..f68ab2e 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -127,7 +127,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 3fc326b..8233978 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -191,7 +191,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 988b96d..d2172e9 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -122,7 +122,6 @@ #define CONFIG_SYS_SDRAM_SIZE 1024 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index a167bae..13effde 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -331,7 +331,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 94556a7..2d61c19 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -89,7 +89,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 7c5961a..281a993 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -116,7 +116,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 87056db..f02634b 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -57,7 +57,6 @@ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CACHE_LINE_INTERLEAVING 0x20000000 #define PAGE_INTERLEAVING 0x21000000 #define BANK_INTERLEAVING 0x22000000 @@ -103,7 +102,6 @@ #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 806fc27..6480116 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -79,7 +79,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 4fd6f4d..e82df33 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -83,7 +83,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 49c485e..0d5b1ff 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -41,7 +41,6 @@ #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_DDR_ECC diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index cc8b794..b88aeb4 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -37,7 +37,6 @@ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x54 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 #define CONFIG_DDR_ECC diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index f37cf88..5d78560 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -48,7 +48,6 @@ #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_DDR_ECC diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 6203142..35e6350 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -47,7 +47,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x54 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 #define CONFIG_DDR_ECC diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2d5d30d..37d692e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3320,7 +3320,6 @@ CONFIG_NR_DRAM_POPULATED CONFIG_NS16550_MIN_FUNCTIONS CONFIG_NS8382X CONFIG_NS87308 -CONFIG_NUM_DDR_CONTROLLERS CONFIG_NUM_DSP_CPUS CONFIG_NUM_PAMU CONFIG_OCLK_DIV
On Wed, Dec 28, 2016 at 08:43:44AM -0800, York Sun wrote:
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/cpu/mpc85xx/cpu.c | 22 +++++++++++----------- arch/powerpc/cpu/mpc85xx/cpu_init.c | 16 ++++++++-------- board/freescale/b4860qds/ddr.c | 4 ++-- board/freescale/corenet_ds/ddr.c | 6 +++--- drivers/ddr/fsl/Kconfig | 2 +- drivers/ddr/fsl/arm_ddr_gen3.c | 6 +++--- drivers/ddr/fsl/ctrl_regs.c | 6 +++--- drivers/ddr/fsl/fsl_ddr_gen4.c | 6 +++--- drivers/ddr/fsl/interactive.c | 14 +++++++------- drivers/ddr/fsl/main.c | 30 +++++++++++++++--------------- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 6 +++--- drivers/ddr/fsl/options.c | 30 +++++++++++++++--------------- drivers/ddr/fsl/util.c | 28 ++++++++++++++-------------- include/configs/B4860QDS.h | 2 +- include/configs/P2041RDB.h | 2 +- include/configs/T102xQDS.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T1040QDS.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/corenet_ds.h | 2 +- include/configs/cyrus.h | 2 +- include/configs/km/kmp204x-common.h | 2 +- include/configs/t4qds.h | 2 +- include/fsl_ddr.h | 3 +-- scripts/config_whitelist.txt | 1 - 28 files changed, 102 insertions(+), 104 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index d180c73..cc30fa6 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -482,17 +482,17 @@ static void dump_spd_ddr_reg(void) int i, j, k, m; u8 *p_8; u32 *p_32; - struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS]; + struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS]; generic_spd_eeprom_t - spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; + spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
puts("SPD data of all dimms (zero value is omitted)...\n"); puts("Byte (hex) "); k = 1; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) printf("Dimm%d ", k++); } @@ -500,7 +500,7 @@ static void dump_spd_ddr_reg(void) for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { m = 0; printf("%3d (0x%02x) ", k, k); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { p_8 = (u8 *) &spd[i][j]; if (p_8[k]) { @@ -516,22 +516,22 @@ static void dump_spd_ddr_reg(void) puts("\r"); }
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { switch (i) { case 0: ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) case 3: ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; @@ -545,13 +545,13 @@ static void dump_spd_ddr_reg(void) printf("DDR registers dump for all controllers " "(zero value is omitted)...\n"); puts("Offset (hex) "); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); puts("\n"); for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) { m = 0; printf("%6d (0x%04x)", k * 4, k * 4); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { p_32 = (u32 *) ddr[i]; if (p_32[k]) { printf(" 0x%08x", p_32[k]); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4dff5c8..822844d 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -378,10 +378,10 @@ void fsl_erratum_a007212_workaround(void) u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); #endif @@ -409,25 +409,25 @@ void fsl_erratum_a007212_workaround(void) ddr_pll_ratio >>= 1;
setbits_be32(plldadcr1, 0x02000001); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) setbits_be32(plldadcr2, 0x02000001); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) setbits_be32(plldadcr3, 0x02000001); #endif #endif setbits_be32(dpdovrcr4, 0xe0000000); out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); #endif #endif udelay(100); clrbits_be32(plldadcr1, 0x02000001); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) clrbits_be32(plldadcr2, 0x02000001); -#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) clrbits_be32(plldadcr3, 0x02000001); #endif #endif diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index 3885acc..99cd884 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -213,7 +213,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
debug("rank density is 0x%llx, ctlr density is 0x%llx\n", rank_density, ctlr_density); - for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { + for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) { switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: @@ -237,7 +237,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, * Simple linear assignment if memory * controllers are not interleaved. */ - for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { + for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) { total_ctlr_mem = 0; pinfo->common_timing_params[i].base_address = current_mem_base; diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index f3ba41a..9c1a4c2 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; * Fixed sdram init -- doesn't use serial presence detect. */ extern fixed_ddr_parm_t fixed_ddr_parm_0[]; -#if (CONFIG_NUM_DDR_CONTROLLERS == 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) extern fixed_ddr_parm_t fixed_ddr_parm_1[]; #endif
@@ -56,7 +56,7 @@ phys_size_t fixed_sdram(void) ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) memcpy(&ddr_cfg_regs, fixed_ddr_parm_1[i].ddr_settings, sizeof(ddr_cfg_regs)); @@ -76,7 +76,7 @@ phys_size_t fixed_sdram(void) return 0; } } else { -#if (CONFIG_NUM_DDR_CONTROLLERS == 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) /* We require both controllers have identical DIMMs */ lawbar1_target_id = LAW_TRGT_IF_DDR_1; if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index b035502..a3d2bd5 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -23,7 +23,7 @@ config SYS_FSL_DDR_LE menu "Freescale DDR controllers" depends on SYS_FSL_DDR
-config NUM_DDR_CONTROLLERS +config SYS_NUM_DDR_CTLRS int "Maximum DDR controllers" default 3 if ARCH_LS2080A || \ ARCH_T4240 diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index 7160da4..5b7ced5 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -40,17 +40,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) case 3: ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index f7e87b8..21687dd 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -2318,17 +2318,17 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num, case 0: ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) case 3: ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index dadcb3a..e0f9e2c 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -68,17 +68,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) case 3: ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 49352b3..202ad13 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -763,7 +763,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, debug("fsl_ddr_regs_edit: ctrl_num = %u, " "regname = %s, value = %s\n", ctrl_num, regname, value_str); - if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS) + if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS) return;
ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]); @@ -1685,7 +1685,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 1: DIMM SPD data */ if (do_mask & STEP_GET_SPD) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { if (!(ctrl_mask & (1 << i))) continue;
@@ -1706,7 +1706,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 2: DIMM Parameters */ if (do_mask & STEP_COMPUTE_DIMM_PARMS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { if (!(ctrl_mask & (1 << i))) continue; for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { @@ -1725,7 +1725,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 3: Common Parameters */ if (do_mask & STEP_COMPUTE_COMMON_PARMS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { if (!(ctrl_mask & (1 << i))) continue; printf(""lowest common" DIMM parameters: " @@ -1739,7 +1739,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 4: User Configuration Options */ if (do_mask & STEP_GATHER_OPTS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { if (!(ctrl_mask & (1 << i))) continue; printf("User Config Options: Controller=%u\n", i); @@ -1751,7 +1751,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 5: Address assignment */ if (do_mask & STEP_ASSIGN_ADDRESSES) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { if (!(ctrl_mask & (1 << i))) continue; for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { @@ -1766,7 +1766,7 @@ static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
/* STEP 6: computed controller register values */ if (do_mask & STEP_COMPUTE_REGS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { if (!(ctrl_mask & (1 << i))) continue; printf("Computed Register Values: Controller=%u\n", i); diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 479184f..159c22e 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -40,35 +40,35 @@ void fsl_ddr_set_intl3r(const unsigned int granule_size); #if defined(SPD_EEPROM_ADDRESS) || \ defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) -#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { +#if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { [0][0] = SPD_EEPROM_ADDRESS, }; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { +#elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ }; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { +#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ }; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { +#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ }; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { +#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ }; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { +#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ @@ -146,7 +146,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, unsigned int i; unsigned int i2c_address = 0;
- if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { + if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); return; } @@ -430,7 +430,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, assert_reset = pinfo->board_need_mem_reset();
/* data bus width capacity adjust shift amount */ - unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; + unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
for (i = first_ctrl; i <= last_ctrl; i++) dbw_capacity_adjust[i] = 0; @@ -720,7 +720,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo) &pinfo->common_timing_params[i], law_memctl, i); } -#if CONFIG_NUM_DDR_CONTROLLERS > 3 +#if CONFIG_SYS_NUM_DDR_CTLRS > 3 else if (i == 2) { law_memctl = LAW_TRGT_IF_DDR_INTLV_34; fsl_ddr_set_lawbar( diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 1bfb9d4..afbed59 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -44,17 +44,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) case 3: ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 793d12a..d6a8fcb 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -1077,7 +1077,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving * with 256 Byte is enabled. */ -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if (CONFIG_SYS_NUM_DDR_CTLRS > 1) if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B ; @@ -1107,39 +1107,39 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, "ctlr_intlv", "cacheline", buf)) { popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 0 : FSL_DDR_CACHE_LINE_INTERLEAVING; popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 0 : 1; } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "page", buf)) { popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 0 : FSL_DDR_PAGE_INTERLEAVING; popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 0 : 1; } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "bank", buf)) { popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 0 : FSL_DDR_BANK_INTERLEAVING; popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 0 : 1; } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "superbank", buf)) { popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 0 : FSL_DDR_SUPERBANK_INTERLEAVING; popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? 0 : 1; -#if (CONFIG_NUM_DDR_CONTROLLERS == 3) +#if (CONFIG_SYS_NUM_DDR_CTLRS == 3) } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "3way_1KB", buf)) { @@ -1155,7 +1155,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, "3way_8KB", buf)) { popts->memctl_interleaving_mode = FSL_DDR_3WAY_8KB_INTERLEAVING; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 4) +#elif (CONFIG_SYS_NUM_DDR_CTLRS == 4) } else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", "4way_1KB", buf)) { @@ -1178,7 +1178,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, } #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */ done: -#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ +#endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */ if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { /* test null first. if CONFIG_HWCONFIG is not defined, @@ -1356,10 +1356,10 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: case FSL_DDR_SUPERBANK_INTERLEAVING: -#if (3 == CONFIG_NUM_DDR_CONTROLLERS) +#if (3 == CONFIG_SYS_NUM_DDR_CTLRS) k = 2; #else - k = CONFIG_NUM_DDR_CONTROLLERS; + k = CONFIG_SYS_NUM_DDR_CTLRS; #endif break; case FSL_DDR_3WAY_1KB_INTERLEAVING: @@ -1369,7 +1369,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) case FSL_DDR_4WAY_4KB_INTERLEAVING: case FSL_DDR_4WAY_8KB_INTERLEAVING: default: - k = CONFIG_NUM_DDR_CONTROLLERS; + k = CONFIG_SYS_NUM_DDR_CTLRS; break; } debug("%d of %d controllers are interleaving.\n", j, k); diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 9977779..b58784b 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -30,17 +30,17 @@ u32 fsl_ddr_get_version(unsigned int ctrl_num) case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) case 3: ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; @@ -174,23 +174,23 @@ void print_ddr_info(unsigned int start_ctrl) struct ccsr_ddr __iomem *ddr = (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
-#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) +#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3) u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); #endif -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if (CONFIG_SYS_NUM_DDR_CTLRS > 1) uint32_t cs0_config = ddr_in32(&ddr->cs0_config); #endif uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); int cas_lat;
-#if CONFIG_NUM_DDR_CONTROLLERS >= 2 +#if CONFIG_SYS_NUM_DDR_CTLRS >= 2 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || (start_ctrl == 1)) { ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; sdram_cfg = ddr_in32(&ddr->sdram_cfg); } #endif -#if CONFIG_NUM_DDR_CONTROLLERS >= 3 +#if CONFIG_SYS_NUM_DDR_CTLRS >= 3 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || (start_ctrl == 2)) { ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; @@ -246,7 +246,7 @@ void print_ddr_info(unsigned int start_ctrl) else puts(", ECC off)");
-#if (CONFIG_NUM_DDR_CONTROLLERS == 3) +#if (CONFIG_SYS_NUM_DDR_CTLRS == 3) #ifdef CONFIG_E6500 if (*mcintl3r & 0x80000000) { puts("\n"); @@ -268,7 +268,7 @@ void print_ddr_info(unsigned int start_ctrl) } #endif #endif -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) +#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) if ((cs0_config & 0x20000000) && (start_ctrl == 0)) { puts("\n"); puts(" DDR Controller Interleaving Mode: "); @@ -337,8 +337,8 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, { unsigned int i; u32 ddrc_debug20; - u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {}; - u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {}; + u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {}; + u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {}; struct ccsr_ddr __iomem *ddr;
for (i = first_ctrl; i <= last_ctrl; i++) { @@ -346,17 +346,17 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) case 3: ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index e5c220e..3ad9f80 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -62,7 +62,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 6575aca..149da1f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -40,7 +40,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 33a16d2..cf30e98 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -22,7 +22,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 6522bbf..eafa554 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -22,7 +22,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8393619..e123639 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -53,7 +53,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 4ee17f9..5f4a613 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -164,7 +164,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 18143e5..29034f9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -33,7 +33,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 36474e3..b16d78f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -27,7 +27,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index f68ab2e..8d3c928 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -72,7 +72,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 115df2a..c9c00c5 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -58,7 +58,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 6f04325..b94e120 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -49,7 +49,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 22194f9..b4cdb67 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -34,7 +34,7 @@ #define CONFIG_MP /* support multiple processors */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index e82df33..0f59eb1 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -25,7 +25,7 @@ #endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 0c3be0e..261b94e 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -15,7 +15,7 @@
#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS /* All controllers are for main memory */ -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS #endif
#ifdef CONFIG_SYS_FSL_DDR_LE @@ -54,7 +54,6 @@ compute_dimm_parameters(const unsigned int ctrl_num, * * All data structures have to be on the stack */ -#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
typedef struct { diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 37d692e..df3965f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -6630,7 +6630,6 @@ CONFIG_SYS_NS87308_UART2 CONFIG_SYS_NS87308_UART2_BASE CONFIG_SYS_NUM_ADDR_MAP CONFIG_SYS_NUM_CPC -CONFIG_SYS_NUM_DDR_CTLRS CONFIG_SYS_NUM_FM1_10GEC CONFIG_SYS_NUM_FM1_DTSEC CONFIG_SYS_NUM_FM2_10GEC
On Wed, Dec 28, 2016 at 08:43:45AM -0800, York Sun wrote:
These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use Kconfig to select DDR version instead of using config header.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 17 +++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 12 ------------ 2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 9154168..7b64ae0 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -327,6 +327,7 @@ config ARCH_B4420 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005871 select SYS_FSL_ERRATUM_A006379 @@ -346,6 +347,7 @@ config ARCH_B4860 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005871 select SYS_FSL_ERRATUM_A006379 @@ -364,6 +366,7 @@ config ARCH_B4860 config ARCH_BSC9131 bool select FSL_LAW + select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 @@ -375,6 +378,7 @@ config ARCH_BSC9131 config ARCH_BSC9132 bool select FSL_LAW + select SYS_FSL_DDR_VER_46 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_A005434 @@ -390,6 +394,7 @@ config ARCH_BSC9132 config ARCH_C29X bool select FSL_LAW + select SYS_FSL_DDR_VER_46 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 @@ -641,6 +646,7 @@ config ARCH_P3041 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 select SYS_FSL_ERRATUM_A005812 @@ -662,6 +668,7 @@ config ARCH_P4080 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004580 select SYS_FSL_ERRATUM_A004849 @@ -694,6 +701,7 @@ config ARCH_P5020 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_DDR_A003 @@ -711,6 +719,7 @@ config ARCH_P5040 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004699 select SYS_FSL_ERRATUM_A005812 @@ -731,6 +740,7 @@ config ARCH_T1023 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 @@ -745,6 +755,7 @@ config ARCH_T1024 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 @@ -759,6 +770,7 @@ config ARCH_T1040 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A009663 @@ -774,6 +786,7 @@ config ARCH_T1042 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A009663 @@ -789,6 +802,7 @@ config ARCH_T2080 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007186 @@ -804,6 +818,7 @@ config ARCH_T2081 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A007186 @@ -819,6 +834,7 @@ config ARCH_T4160 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 select SYS_FSL_ERRATUM_A005871 select SYS_FSL_ERRATUM_A006379 @@ -835,6 +851,7 @@ config ARCH_T4240 bool select E500MC select FSL_LAW + select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 select SYS_FSL_ERRATUM_A005871 select SYS_FSL_ERRATUM_A006261 diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index dbc8d7a..4986f38 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -156,7 +156,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -178,7 +177,6 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -198,7 +196,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 @@ -221,7 +218,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -234,7 +230,6 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 @@ -245,7 +240,6 @@ #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 @@ -287,7 +281,6 @@ #define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PME_CLK 0 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM1_CLK 3 @@ -324,7 +317,6 @@ #define CONFIG_SYS_CPRI_CLK 3 #define CONFIG_SYS_ULB_CLK 4 #define CONFIG_SYS_ETVPE_CLK 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 @@ -369,7 +361,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 #define CONFIG_FM_PLAT_CLK_DIV 1 @@ -404,7 +395,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 @@ -453,7 +443,6 @@ #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 per rcw field value */ #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 @@ -470,7 +459,6 @@ #elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2_1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
On Wed, Dec 28, 2016 at 08:43:46AM -0800, York Sun wrote:
Use Kconfig to select DDR version instead of using config header.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
After most config options are moved to Kconfig, the unused ifdef or elif can be removed.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/include/asm/config_mpc85xx.h | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4986f38..2a826fe 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -22,25 +22,13 @@ #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SEC_MON_BE
-#if defined(CONFIG_ARCH_MPC8536) - -#elif defined(CONFIG_ARCH_MPC8540) - -#elif defined(CONFIG_ARCH_MPC8541) - -#elif defined(CONFIG_ARCH_MPC8544) - -#elif defined(CONFIG_ARCH_MPC8548) +#if defined(CONFIG_ARCH_MPC8548) #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#elif defined(CONFIG_ARCH_MPC8555) - -#elif defined(CONFIG_ARCH_MPC8560) - #elif defined(CONFIG_ARCH_MPC8568) #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 @@ -61,8 +49,6 @@ #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#elif defined(CONFIG_ARCH_MPC8572) - #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 @@ -463,10 +449,6 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
-#elif defined(CONFIG_ARCH_QEMU_E500) - -#else -#error Processor type not defined for this platform #endif
#ifdef CONFIG_E6500
On Wed, Dec 28, 2016 at 08:43:47AM -0800, York Sun wrote:
After most config options are moved to Kconfig, the unused ifdef or elif can be removed.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use Kconfig option E6500 and clean up existing usage.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 16 ++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 9 --------- scripts/config_whitelist.txt | 1 - 3 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 7b64ae0..8b905e2 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -326,6 +326,7 @@ endchoice config ARCH_B4420 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 @@ -346,6 +347,7 @@ config ARCH_B4420 config ARCH_B4860 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 @@ -801,6 +803,7 @@ config ARCH_T1042 config ARCH_T2080 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 @@ -817,6 +820,7 @@ config ARCH_T2080 config ARCH_T2081 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 @@ -833,6 +837,7 @@ config ARCH_T2081 config ARCH_T4160 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 @@ -850,6 +855,7 @@ config ARCH_T4160 config ARCH_T4240 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 @@ -880,6 +886,11 @@ config E500MC help Enble PowerPC E500MC core
+config E6500 + bool + help + Enable PowerPC E6500 core + config FSL_LAW bool help @@ -1160,6 +1171,11 @@ config SYS_FSL_NUM_LAWS Number of local access windows. This is fixed per SoC. If not sure, do not change.
+config SYS_FSL_THREADS_PER_CORE + int + default 2 if E6500 + default 1 + config SYS_NUM_TLBCAMS int "Number of TLB CAM entries" default 64 if E500MC diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 2a826fe..92c96d7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -238,7 +238,6 @@ #define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) -#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ @@ -284,7 +283,6 @@ #define CONFIG_SYS_FSL_PCI_VER_3_X
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) -#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ @@ -399,7 +397,6 @@ #define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) -#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ @@ -451,12 +448,6 @@
#endif
-#ifdef CONFIG_E6500 -#define CONFIG_SYS_FSL_THREADS_PER_CORE 2 -#else -#define CONFIG_SYS_FSL_THREADS_PER_CORE 1 -#endif - #if !defined(CONFIG_ARCH_C29X) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index df3965f..2cc8f0c 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -5517,7 +5517,6 @@ CONFIG_SYS_FSL_SRIO_OB_WIN_NUM CONFIG_SYS_FSL_SRIO_OFFSET CONFIG_SYS_FSL_SRK_LE CONFIG_SYS_FSL_TBCLK_DIV -CONFIG_SYS_FSL_THREADS_PER_CORE CONFIG_SYS_FSL_TIMER_ADDR CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_FSL_USB1_PHY_ENABLE
On Wed, Dec 28, 2016 at 08:43:48AM -0800, York Sun wrote:
Use Kconfig option E6500 and clean up existing usage.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use Kconfig option to select chassis version.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 21 +++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 10 ---------- scripts/config_whitelist.txt | 2 -- 3 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 8b905e2..ac6c197 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -341,6 +341,7 @@ config ARCH_B4420 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -362,6 +363,7 @@ config ARCH_B4860 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -641,6 +643,7 @@ config ARCH_P2041 select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -663,6 +666,7 @@ config ARCH_P3041 select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -696,6 +700,7 @@ config ARCH_P4080 select SYS_P4080_ERRATUM_SERDES_A005 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -714,6 +719,7 @@ config ARCH_P5020 select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -732,6 +738,7 @@ config ARCH_P5040 select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -750,6 +757,7 @@ config ARCH_T1023 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
@@ -765,6 +773,7 @@ config ARCH_T1024 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
@@ -781,6 +790,7 @@ config ARCH_T1040 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
@@ -797,6 +807,7 @@ config ARCH_T1042 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
@@ -814,6 +825,7 @@ config ARCH_T2080 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -831,6 +843,7 @@ config ARCH_T2081 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -849,6 +862,7 @@ config ARCH_T4160 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -868,6 +882,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -1127,6 +1142,12 @@ config SYS_P4080_ERRATUM_SERDES_A001 config SYS_P4080_ERRATUM_SERDES_A005 bool
+config SYS_FSL_QORIQ_CHASSIS1 + bool + +config SYS_FSL_QORIQ_CHASSIS2 + bool + config SYS_FSL_NUM_LAWS int "Number of local access windows" depends on FSL_LAW diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 92c96d7..8cde05c 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -117,7 +117,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_NUM_FMAN 1 @@ -136,7 +135,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041) -#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_NUM_FMAN 1 @@ -155,7 +153,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_NUM_FMAN 2 @@ -176,7 +173,6 @@
#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_NUM_FMAN 1 @@ -196,7 +192,6 @@
#elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_PPC64 -#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_NUM_FMAN 2 @@ -240,7 +235,6 @@ #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #ifdef CONFIG_ARCH_T4240 @@ -285,7 +279,6 @@ #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ @@ -334,7 +327,6 @@ #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 @@ -367,7 +359,6 @@ #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FMAN_V3 @@ -399,7 +390,6 @@ #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_QMAN_V3 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2cc8f0c..241d047 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -5461,8 +5461,6 @@ CONFIG_SYS_FSL_QBMAN_SIZE_1 CONFIG_SYS_FSL_QMAN_ADDR CONFIG_SYS_FSL_QMAN_OFFSET CONFIG_SYS_FSL_QMAN_V3 -CONFIG_SYS_FSL_QORIQ_CHASSIS1 -CONFIG_SYS_FSL_QORIQ_CHASSIS2 CONFIG_SYS_FSL_QSPI_AHB CONFIG_SYS_FSL_QSPI_BASE CONFIG_SYS_FSL_QSPI_BASE1
On Wed, Dec 28, 2016 at 08:43:49AM -0800, York Sun wrote:
Use Kconfig option to select chassis version.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
Use Kconfig option SYS_PPC64 instead.
Signed-off-by: York Sun york.sun@nxp.com
---
arch/powerpc/cpu/mpc85xx/Kconfig | 11 +++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 5 ----- scripts/config_whitelist.txt | 1 - 3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index ac6c197..53c7802 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -344,6 +344,7 @@ config ARCH_B4420 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64
config ARCH_B4860 bool @@ -366,6 +367,7 @@ config ARCH_B4860 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64
config ARCH_BSC9131 bool @@ -722,6 +724,7 @@ config ARCH_P5020 select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64
config ARCH_P5040 bool @@ -741,6 +744,7 @@ config ARCH_P5040 select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64
config ARCH_QEMU_E500 bool @@ -828,6 +832,7 @@ config ARCH_T2080 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64
config ARCH_T2081 bool @@ -846,6 +851,7 @@ config ARCH_T2081 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64
config ARCH_T4160 bool @@ -865,6 +871,7 @@ config ARCH_T4160 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64
config ARCH_T4240 bool @@ -885,6 +892,7 @@ config ARCH_T4240 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select SYS_PPC64
config BOOKE bool @@ -1205,6 +1213,9 @@ config SYS_NUM_TLBCAMS Number of TLB CAM entries for Book-E chips. 64 for E500MC, 16 for other E500 SoCs.
+config SYS_PPC64 + bool + config SYS_PPC_E500_USE_DEBUG_TLB bool
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8cde05c..6fd218a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -172,7 +172,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ -#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_NUM_FMAN 1 @@ -191,7 +190,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
#elif defined(CONFIG_ARCH_P5040) -#define CONFIG_SYS_PPC64 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_NUM_FMAN 2 @@ -233,7 +231,6 @@ #define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) -#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ @@ -277,7 +274,6 @@ #define CONFIG_SYS_FSL_PCI_VER_3_X
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) -#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ @@ -388,7 +384,6 @@ #define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 241d047..43c5cdc 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -7134,7 +7134,6 @@ CONFIG_SYS_POST_WATCHDOG CONFIG_SYS_POST_WORD_ADDR CONFIG_SYS_POWER_MANAGER CONFIG_SYS_PPC4XX_USB_ADDR -CONFIG_SYS_PPC64 CONFIG_SYS_PPC_DDR_WIMGE CONFIG_SYS_PQSPAR CONFIG_SYS_PRELIM_OR_AM
On Wed, Dec 28, 2016 at 08:43:50AM -0800, York Sun wrote:
Use Kconfig option SYS_PPC64 instead.
Signed-off-by: York Sun york.sun@nxp.com
Applied to u-boot/master, thanks!
On Wed, Dec 28, 2016 at 08:43:26AM -0800, York Sun wrote:
In this set, more mpc85xx config options are moved into Kconfig, including some shared configuration for DDR, crypto, mmc, etc.
York Sun (24): powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 powerpc: T1023RDB: Remove macro CONFIG_T1023RDB powerpc: T1024RDB: Remove macro CONFIG_T1024RDB powerpc: T1040QDS: Remove macro CONFIG_T1040QDS powerpc: T2080QDS: Remove macro T2080QDS powerpc: T2080RDB: Remove macro CONFIG_T2080RDB powerpc: T2081QDS: Remove macro T2081QDS powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS fsl_ddr: Move DDR config options to driver Kconfig arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig powerpc: mpc85xx: Remove unused ifdef in config header powerpc: E6500: Move macro CONFIG_E6500 to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to Kconfig powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 to Kconfig
There were a few minor problems in this series which I fixed up. The only remaining "issue" here is that sbc8641d has a ~3KiB size increase. This is due to the issue that previously it did _not_ define CONFIG_SYS_FSL_DDR2 but only CONFIG_SYS_FSL_DDR_86XX and that was a valid build. Now that CONFIG_SYS_FSL_DDR2 is set too, other files are being included and linked.
On 01/05/2017 05:28 AM, Tom Rini wrote:
On Wed, Dec 28, 2016 at 08:43:26AM -0800, York Sun wrote:
In this set, more mpc85xx config options are moved into Kconfig, including some shared configuration for DDR, crypto, mmc, etc.
York Sun (24): powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 powerpc: T1023RDB: Remove macro CONFIG_T1023RDB powerpc: T1024RDB: Remove macro CONFIG_T1024RDB powerpc: T1040QDS: Remove macro CONFIG_T1040QDS powerpc: T2080QDS: Remove macro T2080QDS powerpc: T2080RDB: Remove macro CONFIG_T2080RDB powerpc: T2081QDS: Remove macro T2081QDS powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS fsl_ddr: Move DDR config options to driver Kconfig arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig powerpc: mpc85xx: Remove unused ifdef in config header powerpc: E6500: Move macro CONFIG_E6500 to Kconfig powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to Kconfig powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 to Kconfig
There were a few minor problems in this series which I fixed up. The only remaining "issue" here is that sbc8641d has a ~3KiB size increase. This is due to the issue that previously it did _not_ define CONFIG_SYS_FSL_DDR2 but only CONFIG_SYS_FSL_DDR_86XX and that was a valid build. Now that CONFIG_SYS_FSL_DDR2 is set too, other files are being included and linked.
Thanks, Tom. I will look into SBC8641.
York
On 01/05/2017 05:28 AM, Tom Rini wrote:
There were a few minor problems in this series which I fixed up. The only remaining "issue" here is that sbc8641d has a ~3KiB size increase. This is due to the issue that previously it did _not_ define CONFIG_SYS_FSL_DDR2 but only CONFIG_SYS_FSL_DDR_86XX and that was a valid build. Now that CONFIG_SYS_FSL_DDR2 is set too, other files are being included and linked.
I found out why. Another config macro CONFIG_SPD_EEPROM is undefined in sbc8641 header file to skip the DDR driver. This board has the option to go both ways. A proper fix will be lifting this config macro to Kconfig. It is on my to-do list.
York
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York Sun -
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