[U-Boot] [PATCH v5 0/7] Change ARM926EJ-S startup code, hawkboard and calimain
Hi,
In this patchset I tried to put everything from the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html
Although this is the first version of this patchset, the version number is v5 since Sughosh's patches were already v4.
Regards, Christian
Christian Riesch (5): arm, davinci: Add lowlevel_init for SoCs other than DM644X arm, arm926ejs: Do cpu critical inits only for boards that require it arm, arm926ejs: Do not clear the V bit on DA850 SoCs arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not defined arm, davinci: Add support for the Calimain board from OMICRON electronics
Sughosh Ganu (2): arm, arm926ejs: Flush the data cache before disabling it Changes to move hawkboard to the new spl infrastructure
MAINTAINERS | 5 + arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 24 +- arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S | 4 + arch/arm/cpu/arm926ejs/davinci/spl.c | 4 +- arch/arm/cpu/arm926ejs/start.S | 26 +- arch/arm/include/asm/arch-davinci/da850_lowlevel.h | 9 + board/davinci/da8xxevm/da850evm.c | 4 +- board/davinci/da8xxevm/hawkboard.c | 23 ++ board/davinci/da8xxevm/hawkboard_nand_spl.c | 115 ------- .../{u-boot-spl.lds => u-boot-spl-da850evm.lds} | 0 .../davinci/da8xxevm/u-boot-spl-hawk.lds | 22 +- board/enbw/enbw_cmc/enbw_cmc.c | 13 +- board/omicron/calimain/Makefile | 45 +++ board/omicron/calimain/calimain.c | 188 ++++++++++ boards.cfg | 2 +- doc/README.hawkboard | 43 ++-- include/configs/calimain.h | 362 ++++++++++++++++++++ include/configs/cam_enc_4xx.h | 6 - include/configs/da850evm.h | 6 +- include/configs/enbw_cmc.h | 5 +- include/configs/hawkboard.h | 23 +- nand_spl/board/davinci/da8xxevm/Makefile | 155 --------- 22 files changed, 738 insertions(+), 346 deletions(-) delete mode 100644 board/davinci/da8xxevm/hawkboard_nand_spl.c rename board/davinci/da8xxevm/{u-boot-spl.lds => u-boot-spl-da850evm.lds} (100%) rename nand_spl/board/davinci/da8xxevm/u-boot.lds => board/davinci/da8xxevm/u-boot-spl-hawk.lds (86%) create mode 100644 board/omicron/calimain/Makefile create mode 100644 board/omicron/calimain/calimain.c create mode 100644 include/configs/calimain.h delete mode 100644 nand_spl/board/davinci/da8xxevm/Makefile
The low level initialization code in arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for DM644X SoCs only. This patch makes the lowlevel_init function in this file a dummy function for SoCs other than DM644X.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Cc: Tom Rini trini@ti.com Cc: Sergey Kubushyn ksi@koi8.net --- arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S index 7a169b1..5b39484 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S @@ -49,6 +49,7 @@
.globl lowlevel_init lowlevel_init: +#ifdef CONFIG_SOC_DM644X
/*-------------------------------------------------------* * Mask all IRQs by setting all bits in the EINT default * @@ -707,3 +708,6 @@ DDR2_START_ADDR: .word 0x80000000 DUMMY_VAL: .word 0xa55aa55a +#else /* CONFIG_SOC_DM644X */ + mov pc, lr +#endif
Hello Christian,
Christian Riesch wrote:
The low level initialization code in arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for DM644X SoCs only. This patch makes the lowlevel_init function in this file a dummy function for SoCs other than DM644X.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Cc: Tom Rini trini@ti.com Cc: Sergey Kubushyn ksi@koi8.net
arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
Acked-by: Heiko Schocher hs@denx.de
Tested on the cam_enc_4xx and enbw_cmc board, so:
Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
This patch reverts commit ca4b55800ed74207c35271bf7335a092d4955416 "arm, arm926ejs: always do cpu critical inits" since it impacts all arm926ejs based configurations and caused problems, e.g., with the hawkboard.
Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines from the board configurations that need low level initialization.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com Cc: Heiko Schocher hs@denx.de --- arch/arm/cpu/arm926ejs/start.S | 6 ++++-- include/configs/cam_enc_4xx.h | 6 ------ include/configs/da850evm.h | 1 - include/configs/enbw_cmc.h | 1 - 4 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 6a09c02..bb4d00b 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -194,7 +194,9 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit +#endif
/* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: @@ -353,6 +355,7 @@ _dynsym_start_ofs: * ************************************************************************* */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* * flush v4 I/D caches @@ -371,15 +374,14 @@ cpu_init_crit: orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* * Go setup Memory and board specific bits prior to relocation. */ mov ip, lr /* perserve link reg across call */ bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SPL_BUILD /* diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index a21d448..f4fe444 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -265,12 +265,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0xc0000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
-/* - * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is - * done in board_init_f from c code. - */ -#define CONFIG_SKIP_LOWLEVEL_INIT - /* for UBL header */ #define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index fcbbace..f15a0a6 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc1080000
/* diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index c427dc7..21cf647 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_DA850_LOWLEVEL #define CONFIG_ARCH_CPU_INIT #define CONFIG_DA8XX_GPIO
Hello Christian,
Christian Riesch wrote:
This patch reverts commit ca4b55800ed74207c35271bf7335a092d4955416 "arm, arm926ejs: always do cpu critical inits" since it impacts all arm926ejs based configurations and caused problems, e.g., with the hawkboard.
Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines from the board configurations that need low level initialization.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com Cc: Heiko Schocher hs@denx.de
arch/arm/cpu/arm926ejs/start.S | 6 ++++-- include/configs/cam_enc_4xx.h | 6 ------ include/configs/da850evm.h | 1 - include/configs/enbw_cmc.h | 1 - 4 files changed, 4 insertions(+), 10 deletions(-)
Acked-by: Heiko Schocher hs@denx.de
Tested on the cam_enc_4xx and enbw_cmc board, so:
Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
From: Sughosh Ganu urwithsughosh@gmail.com
The current implementation invalidates the data cache before turning it off and causes problems on the hawkboard. See the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html
According to the ARM926EJ-S Technical Reference Manual, the cache should be flushed instead.
Also fix the comments to match code.
Signed-off-by: Sughosh Ganu urwithsughosh@gmail.com
Rebased and corrected commit message.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com --- arch/arm/cpu/arm926ejs/start.S | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index bb4d00b..b39ed8a 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -358,14 +358,18 @@ _dynsym_start_ofs: #ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* - * flush v4 I/D caches + * flush D cache before disabling it */ mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ +flush_dcache: + mrc p15, 0, r15, c7, c10, 3 + bne flush_dcache + + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
/* - * disable MMU stuff and caches + * disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
Hello Christian,
Christian Riesch wrote:
From: Sughosh Ganu urwithsughosh@gmail.com
The current implementation invalidates the data cache before turning it off and causes problems on the hawkboard. See the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html
According to the ARM926EJ-S Technical Reference Manual, the cache should be flushed instead.
Also fix the comments to match code.
Signed-off-by: Sughosh Ganu urwithsughosh@gmail.com
Rebased and corrected commit message.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com
arch/arm/cpu/arm926ejs/start.S | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-)
Acked-by: Heiko Schocher hs@denx.de
Tested on the cam_enc_4xx and enbw_cmc board, so:
Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
The V bit of the c1 register of CP15 should not be cleared since the SoC has no valid memory at 0x00000000.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Reported-by: Sughosh Ganu urwithsughosh@gmail.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com --- arch/arm/cpu/arm926ejs/start.S | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b39ed8a..b350480 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -372,7 +372,10 @@ flush_dcache: * disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ +#ifndef CONFIG_SOC_DA850 + bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ +#endif bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
hi Christian,
On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch < christian.riesch@omicron.at> wrote:
The V bit of the c1 register of CP15 should not be cleared since the SoC has no valid memory at 0x00000000.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Reported-by: Sughosh Ganu urwithsughosh@gmail.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com
arch/arm/cpu/arm926ejs/start.S | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b39ed8a..b350480 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -372,7 +372,10 @@ flush_dcache: * disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS)*/
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */+#ifndef CONFIG_SOC_DA850
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */+#endif
Instead of checking for a particular SOC, can we introduce a generic config, something like CONFIG_EXCEPTION_VECTORS_LOW. This way, if other SOC's have a similar requirement, it won't be needed to keep adding checks here. It would also help in case this needs to be implemented for other arm cores, so that we can have a common config option for bypassing this V-bit clear. Just my suggestion. Maybe Tom and Albert can comment.
I will test your patch series on my hawkboard and let you know the results tomorrow. Thanks for clubbing it all together.
-sughosh
Hello Sughosh,
Sughosh Ganu wrote:
hi Christian,
On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch < christian.riesch@omicron.at> wrote:
The V bit of the c1 register of CP15 should not be cleared since the SoC has no valid memory at 0x00000000.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Reported-by: Sughosh Ganu urwithsughosh@gmail.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com
arch/arm/cpu/arm926ejs/start.S | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b39ed8a..b350480 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -372,7 +372,10 @@ flush_dcache: * disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS)*/
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */+#ifndef CONFIG_SOC_DA850
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */+#endif
Instead of checking for a particular SOC, can we introduce a generic config, something like CONFIG_EXCEPTION_VECTORS_LOW. This way, if other SOC's have a similar requirement, it won't be needed to keep adding checks here. It would also help in case this needs to be implemented for other arm cores, so that we can have a common config option for bypassing this V-bit clear. Just my suggestion. Maybe Tom and Albert can comment.
Yep, I vote for this too, also this config option should be documented in the README.
I will test your patch series on my hawkboard and let you know the results tomorrow. Thanks for clubbing it all together.
Yep, thanks!
Currently testing it on the enbw_cmc board, looks good. I test the patches also on the cam_enc_4xx board ... and post the results.
bye, Heiko
Hello Heiko and Sughosh,
On Wed, Feb 1, 2012 at 8:33 AM, Heiko Schocher hs@denx.de wrote:
Sughosh Ganu wrote:
On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch < christian.riesch@omicron.at> wrote:
The V bit of the c1 register of CP15 should not be cleared since the SoC has no valid memory at 0x00000000.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Reported-by: Sughosh Ganu urwithsughosh@gmail.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com
arch/arm/cpu/arm926ejs/start.S | Â Â 5 ++++- Â 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b39ed8a..b350480 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -372,7 +372,10 @@ flush_dcache:     * disable MMU and D cache, and enable I cache     */     mrc   p15, 0, r0, c1, c0, 0
- bic   r0, r0, #0x00002300   /* clear bits 13, 9:8 (--V- --RS)
*/
- bic   r0, r0, #0x00000300   /* clear bits 9:8 (---- --RS) */
+#ifndef CONFIG_SOC_DA850
- bic   r0, r0, #0x00002000   /* clear bit 13 (--V- ----) */
+#endif
Instead of checking for a particular SOC, can we introduce a generic config, something like CONFIG_EXCEPTION_VECTORS_LOW. This way, if other SOC's have a similar requirement, it won't be needed to keep adding checks here. It would also help in case this needs to be implemented for other arm cores, so that we can have a common config option for bypassing this V-bit clear. Just my suggestion. Maybe Tom and Albert can comment.
Yep, I vote for this too, also this config option should be documented in the README.
Ok, I'll change this to
#ifdef CONFIG_EXCEPTION_VECTORS_HIGH orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ #else bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ #endif
Or should it be CONFIG_SYS_EXCEPTION_VECTORS_HIGH? I think I don't understand the explanation in README whether it should be _SYS_ or not.
Regards, Christian
Hello Christian,
Christian Riesch wrote:
Hello Heiko and Sughosh,
On Wed, Feb 1, 2012 at 8:33 AM, Heiko Schocher hs@denx.de wrote:
Sughosh Ganu wrote:
On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch < christian.riesch@omicron.at> wrote:
The V bit of the c1 register of CP15 should not be cleared since the SoC has no valid memory at 0x00000000.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Reported-by: Sughosh Ganu urwithsughosh@gmail.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com
arch/arm/cpu/arm926ejs/start.S | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b39ed8a..b350480 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -372,7 +372,10 @@ flush_dcache: * disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS)*/
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */+#ifndef CONFIG_SOC_DA850
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */+#endif
Instead of checking for a particular SOC, can we introduce a generic config, something like CONFIG_EXCEPTION_VECTORS_LOW. This way, if other SOC's have a similar requirement, it won't be needed to keep adding checks here. It would also help in case this needs to be implemented for other arm cores, so that we can have a common config option for bypassing this V-bit clear. Just my suggestion. Maybe Tom and Albert can comment.
Yep, I vote for this too, also this config option should be documented in the README.
Ok, I'll change this to
#ifdef CONFIG_EXCEPTION_VECTORS_HIGH orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ #else bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ #endif
Or should it be CONFIG_SYS_EXCEPTION_VECTORS_HIGH? I think I don't understand the explanation in README whether it should be _SYS_ or not.
It should be CONFIG_SYS as this is a hardware dependend config option.
bye, Heiko
Hello Christian,
Christian Riesch wrote:
The V bit of the c1 register of CP15 should not be cleared since the SoC has no valid memory at 0x00000000.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Reported-by: Sughosh Ganu urwithsughosh@gmail.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com
arch/arm/cpu/arm926ejs/start.S | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
beside of the define name change and an README entry:
Acked-by: Heiko Schocher hs@denx.de
Tested on the cam_enc_4xx and enbw_cmc board, so:
Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
Signed-off-by: Christian Riesch christian.riesch@omicron.at Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com --- arch/arm/cpu/arm926ejs/start.S | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b350480..829065f 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -369,7 +369,8 @@ flush_dcache: mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
/* - * disable MMU and D cache, and enable I cache + * disable MMU and D cache + * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ @@ -378,7 +379,9 @@ flush_dcache: #endif bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ +#ifndef CONFIG_SYS_ICACHE_OFF orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ +#endif mcr p15, 0, r0, c1, c0, 0
/*
Hello Christian,
Christian Riesch wrote:
Signed-off-by: Christian Riesch christian.riesch@omicron.at Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com
arch/arm/cpu/arm926ejs/start.S | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
Acked-by: Heiko Schocher hs@denx.de
Tested on the cam_enc_4xx and enbw_cmc board, so:
Tested-by: Heiko Schocher hs@denx.de
bye, Heiko
From: Sughosh Ganu urwithsughosh@gmail.com
This patch moves hawkboard to the new spl infrastructure from the older nand_spl one.
Removed the hawkboard_nand_config build option -- The spl code now gets compiled with hawkboard_config, after building the main u-boot image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard to reflect the same.
Signed-off-by: Sughosh Ganu urwithsughosh@gmail.com Signed-off-by: Heiko Schocher hs@denx.de Cc: Heiko Schocher hs@denx.de Cc: Christian Riesch christian.riesch@omicron.at Cc: Sudhakar Rajashekhara sudhakar.raj@ti.com Cc: Tom Rini trini@ti.com Acked-by: Christian Riesch christian.riesch@omicron.at --- arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 24 ++- arch/arm/cpu/arm926ejs/davinci/spl.c | 4 +- arch/arm/include/asm/arch-davinci/da850_lowlevel.h | 9 + board/davinci/da8xxevm/da850evm.c | 4 +- board/davinci/da8xxevm/hawkboard.c | 23 +++ board/davinci/da8xxevm/hawkboard_nand_spl.c | 115 --------------- .../{u-boot-spl.lds => u-boot-spl-da850evm.lds} | 0 .../davinci/da8xxevm/u-boot-spl-hawk.lds | 22 ++- board/enbw/enbw_cmc/enbw_cmc.c | 13 +-- boards.cfg | 1 - doc/README.hawkboard | 43 +++--- include/configs/da850evm.h | 5 +- include/configs/enbw_cmc.h | 4 +- include/configs/hawkboard.h | 23 +++- nand_spl/board/davinci/da8xxevm/Makefile | 155 -------------------- 15 files changed, 114 insertions(+), 331 deletions(-) delete mode 100644 board/davinci/da8xxevm/hawkboard_nand_spl.c rename board/davinci/da8xxevm/{u-boot-spl.lds => u-boot-spl-da850evm.lds} (100%) rename nand_spl/board/davinci/da8xxevm/u-boot.lds => board/davinci/da8xxevm/u-boot-spl-hawk.lds (86%) delete mode 100644 nand_spl/board/davinci/da8xxevm/Makefile
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index eec06bc..df7d6a2 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -32,6 +32,7 @@ #include <asm/arch/emif_defs.h> #include <asm/arch/pll_defs.h>
+#if defined(CONFIG_SYS_DA850_PLL_INIT) void da850_waitloop(unsigned long loopcnt) { unsigned long i; @@ -163,7 +164,9 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
return 0; } +#endif /* CONFIG_SYS_DA850_PLL_INIT */
+#if defined(CONFIG_SYS_DA850_DDR_INIT) int da850_ddr_setup(void) { unsigned long tmp; @@ -242,6 +245,7 @@ int da850_ddr_setup(void)
return 0; } +#endif /* CONFIG_SYS_DA850_DDR_INIT */
__attribute__((weak)) void board_gpio_init(void) @@ -249,10 +253,6 @@ void board_gpio_init(void) return; }
-/* pinmux_resource[] vector is defined in the board specific file */ -extern const struct pinmux_resource pinmuxes[]; -extern const int pinmuxes_size; - int arch_cpu_init(void) { /* Unlock kick registers */ @@ -266,13 +266,11 @@ int arch_cpu_init(void) if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size)) return 1;
+#if defined(CONFIG_SYS_DA850_PLL_INIT) /* PLL setup */ da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM); da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM); - - /* GPIO setup */ - board_gpio_init(); - +#endif /* setup CSn config */ #if defined(CONFIG_SYS_DA850_CS2CFG) writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr); @@ -281,7 +279,12 @@ int arch_cpu_init(void) writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr); #endif
- lpsc_on(CONFIG_SYS_DA850_LPSC_UART); + da8xx_configure_lpsc_items(lpsc, lpsc_size); + + /* GPIO setup */ + board_gpio_init(); + + NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
@@ -293,6 +296,9 @@ int arch_cpu_init(void) DAVINCI_UART_PWREMU_MGMT_UTRST), &davinci_uart2_ctrl_regs->pwremu_mgmt);
+#if defined(CONFIG_SYS_DA850_DDR_INIT) da850_ddr_setup(); +#endif + return 0; } diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c index f475f9b..74632e5 100644 --- a/arch/arm/cpu/arm926ejs/davinci/spl.c +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c @@ -74,12 +74,12 @@ void board_init_f(ulong dummy)
void board_init_r(gd_t *id, ulong dummy) { -#ifdef CONFIG_SOC_DM365 +#ifdef CONFIG_SPL_NAND_LOAD nand_init(); puts("Nand boot...\n"); nand_boot(); #endif -#ifdef CONFIG_SOC_DA8XX +#ifdef CONFIG_SPL_SPI_LOAD mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
diff --git a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h index e489c47..11ed91d 100644 --- a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h +++ b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h @@ -24,6 +24,15 @@ #ifndef __DA850_LOWLEVEL_H #define __DA850_LOWLEVEL_H
+#include <asm/arch/pinmux_defs.h> + +/* pinmux_resource[] vector is defined in the board specific file */ +extern const struct pinmux_resource pinmuxes[]; +extern const int pinmuxes_size; + +extern const struct lpsc_resource lpsc[]; +extern const int lpsc_size; + /* NOR Boot Configuration Word Field Descriptions */ #define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8) #define DA850_NORBOOT_METHOD_DIRECT (1 << 4) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 9bd3e71..34ef53d 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -137,7 +137,7 @@ const struct pinmux_resource pinmuxes[] = {
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
-static const struct lpsc_resource lpsc[] = { +const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ { DAVINCI_LPSC_EMAC }, /* image download */ @@ -145,6 +145,8 @@ static const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_GPIO }, };
+const int lpsc_size = ARRAY_SIZE(lpsc); + #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 #endif diff --git a/board/davinci/da8xxevm/hawkboard.c b/board/davinci/da8xxevm/hawkboard.c index 9d4e238..b694258 100644 --- a/board/davinci/da8xxevm/hawkboard.c +++ b/board/davinci/da8xxevm/hawkboard.c @@ -27,10 +27,33 @@ #include <asm/arch/hardware.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> +#include <asm/arch/pinmux_defs.h> #include <ns16550.h>
DECLARE_GLOBAL_DATA_PTR;
+const struct pinmux_resource pinmuxes[] = { + PINMUX_ITEM(emac_pins_mii), + PINMUX_ITEM(emac_pins_mdio), + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ + { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ + { DAVINCI_LPSC_EMAC }, /* image download */ + { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_GPIO }, +}; + +const int lpsc_size = ARRAY_SIZE(lpsc); + int board_init(void) { /* arch number of the board */ diff --git a/board/davinci/da8xxevm/hawkboard_nand_spl.c b/board/davinci/da8xxevm/hawkboard_nand_spl.c deleted file mode 100644 index df97963..0000000 --- a/board/davinci/da8xxevm/hawkboard_nand_spl.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Modified for Hawkboard - Syed Mohammed Khasim khasim@beagleboard.org - * - * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. nsekhar@ti.com - * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net - * Copyright (C) 2004 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * ---------------------------------------------------------------------------- - */ - -#include <common.h> -#include <asm/errno.h> -#include <asm/arch/hardware.h> -#include <asm/io.h> -#include <asm/arch/davinci_misc.h> -#include <asm/arch/pinmux_defs.h> -#include <ns16550.h> -#include <nand.h> - -DECLARE_GLOBAL_DATA_PTR; - -static const struct pinmux_resource pinmuxes[] = { - PINMUX_ITEM(emac_pins_mii), - PINMUX_ITEM(emac_pins_mdio), - PINMUX_ITEM(emifa_pins_cs3), - PINMUX_ITEM(emifa_pins_cs4), - PINMUX_ITEM(emifa_pins_nand), - PINMUX_ITEM(uart2_pins_txrx), - PINMUX_ITEM(uart2_pins_rtscts), -}; - -static const struct lpsc_resource lpsc[] = { - { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ - { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ - { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART2 }, /* console */ - { DAVINCI_LPSC_GPIO }, -}; - -void board_init_f(ulong bootflag) -{ - /* - * Kick Registers need to be set to allow access to Pin Mux registers - */ - writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); - writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); - - /* setup the SUSPSRC for ARM to control emulation suspend */ - writel(readl(&davinci_syscfg_regs->suspsrc) & - ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | - DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | - DAVINCI_SYSCFG_SUSPSRC_UART2), &davinci_syscfg_regs->suspsrc); - - /* Power on required peripherals - * ARM does not have acess by default to PSC0 and PSC1 - * assuming here that the DSP bootloader has set the IOPU - * such that PSC access is available to ARM - */ - da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)); - - /* configure pinmux settings */ - davinci_configure_pin_mux_items(pinmuxes, - ARRAY_SIZE(pinmuxes)); - - writel(readl(&davinci_uart2_ctrl_regs->pwremu_mgmt) | - (DAVINCI_UART_PWREMU_MGMT_FREE) | - (DAVINCI_UART_PWREMU_MGMT_URRST) | - (DAVINCI_UART_PWREMU_MGMT_UTRST), - &davinci_uart2_ctrl_regs->pwremu_mgmt); - - NS16550_init((NS16550_t)(DAVINCI_UART2_BASE), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - - puts("Nand boot...\n"); - - nand_boot(); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} - -void putc(char c) -{ - if (gd->flags & GD_FLG_SILENT) - return; - - if (c == '\n') - NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), '\r'); - - NS16550_putc((NS16550_t)(DAVINCI_UART2_BASE), c); -} - -void hang(void) -{ - puts("### ERROR ### Please RESET the board ###\n"); - for (;;) - ; -} diff --git a/board/davinci/da8xxevm/u-boot-spl.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds similarity index 100% rename from board/davinci/da8xxevm/u-boot-spl.lds rename to board/davinci/da8xxevm/u-boot-spl-da850evm.lds diff --git a/nand_spl/board/davinci/da8xxevm/u-boot.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds similarity index 86% rename from nand_spl/board/davinci/da8xxevm/u-boot.lds rename to board/davinci/da8xxevm/u-boot-spl-hawk.lds index 638ffd9..b3a41af 100644 --- a/nand_spl/board/davinci/da8xxevm/u-boot.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -34,11 +34,11 @@ SECTIONS . = ALIGN(4); .text : { - start.o (.text) - cpu.o (.text) - nand_boot.o (.text) + arch/arm/cpu/arm926ejs/start.o (.text) + arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text) + drivers/mtd/nand/libnand.o (.text)
- *(.text) + *(.text*) }
. = ALIGN(4); @@ -68,10 +68,14 @@ SECTIONS
__got_end = .;
- _end = .; + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + }
- . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - __bss_end__ = .; + _end = .; } diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index 98dda1e..16d1b08 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -49,7 +49,7 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct lpsc_resource lpsc[] = { +const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_AEMIF }, { DAVINCI_LPSC_SPI1 }, { DAVINCI_LPSC_ARM_RAM_ROM }, @@ -65,6 +65,8 @@ static const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_USB11 }, };
+const int lpsc_size = ARRAY_SIZE(lpsc); + static const struct pinmux_config enbw_pins[] = { { pinmux(0), 8, 0 }, { pinmux(0), 8, 1 }, @@ -549,15 +551,6 @@ void board_gpio_init(void) struct davinci_gpio *gpio = davinci_gpio_bank01;
/* - * Power on required peripherals - * ARM does not have access by default to PSC0 and PSC1 - * assuming here that the DSP bootloader has set the IOPU - * such that PSC access is available to ARM - */ - if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) - return; - - /* * set LED (gpio Interface not usable here) * set LED pins to output and state 0 */ diff --git a/boards.cfg b/boards.cfg index 7e065bf..fc782dc 100644 --- a/boards.cfg +++ b/boards.cfg @@ -133,7 +133,6 @@ davinci_sffsdr arm arm926ejs sffsdr davinci davinci_sonata arm arm926ejs sonata davinci davinci ea20 arm arm926ejs ea20 davinci davinci hawkboard arm arm926ejs da8xxevm davinci davinci -hawkboard_nand arm arm926ejs da8xxevm davinci davinci hawkboard:NAND_U_BOOT hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT enbw_cmc arm arm926ejs enbw_cmc enbw davinci km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI diff --git a/doc/README.hawkboard b/doc/README.hawkboard index b7afec4..d6ae02e 100644 --- a/doc/README.hawkboard +++ b/doc/README.hawkboard @@ -9,8 +9,8 @@ executes upon reset is the Rom Boot Loader(RBL) which sits in the internal ROM of the omap. The RBL initialises the memory and the nand controller, and copies the image stored at a predefined location(block 1) of the nand flash. The image loaded by the RBL to the memory is the -AIS signed nand_spl image. This, in turns copies the u-boot binary -from the nand flash to the memory and jumps to the u-boot entry point. +AIS signed spl image. This, in turns copies the u-boot binary from the +nand flash to the memory and jumps to the u-boot entry point.
AIS is an image format defined by TI for the images that are to be loaded to memory by the RBL. The image is divided into a series of @@ -20,14 +20,14 @@ and the size of the section, which is used by the RBL to load the image. At the end of the image the RBL jumps to the image entry point.
-The secondary stage bootloader(nand_spl) which is loaded by the RBL -then loads the u-boot from a predefined location in the nand to the -memory and jumps to the u-boot entry point. +The secondary stage bootloader(spl) which is loaded by the RBL then +loads the u-boot from a predefined location in the nand to the memory +and jumps to the u-boot entry point.
The reason a secondary stage bootloader is used is because the ECC layout expected by the RBL is not the same as that used by -u-boot/linux. This also implies that for flashing the nand_spl image, -we need to use the u-boot which uses the ECC layout expected by the +u-boot/linux. This also implies that for flashing the spl image,we +need to use the u-boot which uses the ECC layout expected by the RBL[1]. Booting u-boot over UART(UART boot) is explained here[2].
@@ -35,20 +35,19 @@ Compilation =========== Three images might be needed
-* nand_spl - This is the secondary bootloader which boots the u-boot +* spl - This is the secondary bootloader which boots the u-boot binary.
- hawkboard_nand_config - - The nand_spl ELF gets generated under nand_spl/u-boot-spl. This - needs to be processed with the AISGen tool for generating the AIS - signed image to be flashed. Steps for generating the AIS image are - explained here[3]. - * u-boot binary - This is the image flashed to the nand and copied to - the memory by the nand_spl. + the memory by the spl. + + Both the images get compiled with hawkboard_config, with the TOPDIR + containing the u-boot images, and the spl image under the spl + directory.
- hawkboard_config + The spl image needs to be processed with the AISGen tool for + generating the AIS signed image to be flashed. Steps for generating + the AIS image are explained here[3].
* u-boot for uart boot - This is same as the u-boot binary generated above, with the sole difference of the CONFIG_SYS_TEXT_BASE being @@ -59,17 +58,17 @@ Three images might be needed
Flashing the images to Nand =========================== -The nand_spl AIS image needs to be flashed to the block 1 of the -Nand flash, as that is the location the RBL expects the image[4]. For -flashing the nand_spl, boot over the u-boot specified in [1], and -flash the image +The spl AIS image needs to be flashed to the block 1 of the Nand +flash, as that is the location the RBL expects the image[4]. For +flashing the spl, boot over the u-boot specified in [1], and flash the +image
=> tftpboot 0xc0700000 <nand_spl_ais.bin> => nand erase 0x20000 0x20000 => nand write.e 0xc0700000 0x20000 <nand_spl_size>
The u-boot binary is flashed at location 0xe0000(block 6) of the nand -flash. The nand_spl loader expects the u-boot at this location. For +flash. The spl loader expects the u-boot at this location. For flashing the u-boot binary
=> tftpboot 0xc0700000 u-boot.bin diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index f15a0a6..d63f2d8 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -43,6 +43,8 @@ #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0xc1080000 +#define CONFIG_SYS_DA850_PLL_INIT +#define CONFIG_SYS_DA850_DDR_INIT
/* * Memory Info @@ -141,7 +143,6 @@ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2
#define CONFIG_SPI #define CONFIG_SPI_FLASH @@ -318,7 +319,7 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" #define CONFIG_SPL_STACK 0x8001ff00 #define CONFIG_SPL_TEXT_BASE 0x80000000 #define CONFIG_SPL_MAX_SIZE 32768 diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index 21cf647..26ea891 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -47,6 +47,8 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_DA850_LOWLEVEL #define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_DA850_PLL_INIT +#define CONFIG_SYS_DA850_DDR_INIT #define CONFIG_DA8XX_GPIO #define CONFIG_HOSTNAME enbw_cmc #define CONFIG_DISPLAY_CPUINFO @@ -82,7 +84,7 @@ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2 + /* * I2C Configuration */ diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index 12acb27..9dd0516 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -43,12 +43,29 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_UART_U_BOOT) +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ + DAVINCI_SYSCFG_SUSPSRC_EMAC | \ + DAVINCI_SYSCFG_SUSPSRC_I2C | \ + DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ + DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2) + +#if defined(CONFIG_UART_U_BOOT) #define CONFIG_SYS_TEXT_BASE 0xc1080000 -#else +#elif !defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_TEXT_BASE 0xc1180000 #endif
+/* Spl */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_LOAD +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-hawk.lds" +#define CONFIG_SPL_TEXT_BASE 0xc1080000 +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + /* * Memory Info */ @@ -84,9 +101,7 @@ /* * Network & Ethernet Configuration */ -#if !defined(CONFIG_NAND_SPL) #define CONFIG_DRIVER_TI_EMAC -#endif #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/nand_spl/board/davinci/da8xxevm/Makefile b/nand_spl/board/davinci/da8xxevm/Makefile deleted file mode 100644 index 7746e41..0000000 --- a/nand_spl/board/davinci/da8xxevm/Makefile +++ /dev/null @@ -1,155 +0,0 @@ -# -# (C) Copyright 2006-2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -CONFIG_NAND_SPL = y - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL - -SOBJS = _divsi3.o \ - _udivsi3.o \ - start.o - -COBJS = cpu.o \ - davinci_nand.o \ - pinmux.o \ - da850_pinmux.o \ - div0.o \ - hawkboard_nand_spl.o \ - misc.o \ - nand_boot.o \ - ns16550.o \ - psc.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin \ - $(nandobj)u-boot-spl-16k.bin - -all: $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from board directory -$(obj)pinmux.c: - @rm -f $@ - @ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/pinmux.c $@ - -$(obj)da850_pinmux.c: - @rm -f $@ - @ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c $@ - -# from drivers/mtd/nand directory -$(obj)davinci_nand.c: - @rm -f $@ - @ln -s $(TOPDIR)/drivers/mtd/nand/davinci_nand.c $@ - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $@ - @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@ - -# from drivers/serial directory -$(obj)ns16550.c: - @rm -f $@ - @ln -sf $(TOPDIR)/drivers/serial/ns16550.c $@ - -# from cpu directory -$(obj)start.S: - @rm -f $@ - ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/start.S $@ - -# from lib directory -$(obj)_udivsi3.S: - @rm -f $@ - ln -s $(TOPDIR)/arch/arm/lib/_udivsi3.S $@ - -# from lib directory -$(obj)_divsi3.S: - @rm -f $@ - ln -s $(TOPDIR)/arch/arm/lib/_divsi3.S $@ - -# from lib directory -$(obj)div0.c: - @rm -f $@ - ln -s $(TOPDIR)/arch/arm/lib/div0.c $@ - -# from SoC directory -$(obj)cpu.c: - @rm -f $@ - @ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/cpu.c $@ - -$(obj)misc.c: - @rm -f $@ - ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/misc.c $@ - -# from board directory -$(obj)hawkboard_nand_spl.c: - @rm -f $@ - ln -s $(TOPDIR)/board/davinci/da8xxevm/hawkboard_nand_spl.c $@ - -$(obj)psc.c: - @rm -f $@ - ln -s $(TOPDIR)/arch/arm/cpu/arm926ejs/davinci/psc.c $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -#########################################################################
This patch adds support for the Calimain board from OMICRON electronics GmbH. The board features a Texas Instruments AM1808 SoC, 128 MB DDR2 memory, and 64 MB NOR flash memory connected to CS2 and CS3.
Signed-off-by: Christian Riesch christian.riesch@omicron.at --- MAINTAINERS | 5 + board/omicron/calimain/Makefile | 45 +++++ board/omicron/calimain/calimain.c | 188 +++++++++++++++++++ boards.cfg | 1 + include/configs/calimain.h | 362 +++++++++++++++++++++++++++++++++++++ 5 files changed, 601 insertions(+), 0 deletions(-) create mode 100644 board/omicron/calimain/Makefile create mode 100644 board/omicron/calimain/calimain.c create mode 100644 include/configs/calimain.h
diff --git a/MAINTAINERS b/MAINTAINERS index 353f23d..61f9537 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -796,6 +796,11 @@ Thierry Reding thierry.reding@avionic-design.de plutux Tegra2 (ARM7 & A9 Dual Core) medcom Tegra2 (ARM7 & A9 Dual Core)
+Christian Riesch christian.riesch@omicron.at +Manfred Rudigier manfred.rudigier@omicron.at + + calimain ARM926EJS (AM1808 SoC) + Tom Rini trini@ti.com
omap3_evm ARM ARMV7 (OMAP3xx SoC) diff --git a/board/omicron/calimain/Makefile b/board/omicron/calimain/Makefile new file mode 100644 index 0000000..cd1f0d4 --- /dev/null +++ b/board/omicron/calimain/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c new file mode 100644 index 0000000..97ba74a --- /dev/null +++ b/board/omicron/calimain/calimain.c @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2011 OMICRON electronics GmbH + * + * Based on da850evm.c. Original Copyrights follow: + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. nick.thompson@gefanuc.com + * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <i2c.h> +#include <net.h> +#include <netdev.h> +#include <watchdog.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/gpio.h> +#include <asm/arch/emif_defs.h> +#include <asm/arch/emac_defs.h> +#include <asm/arch/pinmux_defs.h> +#include <asm/arch/davinci_misc.h> +#include <asm/arch/timer_defs.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CALIMAIN_HWVERSION_MASK 0x7f000000 +#define CALIMAIN_HWVERSION_SHIFT 24 + +/* Hardware version pinmux settings */ +const struct pinmux_config hwversion_pins[] = { + { pinmux(16), 8, 2 }, /* GP7[15] */ + { pinmux(16), 8, 3 }, /* GP7[14] */ + { pinmux(16), 8, 4 }, /* GP7[13] */ + { pinmux(16), 8, 5 }, /* GP7[12] */ + { pinmux(16), 8, 6 }, /* GP7[11] */ + { pinmux(16), 8, 7 }, /* GP7[10] */ + { pinmux(17), 8, 0 }, /* GP7[9] */ + { pinmux(17), 8, 1 } /* GP7[8] */ +}; + +const struct pinmux_resource pinmuxes[] = { + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(emac_pins_mii), + PINMUX_ITEM(emac_pins_mdio), + PINMUX_ITEM(emifa_pins_nor), + PINMUX_ITEM(emifa_pins_cs2), + PINMUX_ITEM(emifa_pins_cs3), +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ + { DAVINCI_LPSC_EMAC }, /* image download */ + { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_GPIO }, +}; + +const int lpsc_size = ARRAY_SIZE(lpsc); + +/* read board revision from GPIO7[8..14] */ +u32 get_board_rev(void) +{ + lpsc_on(DAVINCI_LPSC_GPIO); + if (davinci_configure_pin_mux(hwversion_pins, + ARRAY_SIZE(hwversion_pins)) != 0) + return 0xffffffff; + + return (davinci_gpio_bank67->in_data & CALIMAIN_HWVERSION_MASK) + >> CALIMAIN_HWVERSION_SHIFT; +} + +/* + * determine the oscillator frequency depending on the board revision + * + * rev 0x00 ... 25 MHz oscillator + * rev 0x01 ... 24 MHz oscillator + */ +int calimain_get_osc_freq(void) +{ + u32 rev; + int freq; + + rev = get_board_rev(); + switch (rev) { + case 0x00: + freq = 25000000; + break; + default: + freq = 24000000; + break; + } + return freq; +} + +int board_init(void) +{ + int val; + +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + +#ifdef CONFIG_DRIVER_TI_EMAC + /* select emac MII mode */ + val = readl(&davinci_syscfg_regs->cfgchip3); + val &= ~(1 << 8); + writel(val, &davinci_syscfg_regs->cfgchip3); +#endif /* CONFIG_DRIVER_TI_EMAC */ + +#ifdef CONFIG_HW_WATCHDOG + davinci_hw_watchdog_enable(); +#endif + + printf("Input clock frequency: %d Hz\n", calimain_get_osc_freq()); + printf("Board revision: %d\n", get_board_rev()); + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ + +#ifdef CONFIG_HW_WATCHDOG +void hw_watchdog_reset(void) +{ + davinci_hw_watchdog_reset(); +} +#endif + +#if defined(CONFIG_BOOTCOUNT_LIMIT) +void bootcount_store(ulong a) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; + + /* + * write RTC kick register to enable write + * for RTC Scratch registers. Cratch0 and 1 are + * used for bootcount values. + */ + writel(RTC_KICK0R_WE, ®->kick0r); + writel(RTC_KICK1R_WE, ®->kick1r); + writel(a, ®->scratch0); + writel(BOOTCOUNT_MAGIC, ®->scratch1); +} + +ulong bootcount_load(void) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; + + if (readl(®->scratch1) != BOOTCOUNT_MAGIC) + return 0; + else + return readl(®->scratch0); +} +#endif diff --git a/boards.cfg b/boards.cfg index fc782dc..e8269ef 100644 --- a/boards.cfg +++ b/boards.cfg @@ -135,6 +135,7 @@ ea20 arm arm926ejs ea20 davinci davinci hawkboard arm arm926ejs da8xxevm davinci davinci hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT enbw_cmc arm arm926ejs enbw_cmc enbw davinci +calimain arm arm926ejs calimain omicron davinci km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_RECONFIG_XLX mgcoge3un arm arm926ejs km_arm keymile kirkwood diff --git a/include/configs/calimain.h b/include/configs/calimain.h new file mode 100644 index 0000000..2733f5f --- /dev/null +++ b/include/configs/calimain.h @@ -0,0 +1,362 @@ +/* + * Copyright (C) 2011 OMICRON electronics GmbH + * + * Based on da850evm.h. Original Copyrights follow: + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ +#define CONFIG_DRIVER_TI_EMAC +#define MACH_TYPE_CALIMAIN 3528 +#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN + +/* + * SoC Configuration + */ +#define CONFIG_MACH_DAVINCI_CALIMAIN +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_DA850_LOWLEVEL +#define CONFIG_SYS_DA850_PLL_INIT +#define CONFIG_SYS_DA850_DDR_INIT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DA8XX_GPIO +#define CONFIG_HW_WATCHDOG +#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE +#define CONFIG_SYS_WDT_PERIOD_LOW \ + (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */ +#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 +#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) + +/* + * PLL configuration + */ +#define CONFIG_SYS_DV_CLKMODE 0 +#define CONFIG_SYS_DA850_PLL0_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 +#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 + +#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 + +#define CONFIG_SYS_DA850_PLL0_PLLM \ + ((calimain_get_osc_freq() == 25000000) ? 23 : 24) +#define CONFIG_SYS_DA850_PLL1_PLLM \ + ((calimain_get_osc_freq() == 25000000) ? 20 : 21) + +/* + * DDR2 memory configuration + */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ + (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 + +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ + (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WTR_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (2 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 + +/* + * Flash memory timing + */ + +#define CONFIG_SYS_DA850_CS2CFG ( \ + DAVINCI_ABCR_WSETUP(2) | \ + DAVINCI_ABCR_WSTROBE(5) | \ + DAVINCI_ABCR_WHOLD(3) | \ + DAVINCI_ABCR_RSETUP(1) | \ + DAVINCI_ABCR_RSTROBE(14) | \ + DAVINCI_ABCR_RHOLD(0) | \ + DAVINCI_ABCR_TA(3) | \ + DAVINCI_ABCR_ASIZE_16BIT) + +/* single 64 MB NOR flash device connected to CS2 and CS3 */ +#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ + +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ + DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2 | \ + DAVINCI_SYSCFG_SUSPSRC_EMAC | \ + DAVINCI_SYSCFG_SUSPSRC_I2C) + +/* memtest start addr */ +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) + +/* memtest will be run on 16MB */ +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20)) + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ +#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2) +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */ +#define CONFIG_SYS_MAX_FLASH_SECT \ + ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3) + +/* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +/* + * U-Boot general configuration + */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "Calimain > " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) +#define CONFIG_LOADADDR 0xc0700000 +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "" +#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;" +#define CONFIG_BOOTDELAY 0 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_DELAY_STR "\x0d" /* press ENTER to interrupt BOOT */ +#define CONFIG_RESET_TO_RETRY + +/* + * Default environment settings + * gpio0 = button, gpio1 = led green, gpio2 = led red + * verify = n ... disable kernel checksum verification for faster booting + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "tftpdir=calimero\0" \ + "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \ + "erase 0x60800000 +0x400000; " \ + "cp.b $loadaddr 0x60800000 $filesize\0" \ + "flashrootfs=" \ + "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \ + "erase 0x60c00000 +0x2e00000; " \ + "cp.b $loadaddr 0x60c00000 $filesize\0" \ + "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \ + "protect off all; " \ + "erase 0x60000000 +0x80000; " \ + "cp.b $loadaddr 0x60000000 $filesize\0" \ + "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \ + "erase 0x60080000 +0x780000; " \ + "cp.b $loadaddr 0x60080000 $filesize\0" \ + "erase_persistent=erase 0x63a00000 +0x600000;\0" \ + "bootnor=setenv bootargs console=ttyS2,115200n8 " \ + "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ + "rootwait ethaddr=$ethaddr; " \ + "gpio c 1; gpio s 2; bootm 0x60800000\0" \ + "bootrlk=gpio s 1; gpio s 2;" \ + "setenv bootargs console=ttyS2,115200n8 " \ + "ethaddr=$ethaddr; bootm 0x60080000\0" \ + "boottftp=setenv bootargs console=ttyS2,115200n8 " \ + "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ + "rootwait ethaddr=$ethaddr; " \ + "tftpboot $loadaddr $tftpdir/uImage;" \ + "gpio c 1; gpio s 2; bootm $loadaddr\0" \ + "checkupdate=if test -n $update_flag; then " \ + "echo Previous update failed - starting RLK; " \ + "run bootrlk; fi; " \ + "if test -n $initial_setup; then " \ + "echo Running initial setup procedure; " \ + "sleep 1; run flashall; fi\0" \ + "product=accessory\0" \ + "serial=XX12345\0" \ + "checknor=" \ + "if gpio i 0; then run bootnor; fi;\0" \ + "checkrlk=" \ + "if gpio i 0; then run bootrlk; fi;\0" \ + "checkbutton=" \ + "run checknor; sleep 1;" \ + "run checknor; sleep 1;" \ + "run checknor; sleep 1;" \ + "run checknor; sleep 1;" \ + "run checknor;" \ + "gpio s 1; gpio s 2;" \ + "echo ---- Release button to boot RLK ----;" \ + "run checkrlk; sleep 1;" \ + "run checkrlk; sleep 1;" \ + "run checkrlk; sleep 1;" \ + "run checkrlk; sleep 1;" \ + "run checkrlk; sleep 1;" \ + "run checkrlk;" \ + "echo ---- Factory reset requested ----;" \ + "gpio c 1;" \ + "setenv factory_reset true;" \ + "saveenv;" \ + "run bootnor;\0" \ + "flashall=run flashrlk;" \ + "run flashkernel;" \ + "run flashrootfs;" \ + "setenv erase_datafs true;" \ + "setenv initial_setup;" \ + "saveenv;" \ + "run bootnor;\0" \ + "verify=n\0" \ + "clearenv=protect off all;" \ + "erase 0x60040000 +0x40000;\0" \ + "bootlimit=3\0" \ + "altbootcmd=run bootrlk\0" + +#define CONFIG_PREBOOT \ + "echo Version: $ver; " \ + "echo Serial: $serial; " \ + "echo MAC: $ethaddr; " \ + "echo Product: $product; " \ + "gpio c 1; gpio c 2;" + +/* + * U-Boot commands + */ +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_GPIO + +#ifndef CONFIG_DRIVER_TI_EMAC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#endif + +/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +/* initial stack pointer in internal SRAM */ +#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) + +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE + +#ifndef __ASSEMBLY__ +int calimain_get_osc_freq(void); +#endif + +#endif /* __CONFIG_H */
hi Christian,
On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch < christian.riesch@omicron.at> wrote:
Hi,
In this patchset I tried to put everything from the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html
Although this is the first version of this patchset, the version number is v5 since Sughosh's patches were already v4.
Regards, Christian
Christian Riesch (5): arm, davinci: Add lowlevel_init for SoCs other than DM644X arm, arm926ejs: Do cpu critical inits only for boards that require it arm, arm926ejs: Do not clear the V bit on DA850 SoCs arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not defined arm, davinci: Add support for the Calimain board from OMICRON electronics
Sughosh Ganu (2): arm, arm926ejs: Flush the data cache before disabling it Changes to move hawkboard to the new spl infrastructure
Tested with an image with all patches applied on hawkboard. Board boots up fine.
Tested-by: Sughosh Ganu urwithsughosh@gmail.com
-sughosh
participants (3)
-
Christian Riesch -
Heiko Schocher -
Sughosh Ganu