Hi Alvaro,

On 18 May 2017 at 13:29, Álvaro Fernández Rojas noltari@gmail.com wrote:

Command bytes are part of the written bytes and they should be taken into account when sending a spi transfer.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com

drivers/mtd/spi/spi_flash.c | 2 +- drivers/spi/Kconfig | 3 +++ include/spi.h | 8 +++++++- 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index e44c10f..748cc32 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -380,7 +380,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,

            if (spi->max_write_size)
                    chunk_len = min(chunk_len,

•                                   (size_t)spi->max_write_size);
  

•                                   spi_max_write(spi, sizeof(cmd)));
  
            spi_flash_addr(write_addr, cmd);
  
  

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f3f7dbe..a00d401 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -13,6 +13,9 @@ config DM_SPI typically use driver-private data instead of extending the spi_slave structure.

+config SPI_MAX_WRITE_CMD_BYTES

•   bool "Include command bytes when determining max write size"
  

Do you really need this, or can you just always do this? If you need it, please add detailed help.

if DM_SPI

config ALTERA_SPI diff --git a/include/spi.h b/include/spi.h index 75a994c..310fa4d 100644 --- a/include/spi.h +++ b/include/spi.h @@ -63,6 +63,12 @@ struct dm_spi_slave_platdata {

#endif /* CONFIG_DM_SPI */

+#ifdef CONFIG_SPI_MAX_WRITE_CMD_BYTES +#define spi_max_write(spi, len) (spi->max_write_size - len) +#else +#define spi_max_write(spi, len) (spi->max_write_size) +#endif

/**

• struct spi_slave - Representation of a SPI slave

@@ -89,7 +95,7 @@ struct dm_spi_slave_platdata {

• @max_read_size: If non-zero, the maximum number of bytes which can

•                 be read at once.
  

• @max_write_size: If non-zero, the maximum number of bytes which can

• •                 be written at once, excluding command bytes.
    

• •                 be written at once.
    

  • @memory_map: Address of read-only SPI flash access.
  • @flags: Indication of SPI flags.
  */

-- 2.1.4

Regards, Simon

On Fri, May 19, 2017 at 12:59 AM, Álvaro Fernández Rojas noltari@gmail.com wrote:

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c Instead of supporting both HW revisions of the controller in a single build, support has been split by the selected config to save space.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com

drivers/spi/Kconfig | 23 +++ drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_spi.c | 404 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 428 insertions(+) create mode 100644 drivers/spi/bcm63xx_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a00d401..d458dd7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -43,6 +43,29 @@ config ATMEL_SPI many AT32 (AVR32) and AT91 (ARM) chips. This driver can be used to access the SPI Flash, such as AT25DF321.

+choice

•   prompt "BCM63xx SPI driver"
  

•   depends on ARCH_BMIPS
  

•   optional
  

+config BCM6338_SPI

•   bool "BCM6338 SPI driver"
  

•   select SPI_MAX_WRITE_CMD_BYTES
  

•   help
  

•     Enable the BCM6338 SPI driver. This driver can be used to
  

•     access the SPI NOR flash on platforms embedding this Broadcom
  

•     SPI core.
  

+config BCM6358_SPI

•   bool "BCM6358 SPI driver"
  

•   select SPI_MAX_WRITE_CMD_BYTES
  

•   help
  

•     Enable the BCM6358 SPI driver. This driver can be used to
  

•     access the SPI NOR flash on platforms embedding this Broadcom
  

•     SPI core.
  

+endchoice

config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c090562..c9ba648 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o +obj-$(CONFIG_BCM6338_SPI)$(CONFIG_BCM6358_SPI) += bcm63xx_spi.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c new file mode 100644 index 0000000..6e64607 --- /dev/null +++ b/drivers/spi/bcm63xx_spi.c @@ -0,0 +1,404 @@ +/*

• • Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com
• • Derived from linux/drivers/spi/spi-bcm63xx.c:

• • Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
    

• • Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
    

• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <reset.h> +#include <asm/io.h>

+DECLARE_GLOBAL_DATA_PTR;

+#if defined(CONFIG_BCM6338_SPI)

+# define SPI_DT_ID "brcm,bcm6338-spi"

+/* SPI Command register */ +# define SPI_CMD_REG 0x00

+/* SPI Interrupt registers */ +# define SPI_IR_STAT_REG 0x02 +# define SPI_IR_MASK_REG 0x04

+/* SPI Clock register */ +# define SPI_CLK_REG 0x06

+/* SPI Fill register */ +# define SPI_FILL_REG 0x07

+/* SPI Control register (8 bit) */ +# define SPI_CTL_REG 0x40 +# define SPI_CTL_BYTES_SHIFT 0 +# define SPI_CTL_BYTES_MASK (0x3f << SPI_CTL_BYTES_SHIFT) +# define SPI_CTL_TYPE_SHIFT 6 +# define SPI_CTL_TYPE_FD_RW (0 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_W (1 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_R (2 << SPI_CTL_TYPE_SHIFT)

+# define bcm63xx_spi_wctl(v,a) writeb_be(v, a);

+/* SPI TX Data registers */ +# define SPI_TX_DATA_REG 0x41 +# define SPI_TX_DATA_SIZE 0x3f

+/* SPI RX Data registers */ +# define SPI_RX_DATA_REG 0x80 +# define SPI_RX_DATA_SIZE 0x3f

+#elif defined(CONFIG_BCM6358_SPI)

+# define SPI_DT_ID "brcm,bcm6358-spi"

+/* SPI Control register (16 bit) */ +# define SPI_CTL_REG 0x000 +# define SPI_CTL_BYTES_SHIFT 0 +# define SPI_CTL_BYTES_MASK (0x3ff << SPI_CTL_BYTES_SHIFT) +# define SPI_CTL_TYPE_SHIFT 14 +# define SPI_CTL_TYPE_FD_RW (0 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_W (1 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_R (2 << SPI_CTL_TYPE_SHIFT)

+# define bcm63xx_spi_wctl(v,a) writew_be(v, a);

+/* SPI TX Data registers */ +# define SPI_TX_DATA_REG 0x002 +# define SPI_TX_DATA_SIZE 0x21e

+/* SPI RX Data registers */ +# define SPI_RX_DATA_REG 0x400 +# define SPI_RX_DATA_SIZE 0x220

+/* SPI Command register */ +# define SPI_CMD_REG 0x700

+/* SPI Interrupt registers */ +# define SPI_IR_STAT_REG 0x702 +# define SPI_IR_MASK_REG 0x704

+/* SPI Clock register */ +# define SPI_CLK_REG 0x706

+/* SPI Fill register */ +# define SPI_FILL_REG 0x707

+#endif

+/* SPI Command register */ +#define SPI_CMD_OP_SHIFT 0 +#define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT) +#define SPI_CMD_SLAVE_SHIFT 4 +#define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT) +#define SPI_CMD_PREPEND_SHIFT 8 +#define SPI_CMD_PREPEND_BYTES 0xf +#define SPI_CMD_3WIRE_SHIFT 12 +#define SPI_CMD_3WIRE_MASK (1 << SPI_CMD_3WIRE_SHIFT)

+/* SPI Interrupt registers */ +#define SPI_IR_DONE_SHIFT 0 +#define SPI_IR_DONE_MASK (1 << SPI_IR_DONE_SHIFT) +#define SPI_IR_RXOVER_SHIFT 1 +#define SPI_IR_RXOVER_MASK (1 << SPI_IR_RXOVER_SHIFT) +#define SPI_IR_TXUNDER_SHIFT 2 +#define SPI_IR_TXUNDER_MASK (1 << SPI_IR_TXUNDER_SHIFT) +#define SPI_IR_TXOVER_SHIFT 3 +#define SPI_IR_TXOVER_MASK (1 << SPI_IR_TXOVER_SHIFT) +#define SPI_IR_RXUNDER_SHIFT 4 +#define SPI_IR_RXUNDER_MASK (1 << SPI_IR_RXUNDER_SHIFT) +#define SPI_IR_CLEAR_MASK (SPI_IR_DONE_MASK |\

•                            SPI_IR_RXOVER_MASK |\
  

•                            SPI_IR_TXUNDER_MASK |\
  

•                            SPI_IR_TXOVER_MASK |\
  

•                            SPI_IR_RXUNDER_MASK)
  

+/* SPI Clock register */ +#define SPI_CLK_SHIFT 0 +#define SPI_CLK_20MHZ (0 << SPI_CLK_SHIFT) +#define SPI_CLK_0_391MHZ (1 << SPI_CLK_SHIFT) +#define SPI_CLK_0_781MHZ (2 << SPI_CLK_SHIFT) +#define SPI_CLK_1_563MHZ (3 << SPI_CLK_SHIFT) +#define SPI_CLK_3_125MHZ (4 << SPI_CLK_SHIFT) +#define SPI_CLK_6_250MHZ (5 << SPI_CLK_SHIFT) +#define SPI_CLK_12_50MHZ (6 << SPI_CLK_SHIFT) +#define SPI_CLK_25MHZ (7 << SPI_CLK_SHIFT) +#define SPI_CLK_MASK (7 << SPI_CLK_SHIFT) +#define SPI_CLK_SSOFF_SHIFT 3 +#define SPI_CLK_SSOFF_2 (2 << SPI_CLK_SSOFF_SHIFT) +#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT) +#define SPI_CLK_BSWAP_SHIFT 7 +#define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)

+#define SPI_CLK_CNT 8 +static const unsigned bcm63xx_spi_freq_table[SPI_CLK_CNT][2] = {

•   { 25000000, SPI_CLK_25MHZ },
  

•   { 20000000, SPI_CLK_20MHZ },
  

•   { 12500000, SPI_CLK_12_50MHZ },
  

•   {  6250000, SPI_CLK_6_250MHZ },
  

•   {  3125000, SPI_CLK_3_125MHZ },
  

•   {  1563000, SPI_CLK_1_563MHZ },
  

•   {   781000, SPI_CLK_0_781MHZ },
  

•   {   391000, SPI_CLK_0_391MHZ }
  

+};

+struct bcm63xx_spi_priv {

•   void __iomem *regs;
  

•   uint8_t num_cs;
  

•   size_t tx_bytes;
  

+};

+static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,

•                      struct spi_cs_info *info)
  

+{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   if (cs >= priv->num_cs) {
  

•           error("no cs %u\n", cs);
  

•           return -ENODEV;
  

•   }
  

•   return 0;
  

+}

+static int bcm63xx_spi_set_mode(struct udevice *bus, uint mode) +{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   if (mode & SPI_LSB_FIRST)
  

•           setbits_8(priv->regs + SPI_CLK_REG, SPI_CLK_BSWAP_MASK);
  

•   else
  

•           clrbits_8(priv->regs + SPI_CLK_REG, SPI_CLK_BSWAP_MASK);
  

•   return 0;
  

+}

+static int bcm63xx_spi_set_speed(struct udevice *bus, uint speed) +{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   uint8_t clk_cfg;
  

•   int i;
  

•   /* default to lowest clock configuration */
  

•   clk_cfg = SPI_CLK_0_391MHZ;
  

•   /* find the closest clock configuration */
  

•   for (i = 0; i < SPI_CLK_CNT; i++) {
  

•           if (speed >= bcm63xx_spi_freq_table[i][0]) {
  

•                   clk_cfg = bcm63xx_spi_freq_table[i][1];
  

•                   break;
  

•           }
  

•   }
  

•   /* write clock configuration */
  

•   clrsetbits_8(priv->regs + SPI_CLK_REG,
  

•                SPI_CLK_SSOFF_MASK | SPI_CLK_MASK,
  

•                clk_cfg | SPI_CLK_SSOFF_2);
  

•   return 0;
  

+}

+/*

• • BCM63xx SPI driver doesn't allow keeping CS active between transfers since
• • they are HW controlled.
• • However, it provides a mechanism to prepend write transfers prior to read
• • transfers (with a maximum prepend of 15 bytes), which is usually enough for
• • SPI-connected flashes since reading requires prepending a write transfer of
• • 5 bytes.
• • This implementation takes advantage of the prepend mechanism and combines
• • multiple transfers into a single one where possible (single/multiple write
• • transfer(s) followed by a final read/write transfer).
• • However, it's not possible to buffer reads, which means that read transfers
• • should always be done as the final ones.
• • On the other hand, take into account that combining write transfers into
• • a single one is just buffering and doesn't require prepend mechanism.
• */

+static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen,

•           const void *dout, void *din, unsigned long flags)
  

+{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
  

•   size_t data_bytes = bitlen / 8;
  

•   if (flags & SPI_XFER_BEGIN) {
  

•           /* clear prepends */
  

•           priv->tx_bytes = 0;
  

•           /* initialize hardware */
  

•           writeb_be(0, priv->regs + SPI_IR_MASK_REG);
  

•   }
  

•   if (din) {
  

•           /* buffering reads not possible since cs is hw controlled */
  

•           if (!(flags & SPI_XFER_END)) {
  

•                   error("unable to buffer reads\n");
  

•                   return -EINVAL;
  

•           }
  

•           /* check rx size */
  

•            if (data_bytes > SPI_RX_DATA_SIZE) {
  

•                   error("max rx bytes exceeded\n");
  

•                   return -EMSGSIZE;
  

•           }
  

•   }
  

•   if (dout) {
  

•           /* check tx size */
  

•           if (priv->tx_bytes + data_bytes > SPI_TX_DATA_SIZE) {
  

•                   error("max tx bytes exceeded\n");
  

•                   return -EMSGSIZE;
  

•           }
  

•           /* copy tx data */
  

•           memcpy_toio(priv->regs + SPI_TX_DATA_REG + priv->tx_bytes,
  

•                       dout, data_bytes);
  

•           priv->tx_bytes += data_bytes;
  

•   }
  

•   if (flags & SPI_XFER_END) {
  

•           struct dm_spi_slave_platdata *plat =
  

•                   dev_get_parent_platdata(dev);
  

•           uint16_t val = 0;
  

•           uint8_t irq;
  

•           /* determine control config */
  

•           if (dout && !din) {
  

•                   /* buffered write transfers */
  

•                   val |= (priv->tx_bytes << SPI_CTL_BYTES_SHIFT);
  

•                   val |= SPI_CTL_TYPE_HD_W;
  

•                   priv->tx_bytes = 0;
  

•           } else {
  

•                   if (dout && din && (flags & SPI_XFER_ONCE)) {
  

•                           /* full duplex read/write */
  

•                           val |= (data_bytes << SPI_CTL_BYTES_SHIFT);
  

•                           val |= SPI_CTL_TYPE_FD_RW;
  

•                           priv->tx_bytes = 0;
  

•                   } else {
  

•                           /* prepended write transfer */
  

•                           val |= (data_bytes << SPI_CTL_BYTES_SHIFT);
  

•                           val |= SPI_CTL_TYPE_HD_R;
  

•                           if (priv->tx_bytes > SPI_CMD_PREPEND_BYTES) {
  

•                                   error("max prepend bytes exceeded\n");
  

•                                   return -EMSGSIZE;
  

•                           }
  

•                   }
  

•           }
  

•           bcm63xx_spi_wctl(val, priv->regs + SPI_CTL_REG);
  

•           /* clear interrupts */
  

•           writeb_be(SPI_IR_CLEAR_MASK, priv->regs + SPI_IR_STAT_REG);
  

•           /* issue the transfer */
  

•           val = SPI_CMD_OP_START;
  

•           val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK;
  

•           val |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT);
  

•           if (plat->mode & SPI_3WIRE)
  

•                   val |= SPI_CMD_3WIRE_MASK;
  

•           writew_be(val, priv->regs + SPI_CMD_REG);
  

•           /* enable interrupts */
  

•           writeb_be(SPI_IR_DONE_MASK, priv->regs + SPI_IR_MASK_REG);
  

•           do {
  

•                   /* read interupts */
  

•                   irq = readb_be(priv->regs + SPI_IR_STAT_REG);
  

•                   /* transfer completed */
  

•                   if (irq & SPI_IR_DONE_MASK)
  

•                           break;
  

•           } while (1);
  

•           /* copy rx data */
  

•           if (din)
  

•                   memcpy_fromio(din, priv->regs + SPI_RX_DATA_REG,
  

•                                 data_bytes);
  

•   }
  

•   return 0;
  

+}

+static const struct dm_spi_ops bcm63xx_spi_ops = {

•   .cs_info = bcm63xx_spi_cs_info,
  

•   .set_mode = bcm63xx_spi_set_mode,
  

•   .set_speed = bcm63xx_spi_set_speed,
  

•   .xfer = bcm63xx_spi_xfer,
  

+};

+static const struct udevice_id bcm63xx_spi_ids[] = {

•   { .compatible = SPI_DT_ID, },
  

•   { /* sentinel */ }
  

Try to add .data with reg_space of respective controller, this will eventually reduce to driver configs and make it CONFIG_BCM63XX and reduce unneeded#ifdef.

thanks!

On Wed, Jun 7, 2017 at 9:05 PM, Álvaro Fernández Rojas noltari@gmail.com wrote:

Hi Jagan,

El 7/6/17 a las 9:35, Jagan Teki escribió:

...

On Fri, May 19, 2017 at 12:59 AM, Álvaro Fernández Rojas noltari@gmail.com wrote:

...

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c Instead of supporting both HW revisions of the controller in a single build, support has been split by the selected config to save space.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com

drivers/spi/Kconfig | 23 +++ drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_spi.c | 404 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 428 insertions(+) create mode 100644 drivers/spi/bcm63xx_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a00d401..d458dd7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -43,6 +43,29 @@ config ATMEL_SPI many AT32 (AVR32) and AT91 (ARM) chips. This driver can be used to access the SPI Flash, such as AT25DF321.

+choice

•   prompt "BCM63xx SPI driver"
  

•   depends on ARCH_BMIPS
  

•   optional
  

+config BCM6338_SPI

•   bool "BCM6338 SPI driver"
  

•   select SPI_MAX_WRITE_CMD_BYTES
  

•   help
  

•     Enable the BCM6338 SPI driver. This driver can be used to
  

•     access the SPI NOR flash on platforms embedding this Broadcom
  

•     SPI core.
  

+config BCM6358_SPI

•   bool "BCM6358 SPI driver"
  

•   select SPI_MAX_WRITE_CMD_BYTES
  

•   help
  

•     Enable the BCM6358 SPI driver. This driver can be used to
  

•     access the SPI NOR flash on platforms embedding this Broadcom
  

•     SPI core.
  

+endchoice

config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c090562..c9ba648 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o +obj-$(CONFIG_BCM6338_SPI)$(CONFIG_BCM6358_SPI) += bcm63xx_spi.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c new file mode 100644 index 0000000..6e64607 --- /dev/null +++ b/drivers/spi/bcm63xx_spi.c @@ -0,0 +1,404 @@ +/*

• • Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com
• • Derived from linux/drivers/spi/spi-bcm63xx.c:

• • Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
    

• • Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
    

• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <reset.h> +#include <asm/io.h>

+DECLARE_GLOBAL_DATA_PTR;

+#if defined(CONFIG_BCM6338_SPI)

+# define SPI_DT_ID "brcm,bcm6338-spi"

+/* SPI Command register */ +# define SPI_CMD_REG 0x00

+/* SPI Interrupt registers */ +# define SPI_IR_STAT_REG 0x02 +# define SPI_IR_MASK_REG 0x04

+/* SPI Clock register */ +# define SPI_CLK_REG 0x06

+/* SPI Fill register */ +# define SPI_FILL_REG 0x07

+/* SPI Control register (8 bit) */ +# define SPI_CTL_REG 0x40 +# define SPI_CTL_BYTES_SHIFT 0 +# define SPI_CTL_BYTES_MASK (0x3f << SPI_CTL_BYTES_SHIFT) +# define SPI_CTL_TYPE_SHIFT 6 +# define SPI_CTL_TYPE_FD_RW (0 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_W (1 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_R (2 << SPI_CTL_TYPE_SHIFT)

+# define bcm63xx_spi_wctl(v,a) writeb_be(v, a);

+/* SPI TX Data registers */ +# define SPI_TX_DATA_REG 0x41 +# define SPI_TX_DATA_SIZE 0x3f

+/* SPI RX Data registers */ +# define SPI_RX_DATA_REG 0x80 +# define SPI_RX_DATA_SIZE 0x3f

+#elif defined(CONFIG_BCM6358_SPI)

+# define SPI_DT_ID "brcm,bcm6358-spi"

+/* SPI Control register (16 bit) */ +# define SPI_CTL_REG 0x000 +# define SPI_CTL_BYTES_SHIFT 0 +# define SPI_CTL_BYTES_MASK (0x3ff << SPI_CTL_BYTES_SHIFT) +# define SPI_CTL_TYPE_SHIFT 14 +# define SPI_CTL_TYPE_FD_RW (0 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_W (1 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_R (2 << SPI_CTL_TYPE_SHIFT)

+# define bcm63xx_spi_wctl(v,a) writew_be(v, a);

+/* SPI TX Data registers */ +# define SPI_TX_DATA_REG 0x002 +# define SPI_TX_DATA_SIZE 0x21e

+/* SPI RX Data registers */ +# define SPI_RX_DATA_REG 0x400 +# define SPI_RX_DATA_SIZE 0x220

+/* SPI Command register */ +# define SPI_CMD_REG 0x700

+/* SPI Interrupt registers */ +# define SPI_IR_STAT_REG 0x702 +# define SPI_IR_MASK_REG 0x704

+/* SPI Clock register */ +# define SPI_CLK_REG 0x706

+/* SPI Fill register */ +# define SPI_FILL_REG 0x707

+#endif

+/* SPI Command register */ +#define SPI_CMD_OP_SHIFT 0 +#define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT) +#define SPI_CMD_SLAVE_SHIFT 4 +#define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT) +#define SPI_CMD_PREPEND_SHIFT 8 +#define SPI_CMD_PREPEND_BYTES 0xf +#define SPI_CMD_3WIRE_SHIFT 12 +#define SPI_CMD_3WIRE_MASK (1 << SPI_CMD_3WIRE_SHIFT)

+/* SPI Interrupt registers */ +#define SPI_IR_DONE_SHIFT 0 +#define SPI_IR_DONE_MASK (1 << SPI_IR_DONE_SHIFT) +#define SPI_IR_RXOVER_SHIFT 1 +#define SPI_IR_RXOVER_MASK (1 << SPI_IR_RXOVER_SHIFT) +#define SPI_IR_TXUNDER_SHIFT 2 +#define SPI_IR_TXUNDER_MASK (1 << SPI_IR_TXUNDER_SHIFT) +#define SPI_IR_TXOVER_SHIFT 3 +#define SPI_IR_TXOVER_MASK (1 << SPI_IR_TXOVER_SHIFT) +#define SPI_IR_RXUNDER_SHIFT 4 +#define SPI_IR_RXUNDER_MASK (1 << SPI_IR_RXUNDER_SHIFT) +#define SPI_IR_CLEAR_MASK (SPI_IR_DONE_MASK |\

•                            SPI_IR_RXOVER_MASK |\
  

•                            SPI_IR_TXUNDER_MASK |\
  

•                            SPI_IR_TXOVER_MASK |\
  

•                            SPI_IR_RXUNDER_MASK)
  

+/* SPI Clock register */ +#define SPI_CLK_SHIFT 0 +#define SPI_CLK_20MHZ (0 << SPI_CLK_SHIFT) +#define SPI_CLK_0_391MHZ (1 << SPI_CLK_SHIFT) +#define SPI_CLK_0_781MHZ (2 << SPI_CLK_SHIFT) +#define SPI_CLK_1_563MHZ (3 << SPI_CLK_SHIFT) +#define SPI_CLK_3_125MHZ (4 << SPI_CLK_SHIFT) +#define SPI_CLK_6_250MHZ (5 << SPI_CLK_SHIFT) +#define SPI_CLK_12_50MHZ (6 << SPI_CLK_SHIFT) +#define SPI_CLK_25MHZ (7 << SPI_CLK_SHIFT) +#define SPI_CLK_MASK (7 << SPI_CLK_SHIFT) +#define SPI_CLK_SSOFF_SHIFT 3 +#define SPI_CLK_SSOFF_2 (2 << SPI_CLK_SSOFF_SHIFT) +#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT) +#define SPI_CLK_BSWAP_SHIFT 7 +#define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)

+#define SPI_CLK_CNT 8 +static const unsigned bcm63xx_spi_freq_table[SPI_CLK_CNT][2] = {

•   { 25000000, SPI_CLK_25MHZ },
  

•   { 20000000, SPI_CLK_20MHZ },
  

•   { 12500000, SPI_CLK_12_50MHZ },
  

•   {  6250000, SPI_CLK_6_250MHZ },
  

•   {  3125000, SPI_CLK_3_125MHZ },
  

•   {  1563000, SPI_CLK_1_563MHZ },
  

•   {   781000, SPI_CLK_0_781MHZ },
  

•   {   391000, SPI_CLK_0_391MHZ }
  

+};

+struct bcm63xx_spi_priv {

•   void __iomem *regs;
  

•   uint8_t num_cs;
  

•   size_t tx_bytes;
  

+};

+static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,

•                      struct spi_cs_info *info)
  

+{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   if (cs >= priv->num_cs) {
  

•           error("no cs %u\n", cs);
  

•           return -ENODEV;
  

•   }
  

•   return 0;
  

+}

+static int bcm63xx_spi_set_mode(struct udevice *bus, uint mode) +{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   if (mode & SPI_LSB_FIRST)
  

•           setbits_8(priv->regs + SPI_CLK_REG, SPI_CLK_BSWAP_MASK);
  

•   else
  

•           clrbits_8(priv->regs + SPI_CLK_REG, SPI_CLK_BSWAP_MASK);
  

•   return 0;
  

+}

+static int bcm63xx_spi_set_speed(struct udevice *bus, uint speed) +{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   uint8_t clk_cfg;
  

•   int i;
  

•   /* default to lowest clock configuration */
  

•   clk_cfg = SPI_CLK_0_391MHZ;
  

•   /* find the closest clock configuration */
  

•   for (i = 0; i < SPI_CLK_CNT; i++) {
  

•           if (speed >= bcm63xx_spi_freq_table[i][0]) {
  

•                   clk_cfg = bcm63xx_spi_freq_table[i][1];
  

•                   break;
  

•           }
  

•   }
  

•   /* write clock configuration */
  

•   clrsetbits_8(priv->regs + SPI_CLK_REG,
  

•                SPI_CLK_SSOFF_MASK | SPI_CLK_MASK,
  

•                clk_cfg | SPI_CLK_SSOFF_2);
  

•   return 0;
  

+}

+/*

• • BCM63xx SPI driver doesn't allow keeping CS active between transfers since
• • they are HW controlled.
• • However, it provides a mechanism to prepend write transfers prior to read
• • transfers (with a maximum prepend of 15 bytes), which is usually enough for
• • SPI-connected flashes since reading requires prepending a write transfer of
• • 5 bytes.
• • This implementation takes advantage of the prepend mechanism and combines
• • multiple transfers into a single one where possible (single/multiple write
• • transfer(s) followed by a final read/write transfer).
• • However, it's not possible to buffer reads, which means that read transfers
• • should always be done as the final ones.
• • On the other hand, take into account that combining write transfers into
• • a single one is just buffering and doesn't require prepend mechanism.
• */

+static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen,

•           const void *dout, void *din, unsigned long flags)
  

+{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
  

•   size_t data_bytes = bitlen / 8;
  

•   if (flags & SPI_XFER_BEGIN) {
  

•           /* clear prepends */
  

•           priv->tx_bytes = 0;
  

•           /* initialize hardware */
  

•           writeb_be(0, priv->regs + SPI_IR_MASK_REG);
  

•   }
  

•   if (din) {
  

•           /* buffering reads not possible since cs is hw controlled */
  

•           if (!(flags & SPI_XFER_END)) {
  

•                   error("unable to buffer reads\n");
  

•                   return -EINVAL;
  

•           }
  

•           /* check rx size */
  

•            if (data_bytes > SPI_RX_DATA_SIZE) {
  

•                   error("max rx bytes exceeded\n");
  

•                   return -EMSGSIZE;
  

•           }
  

•   }
  

•   if (dout) {
  

•           /* check tx size */
  

•           if (priv->tx_bytes + data_bytes > SPI_TX_DATA_SIZE) {
  

•                   error("max tx bytes exceeded\n");
  

•                   return -EMSGSIZE;
  

•           }
  

•           /* copy tx data */
  

•           memcpy_toio(priv->regs + SPI_TX_DATA_REG + priv->tx_bytes,
  

•                       dout, data_bytes);
  

•           priv->tx_bytes += data_bytes;
  

•   }
  

•   if (flags & SPI_XFER_END) {
  

•           struct dm_spi_slave_platdata *plat =
  

•                   dev_get_parent_platdata(dev);
  

•           uint16_t val = 0;
  

•           uint8_t irq;
  

•           /* determine control config */
  

•           if (dout && !din) {
  

•                   /* buffered write transfers */
  

•                   val |= (priv->tx_bytes << SPI_CTL_BYTES_SHIFT);
  

•                   val |= SPI_CTL_TYPE_HD_W;
  

•                   priv->tx_bytes = 0;
  

•           } else {
  

•                   if (dout && din && (flags & SPI_XFER_ONCE)) {
  

•                           /* full duplex read/write */
  

•                           val |= (data_bytes << SPI_CTL_BYTES_SHIFT);
  

•                           val |= SPI_CTL_TYPE_FD_RW;
  

•                           priv->tx_bytes = 0;
  

•                   } else {
  

•                           /* prepended write transfer */
  

•                           val |= (data_bytes << SPI_CTL_BYTES_SHIFT);
  

•                           val |= SPI_CTL_TYPE_HD_R;
  

•                           if (priv->tx_bytes > SPI_CMD_PREPEND_BYTES) {
  

•                                   error("max prepend bytes exceeded\n");
  

•                                   return -EMSGSIZE;
  

•                           }
  

•                   }
  

•           }
  

•           bcm63xx_spi_wctl(val, priv->regs + SPI_CTL_REG);
  

•           /* clear interrupts */
  

•           writeb_be(SPI_IR_CLEAR_MASK, priv->regs + SPI_IR_STAT_REG);
  

•           /* issue the transfer */
  

•           val = SPI_CMD_OP_START;
  

•           val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK;
  

•           val |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT);
  

•           if (plat->mode & SPI_3WIRE)
  

•                   val |= SPI_CMD_3WIRE_MASK;
  

•           writew_be(val, priv->regs + SPI_CMD_REG);
  

•           /* enable interrupts */
  

•           writeb_be(SPI_IR_DONE_MASK, priv->regs + SPI_IR_MASK_REG);
  

•           do {
  

•                   /* read interupts */
  

•                   irq = readb_be(priv->regs + SPI_IR_STAT_REG);
  

•                   /* transfer completed */
  

•                   if (irq & SPI_IR_DONE_MASK)
  

•                           break;
  

•           } while (1);
  

•           /* copy rx data */
  

•           if (din)
  

•                   memcpy_fromio(din, priv->regs + SPI_RX_DATA_REG,
  

•                                 data_bytes);
  

•   }
  

•   return 0;
  

+}

+static const struct dm_spi_ops bcm63xx_spi_ops = {

•   .cs_info = bcm63xx_spi_cs_info,
  

•   .set_mode = bcm63xx_spi_set_mode,
  

•   .set_speed = bcm63xx_spi_set_speed,
  

•   .xfer = bcm63xx_spi_xfer,
  

+};

+static const struct udevice_id bcm63xx_spi_ids[] = {

•   { .compatible = SPI_DT_ID, },
  

•   { /* sentinel */ }
  

Try to add .data with reg_space of respective controller, this will eventually reduce to driver configs and make it CONFIG_BCM63XX and reduce unneeded#ifdef.

This implies adding considerable bloat to the driver... Is it imperative for the driver to be accepted?

Yes, as per as recent U-boot developement we're trying to reduce defconfig code as possible and even this method can improve code quality.

thanks!

On Thu, Jun 8, 2017 at 12:05 AM, Álvaro Fernández Rojas noltari@gmail.com wrote:

Hi Jagan,

El 07/06/2017 a las 19:29, Jagan Teki escribió:

...

On Wed, Jun 7, 2017 at 9:05 PM, Álvaro Fernández Rojas noltari@gmail.com wrote:

...

Hi Jagan,

El 7/6/17 a las 9:35, Jagan Teki escribió:

...

On Fri, May 19, 2017 at 12:59 AM, Álvaro Fernández Rojas noltari@gmail.com wrote:

...

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c Instead of supporting both HW revisions of the controller in a single build, support has been split by the selected config to save space.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com

drivers/spi/Kconfig | 23 +++ drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_spi.c | 404 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 428 insertions(+) create mode 100644 drivers/spi/bcm63xx_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a00d401..d458dd7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -43,6 +43,29 @@ config ATMEL_SPI many AT32 (AVR32) and AT91 (ARM) chips. This driver can be used to access the SPI Flash, such as AT25DF321.

+choice

•   prompt "BCM63xx SPI driver"
  

•   depends on ARCH_BMIPS
  

•   optional
  

+config BCM6338_SPI

•   bool "BCM6338 SPI driver"
  

•   select SPI_MAX_WRITE_CMD_BYTES
  

•   help
  

•     Enable the BCM6338 SPI driver. This driver can be used to
  

•     access the SPI NOR flash on platforms embedding this Broadcom
  

•     SPI core.
  

+config BCM6358_SPI

•   bool "BCM6358 SPI driver"
  

•   select SPI_MAX_WRITE_CMD_BYTES
  

•   help
  

•     Enable the BCM6358 SPI driver. This driver can be used to
  

•     access the SPI NOR flash on platforms embedding this Broadcom
  

•     SPI core.
  

+endchoice

config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c090562..c9ba648 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o +obj-$(CONFIG_BCM6338_SPI)$(CONFIG_BCM6358_SPI) += bcm63xx_spi.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c new file mode 100644 index 0000000..6e64607 --- /dev/null +++ b/drivers/spi/bcm63xx_spi.c @@ -0,0 +1,404 @@ +/*

• • Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com
• • Derived from linux/drivers/spi/spi-bcm63xx.c:

• • Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
    

• • Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
    

• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <reset.h> +#include <asm/io.h>

+DECLARE_GLOBAL_DATA_PTR;

+#if defined(CONFIG_BCM6338_SPI)

+# define SPI_DT_ID "brcm,bcm6338-spi"

+/* SPI Command register */ +# define SPI_CMD_REG 0x00

+/* SPI Interrupt registers */ +# define SPI_IR_STAT_REG 0x02 +# define SPI_IR_MASK_REG 0x04

+/* SPI Clock register */ +# define SPI_CLK_REG 0x06

+/* SPI Fill register */ +# define SPI_FILL_REG 0x07

+/* SPI Control register (8 bit) */ +# define SPI_CTL_REG 0x40 +# define SPI_CTL_BYTES_SHIFT 0 +# define SPI_CTL_BYTES_MASK (0x3f << SPI_CTL_BYTES_SHIFT) +# define SPI_CTL_TYPE_SHIFT 6 +# define SPI_CTL_TYPE_FD_RW (0 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_W (1 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_R (2 << SPI_CTL_TYPE_SHIFT)

+# define bcm63xx_spi_wctl(v,a) writeb_be(v, a);

+/* SPI TX Data registers */ +# define SPI_TX_DATA_REG 0x41 +# define SPI_TX_DATA_SIZE 0x3f

+/* SPI RX Data registers */ +# define SPI_RX_DATA_REG 0x80 +# define SPI_RX_DATA_SIZE 0x3f

+#elif defined(CONFIG_BCM6358_SPI)

+# define SPI_DT_ID "brcm,bcm6358-spi"

+/* SPI Control register (16 bit) */ +# define SPI_CTL_REG 0x000 +# define SPI_CTL_BYTES_SHIFT 0 +# define SPI_CTL_BYTES_MASK (0x3ff << SPI_CTL_BYTES_SHIFT) +# define SPI_CTL_TYPE_SHIFT 14 +# define SPI_CTL_TYPE_FD_RW (0 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_W (1 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_R (2 << SPI_CTL_TYPE_SHIFT)

+# define bcm63xx_spi_wctl(v,a) writew_be(v, a);

+/* SPI TX Data registers */ +# define SPI_TX_DATA_REG 0x002 +# define SPI_TX_DATA_SIZE 0x21e

+/* SPI RX Data registers */ +# define SPI_RX_DATA_REG 0x400 +# define SPI_RX_DATA_SIZE 0x220

+/* SPI Command register */ +# define SPI_CMD_REG 0x700

+/* SPI Interrupt registers */ +# define SPI_IR_STAT_REG 0x702 +# define SPI_IR_MASK_REG 0x704

+/* SPI Clock register */ +# define SPI_CLK_REG 0x706

+/* SPI Fill register */ +# define SPI_FILL_REG 0x707

+#endif

+/* SPI Command register */ +#define SPI_CMD_OP_SHIFT 0 +#define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT) +#define SPI_CMD_SLAVE_SHIFT 4 +#define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT) +#define SPI_CMD_PREPEND_SHIFT 8 +#define SPI_CMD_PREPEND_BYTES 0xf +#define SPI_CMD_3WIRE_SHIFT 12 +#define SPI_CMD_3WIRE_MASK (1 << SPI_CMD_3WIRE_SHIFT)

+/* SPI Interrupt registers */ +#define SPI_IR_DONE_SHIFT 0 +#define SPI_IR_DONE_MASK (1 << SPI_IR_DONE_SHIFT) +#define SPI_IR_RXOVER_SHIFT 1 +#define SPI_IR_RXOVER_MASK (1 << SPI_IR_RXOVER_SHIFT) +#define SPI_IR_TXUNDER_SHIFT 2 +#define SPI_IR_TXUNDER_MASK (1 << SPI_IR_TXUNDER_SHIFT) +#define SPI_IR_TXOVER_SHIFT 3 +#define SPI_IR_TXOVER_MASK (1 << SPI_IR_TXOVER_SHIFT) +#define SPI_IR_RXUNDER_SHIFT 4 +#define SPI_IR_RXUNDER_MASK (1 << SPI_IR_RXUNDER_SHIFT) +#define SPI_IR_CLEAR_MASK (SPI_IR_DONE_MASK |\

•                            SPI_IR_RXOVER_MASK |\
  

•                            SPI_IR_TXUNDER_MASK |\
  

•                            SPI_IR_TXOVER_MASK |\
  

•                            SPI_IR_RXUNDER_MASK)
  

+/* SPI Clock register */ +#define SPI_CLK_SHIFT 0 +#define SPI_CLK_20MHZ (0 << SPI_CLK_SHIFT) +#define SPI_CLK_0_391MHZ (1 << SPI_CLK_SHIFT) +#define SPI_CLK_0_781MHZ (2 << SPI_CLK_SHIFT) +#define SPI_CLK_1_563MHZ (3 << SPI_CLK_SHIFT) +#define SPI_CLK_3_125MHZ (4 << SPI_CLK_SHIFT) +#define SPI_CLK_6_250MHZ (5 << SPI_CLK_SHIFT) +#define SPI_CLK_12_50MHZ (6 << SPI_CLK_SHIFT) +#define SPI_CLK_25MHZ (7 << SPI_CLK_SHIFT) +#define SPI_CLK_MASK (7 << SPI_CLK_SHIFT) +#define SPI_CLK_SSOFF_SHIFT 3 +#define SPI_CLK_SSOFF_2 (2 << SPI_CLK_SSOFF_SHIFT) +#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT) +#define SPI_CLK_BSWAP_SHIFT 7 +#define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)

+#define SPI_CLK_CNT 8 +static const unsigned bcm63xx_spi_freq_table[SPI_CLK_CNT][2] = {

•   { 25000000, SPI_CLK_25MHZ },
  

•   { 20000000, SPI_CLK_20MHZ },
  

•   { 12500000, SPI_CLK_12_50MHZ },
  

•   {  6250000, SPI_CLK_6_250MHZ },
  

•   {  3125000, SPI_CLK_3_125MHZ },
  

•   {  1563000, SPI_CLK_1_563MHZ },
  

•   {   781000, SPI_CLK_0_781MHZ },
  

•   {   391000, SPI_CLK_0_391MHZ }
  

+};

+struct bcm63xx_spi_priv {

•   void __iomem *regs;
  

•   uint8_t num_cs;
  

•   size_t tx_bytes;
  

+};

+static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,

•                      struct spi_cs_info *info)
  

+{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   if (cs >= priv->num_cs) {
  

•           error("no cs %u\n", cs);
  

•           return -ENODEV;
  

•   }
  

•   return 0;
  

+}

+static int bcm63xx_spi_set_mode(struct udevice *bus, uint mode) +{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   if (mode & SPI_LSB_FIRST)
  

•           setbits_8(priv->regs + SPI_CLK_REG, SPI_CLK_BSWAP_MASK);
  

•   else
  

•           clrbits_8(priv->regs + SPI_CLK_REG, SPI_CLK_BSWAP_MASK);
  

•   return 0;
  

+}

+static int bcm63xx_spi_set_speed(struct udevice *bus, uint speed) +{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   uint8_t clk_cfg;
  

•   int i;
  

•   /* default to lowest clock configuration */
  

•   clk_cfg = SPI_CLK_0_391MHZ;
  

•   /* find the closest clock configuration */
  

•   for (i = 0; i < SPI_CLK_CNT; i++) {
  

•           if (speed >= bcm63xx_spi_freq_table[i][0]) {
  

•                   clk_cfg = bcm63xx_spi_freq_table[i][1];
  

•                   break;
  

•           }
  

•   }
  

•   /* write clock configuration */
  

•   clrsetbits_8(priv->regs + SPI_CLK_REG,
  

•                SPI_CLK_SSOFF_MASK | SPI_CLK_MASK,
  

•                clk_cfg | SPI_CLK_SSOFF_2);
  

•   return 0;
  

+}

+/*

• • BCM63xx SPI driver doesn't allow keeping CS active between transfers since
• • they are HW controlled.
• • However, it provides a mechanism to prepend write transfers prior to read
• • transfers (with a maximum prepend of 15 bytes), which is usually enough for
• • SPI-connected flashes since reading requires prepending a write transfer of
• • 5 bytes.
• • This implementation takes advantage of the prepend mechanism and combines
• • multiple transfers into a single one where possible (single/multiple write
• • transfer(s) followed by a final read/write transfer).
• • However, it's not possible to buffer reads, which means that read transfers
• • should always be done as the final ones.
• • On the other hand, take into account that combining write transfers into
• • a single one is just buffering and doesn't require prepend mechanism.
• */

+static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen,

•           const void *dout, void *din, unsigned long flags)
  

+{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
  

•   size_t data_bytes = bitlen / 8;
  

•   if (flags & SPI_XFER_BEGIN) {
  

•           /* clear prepends */
  

•           priv->tx_bytes = 0;
  

•           /* initialize hardware */
  

•           writeb_be(0, priv->regs + SPI_IR_MASK_REG);
  

•   }
  

•   if (din) {
  

•           /* buffering reads not possible since cs is hw controlled */
  

•           if (!(flags & SPI_XFER_END)) {
  

•                   error("unable to buffer reads\n");
  

•                   return -EINVAL;
  

•           }
  

•           /* check rx size */
  

•            if (data_bytes > SPI_RX_DATA_SIZE) {
  

•                   error("max rx bytes exceeded\n");
  

•                   return -EMSGSIZE;
  

•           }
  

•   }
  

•   if (dout) {
  

•           /* check tx size */
  

•           if (priv->tx_bytes + data_bytes > SPI_TX_DATA_SIZE) {
  

•                   error("max tx bytes exceeded\n");
  

•                   return -EMSGSIZE;
  

•           }
  

•           /* copy tx data */
  

•           memcpy_toio(priv->regs + SPI_TX_DATA_REG + priv->tx_bytes,
  

•                       dout, data_bytes);
  

•           priv->tx_bytes += data_bytes;
  

•   }
  

•   if (flags & SPI_XFER_END) {
  

•           struct dm_spi_slave_platdata *plat =
  

•                   dev_get_parent_platdata(dev);
  

•           uint16_t val = 0;
  

•           uint8_t irq;
  

•           /* determine control config */
  

•           if (dout && !din) {
  

•                   /* buffered write transfers */
  

•                   val |= (priv->tx_bytes << SPI_CTL_BYTES_SHIFT);
  

•                   val |= SPI_CTL_TYPE_HD_W;
  

•                   priv->tx_bytes = 0;
  

•           } else {
  

•                   if (dout && din && (flags & SPI_XFER_ONCE)) {
  

•                           /* full duplex read/write */
  

•                           val |= (data_bytes << SPI_CTL_BYTES_SHIFT);
  

•                           val |= SPI_CTL_TYPE_FD_RW;
  

•                           priv->tx_bytes = 0;
  

•                   } else {
  

•                           /* prepended write transfer */
  

•                           val |= (data_bytes << SPI_CTL_BYTES_SHIFT);
  

•                           val |= SPI_CTL_TYPE_HD_R;
  

•                           if (priv->tx_bytes > SPI_CMD_PREPEND_BYTES) {
  

•                                   error("max prepend bytes exceeded\n");
  

•                                   return -EMSGSIZE;
  

•                           }
  

•                   }
  

•           }
  

•           bcm63xx_spi_wctl(val, priv->regs + SPI_CTL_REG);
  

•           /* clear interrupts */
  

•           writeb_be(SPI_IR_CLEAR_MASK, priv->regs + SPI_IR_STAT_REG);
  

•           /* issue the transfer */
  

•           val = SPI_CMD_OP_START;
  

•           val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK;
  

•           val |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT);
  

•           if (plat->mode & SPI_3WIRE)
  

•                   val |= SPI_CMD_3WIRE_MASK;
  

•           writew_be(val, priv->regs + SPI_CMD_REG);
  

•           /* enable interrupts */
  

•           writeb_be(SPI_IR_DONE_MASK, priv->regs + SPI_IR_MASK_REG);
  

•           do {
  

•                   /* read interupts */
  

•                   irq = readb_be(priv->regs + SPI_IR_STAT_REG);
  

•                   /* transfer completed */
  

•                   if (irq & SPI_IR_DONE_MASK)
  

•                           break;
  

•           } while (1);
  

•           /* copy rx data */
  

•           if (din)
  

•                   memcpy_fromio(din, priv->regs + SPI_RX_DATA_REG,
  

•                                 data_bytes);
  

•   }
  

•   return 0;
  

+}

+static const struct dm_spi_ops bcm63xx_spi_ops = {

•   .cs_info = bcm63xx_spi_cs_info,
  

•   .set_mode = bcm63xx_spi_set_mode,
  

•   .set_speed = bcm63xx_spi_set_speed,
  

•   .xfer = bcm63xx_spi_xfer,
  

+};

+static const struct udevice_id bcm63xx_spi_ids[] = {

•   { .compatible = SPI_DT_ID, },
  

•   { /* sentinel */ }
  

Try to add .data with reg_space of respective controller, this will eventually reduce to driver configs and make it CONFIG_BCM63XX and reduce unneeded#ifdef.

This implies adding considerable bloat to the driver... Is it imperative for the driver to be accepted?

Yes, as per as recent U-boot developement we're trying to reduce defconfig code as possible and even this method can improve code quality.

I don't think that method applies here, since u-boot is usally built for each SoC and supporting two cores in the same build makes no sense to me. These should be done in two different drivers but I merged them into a single one to improve maintainability.

I don't like the approch of adding ifdef with two controller reg_space, we have .data that has been used in many dm-driver, let's have a try.

BTW, two u-boot developers already reviewed this patch and didn't complain about it...

Wrong statement, it is community project every-body comment need to be considrable.

thanks!

For some SPI controllers it's not possible to keep the CS active between transfers and they are limited to a known number of bytes. This splits spi_flash reads into different iterations in order to respect the SPI controller limits.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org --- v2: no changes

drivers/mtd/spi/spi_flash.c | 3 +++ include/spi.h | 3 +++ 2 files changed, 6 insertions(+)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index ab7910b..e44c10f 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -487,6 +487,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, else read_len = remain_len;

+ if (spi->max_read_size) + read_len = min(read_len, spi->max_read_size); + spi_flash_addr(read_addr, cmd);

ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); diff --git a/include/spi.h b/include/spi.h index deb65ef..75a994c 100644 --- a/include/spi.h +++ b/include/spi.h @@ -86,6 +86,8 @@ struct dm_spi_slave_platdata { * @cs: ID of the chip select connected to the slave. * @mode: SPI mode to use for this slave (see SPI mode flags) * @wordlen: Size of SPI word in number of bits + * @max_read_size: If non-zero, the maximum number of bytes which can + * be read at once. * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. * @memory_map: Address of read-only SPI flash access. @@ -102,6 +104,7 @@ struct spi_slave { #endif uint mode; unsigned int wordlen; + unsigned int max_read_size; unsigned int max_write_size; void *memory_map; u8 option;

Hi Jagan,

El 7/6/17 a las 9:30, Jagan Teki escribió:

On Mon, May 22, 2017 at 11:51 PM, Álvaro Fernández Rojas noltari@gmail.com wrote:

...

Command bytes are part of the written bytes and they should be taken into account when sending a spi transfer.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com

v2: Introduce changes requested by Simon Glass:

• Always include command bytes when determining max write size.

drivers/mtd/spi/spi_flash.c | 2 +- include/spi.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index e44c10f..5b8cbc9 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -380,7 +380,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,

            if (spi->max_write_size)
                    chunk_len = min(chunk_len,

•                                   (size_t)spi->max_write_size);
  

•                                   spi->max_write_size - len);
  

This can be squashed with 01/10 with proper commit message?

I think it's better if we keep it as two patches, because they are different features...

thanks!

Thanks.

Hi Jagan,

El 07/06/2017 a las 19:28, Jagan Teki escribió:

On Wed, Jun 7, 2017 at 9:03 PM, Álvaro Fernández Rojas noltari@gmail.com wrote:

...

Hi Jagan,

El 7/6/17 a las 9:30, Jagan Teki escribió:

...

On Mon, May 22, 2017 at 11:51 PM, Álvaro Fernández Rojas noltari@gmail.com wrote:

...

Command bytes are part of the written bytes and they should be taken into account when sending a spi transfer.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com

v2: Introduce changes requested by Simon Glass:

• Always include command bytes when determining max write size.

drivers/mtd/spi/spi_flash.c | 2 +- include/spi.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index e44c10f..5b8cbc9 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -380,7 +380,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,

            if (spi->max_write_size)
                    chunk_len = min(chunk_len,

•                                   (size_t)spi->max_write_size);
  

•                                   spi->max_write_size - len);
  

This can be squashed with 01/10 with proper commit message?

I think it's better if we keep it as two patches, because they are different features...

Fine, but adding immediate change followed by previous change deletion doesn't look feature that exist.

Nope, there's no previous change deletion. First patch adds support for limited reads and second patch fixes limited writes...

thanks!

Thanks

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v2: add spi alias

arch/mips/dts/brcm,bcm6338.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index eb51a43..98bda9c 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6338";

+ aliases { + spi0 = &spi; + }; + cpus { reg = <0xfffe0000 0x4>; #address-cells = <1>; @@ -109,6 +113,19 @@ status = "disabled"; };

+ spi: spi@fffe0c00 { + compatible = "brcm,bcm6338-spi"; + reg = <0xfffe0c00 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6338_CLK_SPI>; + resets = <&periph_rst BCM6338_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + memory-controller@fffe3100 { compatible = "brcm,bcm6338-mc"; reg = <0xfffe3100 0x38>;

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v2: add spi alias

arch/mips/dts/brcm,bcm6358.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 4f63cf8..1662783 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6358";

+ aliases { + spi0 = &spi; + }; + cpus { reg = <0xfffe0000 0x4>; #address-cells = <1>; @@ -142,6 +146,19 @@ status = "disabled"; };

+ spi: spi@fffe0800 { + compatible = "brcm,bcm6358-spi"; + reg = <0xfffe0800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6358_CLK_SPI>; + resets = <&periph_rst BCM6358_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + memory-controller@fffe1200 { compatible = "brcm,bcm6358-mc"; reg = <0xfffe1200 0x4c>;

This driver manages the low speed SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v2: add spi alias

arch/mips/dts/brcm,bcm63268.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 113a96b..6e3d9c3 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -13,6 +13,10 @@ / { compatible = "brcm,bcm63268";

+ aliases { + spi0 = &lsspi; + }; + cpus { reg = <0x10000000 0x4>; #address-cells = <1>; @@ -136,6 +140,19 @@ #power-domain-cells = <1>; };

+ lsspi: spi@10000800 { + compatible = "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM63268_CLK_SPI>; + resets = <&periph_rst BCM63268_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <8>; + + status = "disabled"; + }; + leds: led-controller@10001900 { compatible = "brcm,bcm6328-leds"; reg = <0x10001900 0x24>;

It's a Spansion (s25fl064a) 8 MB SPI flash.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v2: remove spi alias

arch/mips/dts/netgear,cg3100d.dts | 12 ++++++++++++ configs/netgear_cg3100d_ram_defconfig | 8 ++++++++ 2 files changed, 20 insertions(+)

diff --git a/arch/mips/dts/netgear,cg3100d.dts b/arch/mips/dts/netgear,cg3100d.dts index db1e2e7..5f85c73 100644 --- a/arch/mips/dts/netgear,cg3100d.dts +++ b/arch/mips/dts/netgear,cg3100d.dts @@ -90,6 +90,18 @@ status = "okay"; };

+&spi { + status = "okay"; + + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <25000000>; + }; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig index a6eff10..da2426b 100644 --- a/configs/netgear_cg3100d_ram_defconfig +++ b/configs/netgear_cg3100d_ram_defconfig @@ -3,6 +3,7 @@ CONFIG_BAUDRATE=115200 CONFIG_BCM6345_CLK=y CONFIG_BCM6345_GPIO=y CONFIG_BCM6345_SERIAL=y +CONFIG_BCM6358_SPI=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_NETGEAR_CG3100D=y # CONFIG_CMD_BOOTD is not set @@ -27,6 +28,8 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_SAVEENV is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y # CONFIG_CMD_XIMG is not set CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d" CONFIG_DISPLAY_CPUINFO=y @@ -34,6 +37,8 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DM_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_HUSH_PARSER=y CONFIG_LED=y CONFIG_LED_BCM6328=y @@ -47,6 +52,9 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_RESET=y CONFIG_RESET_BCM6345=y CONFIG_SOC_BMIPS_BCM3380=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPL_SERIAL_PRESENT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_NO_FLASH=y

For some SPI controllers it's not possible to keep the CS active between transfers and they are limited to a known number of bytes. This splits spi_flash reads into different iterations in order to respect the SPI controller limits.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org --- v3: no changes v2: no changes

drivers/mtd/spi/spi_flash.c | 3 +++ include/spi.h | 3 +++ 2 files changed, 6 insertions(+)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 0034a28..5ee33d8 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -487,6 +487,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, else read_len = remain_len;

+ if (spi->max_read_size) + read_len = min(read_len, spi->max_read_size); + spi_flash_addr(read_addr, cmd);

ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); diff --git a/include/spi.h b/include/spi.h index 8c4b882..d0fa537 100644 --- a/include/spi.h +++ b/include/spi.h @@ -86,6 +86,8 @@ struct dm_spi_slave_platdata { * @cs: ID of the chip select connected to the slave. * @mode: SPI mode to use for this slave (see SPI mode flags) * @wordlen: Size of SPI word in number of bits + * @max_read_size: If non-zero, the maximum number of bytes which can + * be read at once. * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. * @memory_map: Address of read-only SPI flash access. @@ -102,6 +104,7 @@ struct spi_slave { #endif uint mode; unsigned int wordlen; + unsigned int max_read_size; unsigned int max_write_size; void *memory_map; u8 option;

Command bytes are part of the written bytes and they should be taken into account when sending a spi transfer.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org --- v3: Fix bug introduced in v2: sizeof(cmd) vs len v2: Introduce changes requested by Simon Glass: - Always include command bytes when determining max write size.

drivers/mtd/spi/spi_flash.c | 2 +- include/spi.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 5ee33d8..1e194ce 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -380,7 +380,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,

if (spi->max_write_size) chunk_len = min(chunk_len, - (size_t)spi->max_write_size); + spi->max_write_size - sizeof(cmd));

spi_flash_addr(write_addr, cmd);

diff --git a/include/spi.h b/include/spi.h index d0fa537..c4e1da6 100644 --- a/include/spi.h +++ b/include/spi.h @@ -89,7 +89,7 @@ struct dm_spi_slave_platdata { * @max_read_size: If non-zero, the maximum number of bytes which can * be read at once. * @max_write_size: If non-zero, the maximum number of bytes which can - * be written at once, excluding command bytes. + * be written at once. * @memory_map: Address of read-only SPI flash access. * @flags: Indication of SPI flags. */

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c Instead of supporting both HW revisions of the controller in a single build, support has been split by the selected config to save space.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org --- v3: rename BCM6338 SPI driver to BCM6348 switch to devfdt_get_addr_size_index() v2: no changes

drivers/spi/Kconfig | 21 +++ drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_spi.c | 404 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 426 insertions(+) create mode 100644 drivers/spi/bcm63xx_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index bef864f..0b408db 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -40,6 +40,27 @@ config ATMEL_SPI many AT32 (AVR32) and AT91 (ARM) chips. This driver can be used to access the SPI Flash, such as AT25DF321.

+choice + prompt "BCM63xx SPI driver" + depends on ARCH_BMIPS + optional + +config BCM6348_SPI + bool "BCM6348 SPI driver" + help + Enable the BCM6348 SPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this Broadcom + SPI core. + +config BCM6358_SPI + bool "BCM6358 SPI driver" + help + Enable the BCM6358 SPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this Broadcom + SPI core. + +endchoice + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c090562..2795a34 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o +obj-$(CONFIG_BCM6348_SPI)$(CONFIG_BCM6358_SPI) += bcm63xx_spi.o obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c new file mode 100644 index 0000000..d3aad70 --- /dev/null +++ b/drivers/spi/bcm63xx_spi.c @@ -0,0 +1,404 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com + * + * Derived from linux/drivers/spi/spi-bcm63xx.c: + * Copyright (C) 2009-2012 Florian Fainelli florian@openwrt.org + * Copyright (C) 2010 Tanguy Bouzeloc tanguy.bouzeloc@efixo.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <reset.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_BCM6348_SPI) + +# define SPI_DT_ID "brcm,bcm6348-spi" + +/* SPI Command register */ +# define SPI_CMD_REG 0x00 + +/* SPI Interrupt registers */ +# define SPI_IR_STAT_REG 0x02 +# define SPI_IR_MASK_REG 0x04 + +/* SPI Clock register */ +# define SPI_CLK_REG 0x06 + +/* SPI Fill register */ +# define SPI_FILL_REG 0x07 + +/* SPI Control register (8 bit) */ +# define SPI_CTL_REG 0x40 +# define SPI_CTL_BYTES_SHIFT 0 +# define SPI_CTL_BYTES_MASK (0x3f << SPI_CTL_BYTES_SHIFT) +# define SPI_CTL_TYPE_SHIFT 6 +# define SPI_CTL_TYPE_FD_RW (0 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_W (1 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_R (2 << SPI_CTL_TYPE_SHIFT) + +# define bcm63xx_spi_wctl(v,a) writeb_be(v, a); + +/* SPI TX Data registers */ +# define SPI_TX_DATA_REG 0x41 +# define SPI_TX_DATA_SIZE 0x3f + +/* SPI RX Data registers */ +# define SPI_RX_DATA_REG 0x80 +# define SPI_RX_DATA_SIZE 0x3f + +#elif defined(CONFIG_BCM6358_SPI) + +# define SPI_DT_ID "brcm,bcm6358-spi" + +/* SPI Control register (16 bit) */ +# define SPI_CTL_REG 0x000 +# define SPI_CTL_BYTES_SHIFT 0 +# define SPI_CTL_BYTES_MASK (0x3ff << SPI_CTL_BYTES_SHIFT) +# define SPI_CTL_TYPE_SHIFT 14 +# define SPI_CTL_TYPE_FD_RW (0 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_W (1 << SPI_CTL_TYPE_SHIFT) +# define SPI_CTL_TYPE_HD_R (2 << SPI_CTL_TYPE_SHIFT) + +# define bcm63xx_spi_wctl(v,a) writew_be(v, a); + +/* SPI TX Data registers */ +# define SPI_TX_DATA_REG 0x002 +# define SPI_TX_DATA_SIZE 0x21e + +/* SPI RX Data registers */ +# define SPI_RX_DATA_REG 0x400 +# define SPI_RX_DATA_SIZE 0x220 + +/* SPI Command register */ +# define SPI_CMD_REG 0x700 + +/* SPI Interrupt registers */ +# define SPI_IR_STAT_REG 0x702 +# define SPI_IR_MASK_REG 0x704 + +/* SPI Clock register */ +# define SPI_CLK_REG 0x706 + +/* SPI Fill register */ +# define SPI_FILL_REG 0x707 + +#endif + +/* SPI Command register */ +#define SPI_CMD_OP_SHIFT 0 +#define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT) +#define SPI_CMD_SLAVE_SHIFT 4 +#define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT) +#define SPI_CMD_PREPEND_SHIFT 8 +#define SPI_CMD_PREPEND_BYTES 0xf +#define SPI_CMD_3WIRE_SHIFT 12 +#define SPI_CMD_3WIRE_MASK (1 << SPI_CMD_3WIRE_SHIFT) + +/* SPI Interrupt registers */ +#define SPI_IR_DONE_SHIFT 0 +#define SPI_IR_DONE_MASK (1 << SPI_IR_DONE_SHIFT) +#define SPI_IR_RXOVER_SHIFT 1 +#define SPI_IR_RXOVER_MASK (1 << SPI_IR_RXOVER_SHIFT) +#define SPI_IR_TXUNDER_SHIFT 2 +#define SPI_IR_TXUNDER_MASK (1 << SPI_IR_TXUNDER_SHIFT) +#define SPI_IR_TXOVER_SHIFT 3 +#define SPI_IR_TXOVER_MASK (1 << SPI_IR_TXOVER_SHIFT) +#define SPI_IR_RXUNDER_SHIFT 4 +#define SPI_IR_RXUNDER_MASK (1 << SPI_IR_RXUNDER_SHIFT) +#define SPI_IR_CLEAR_MASK (SPI_IR_DONE_MASK |\ + SPI_IR_RXOVER_MASK |\ + SPI_IR_TXUNDER_MASK |\ + SPI_IR_TXOVER_MASK |\ + SPI_IR_RXUNDER_MASK) + +/* SPI Clock register */ +#define SPI_CLK_SHIFT 0 +#define SPI_CLK_20MHZ (0 << SPI_CLK_SHIFT) +#define SPI_CLK_0_391MHZ (1 << SPI_CLK_SHIFT) +#define SPI_CLK_0_781MHZ (2 << SPI_CLK_SHIFT) +#define SPI_CLK_1_563MHZ (3 << SPI_CLK_SHIFT) +#define SPI_CLK_3_125MHZ (4 << SPI_CLK_SHIFT) +#define SPI_CLK_6_250MHZ (5 << SPI_CLK_SHIFT) +#define SPI_CLK_12_50MHZ (6 << SPI_CLK_SHIFT) +#define SPI_CLK_25MHZ (7 << SPI_CLK_SHIFT) +#define SPI_CLK_MASK (7 << SPI_CLK_SHIFT) +#define SPI_CLK_SSOFF_SHIFT 3 +#define SPI_CLK_SSOFF_2 (2 << SPI_CLK_SSOFF_SHIFT) +#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT) +#define SPI_CLK_BSWAP_SHIFT 7 +#define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT) + +#define SPI_CLK_CNT 8 +static const unsigned bcm63xx_spi_freq_table[SPI_CLK_CNT][2] = { + { 25000000, SPI_CLK_25MHZ }, + { 20000000, SPI_CLK_20MHZ }, + { 12500000, SPI_CLK_12_50MHZ }, + { 6250000, SPI_CLK_6_250MHZ }, + { 3125000, SPI_CLK_3_125MHZ }, + { 1563000, SPI_CLK_1_563MHZ }, + { 781000, SPI_CLK_0_781MHZ }, + { 391000, SPI_CLK_0_391MHZ } +}; + +struct bcm63xx_spi_priv { + void __iomem *regs; + uint8_t num_cs; + size_t tx_bytes; +}; + +static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + struct bcm63xx_spi_priv *priv = dev_get_priv(bus); + + if (cs >= priv->num_cs) { + error("no cs %u\n", cs); + return -ENODEV; + } + + return 0; +} + +static int bcm63xx_spi_set_mode(struct udevice *bus, uint mode) +{ + struct bcm63xx_spi_priv *priv = dev_get_priv(bus); + + if (mode & SPI_LSB_FIRST) + setbits_8(priv->regs + SPI_CLK_REG, SPI_CLK_BSWAP_MASK); + else + clrbits_8(priv->regs + SPI_CLK_REG, SPI_CLK_BSWAP_MASK); + + return 0; +} + +static int bcm63xx_spi_set_speed(struct udevice *bus, uint speed) +{ + struct bcm63xx_spi_priv *priv = dev_get_priv(bus); + uint8_t clk_cfg; + int i; + + /* default to lowest clock configuration */ + clk_cfg = SPI_CLK_0_391MHZ; + + /* find the closest clock configuration */ + for (i = 0; i < SPI_CLK_CNT; i++) { + if (speed >= bcm63xx_spi_freq_table[i][0]) { + clk_cfg = bcm63xx_spi_freq_table[i][1]; + break; + } + } + + /* write clock configuration */ + clrsetbits_8(priv->regs + SPI_CLK_REG, + SPI_CLK_SSOFF_MASK | SPI_CLK_MASK, + clk_cfg | SPI_CLK_SSOFF_2); + + return 0; +} + +/* + * BCM63xx SPI driver doesn't allow keeping CS active between transfers since + * they are HW controlled. + * However, it provides a mechanism to prepend write transfers prior to read + * transfers (with a maximum prepend of 15 bytes), which is usually enough for + * SPI-connected flashes since reading requires prepending a write transfer of + * 5 bytes. + * + * This implementation takes advantage of the prepend mechanism and combines + * multiple transfers into a single one where possible (single/multiple write + * transfer(s) followed by a final read/write transfer). + * However, it's not possible to buffer reads, which means that read transfers + * should always be done as the final ones. + * On the other hand, take into account that combining write transfers into + * a single one is just buffering and doesn't require prepend mechanism. + */ +static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent); + size_t data_bytes = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) { + /* clear prepends */ + priv->tx_bytes = 0; + + /* initialize hardware */ + writeb_be(0, priv->regs + SPI_IR_MASK_REG); + } + + if (din) { + /* buffering reads not possible since cs is hw controlled */ + if (!(flags & SPI_XFER_END)) { + error("unable to buffer reads\n"); + return -EINVAL; + } + + /* check rx size */ + if (data_bytes > SPI_RX_DATA_SIZE) { + error("max rx bytes exceeded\n"); + return -EMSGSIZE; + } + } + + if (dout) { + /* check tx size */ + if (priv->tx_bytes + data_bytes > SPI_TX_DATA_SIZE) { + error("max tx bytes exceeded\n"); + return -EMSGSIZE; + } + + /* copy tx data */ + memcpy_toio(priv->regs + SPI_TX_DATA_REG + priv->tx_bytes, + dout, data_bytes); + priv->tx_bytes += data_bytes; + } + + if (flags & SPI_XFER_END) { + struct dm_spi_slave_platdata *plat = + dev_get_parent_platdata(dev); + uint16_t val = 0; + uint8_t irq; + + /* determine control config */ + if (dout && !din) { + /* buffered write transfers */ + val |= (priv->tx_bytes << SPI_CTL_BYTES_SHIFT); + val |= SPI_CTL_TYPE_HD_W; + priv->tx_bytes = 0; + } else { + if (dout && din && (flags & SPI_XFER_ONCE)) { + /* full duplex read/write */ + val |= (data_bytes << SPI_CTL_BYTES_SHIFT); + val |= SPI_CTL_TYPE_FD_RW; + priv->tx_bytes = 0; + } else { + /* prepended write transfer */ + val |= (data_bytes << SPI_CTL_BYTES_SHIFT); + val |= SPI_CTL_TYPE_HD_R; + if (priv->tx_bytes > SPI_CMD_PREPEND_BYTES) { + error("max prepend bytes exceeded\n"); + return -EMSGSIZE; + } + } + } + bcm63xx_spi_wctl(val, priv->regs + SPI_CTL_REG); + + /* clear interrupts */ + writeb_be(SPI_IR_CLEAR_MASK, priv->regs + SPI_IR_STAT_REG); + + /* issue the transfer */ + val = SPI_CMD_OP_START; + val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK; + val |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT); + if (plat->mode & SPI_3WIRE) + val |= SPI_CMD_3WIRE_MASK; + writew_be(val, priv->regs + SPI_CMD_REG); + + /* enable interrupts */ + writeb_be(SPI_IR_DONE_MASK, priv->regs + SPI_IR_MASK_REG); + + do { + /* read interupts */ + irq = readb_be(priv->regs + SPI_IR_STAT_REG); + + /* transfer completed */ + if (irq & SPI_IR_DONE_MASK) + break; + } while (1); + + /* copy rx data */ + if (din) + memcpy_fromio(din, priv->regs + SPI_RX_DATA_REG, + data_bytes); + } + + return 0; +} + +static const struct dm_spi_ops bcm63xx_spi_ops = { + .cs_info = bcm63xx_spi_cs_info, + .set_mode = bcm63xx_spi_set_mode, + .set_speed = bcm63xx_spi_set_speed, + .xfer = bcm63xx_spi_xfer, +}; + +static const struct udevice_id bcm63xx_spi_ids[] = { + { .compatible = SPI_DT_ID, }, + { /* sentinel */ } +}; + +static int bcm63xx_spi_child_pre_probe(struct udevice *dev) +{ + struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent); + struct spi_slave *slave = dev_get_parent_priv(dev); + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + + /* check cs */ + if (plat->cs >= priv->num_cs) { + error("no cs %u\n", plat->cs); + return -ENODEV; + } + + /* max read/write sizes */ + slave->max_read_size = SPI_RX_DATA_SIZE; + slave->max_write_size = SPI_TX_DATA_SIZE; + + return 0; +} + +static int bcm63xx_spi_probe(struct udevice *dev) +{ + struct bcm63xx_spi_priv *priv = dev_get_priv(dev); + struct reset_ctl rst_ctl; + struct clk clk; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + addr = devfdt_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "num-cs", 8); + + /* enable clock */ + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + clk_enable(&clk); + clk_free(&clk); + + /* perform reset */ + ret = reset_get_by_index(dev, 0, &rst_ctl); + if (ret < 0) + return ret; + reset_deassert(&rst_ctl); + reset_free(&rst_ctl); + + /* initialize hardware */ + writeb_be(0, priv->regs + SPI_IR_MASK_REG); + + /* set fill register */ + writeb_be(0xff, priv->regs + SPI_FILL_REG); + + return 0; +} + +U_BOOT_DRIVER(bcm63xx_spi) = { + .name = "bcm63xx_spi", + .id = UCLASS_SPI, + .of_match = bcm63xx_spi_ids, + .ops = &bcm63xx_spi_ops, + .priv_auto_alloc_size = sizeof(struct bcm63xx_spi_priv), + .child_pre_probe = bcm63xx_spi_child_pre_probe, + .probe = bcm63xx_spi_probe, +};

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v3: rename BCM6338 SPI driver to BCM6348 v2: add spi alias

arch/mips/dts/brcm,bcm6338.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index eb51a43..0cab44c 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6338";

+ aliases { + spi0 = &spi; + }; + cpus { reg = <0xfffe0000 0x4>; #address-cells = <1>; @@ -109,6 +113,19 @@ status = "disabled"; };

+ spi: spi@fffe0c00 { + compatible = "brcm,bcm6348-spi"; + reg = <0xfffe0c00 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6338_CLK_SPI>; + resets = <&periph_rst BCM6338_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + memory-controller@fffe3100 { compatible = "brcm,bcm6338-mc"; reg = <0xfffe3100 0x38>;

On Sat, Jun 3, 2017 at 3:27 PM, Álvaro Fernández Rojas noltari@gmail.com wrote:

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com

v3: rename BCM6338 SPI driver to BCM6348 v2: add spi alias

arch/mips/dts/brcm,bcm6338.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index eb51a43..0cab44c 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6338";

•   aliases {
  

•           spi0 = &spi;
  

•   };
  

•   cpus {
            reg = <0xfffe0000 0x4>;
            #address-cells = <1>;
  

@@ -109,6 +113,19 @@ status = "disabled"; };

•           spi: spi@fffe0c00 {
  

•                   compatible = "brcm,bcm6348-spi";
  

•                   reg = <0xfffe0c00 0xc0>;
  

•                   #address-cells = <1>;
  

•                   #size-cells = <0>;
  

•                   clocks = <&periph_clk BCM6338_CLK_SPI>;
  

•                   resets = <&periph_rst BCM6338_RST_SPI>;
  

•                   spi-max-frequency = <20000000>;
  

•                   num-cs = <4>;
  

space?

•                   status = "disabled";
  

•           };
  

As per dts(or with new node) additions/update we generally rely with Linux for maximum possible extent So can you try to add this in Linux first so-that we can have proper sync.

thanks!

On Wed, Jun 7, 2017 at 9:08 PM, Álvaro Fernández Rojas noltari@gmail.com wrote:

El 7/6/17 a las 10:00, Jagan Teki escribió:

...

On Sat, Jun 3, 2017 at 3:27 PM, Álvaro Fernández Rojas noltari@gmail.com wrote:

...

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com

v3: rename BCM6338 SPI driver to BCM6348 v2: add spi alias

arch/mips/dts/brcm,bcm6338.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index eb51a43..0cab44c 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6338";

•   aliases {
  

•           spi0 = &spi;
  

•   };
  

•   cpus {
            reg = <0xfffe0000 0x4>;
            #address-cells = <1>;
  

@@ -109,6 +113,19 @@ status = "disabled"; };

•           spi: spi@fffe0c00 {
  

•                   compatible = "brcm,bcm6348-spi";
  

•                   reg = <0xfffe0c00 0xc0>;
  

•                   #address-cells = <1>;
  

•                   #size-cells = <0>;
  

•                   clocks = <&periph_clk BCM6338_CLK_SPI>;
  

•                   resets = <&periph_rst BCM6338_RST_SPI>;
  

•                   spi-max-frequency = <20000000>;
  

•                   num-cs = <4>;
  

space?

I added that space on every disabled node for all the bmips .dtsi files... If you really want it removed I can do that, but it won't be in line with other nodes.

...

...

•                   status = "disabled";
  

•           };
  

As per dts(or with new node) additions/update we generally rely with Linux for maximum possible extent So can you try to add this in Linux first so-that we can have proper sync.

Actually it's already upstream (even though there aren't any users yet): https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindi...

But what about dts file, already in upstream?

thanks!

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v3: rename BCM6338 SPI driver to BCM6348 v2: add spi alias

arch/mips/dts/brcm,bcm6348.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi index 711b643..540b9fe 100644 --- a/arch/mips/dts/brcm,bcm6348.dtsi +++ b/arch/mips/dts/brcm,bcm6348.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6348";

+ aliases { + spi0 = &spi; + }; + cpus { reg = <0xfffe0000 0x4>; #address-cells = <1>; @@ -118,6 +122,19 @@ status = "disabled"; };

+ spi: spi@fffe0c00 { + compatible = "brcm,bcm6348-spi"; + reg = <0xfffe0c00 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6348_CLK_SPI>; + resets = <&periph_rst BCM6348_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + memory-controller@fffe2300 { compatible = "brcm,bcm6338-mc"; reg = <0xfffe2300 0x38>;

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v3: no changes v2: add spi alias

arch/mips/dts/brcm,bcm6358.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 4f63cf8..1662783 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6358";

+ aliases { + spi0 = &spi; + }; + cpus { reg = <0xfffe0000 0x4>; #address-cells = <1>; @@ -142,6 +146,19 @@ status = "disabled"; };

+ spi: spi@fffe0800 { + compatible = "brcm,bcm6358-spi"; + reg = <0xfffe0800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6358_CLK_SPI>; + resets = <&periph_rst BCM6358_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + memory-controller@fffe1200 { compatible = "brcm,bcm6358-mc"; reg = <0xfffe1200 0x4c>;

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v3: no changes v2: add spi alias

arch/mips/dts/brcm,bcm3380.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm3380.dtsi b/arch/mips/dts/brcm,bcm3380.dtsi index 64245eb..f83a6ea 100644 --- a/arch/mips/dts/brcm,bcm3380.dtsi +++ b/arch/mips/dts/brcm,bcm3380.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm3380";

+ aliases { + spi0 = &spi; + }; + cpus { reg = <0x14e00000 0x4>; #address-cells = <1>; @@ -142,6 +146,19 @@ status = "disabled"; };

+ spi: spi@14e02000 { + compatible = "brcm,bcm6358-spi"; + reg = <0x14e02000 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk0 BCM3380_CLK0_SPI>; + resets = <&periph_rst0 BCM3380_RST0_SPI>; + spi-max-frequency = <25000000>; + num-cs = <6>; + + status = "disabled"; + }; + leds: led-controller@14e00f00 { compatible = "brcm,bcm6328-leds"; reg = <0x14e00f00 0x1c>;

This driver manages the low speed SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v3: no changes v2: add spi alias

arch/mips/dts/brcm,bcm63268.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 113a96b..6e3d9c3 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -13,6 +13,10 @@ / { compatible = "brcm,bcm63268";

+ aliases { + spi0 = &lsspi; + }; + cpus { reg = <0x10000000 0x4>; #address-cells = <1>; @@ -136,6 +140,19 @@ #power-domain-cells = <1>; };

+ lsspi: spi@10000800 { + compatible = "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM63268_CLK_SPI>; + resets = <&periph_rst BCM63268_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <8>; + + status = "disabled"; + }; + leds: led-controller@10001900 { compatible = "brcm,bcm6328-leds"; reg = <0x10001900 0x24>;

It's a Winbond (w25x32) 4 MB SPI flash.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v3: rename BCM6338 SPI driver to BCM6348 v2: remove spi alias

arch/mips/dts/sagem,f@st1704.dts | 12 ++++++++++++ configs/sagem_f@st1704_ram_defconfig | 8 ++++++++ 2 files changed, 20 insertions(+)

diff --git a/arch/mips/dts/sagem,f@st1704.dts b/arch/mips/dts/sagem,f@st1704.dts index be15fe5..dd0e5b8 100644 --- a/arch/mips/dts/sagem,f@st1704.dts +++ b/arch/mips/dts/sagem,f@st1704.dts @@ -44,6 +44,18 @@ status = "okay"; };

+&spi { + status = "okay"; + + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + }; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig index 8e89c15..3457116 100644 --- a/configs/sagem_f@st1704_ram_defconfig +++ b/configs/sagem_f@st1704_ram_defconfig @@ -3,6 +3,7 @@ CONFIG_BAUDRATE=115200 CONFIG_BCM6345_CLK=y CONFIG_BCM6345_GPIO=y CONFIG_BCM6345_SERIAL=y +CONFIG_BCM6348_SPI=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_SAGEM_FAST1704=y # CONFIG_CMD_BOOTD is not set @@ -27,6 +28,8 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_SAVEENV is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y # CONFIG_CMD_XIMG is not set CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704" CONFIG_DISPLAY_CPUINFO=y @@ -34,6 +37,8 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DM_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_HUSH_PARSER=y CONFIG_LED=y CONFIG_LED_GPIO=y @@ -45,6 +50,9 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_RESET=y CONFIG_RESET_BCM6345=y CONFIG_SOC_BMIPS_BCM6338=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPL_SERIAL_PRESENT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_NO_FLASH=y

It's a Spansion (s25fl064a) 8 MB SPI flash.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com --- v3: no changes v2: remove spi alias

arch/mips/dts/netgear,cg3100d.dts | 12 ++++++++++++ configs/netgear_cg3100d_ram_defconfig | 8 ++++++++ 2 files changed, 20 insertions(+)

diff --git a/arch/mips/dts/netgear,cg3100d.dts b/arch/mips/dts/netgear,cg3100d.dts index db1e2e7..5f85c73 100644 --- a/arch/mips/dts/netgear,cg3100d.dts +++ b/arch/mips/dts/netgear,cg3100d.dts @@ -90,6 +90,18 @@ status = "okay"; };

+&spi { + status = "okay"; + + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <25000000>; + }; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig index a6eff10..da2426b 100644 --- a/configs/netgear_cg3100d_ram_defconfig +++ b/configs/netgear_cg3100d_ram_defconfig @@ -3,6 +3,7 @@ CONFIG_BAUDRATE=115200 CONFIG_BCM6345_CLK=y CONFIG_BCM6345_GPIO=y CONFIG_BCM6345_SERIAL=y +CONFIG_BCM6358_SPI=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_NETGEAR_CG3100D=y # CONFIG_CMD_BOOTD is not set @@ -27,6 +28,8 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_SAVEENV is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y # CONFIG_CMD_XIMG is not set CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d" CONFIG_DISPLAY_CPUINFO=y @@ -34,6 +37,8 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DM_GPIO=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_HUSH_PARSER=y CONFIG_LED=y CONFIG_LED_BCM6328=y @@ -47,6 +52,9 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_RESET=y CONFIG_RESET_BCM6345=y CONFIG_SOC_BMIPS_BCM3380=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPL_SERIAL_PRESENT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_NO_FLASH=y

Command bytes are part of the written bytes and they should be taken into account when sending a spi transfer.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com --- v4: no changes v3: Fix bug introduced in v2: sizeof(cmd) vs len v2: Introduce changes requested by Simon Glass: - Always include command bytes when determining max write size.

drivers/mtd/spi/spi_flash.c | 2 +- include/spi.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 5ee33d8..1e194ce 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -380,7 +380,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,

if (spi->max_write_size) chunk_len = min(chunk_len, - (size_t)spi->max_write_size); + spi->max_write_size - sizeof(cmd));

spi_flash_addr(write_addr, cmd);

diff --git a/include/spi.h b/include/spi.h index d0fa537..c4e1da6 100644 --- a/include/spi.h +++ b/include/spi.h @@ -89,7 +89,7 @@ struct dm_spi_slave_platdata { * @max_read_size: If non-zero, the maximum number of bytes which can * be read at once. * @max_write_size: If non-zero, the maximum number of bytes which can - * be written at once, excluding command bytes. + * be written at once. * @memory_map: Address of read-only SPI flash access. * @flags: Indication of SPI flags. */

On Wed, Jun 14, 2017 at 3:27 PM, Álvaro Fernández Rojas noltari@gmail.com wrote:

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c Instead of supporting both HW revisions of the controller in a single build, support has been split by the selected config to save space.

Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com

---

v4: Introduce changes suggested by Jagan Teki:

• Add data for each HW controller instead of having two separate configs.
• Also check clock and reset returns as suggested by Simon Glass for HSSPI.

v3: rename BCM6338 SPI driver to BCM6348 switch to devfdt_get_addr_size_index() v2: no changes

drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_spi.c | 419 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 428 insertions(+) create mode 100644 drivers/spi/bcm63xx_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index bef864f..6da78bd 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -40,6 +40,14 @@ config ATMEL_SPI many AT32 (AVR32) and AT91 (ARM) chips. This driver can be used to access the SPI Flash, such as AT25DF321.

+config BCM63XX_SPI

•   bool "BCM6348 SPI driver"
  

•   depends on ARCH_BMIPS
  

•   help
  

•     Enable the BCM6348/BCM6358 SPI driver. This driver can be used to
  

•     access the SPI NOR flash on platforms embedding these Broadcom
  

•     SPI cores.
  

config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c090562..260ba06 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o +obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o

Thanks for doing this change.

obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c new file mode 100644 index 0000000..e1629fa --- /dev/null +++ b/drivers/spi/bcm63xx_spi.c @@ -0,0 +1,419 @@ +/*

• • Copyright (C) 2017 Álvaro Fernández Rojas noltari@gmail.com
• • Derived from linux/drivers/spi/spi-bcm63xx.c:

• • Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
    

• • Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
    

• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <reset.h> +#include <asm/io.h>

+DECLARE_GLOBAL_DATA_PTR;

+/* SPI Clock register */ +#define SPI_CLK_SHIFT 0 +#define SPI_CLK_20MHZ (0 << SPI_CLK_SHIFT) +#define SPI_CLK_0_391MHZ (1 << SPI_CLK_SHIFT) +#define SPI_CLK_0_781MHZ (2 << SPI_CLK_SHIFT) +#define SPI_CLK_1_563MHZ (3 << SPI_CLK_SHIFT) +#define SPI_CLK_3_125MHZ (4 << SPI_CLK_SHIFT) +#define SPI_CLK_6_250MHZ (5 << SPI_CLK_SHIFT) +#define SPI_CLK_12_50MHZ (6 << SPI_CLK_SHIFT) +#define SPI_CLK_25MHZ (7 << SPI_CLK_SHIFT) +#define SPI_CLK_MASK (7 << SPI_CLK_SHIFT) +#define SPI_CLK_SSOFF_SHIFT 3 +#define SPI_CLK_SSOFF_2 (2 << SPI_CLK_SSOFF_SHIFT) +#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT) +#define SPI_CLK_BSWAP_SHIFT 7 +#define SPI_CLK_BSWAP_MASK (1 << SPI_CLK_BSWAP_SHIFT)

+/* SPI Command register */ +#define SPI_CMD_OP_SHIFT 0 +#define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT) +#define SPI_CMD_SLAVE_SHIFT 4 +#define SPI_CMD_SLAVE_MASK (0xf << SPI_CMD_SLAVE_SHIFT) +#define SPI_CMD_PREPEND_SHIFT 8 +#define SPI_CMD_PREPEND_BYTES 0xf +#define SPI_CMD_3WIRE_SHIFT 12 +#define SPI_CMD_3WIRE_MASK (1 << SPI_CMD_3WIRE_SHIFT)

+/* SPI Control register */ +# define SPI_CTL_TYPE_FD_RW 0 +# define SPI_CTL_TYPE_HD_W 1 +# define SPI_CTL_TYPE_HD_R 2

+/* SPI Interrupt registers */ +#define SPI_IR_DONE_SHIFT 0 +#define SPI_IR_DONE_MASK (1 << SPI_IR_DONE_SHIFT) +#define SPI_IR_RXOVER_SHIFT 1 +#define SPI_IR_RXOVER_MASK (1 << SPI_IR_RXOVER_SHIFT) +#define SPI_IR_TXUNDER_SHIFT 2 +#define SPI_IR_TXUNDER_MASK (1 << SPI_IR_TXUNDER_SHIFT) +#define SPI_IR_TXOVER_SHIFT 3 +#define SPI_IR_TXOVER_MASK (1 << SPI_IR_TXOVER_SHIFT) +#define SPI_IR_RXUNDER_SHIFT 4 +#define SPI_IR_RXUNDER_MASK (1 << SPI_IR_RXUNDER_SHIFT) +#define SPI_IR_CLEAR_MASK (SPI_IR_DONE_MASK |\

•                            SPI_IR_RXOVER_MASK |\
  

•                            SPI_IR_TXUNDER_MASK |\
  

•                            SPI_IR_TXOVER_MASK |\
  

•                            SPI_IR_RXUNDER_MASK)
  

+struct bcm63xx_spi_hw {

•   /* SPI Clock register */
  

•   uint16_t clk;
  

•   /* SPI Command register */
  

•   uint16_t cmd;
  

•   /* SPI Control register */
  

•   uint16_t ctl;
  

•   uint8_t ctl_shift;
  

•   /* SPI Fill register */
  

•   uint16_t fill;
  

•   /* SPI Interrupt registers */
  

•   uint16_t ir_stat;
  

•   uint16_t ir_mask;
  

•   /* SPI RX Data registers */
  

•   uint16_t rx;
  

•   uint16_t rx_size;
  

•   /* SPI TX Data registers */
  

•   uint16_t tx;
  

•   uint16_t tx_size;
  

+};

+struct bcm63xx_spi_priv {

•   const struct bcm63xx_spi_hw *hw;
  

•   void __iomem *base;
  

•   size_t tx_bytes;
  

•   uint8_t num_cs;
  

+};

+#define SPI_CLK_CNT 8 +static const unsigned bcm63xx_spi_freq_table[SPI_CLK_CNT][2] = {

•   { 25000000, SPI_CLK_25MHZ },
  

•   { 20000000, SPI_CLK_20MHZ },
  

•   { 12500000, SPI_CLK_12_50MHZ },
  

•   {  6250000, SPI_CLK_6_250MHZ },
  

•   {  3125000, SPI_CLK_3_125MHZ },
  

•   {  1563000, SPI_CLK_1_563MHZ },
  

•   {   781000, SPI_CLK_0_781MHZ },
  

•   {   391000, SPI_CLK_0_391MHZ }
  

+};

+static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,

•                      struct spi_cs_info *info)
  

+{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   if (cs >= priv->num_cs) {
  

•           error("no cs %u\n", cs);
  

•           return -ENODEV;
  

•   }
  

•   return 0;
  

+}

+static int bcm63xx_spi_set_mode(struct udevice *bus, uint mode) +{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   const struct bcm63xx_spi_hw *hw = priv->hw;
  

•   if (mode & SPI_LSB_FIRST)
  

•           setbits_8(priv->base + hw->clk, SPI_CLK_BSWAP_MASK);
  

•   else
  

•           clrbits_8(priv->base + hw->clk, SPI_CLK_BSWAP_MASK);
  

•   return 0;
  

+}

+static int bcm63xx_spi_set_speed(struct udevice *bus, uint speed) +{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(bus);
  

•   const struct bcm63xx_spi_hw *hw = priv->hw;
  

•   uint8_t clk_cfg;
  

•   int i;
  

•   /* default to lowest clock configuration */
  

•   clk_cfg = SPI_CLK_0_391MHZ;
  

•   /* find the closest clock configuration */
  

•   for (i = 0; i < SPI_CLK_CNT; i++) {
  

•           if (speed >= bcm63xx_spi_freq_table[i][0]) {
  

•                   clk_cfg = bcm63xx_spi_freq_table[i][1];
  

•                   break;
  

•           }
  

•   }
  

•   /* write clock configuration */
  

•   clrsetbits_8(priv->base + hw->clk,
  

•                SPI_CLK_SSOFF_MASK | SPI_CLK_MASK,
  

•                clk_cfg | SPI_CLK_SSOFF_2);
  

•   return 0;
  

+}

+/*

• • BCM63xx SPI driver doesn't allow keeping CS active between transfers since
• • they are HW controlled.
• • However, it provides a mechanism to prepend write transfers prior to read
• • transfers (with a maximum prepend of 15 bytes), which is usually enough for
• • SPI-connected flashes since reading requires prepending a write transfer of
• • 5 bytes.
• • This implementation takes advantage of the prepend mechanism and combines
• • multiple transfers into a single one where possible (single/multiple write
• • transfer(s) followed by a final read/write transfer).
• • However, it's not possible to buffer reads, which means that read transfers
• • should always be done as the final ones.
• • On the other hand, take into account that combining write transfers into
• • a single one is just buffering and doesn't require prepend mechanism.
• */

+static int bcm63xx_spi_xfer(struct udevice *dev, unsigned int bitlen,

•           const void *dout, void *din, unsigned long flags)
  

+{

•   struct bcm63xx_spi_priv *priv = dev_get_priv(dev->parent);
  

•   const struct bcm63xx_spi_hw *hw = priv->hw;
  

•   size_t data_bytes = bitlen / 8;
  

•   if (flags & SPI_XFER_BEGIN) {
  

•           /* clear prepends */
  

•           priv->tx_bytes = 0;
  

•           /* initialize hardware */
  

•           writeb_be(0, priv->base + hw->ir_mask);
  

•   }
  

•   if (din) {
  

•           /* buffering reads not possible since cs is hw controlled */
  

•           if (!(flags & SPI_XFER_END)) {
  

•                   error("unable to buffer reads\n");
  

•                   return -EINVAL;
  

•           }
  

•           /* check rx size */
  

•            if (data_bytes > hw->rx_size) {
  

•                   error("max rx bytes exceeded\n");
  

•                   return -EMSGSIZE;
  

•           }
  

•   }
  

•   if (dout) {
  

•           /* check tx size */
  

•           if (priv->tx_bytes + data_bytes > hw->tx_size) {
  

•                   error("max tx bytes exceeded\n");
  

•                   return -EMSGSIZE;
  

•           }
  

•           /* copy tx data */
  

•           memcpy_toio(priv->base + hw->tx + priv->tx_bytes,
  

•                       dout, data_bytes);
  

•           priv->tx_bytes += data_bytes;
  

•   }
  

•   if (flags & SPI_XFER_END) {
  

•           struct dm_spi_slave_platdata *plat =
  

•                   dev_get_parent_platdata(dev);
  

•           uint16_t val;
  

•           uint8_t irq;
  

•           /* determine control config */
  

•           if (dout && !din) {
  

•                   /* buffered write transfers */
  

•                   val = priv->tx_bytes;
  

•                   val |= (SPI_CTL_TYPE_HD_W << hw->ctl_shift);
  

•                   priv->tx_bytes = 0;
  

•           } else {
  

•                   if (dout && din && (flags & SPI_XFER_ONCE)) {
  

•                           /* full duplex read/write */
  

•                           val = data_bytes;
  

•                           val |= (SPI_CTL_TYPE_FD_RW << hw->ctl_shift);
  

•                           priv->tx_bytes = 0;
  

•                   } else {
  

•                           /* prepended write transfer */
  

•                           val = data_bytes;
  

•                           val |= (SPI_CTL_TYPE_HD_R << hw->ctl_shift);
  

•                           if (priv->tx_bytes > SPI_CMD_PREPEND_BYTES) {
  

•                                   error("max prepend bytes exceeded\n");
  

•                                   return -EMSGSIZE;
  

•                           }
  

•                   }
  

•           }
  

•           if (hw->ctl_shift >= 8)
  

•                   writew_be(val, priv->base + hw->ctl);
  

•           else
  

•                   writeb_be(val, priv->base + hw->ctl);
  

•           /* clear interrupts */
  

•           writeb_be(SPI_IR_CLEAR_MASK, priv->base + hw->ir_stat);
  

•           /* issue the transfer */
  

•           val = SPI_CMD_OP_START;
  

•           val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) & SPI_CMD_SLAVE_MASK;
  

•           val |= (priv->tx_bytes << SPI_CMD_PREPEND_SHIFT);
  

•           if (plat->mode & SPI_3WIRE)
  

•                   val |= SPI_CMD_3WIRE_MASK;
  

•           writew_be(val, priv->base + hw->cmd);
  

•           /* enable interrupts */
  

•           writeb_be(SPI_IR_DONE_MASK, priv->base + hw->ir_mask);
  

•           do {
  

•                   /* read interupts */
  

•                   irq = readb_be(priv->base + hw->ir_stat);
  

•                   /* transfer completed */
  

•                   if (irq & SPI_IR_DONE_MASK)
  

•                           break;
  

•           } while (1);
  

•           /* copy rx data */
  

•           if (din)
  

•                   memcpy_fromio(din, priv->base + hw->rx,
  

•                                 data_bytes);
  

•   }
  

•   return 0;
  

+}

+static const struct dm_spi_ops bcm63xx_spi_ops = {

•   .cs_info = bcm63xx_spi_cs_info,
  

•   .set_mode = bcm63xx_spi_set_mode,
  

•   .set_speed = bcm63xx_spi_set_speed,
  

•   .xfer = bcm63xx_spi_xfer,
  

+};

+static const struct bcm63xx_spi_hw bcm63xx_spi_bcm6348 = {

•   .clk = 0x06,
  

•   .cmd = 0x00,
  

•   .ctl = 0x40,
  

•   .ctl_shift = 6,
  

•   .fill = 0x07,
  

•   .ir_stat = 0x02,
  

•   .ir_mask = 0x04,
  

•   .rx = 0x80,
  

•   .rx_size = 0x3f,
  

•   .tx = 0x41,
  

•   .tx_size = 0x3f,
  

+};

Define these hexcodes into macros like SPI_6348_CLK_CFG

+static const struct bcm63xx_spi_hw bcm63xx_spi_bcm6358 = {

•   .clk = 0x706,
  

•   .cmd = 0x700,
  

•   .ctl = 0x000,
  

•   .ctl_shift = 14,
  

•   .fill = 0x707,
  

•   .ir_stat = 0x702,
  

•   .ir_mask = 0x704,
  

•   .rx = 0x400,
  

•   .rx_size = 0x220,
  

•   .tx = 0x002,
  

•   .tx_size = 0x21e,
  

+};

Define these hexcodes into macros like SPI_6358_CLK_CFG

+static const struct udevice_id bcm63xx_spi_ids[] = {

•   {
  

•           .compatible = "brcm,bcm6348-spi",
  

•           .data = (ulong)&bcm63xx_spi_bcm6348,
  

•   }, {
  

•           .compatible = "brcm,bcm6358-spi",
  

•           .data = (ulong)&bcm63xx_spi_bcm6358,
  

•   }, { /* sentinel */ }
  

+};

I think this can even write more like long value instead making it in structure, so-that rotating the 'struct bcm63xx_spi_hw' to respective functions can avoid. like definig members in enum and use these as an offset along with specific reg_space while doing io ops.

thanks!