[U-Boot] [PATCH 1/2] fsl_esdhc: fix wrong clock mask
Fix typo in SYSCTL_CLOCK_MASK, which caused residual in high bits of SDCLKFS.
Signed-off-by: Jin Qing B24347@freescale.com Signed-off-by: Li Yang leoli@freescale.com --- include/fsl_esdhc.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 13ff652..caa784f 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -32,7 +32,7 @@ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 -#define SYSCTL_CLOCK_MASK 0x00000fff +#define SYSCTL_CLOCK_MASK 0x0000fff0 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001
From: Jin Qing b24347@freescale.com
Use timeout value to maximum due to hardware problem. The hardware may take longer to timeout, but it's much better than having a too-short timeout value.
Signed-off-by: Jin Qing b24347@freescale.com Signed-off-by: Li Yang leoli@freescale.com --- drivers/mmc/fsl_esdhc.c | 4 ++++ include/configs/P2020DS.h | 1 + 2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4a86365..d30e15a 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -202,6 +202,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) if (timeout < 0) timeout = 0;
+#ifdef CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT + timeout = 14; +#endif + clrsetbits_be32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
return 0; diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 577d2b5..9bdc9c5 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -714,6 +714,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC #define CONFIG_CMD_EXT2
On Jan 7, 2010, at 2:00 AM, Li Yang wrote:
From: Jin Qing b24347@freescale.com
Use timeout value to maximum due to hardware problem. The hardware may take longer to timeout, but it's much better than having a too-short timeout value.
Signed-off-by: Jin Qing b24347@freescale.com Signed-off-by: Li Yang leoli@freescale.com
drivers/mmc/fsl_esdhc.c | 4 ++++ include/configs/P2020DS.h | 1 + 2 files changed, 5 insertions(+), 0 deletions(-)
Is this associated with an errata on P2020, a board issue?
- k
On Jan 7, 2010, at 2:00 AM, Li Yang wrote:
From: Jin Qing b24347@freescale.com
Use timeout value to maximum due to hardware problem. The hardware may take longer to timeout, but it's much better than having
a too-short timeout value.
Signed-off-by: Jin Qing b24347@freescale.com Signed-off-by: Li Yang leoli@freescale.com
drivers/mmc/fsl_esdhc.c | 4 ++++ include/configs/P2020DS.h | 1 + 2 files changed, 5 insertions(+), 0 deletions(-)
Is this associated with an errata on P2020, a board issue?
I'm not very sure. Looks like a silicon issue. We are using the same workaround as in kernel.
- Leo
On Jan 7, 2010, at 2:00 AM, Li Yang wrote:
Fix typo in SYSCTL_CLOCK_MASK, which caused residual in high bits of SDCLKFS.
Signed-off-by: Jin Qing B24347@freescale.com Signed-off-by: Li Yang leoli@freescale.com
include/fsl_esdhc.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
applied to 85xx.
- k
participants (3)
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Kumar Gala -
Li Yang -
Li Yang-R58472