[U-Boot-Users] 859/866 clock issues
two minor things on the 859/866
1) measure_gclk() is very inaccurate. Better to use the plprcr and CFG_8XX_XIN (which MUST BE 10MHz for that cpu) to derive the "real" bus clock.
2) the 859/866 does NOT support external speeds higher than 66MHz, so if cpu_clk is greater, EBDF01 MUST BE USED IN CFG_SCCR
I have a patch for 1, but i no longer have my 859/866 eval board
I have no patch for 2, but eventually we should come up with some sort of solution; the 859/866 is almost always configured to run faster than 66MHz.
hello,
in message 20031018002619.GB325@zumanetworks.com you wrote:
two minor things on the 859/866
- measure_gclk() is very inaccurate. Better to use the plprcr and
CFG_8XX_XIN (which MUST BE 10MHz for that cpu) to derive the "real" bus clock.
What do you mean by "very inaccurate" - the intention of the function (as documented) is to measure the "Approx. GCLK frequency in Hz". How bad is "very inaccurate" in your case?
- the 859/866 does NOT support external speeds higher than 66MHz,
so if cpu_clk is greater, EBDF01 MUST BE USED IN CFG_SCCR
I think this is the case for ALL MPC8xx processors so far. I have never seen one which would allow a bus clock > 66 MHz.
I have a patch for 1, but i no longer have my 859/866 eval board
Maybe you can share it anyway.
I have no patch for 2, but eventually we should come up with some sort of solution; the 859/866 is almost always configured to run faster than 66MHz.
I don't see why a patch should be needed here. This is a simple matter of getting your board config file right, isn't it?
Best regards,
Wolfgang Denk
On Mon, Oct 20, 2003 at 01:16:17AM +0200, Wolfgang Denk wrote:
hello,
in message 20031018002619.GB325@zumanetworks.com you wrote:
two minor things on the 859/866
- measure_gclk() is very inaccurate. Better to use the plprcr and
CFG_8XX_XIN (which MUST BE 10MHz for that cpu) to derive the "real" bus clock.
What do you mean by "very inaccurate" - the intention of the function (as documented) is to measure the "Approx. GCLK frequency in Hz". How bad is "very inaccurate" in your case?
2-3%
the error of using plprcr + XIN is 0%, and given we know XIN is 10MHz for the 859/866 we are using that now.
- the 859/866 does NOT support external speeds higher than 66MHz,
so if cpu_clk is greater, EBDF01 MUST BE USED IN CFG_SCCR
I think this is the case for ALL MPC8xx processors so far. I have never seen one which would allow a bus clock > 66 MHz.
I have a patch for 1, but i no longer have my 859/866 eval board
Maybe you can share it anyway.
i'll put something together this week, time permitting.
it will be ugly, but you can see what we tried to do.
I have no patch for 2, but eventually we should come up with some sort of solution; the 859/866 is almost always configured to run faster than 66MHz.
I don't see why a patch should be needed here. This is a simple matter of getting your board config file right, isn't it?
yes, but somebody really should add a note to the readme :)
time permitting i will try to.
-nye
Hello,
in message 20031020181719.GA5121@orca.internal.zumanetworks.com you wrote:
- measure_gclk() is very inaccurate. Better to use the plprcr and
CFG_8XX_XIN (which MUST BE 10MHz for that cpu) to derive the "real" bus clock.
What do you mean by "very inaccurate" - the intention of the function (as documented) is to measure the "Approx. GCLK frequency in Hz". How bad is "very inaccurate" in your case?
2-3%
Well, 2...3% means you get 52 instead of 50 MHz? I don't think this is "very inaccurate" - it could be improved by dedicationg more time to the test, but IMHO this is sufficient.
the error of using plprcr + XIN is 0%, and given we know XIN is 10MHz for the 859/866 we are using that now.
But I don't want to make too many assumptions on "known" clock frequencies. I've seen more than one board where the PLL would _not_ lock on the intended clock frequency. It is very nice if you can _see_ that the board is running at 25 MHz even when it's configured for and assumed to be running at 50. This is the whole reason for this test.
Actually, I don't care about a 5% error here. If you do, please disable the function and #define CONFIG_8xx_GCLK_FREQ as you would do on any board without a 32768 Hz oscillator.
- the 859/866 does NOT support external speeds higher than 66MHz,
so if cpu_clk is greater, EBDF01 MUST BE USED IN CFG_SCCR
I think this is the case for ALL MPC8xx processors so far. I have never seen one which would allow a bus clock > 66 MHz.
...
I don't see why a patch should be needed here. This is a simple matter of getting your board config file right, isn't it?
yes, but somebody really should add a note to the readme :)
Ummm... I disagree. It seems obvious to me that you should not run your processor out of specifications, and it is not the purpose of the U-Boot README file to duplicate Motorola's processor specs.
Best regards,
Wolfgang Denk
participants (3)
-
Nye Liu -
nyet＠mrv.com
-
Wolfgang Denk