[PATCH v2 0/4] Add octal DTR support for Macronix flash
This series add support for Macronix octal DTR flash, add second time Softreset with "INVERT" command extension type and follow linux kernel to enable 4byte opcode when possible.
JaimeLiao (4): mtd: spi-nor: macronix: add support for Macronix Octal flash mtd: spi-nor-core: Adding different type of command extension in Soft Reset mtd: spi-nor-core: set 4byte opcode when possible mtd: spi-nor-core: Add support for Macronix Octal flash
drivers/mtd/spi/spi-nor-core.c | 117 +++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi-nor-ids.c | 22 ++++++- include/linux/mtd/spi-nor.h | 13 +++- 3 files changed, 149 insertions(+), 3 deletions(-)
Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding Macronix flash in Octal DTR mode.
Enable Octal DTR mode with 20 dummy cycles to allow running at the maximum supported frequency. -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,...
Signed-off-by: JaimeLiao jaimeliao.tw@gmail.com --- drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 13 +++++- 2 files changed, 94 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index d5d905fa5a..351ca9c3a8 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = { }; #endif /* CONFIG_SPI_FLASH_MT35XU */
+#ifdef CONFIG_SPI_FLASH_MACRONIX +/** + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2. + * @nor: pointer to a 'struct spi_nor' + * + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2. + * Bit 2 of Configuration Register 2 is the DOPI bit for Macronix like OPI memories. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor) +{ + struct spi_mem_op op; + int ret; + u8 buf; + + write_enable(nor); + if (ret) + return ret; + + buf = SPINOR_REG_MXIC_DC_20; + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1), + SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + ret = spi_nor_wait_till_ready(nor); + if (ret) + return ret; + + nor->read_dummy = MXIC_MAX_DC; + write_enable(nor); + if (ret) + return ret; + + buf = SPINOR_REG_MXIC_OPI_DTR_EN; + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1), + SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_err(nor->dev, "Failed to enable octal DTR mode\n"); + return ret; + } + nor->reg_proto = SNOR_PROTO_8_8_8_DTR; + + return 0; +} + +static void macronix_default_init(struct spi_nor *nor) +{ + nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable; +} + +static void macronix_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* + * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when + * SPI_NOR_OCTAL_DTR_READ flag exists. + */ + if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR) + params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; +} + +static struct spi_nor_fixups macronix_fixups = { + .default_init = macronix_default_init, + .post_sfdp = macronix_post_sfdp_fixup, +}; +#endif /* CONFIG_SPI_FLASH_MACRONIX */ + /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed * @nor: pointer to a 'struct spi_nor' * @@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor) if (!strcmp(nor->info->name, "mt35xu512aba")) nor->fixups = &mt35xu512aba_fixups; #endif + +#ifdef CONFIG_SPI_FLASH_MACRONIX + nor->fixups = ¯onix_fixups; +#endif }
int spi_nor_scan(struct spi_nor *nor) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 7ddc4ba2bf..2ad579f66d 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -116,8 +116,17 @@ #define XSR_RDY BIT(7) /* Ready */
/* Used for Macronix and Winbond flashes. */ -#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ -#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ +#define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */ +#define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */ +#define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */ +#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */ +#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */ +#define SPINOR_REG_MXIC_OPI_DTR_DIS 0x1 /* Disable Octal DTR */ +#define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */ +#define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */ +#define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */
/* Used for Spansion flashes only. */ #define SPINOR_OP_BRWR 0x17 /* Bank register write */
Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D in the begging of probe.
Command extension type is not standardized across flash vendors in DTR mode.
For suiting different vendor flash devices, having second times Softreset with different types is clumsy but useful in the begging of probe.
Signed-off-by: JaimeLiao jaimeliao.tw@gmail.com --- drivers/mtd/spi/spi-nor-core.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 351ca9c3a8..707eb9c1d2 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3692,6 +3692,36 @@ static int spi_nor_soft_reset(struct spi_nor *nor) */ udelay(SPI_NOR_SRST_SLEEP_LEN);
+ /* Manufacturers with different command extension type. For suitting + * different flash devices, using command extension type is equal "INVERT" + * when second time Software Reset. + */ + + nor->cmd_ext_type = SPI_NOR_EXT_INVERT; + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DATA); + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_warn(nor->dev, "Software reset enable failed: %d\n", ret); + goto out; + } + + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DATA); + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_warn(nor->dev, "Software reset failed: %d\n", ret); + goto out; + } + + udelay(SPI_NOR_SRST_SLEEP_LEN); + out: nor->cmd_ext_type = ext; return ret;
Hi,
On 20/08/21 02:58PM, JaimeLiao wrote:
Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D in the begging of probe.
Command extension type is not standardized across flash vendors in DTR mode.
For suiting different vendor flash devices, having second times Softreset with different types is clumsy but useful in the begging of probe.
Yes, it is indeed clumsy, and I am not convinced this is the right way to go.
Firstly, you issue the reset twice. This is obviously not ideal and you have to hope the command with incorrect extension is ignored, and not interpreted as something different. But more importantly, you also do the same when called via spi_nor_remove(). At that point you have parsed SFDP and know the flash we are dealing with so you should already know which extension to use.
So here is my suggestion: create a separate function, something like spi_nor_early_soft_reset(). In that function check a config variable to decide which extension to use and temporarily set nor->cmd_ext_type to that. Then in spi_nor_soft_reset() just use nor->cmd_ext_type, no need to hard code the extension. This way you will certainly use the correct extension at remove and will have a more accurate guess at probe time.
I admit this isn't the cleanest solution, but this is the best I can come up with right now.
Signed-off-by: JaimeLiao jaimeliao.tw@gmail.com
drivers/mtd/spi/spi-nor-core.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 351ca9c3a8..707eb9c1d2 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3692,6 +3692,36 @@ static int spi_nor_soft_reset(struct spi_nor *nor) */ udelay(SPI_NOR_SRST_SLEEP_LEN);
- /* Manufacturers with different command extension type. For suitting
* different flash devices, using command extension type is equal "INVERT"* when second time Software Reset.*/- nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
- op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
SPI_MEM_OP_NO_DUMMY,SPI_MEM_OP_NO_ADDR,SPI_MEM_OP_NO_DATA);- spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
- ret = spi_mem_exec_op(nor->spi, &op);
- if (ret) {
dev_warn(nor->dev, "Software reset enable failed: %d\n", ret);goto out;- }
- op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0),
SPI_MEM_OP_NO_DUMMY,SPI_MEM_OP_NO_ADDR,SPI_MEM_OP_NO_DATA);- spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
- ret = spi_mem_exec_op(nor->spi, &op);
- if (ret) {
dev_warn(nor->dev, "Software reset failed: %d\n", ret);goto out;- }
- udelay(SPI_NOR_SRST_SLEEP_LEN);
out: nor->cmd_ext_type = ext; return ret; -- 2.17.1
Hi Pratyush
Thanks for your reply, I want to create "CONFIG_SPI_EXT_INVERT" to separate extension types. Changed as below, do you have any suggestion?
ext = nor->cmd_ext_type; if (!nor->cmd_ext_type) { nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; #ifdef CONFIG_SPI_NOR_EXT_INVERT nor->cmd_ext_type = SPI_NOR_EXT_INVERT; #endif }
Pratyush Yadav p.yadav@ti.com 於 2021年8月30日 週一 下午7:30寫道：
Hi,
On 20/08/21 02:58PM, JaimeLiao wrote:
Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from
8D-8D-8D
in the begging of probe.
Command extension type is not standardized across flash vendors in DTR
mode.
For suiting different vendor flash devices, having second times
Softreset with
different types is clumsy but useful in the begging of probe.
Yes, it is indeed clumsy, and I am not convinced this is the right way to go.
Firstly, you issue the reset twice. This is obviously not ideal and you have to hope the command with incorrect extension is ignored, and not interpreted as something different. But more importantly, you also do the same when called via spi_nor_remove(). At that point you have parsed SFDP and know the flash we are dealing with so you should already know which extension to use.
So here is my suggestion: create a separate function, something like spi_nor_early_soft_reset(). In that function check a config variable to decide which extension to use and temporarily set nor->cmd_ext_type to that. Then in spi_nor_soft_reset() just use nor->cmd_ext_type, no need to hard code the extension. This way you will certainly use the correct extension at remove and will have a more accurate guess at probe time.
I admit this isn't the cleanest solution, but this is the best I can come up with right now.
Signed-off-by: JaimeLiao jaimeliao.tw@gmail.com
drivers/mtd/spi/spi-nor-core.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c
b/drivers/mtd/spi/spi-nor-core.c
index 351ca9c3a8..707eb9c1d2 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3692,6 +3692,36 @@ static int spi_nor_soft_reset(struct spi_nor *nor) */ udelay(SPI_NOR_SRST_SLEEP_LEN);
/* Manufacturers with different command extension type. Forsuitting
* different flash devices, using command extension type is equal"INVERT"
* when second time Software Reset.*/nor->cmd_ext_type = SPI_NOR_EXT_INVERT;op = (structspi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
SPI_MEM_OP_NO_DUMMY,SPI_MEM_OP_NO_ADDR,SPI_MEM_OP_NO_DATA);spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);ret = spi_mem_exec_op(nor->spi, &op);if (ret) {dev_warn(nor->dev, "Software reset enable failed: %d\n",ret);
goto out;}op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST,0),
SPI_MEM_OP_NO_DUMMY,SPI_MEM_OP_NO_ADDR,SPI_MEM_OP_NO_DATA);spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);ret = spi_mem_exec_op(nor->spi, &op);if (ret) {dev_warn(nor->dev, "Software reset failed: %d\n", ret);goto out;}udelay(SPI_NOR_SRST_SLEEP_LEN);out: nor->cmd_ext_type = ext; return ret; -- 2.17.1
-- Regards, Pratyush Yadav Texas Instruments Inc.
Following linux kernel to check address width and 4byte flag to enable 4byte opcode setting.
Signed-off-by: JaimeLiao jaimeliao.tw@gmail.com --- drivers/mtd/spi/spi-nor-core.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 707eb9c1d2..069c6f4630 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3927,6 +3927,10 @@ int spi_nor_scan(struct spi_nor *nor) return -EINVAL; }
+ /* Set 4byte opcodes when possible. */ + if (nor->addr_width == 4 && info->flags & SPI_NOR_4B_OPCODES) + spi_nor_set_4byte_opcodes(nor, info); + /* Send all the required SPI flash commands to initialize device */ ret = spi_nor_init(nor); if (ret)
Adding Macronix Octal flash for Octal DTR support.
The octaflash series can be divided into the following types:
MX25 series : Serial NOR Flash. MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb) LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation. LW/UW series : Support simultaneous Read-while-Write operation in multiple bank architecture. Read-while-write feature which means read data one bank while another bank is programing or erasing.
MX25LM : 3.0V Octal I/O -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,...
MX25UM : 1.8V Octal I/O -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extr...
MX66LM : 3.0V Octal I/O with stacked die -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%...
MX66UM : 1.8V Octal I/O with stacked die -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V...
MX25LW : 3.0V Octal I/O with Read-while-Write MX25UW : 1.8V Octal I/O with Read-while-Write MX66LW : 3.0V Octal I/O with Read-while-Write and stack die MX66UW : 1.8V Octal I/O with Read-while-Write and stack die
About LW/UW series, please contact us freely if you have any questions. For adding Octal NOR Flash IDs, we have validated each Flash on plateform zynq-picozed.
Signed-off-by: JaimeLiao jaimeliao.tw@gmail.com --- drivers/mtd/spi/spi-nor-ids.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index cb3a08872d..5c13ea3a78 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -169,7 +169,27 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, - { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66lm1g45g", 0xc2853b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25lm51245g", 0xc2853a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25lw51245g", 0xc2863a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25lm25645g", 0xc28539, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66um2g45g", 0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66uw2g345g", 0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66um1g45g", 0xc2803b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66uw1g45g", 0xc2813b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25um51245g", 0xc2803a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25uw51245g", 0xc2813a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25uw51345g", 0xc2843a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25um25645g", 0xc28039, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25uw25645g", 0xc28139, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25um25345g", 0xc28339, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25uw25345g", 0xc28439, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25uw12845g", 0xc28138, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25uw12a45g", 0xc28938, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25uw12345g", 0xc28438, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25uw6445g", 0xc28137, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25uw6345g", 0xc28437, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, #endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
participants (3)
-
JaimeLiao -
liao jaime
-
Pratyush Yadav