[U-Boot] [PATCH] arm: mvebu: set 38x and 39x AVS on lower frequency
Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power.
The code is taken from Marvell's U-Boot 2013.01 revision 18.06.
Signed-off-by: Baruch Siach baruch@tkos.co.il --- arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 26 +++++++++++++++++++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 4 +++ arch/arm/mach-mvebu/spl.c | 3 +++ 4 files changed, 36 insertions(+)
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index e6140d67293e..e1128ee90f01 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -163,6 +163,9 @@ int serdes_phy_config(void); */ int ddr3_init(void);
+/* Auto Voltage Scaling */ +void mv_avs_init(void); + /* * get_ref_clk * diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index d387893af37d..e9dd096ad0f5 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -256,3 +256,29 @@ u8 sys_env_device_rev_get(void) value = reg_read(DEV_VERSION_ID_REG); return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS; } + +void mv_avs_init(void) +{ + u32 sar_freq; + + if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X))) + return; + + reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE); + reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE); + + sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); + sar_freq = sar_freq >> SAR_FREQ_OFFSET & SAR_FREQ_MASK; + + /* Set AVS value only for core frequency of 1600MHz or less. + * For higher frequency leave the default value. + */ + if (sar_freq <= 0xd) { + u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL); + + avs_reg_data &= ~(AVS_LOW_VDD_LIMIT_MASK + | AVS_HIGH_VDD_LIMIT_MASK); + avs_reg_data |= AVS_LOW_VDD_SLOW_VAL | AVS_HIGH_VDD_SLOW_VAL; + reg_write(AVS_ENABLED_CONTROL, avs_reg_data); + } +} diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 365332d2b048..1774a5b780ca 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -33,6 +33,8 @@ #define DEV_ID_REG_DEVICE_ID_OFFS 16 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
+#define SAR_FREQ_OFFSET 10 +#define SAR_FREQ_MASK 0x1f #define SAR_DEV_ID_OFFS 27 #define SAR_DEV_ID_MASK 0x7
@@ -155,10 +157,12 @@ #define AVS_LOW_VDD_LIMIT_OFFS 4 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) +#define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS)
#define AVS_HIGH_VDD_LIMIT_OFFS 12 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) +#define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS)
/* Board ID numbers */ #define MARVELL_BOARD_ID_MASK 0x10 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index d54de5195624..3cb27b7f4b20 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -126,6 +126,9 @@ void board_init_f(ulong dummy) ddr3_init(); #endif
+ /* Initialize Auto Voltage Scaling */ + mv_avs_init(); + /* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool.
Hi Baruch,
On Mon, Jun 24, 2019 at 8:30 PM Baruch Siach baruch@tkos.co.il wrote:
Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power.
The code is taken from Marvell's U-Boot 2013.01 revision 18.06.
Signed-off-by: Baruch Siach baruch@tkos.co.il
I gave it a quick spin on DB-88F6820-AMC and x530. Both booted fine.
Reviewed-by: Chris Packham judge.packham@gmail.com Tested-by: Chris Packham judge.packham@gmail.com
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 26 +++++++++++++++++++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 4 +++ arch/arm/mach-mvebu/spl.c | 3 +++ 4 files changed, 36 insertions(+)
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index e6140d67293e..e1128ee90f01 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -163,6 +163,9 @@ int serdes_phy_config(void); */ int ddr3_init(void);
+/* Auto Voltage Scaling */ +void mv_avs_init(void);
/*
- get_ref_clk
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index d387893af37d..e9dd096ad0f5 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -256,3 +256,29 @@ u8 sys_env_device_rev_get(void) value = reg_read(DEV_VERSION_ID_REG); return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS; }
+void mv_avs_init(void) +{
u32 sar_freq;if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))return;reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);sar_freq = sar_freq >> SAR_FREQ_OFFSET & SAR_FREQ_MASK;/* Set AVS value only for core frequency of 1600MHz or less.* For higher frequency leave the default value.*/if (sar_freq <= 0xd) {u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL);avs_reg_data &= ~(AVS_LOW_VDD_LIMIT_MASK| AVS_HIGH_VDD_LIMIT_MASK);avs_reg_data |= AVS_LOW_VDD_SLOW_VAL | AVS_HIGH_VDD_SLOW_VAL;reg_write(AVS_ENABLED_CONTROL, avs_reg_data);}+} diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 365332d2b048..1774a5b780ca 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -33,6 +33,8 @@ #define DEV_ID_REG_DEVICE_ID_OFFS 16 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
+#define SAR_FREQ_OFFSET 10 +#define SAR_FREQ_MASK 0x1f #define SAR_DEV_ID_OFFS 27 #define SAR_DEV_ID_MASK 0x7
@@ -155,10 +157,12 @@ #define AVS_LOW_VDD_LIMIT_OFFS 4 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) +#define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS)
#define AVS_HIGH_VDD_LIMIT_OFFS 12 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) +#define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS)
/* Board ID numbers */ #define MARVELL_BOARD_ID_MASK 0x10 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index d54de5195624..3cb27b7f4b20 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -126,6 +126,9 @@ void board_init_f(ulong dummy) ddr3_init(); #endif
/* Initialize Auto Voltage Scaling */mv_avs_init();/* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool.-- 2.20.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Hi Chris,
On Tue, Jun 25 2019, Chris Packham wrote:
On Mon, Jun 24, 2019 at 8:30 PM Baruch Siach baruch@tkos.co.il wrote:
Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power.
The code is taken from Marvell's U-Boot 2013.01 revision 18.06.
Signed-off-by: Baruch Siach baruch@tkos.co.il
I gave it a quick spin on DB-88F6820-AMC and x530. Both booted fine.
Is there AVS feedback circuit on these boards? If so, have you measured how this patch affects core voltage?
Reviewed-by: Chris Packham judge.packham@gmail.com Tested-by: Chris Packham judge.packham@gmail.com
Thanks, baruch
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 26 +++++++++++++++++++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 4 +++ arch/arm/mach-mvebu/spl.c | 3 +++ 4 files changed, 36 insertions(+)
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index e6140d67293e..e1128ee90f01 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -163,6 +163,9 @@ int serdes_phy_config(void); */ int ddr3_init(void);
+/* Auto Voltage Scaling */ +void mv_avs_init(void);
/*
- get_ref_clk
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index d387893af37d..e9dd096ad0f5 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -256,3 +256,29 @@ u8 sys_env_device_rev_get(void) value = reg_read(DEV_VERSION_ID_REG); return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS; }
+void mv_avs_init(void) +{
u32 sar_freq;if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))return;reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);sar_freq = sar_freq >> SAR_FREQ_OFFSET & SAR_FREQ_MASK;/* Set AVS value only for core frequency of 1600MHz or less.* For higher frequency leave the default value.*/if (sar_freq <= 0xd) {u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL);avs_reg_data &= ~(AVS_LOW_VDD_LIMIT_MASK| AVS_HIGH_VDD_LIMIT_MASK);avs_reg_data |= AVS_LOW_VDD_SLOW_VAL | AVS_HIGH_VDD_SLOW_VAL;reg_write(AVS_ENABLED_CONTROL, avs_reg_data);}+} diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 365332d2b048..1774a5b780ca 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -33,6 +33,8 @@ #define DEV_ID_REG_DEVICE_ID_OFFS 16 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
+#define SAR_FREQ_OFFSET 10 +#define SAR_FREQ_MASK 0x1f #define SAR_DEV_ID_OFFS 27 #define SAR_DEV_ID_MASK 0x7
@@ -155,10 +157,12 @@ #define AVS_LOW_VDD_LIMIT_OFFS 4 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) +#define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS)
#define AVS_HIGH_VDD_LIMIT_OFFS 12 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) +#define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS)
/* Board ID numbers */ #define MARVELL_BOARD_ID_MASK 0x10 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index d54de5195624..3cb27b7f4b20 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -126,6 +126,9 @@ void board_init_f(ulong dummy) ddr3_init(); #endif
/* Initialize Auto Voltage Scaling */mv_avs_init();/* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool.
-- http://baruch.siach.name/blog/ ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
On Tue, Jun 25, 2019 at 5:50 PM Baruch Siach baruch@tkos.co.il wrote:
Hi Chris,
On Tue, Jun 25 2019, Chris Packham wrote:
On Mon, Jun 24, 2019 at 8:30 PM Baruch Siach baruch@tkos.co.il wrote:
Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power.
The code is taken from Marvell's U-Boot 2013.01 revision 18.06.
Signed-off-by: Baruch Siach baruch@tkos.co.il
I gave it a quick spin on DB-88F6820-AMC and x530. Both booted fine.
Is there AVS feedback circuit on these boards? If so, have you measured how this patch affects core voltage?
Both boards have circuitry for AVS_FB although the x530 strapping will probably mean that this code skips it. I'll see if I can measure and difference in behaviour tomorrow.
Reviewed-by: Chris Packham judge.packham@gmail.com Tested-by: Chris Packham judge.packham@gmail.com
Thanks, baruch
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 26 +++++++++++++++++++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 4 +++ arch/arm/mach-mvebu/spl.c | 3 +++ 4 files changed, 36 insertions(+)
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index e6140d67293e..e1128ee90f01 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -163,6 +163,9 @@ int serdes_phy_config(void); */ int ddr3_init(void);
+/* Auto Voltage Scaling */ +void mv_avs_init(void);
/*
- get_ref_clk
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index d387893af37d..e9dd096ad0f5 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -256,3 +256,29 @@ u8 sys_env_device_rev_get(void) value = reg_read(DEV_VERSION_ID_REG); return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS; }
+void mv_avs_init(void) +{
u32 sar_freq;if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))return;reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);sar_freq = sar_freq >> SAR_FREQ_OFFSET & SAR_FREQ_MASK;/* Set AVS value only for core frequency of 1600MHz or less.* For higher frequency leave the default value.*/if (sar_freq <= 0xd) {u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL);avs_reg_data &= ~(AVS_LOW_VDD_LIMIT_MASK| AVS_HIGH_VDD_LIMIT_MASK);avs_reg_data |= AVS_LOW_VDD_SLOW_VAL | AVS_HIGH_VDD_SLOW_VAL;reg_write(AVS_ENABLED_CONTROL, avs_reg_data);}+} diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 365332d2b048..1774a5b780ca 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -33,6 +33,8 @@ #define DEV_ID_REG_DEVICE_ID_OFFS 16 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
+#define SAR_FREQ_OFFSET 10 +#define SAR_FREQ_MASK 0x1f #define SAR_DEV_ID_OFFS 27 #define SAR_DEV_ID_MASK 0x7
@@ -155,10 +157,12 @@ #define AVS_LOW_VDD_LIMIT_OFFS 4 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) +#define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS)
#define AVS_HIGH_VDD_LIMIT_OFFS 12 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) +#define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS)
/* Board ID numbers */ #define MARVELL_BOARD_ID_MASK 0x10 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index d54de5195624..3cb27b7f4b20 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -126,6 +126,9 @@ void board_init_f(ulong dummy) ddr3_init(); #endif
/* Initialize Auto Voltage Scaling */mv_avs_init();/* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool.-- http://baruch.siach.name/blog/ ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
On Tue, Jun 25, 2019 at 7:49 PM Chris Packham judge.packham@gmail.com wrote:
On Tue, Jun 25, 2019 at 5:50 PM Baruch Siach baruch@tkos.co.il wrote:
Hi Chris,
On Tue, Jun 25 2019, Chris Packham wrote:
On Mon, Jun 24, 2019 at 8:30 PM Baruch Siach baruch@tkos.co.il wrote:
Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power.
The code is taken from Marvell's U-Boot 2013.01 revision 18.06.
Signed-off-by: Baruch Siach baruch@tkos.co.il
I gave it a quick spin on DB-88F6820-AMC and x530. Both booted fine.
Is there AVS feedback circuit on these boards? If so, have you measured how this patch affects core voltage?
Both boards have circuitry for AVS_FB although the x530 strapping will probably mean that this code skips it. I'll see if I can measure and difference in behaviour tomorrow.
I did a quick check on the DB-88F6820-AMC board. Before your patch I measured 1.261V on the V_CPU rail. After your patch I measured 1.166V.
Reviewed-by: Chris Packham judge.packham@gmail.com Tested-by: Chris Packham judge.packham@gmail.com
Thanks, baruch
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 26 +++++++++++++++++++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 4 +++ arch/arm/mach-mvebu/spl.c | 3 +++ 4 files changed, 36 insertions(+)
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index e6140d67293e..e1128ee90f01 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -163,6 +163,9 @@ int serdes_phy_config(void); */ int ddr3_init(void);
+/* Auto Voltage Scaling */ +void mv_avs_init(void);
/*
- get_ref_clk
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index d387893af37d..e9dd096ad0f5 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -256,3 +256,29 @@ u8 sys_env_device_rev_get(void) value = reg_read(DEV_VERSION_ID_REG); return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS; }
+void mv_avs_init(void) +{
u32 sar_freq;if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))return;reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);sar_freq = sar_freq >> SAR_FREQ_OFFSET & SAR_FREQ_MASK;/* Set AVS value only for core frequency of 1600MHz or less.* For higher frequency leave the default value.*/if (sar_freq <= 0xd) {u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL);avs_reg_data &= ~(AVS_LOW_VDD_LIMIT_MASK| AVS_HIGH_VDD_LIMIT_MASK);avs_reg_data |= AVS_LOW_VDD_SLOW_VAL | AVS_HIGH_VDD_SLOW_VAL;reg_write(AVS_ENABLED_CONTROL, avs_reg_data);}+} diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 365332d2b048..1774a5b780ca 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -33,6 +33,8 @@ #define DEV_ID_REG_DEVICE_ID_OFFS 16 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
+#define SAR_FREQ_OFFSET 10 +#define SAR_FREQ_MASK 0x1f #define SAR_DEV_ID_OFFS 27 #define SAR_DEV_ID_MASK 0x7
@@ -155,10 +157,12 @@ #define AVS_LOW_VDD_LIMIT_OFFS 4 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) +#define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS)
#define AVS_HIGH_VDD_LIMIT_OFFS 12 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) +#define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS)
/* Board ID numbers */ #define MARVELL_BOARD_ID_MASK 0x10 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index d54de5195624..3cb27b7f4b20 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -126,6 +126,9 @@ void board_init_f(ulong dummy) ddr3_init(); #endif
/* Initialize Auto Voltage Scaling */mv_avs_init();/* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool.-- http://baruch.siach.name/blog/ ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
Hi Baruch,
On 24.06.19 10:29, Baruch Siach wrote:
Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power.
The code is taken from Marvell's U-Boot 2013.01 revision 18.06.
Signed-off-by: Baruch Siach baruch@tkos.co.il
This patch breaks (at least) some Armada XP based boards:
$ ./tools/buildman/buildman theadorable_debug boards.cfg is up to date. Nothing to do. Building current source for 1 boards (1 thread, 16 jobs per thread) arm: + theadorable_debug +arch/arm/mach-mvebu/built-in.o: In function `board_init_f': +arch/arm/mach-mvebu/spl.c:130: undefined reference to `mv_avs_init' +make[2]: *** [scripts/Makefile.spl:404: spl/u-boot-spl] Error 1 +make[1]: *** [Makefile:1727: spl/u-boot-spl] Error 2 +make: *** [Makefile:148: sub-make] Error 2
Could you please check and fix this in v2? Please run a build test at least for all MVEBU boards (buildman mvebu).
Thanks, Stefan
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 26 +++++++++++++++++++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 4 +++ arch/arm/mach-mvebu/spl.c | 3 +++ 4 files changed, 36 insertions(+)
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index e6140d67293e..e1128ee90f01 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -163,6 +163,9 @@ int serdes_phy_config(void); */ int ddr3_init(void);
+/* Auto Voltage Scaling */ +void mv_avs_init(void);
- /*
- get_ref_clk
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index d387893af37d..e9dd096ad0f5 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -256,3 +256,29 @@ u8 sys_env_device_rev_get(void) value = reg_read(DEV_VERSION_ID_REG); return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS; }
+void mv_avs_init(void) +{
- u32 sar_freq;
- if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))
return;- reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);
- reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);
- sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);
- sar_freq = sar_freq >> SAR_FREQ_OFFSET & SAR_FREQ_MASK;
- /* Set AVS value only for core frequency of 1600MHz or less.
* For higher frequency leave the default value.*/- if (sar_freq <= 0xd) {
u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL);avs_reg_data &= ~(AVS_LOW_VDD_LIMIT_MASK| AVS_HIGH_VDD_LIMIT_MASK);avs_reg_data |= AVS_LOW_VDD_SLOW_VAL | AVS_HIGH_VDD_SLOW_VAL;reg_write(AVS_ENABLED_CONTROL, avs_reg_data);- }
+} diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 365332d2b048..1774a5b780ca 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -33,6 +33,8 @@ #define DEV_ID_REG_DEVICE_ID_OFFS 16 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
+#define SAR_FREQ_OFFSET 10 +#define SAR_FREQ_MASK 0x1f #define SAR_DEV_ID_OFFS 27 #define SAR_DEV_ID_MASK 0x7
@@ -155,10 +157,12 @@ #define AVS_LOW_VDD_LIMIT_OFFS 4 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) +#define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS)
#define AVS_HIGH_VDD_LIMIT_OFFS 12 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) +#define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS)
/* Board ID numbers */ #define MARVELL_BOARD_ID_MASK 0x10 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index d54de5195624..3cb27b7f4b20 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -126,6 +126,9 @@ void board_init_f(ulong dummy) ddr3_init(); #endif
- /* Initialize Auto Voltage Scaling */
- mv_avs_init();
- /*
- Return to the BootROM to continue the Marvell xmodem
- UART boot protocol. As initiated by the kwboot tool.
Viele Grüße, Stefan
participants (3)
-
Baruch Siach -
Chris Packham -
Stefan Roese