Hi Simon,

On Fri, Nov 7, 2014 at 4:19 AM, Simon Glass sjg@chromium.org wrote:

Many of the x86 CONFIG options will be common across different boards. Move them to a common file.

Signed-off-by: Simon Glass sjg@chromium.org

include/configs/coreboot.h | 289 ++----------------------------------------- include/configs/x86-common.h | 272 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 285 insertions(+), 276 deletions(-) create mode 100644 include/configs/x86-common.h

diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index fef267f..9ac5306 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -6,7 +6,6 @@

• SPDX-License-Identifier: GPL-2.0+

*/

-#include <asm/ibmpc.h> /*

• board/config.h - configuration options, board specific

*/ @@ -14,27 +13,15 @@ #ifndef __CONFIG_H #define __CONFIG_H

-/*

• • High Level Configuration Options
• • (easy to change)
• */

-#define CONFIG_SYS_COREBOOT -#define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_LAST_STAGE_INIT -#define CONFIG_SYS_VSNPRINTF -#define CONFIG_ZBOOT_32 -#define CONFIG_PHYSMEM -#define CONFIG_SYS_EARLY_PCI_INIT -#define CONFIG_DISPLAY_BOARDINFO_LATE -#define CONFIG_DISPLAY_CPUINFO +#include <configs/x86-common.h>

-#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#define CONFIG_DM_SERIAL +#define CONFIG_SYS_CAR_ADDR 0x19200000 +#define CONFIG_SYS_CAR_SIZE (16 * 1024) +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)

-#define CONFIG_LMB -#define CONFIG_OF_LIBFDT +#define CONFIG_TRACE_EARLY_SIZE (8 << 20) +#define CONFIG_TRACE_EARLY +#define CONFIG_TRACE_EARLY_ADDR 0x01400000

#define CONFIG_BOOTSTAGE #define CONFIG_BOOTSTAGE_REPORT @@ -45,278 +32,28 @@ #define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc #define CONFIG_BOOTSTAGE_USER_COUNT 60

-#define CONFIG_LZO -#define CONFIG_FIT -#undef CONFIG_ZLIB -#undef CONFIG_GZIP -#define CONFIG_SYS_BOOTM_LEN (16 << 20)

-/*-----------------------------------------------------------------------

• • Watchdog Configuration
• */

-#undef CONFIG_WATCHDOG -#undef CONFIG_HW_WATCHDOG

-/* SATA AHCI storage */

-#define CONFIG_SCSI_AHCI

-#ifdef CONFIG_SCSI_AHCI -#define CONFIG_LIBATA -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_SATA_INTEL 1 -#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \

•                   PCI_DEVICE_ID_INTEL_NM10_AHCI},       \
  

•   {PCI_VENDOR_ID_INTEL,           \
  

•                   PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
  

•   {PCI_VENDOR_ID_INTEL, \
  

•                   PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
  

•   {PCI_VENDOR_ID_INTEL,           \
  

•                   PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
  

-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \

•                                    CONFIG_SYS_SCSI_MAX_LUN)
  

-#endif

-/* Generic TPM interfaced through LPC bus */ -#define CONFIG_TPM -#define CONFIG_TPM_TIS_LPC -#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000

-/*-----------------------------------------------------------------------

• • Real Time Clock Configuration
• */

-#define CONFIG_RTC_MC146818 -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS

-/*-----------------------------------------------------------------------

• • Serial Configuration

+/*

• • High Level Configuration Options
• • (easy to change)
  */

-#define CONFIG_COREBOOT_SERIAL -#define CONFIG_SYS_NS16550 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \

•                                    9600, 19200, 38400, 115200}
  

-#define CONFIG_SYS_NS16550_PORT_MAPPED +#define CONFIG_SYS_COREBOOT +#define CONFIG_LAST_STAGE_INIT

#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial,cbmem\0" \ "stderr=vga,serial,cbmem\0"

-#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_STDIO_DEREGISTER #define CONFIG_CBMEM_CONSOLE

-#define CONFIG_CMDLINE_EDITING -#define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER

-#define CONFIG_SUPPORT_VFAT -/************************************************************

• • ATAPI support (experimental)
• ************************************************************/

-#define CONFIG_ATAPI

-/************************************************************

• • DISK Partition support
• ************************************************************/

-#define CONFIG_EFI_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION /* Experimental */

-#define CONFIG_CMD_PART -#define CONFIG_CMD_CBFS -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE -#define CONFIG_PARTITION_UUIDS

-/*-----------------------------------------------------------------------

• • Video Configuration
• */

-#define CONFIG_VIDEO #define CONFIG_VIDEO_COREBOOT -#define CONFIG_VIDEO_SW_CURSOR -#define VIDEO_FB_16BPP_WORD_SWAP -#define CONFIG_I8042_KBD -#define CONFIG_CFB_CONSOLE -#define CONFIG_SYS_CONSOLE_INFO_QUIET

-/* x86 GPIOs are accessed through a PCI device */ -#define CONFIG_INTEL_ICH6_GPIO

-/*-----------------------------------------------------------------------

• • Command line configuration.
• */

-#include <config_cmd_default.h> +#define CONFIG_NR_DRAM_BANKS 4

#define CONFIG_TRACE #define CONFIG_CMD_TRACE #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x01400000

-#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ECHO -#undef CONFIG_CMD_FLASH -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#define CONFIG_CMD_IO -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SETGETDCR -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_TIME -#define CONFIG_CMD_GETTIME -#define CONFIG_CMD_XIMG -#define CONFIG_CMD_SCSI

-#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2

-#define CONFIG_CMD_ZBOOT -#define CONFIG_CMD_ELF

#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS \

•   "root=/dev/sdb3 init=/sbin/init rootwait ro"
  

-#define CONFIG_BOOTCOMMAND \

•   "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
  

-#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 -#endif

-/*

• • Miscellaneous configurable options
• */

-#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \

•                                            sizeof(CONFIG_SYS_PROMPT) + \
  

•                                            16)
  

-#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

-#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x20000000

-/*-----------------------------------------------------------------------

• • SDRAM Configuration
• */

-#define CONFIG_NR_DRAM_BANKS 4

-/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ -#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY -#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T -#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T

-/*-----------------------------------------------------------------------

• • CPU Features
• */

-#define CONFIG_SYS_X86_TSC_TIMER -#define CONFIG_SYS_PCAT_INTERRUPTS -#define CONFIG_SYS_PCAT_TIMER -#define CONFIG_SYS_NUM_IRQS 16

-/*-----------------------------------------------------------------------

• • Memory organization:
• • 32kB Stack
• • 16kB Cache-As-RAM @ 0x19200000
• • 256kB Monitor
• • (128kB + Environment Sector Size) malloc pool
• */

-#define CONFIG_SYS_STACK_SIZE (32 * 1024) -#define CONFIG_SYS_CAR_ADDR 0x19200000 -#define CONFIG_SYS_CAR_SIZE (16 * 1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (0x20000 + 128 * 1024) -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)

-/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE

-/*-----------------------------------------------------------------------

• • FLASH configuration
• */

-#define CONFIG_ICH_SPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SYS_NO_FLASH -#define CONFIG_CMD_SF -#define CONFIG_CMD_SF_TEST -#define CONFIG_CMD_SPI -#define CONFIG_SPI

-/*-----------------------------------------------------------------------

• • Environment configuration
• */

-#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x01000

-/*-----------------------------------------------------------------------

• • PCI configuration
• */

-#define CONFIG_PCI

-#define CONFIG_CROS_EC -#define CONFIG_CROS_EC_LPC -#define CONFIG_CMD_CROS_EC -#define CONFIG_ARCH_EARLY_INIT_R

-/*-----------------------------------------------------------------------

• • USB configuration
• */

-#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_PCI -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_USB_STORAGE -#define CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL

-#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_TFTP_TSIZE -#define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME

-#define CONFIG_CMD_USB

-#define CONFIG_EXTRA_ENV_SETTINGS \

•   CONFIG_STD_DEVICES_SETTINGS
  
  

#endif /* __CONFIG_H */ diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h new file mode 100644 index 0000000..33ff04f --- /dev/null +++ b/include/configs/x86-common.h @@ -0,0 +1,272 @@ +/*

• • Copyright (c) 2011 The Chromium OS Authors.
• • (C) Copyright 2008
• • Graeme Russ, graeme.russ@gmail.com.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <asm/ibmpc.h>

+#ifndef __CONFIG_X86_COMMON_H +#define __CONFIG_X86_COMMON_H

+/*

• • High Level Configuration Options
• • (easy to change)
• */

+#define CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_SYS_VSNPRINTF +#define CONFIG_ZBOOT_32 +#define CONFIG_PHYSMEM +#define CONFIG_SYS_EARLY_PCI_INIT

CONFIG_SYS_EARLY_PCI_INIT is probably chipset specific?

+#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_DISPLAY_CPUINFO

+#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL

One question not related to the patch, is coreboot able to load U-Boot with embedded/separate device tree blob?

+#define CONFIG_LMB +#define CONFIG_OF_LIBFDT

+#define CONFIG_LZO +#define CONFIG_FIT +#undef CONFIG_ZLIB +#undef CONFIG_GZIP +#define CONFIG_SYS_BOOTM_LEN (16 << 20)

+/*-----------------------------------------------------------------------

• • Watchdog Configuration
• */

+#undef CONFIG_WATCHDOG +#undef CONFIG_HW_WATCHDOG

Since these two are undefs, can they be removed?

+/* SATA AHCI storage */

+#define CONFIG_SCSI_AHCI +#define CONFIG_SATA_INTEL +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA +#define CONFIG_SYS_64BIT_LBA +#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \

•                   PCI_DEVICE_ID_INTEL_NM10_AHCI},       \
  

•   {PCI_VENDOR_ID_INTEL,           \
  

•                   PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
  

•   {PCI_VENDOR_ID_INTEL, \
  

•                   PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
  

•   {PCI_VENDOR_ID_INTEL,           \
  

•                   PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
  

CONFIG_SCSI_DEV_LIST is chipset specific, should be put into <board>.h I think.

+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \

•                                    CONFIG_SYS_SCSI_MAX_LUN)
  

+#endif

+/* Generic TPM interfaced through LPC bus */ +#define CONFIG_TPM +#define CONFIG_TPM_TIS_LPC +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000

+/*-----------------------------------------------------------------------

• • Real Time Clock Configuration
• */

+#define CONFIG_RTC_MC146818 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 +#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS

+/*-----------------------------------------------------------------------

• • Serial Configuration
• */

+#define CONFIG_COREBOOT_SERIAL

Coreboot stuff should be board specific.

+#define CONFIG_SYS_NS16550 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \

•                                    9600, 19200, 38400, 115200}
  

+#define CONFIG_SYS_NS16550_PORT_MAPPED

+#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_STDIO_DEREGISTER

+#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER

+#define CONFIG_SUPPORT_VFAT +/************************************************************

• • ATAPI support (experimental)
• ************************************************************/

+#define CONFIG_ATAPI

+/************************************************************

• • DISK Partition support
• ************************************************************/

+#define CONFIG_EFI_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION /* Experimental */

+#define CONFIG_CMD_PART +#define CONFIG_CMD_CBFS +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_PARTITION_UUIDS

+#define CONFIG_SYS_CONSOLE_INFO_QUIET

+/* x86 GPIOs are accessed through a PCI device */ +#define CONFIG_INTEL_ICH6_GPIO

+/*-----------------------------------------------------------------------

• • Command line configuration.
• */

+#include <config_cmd_default.h>

+#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ECHO +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_IO +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ITEST +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SETGETDCR +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_TIME +#define CONFIG_CMD_GETTIME +#define CONFIG_CMD_XIMG +#define CONFIG_CMD_SCSI

+#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2

+#define CONFIG_CMD_ZBOOT +#define CONFIG_CMD_ELF

+#define CONFIG_BOOTARGS \

•   "root=/dev/sdb3 init=/sbin/init rootwait ro"
  

+#define CONFIG_BOOTCOMMAND \

•   "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
  

+#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 +#endif

+/*

• • Miscellaneous configurable options
• */

+#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \

•                                            sizeof(CONFIG_SYS_PROMPT) + \
  

•                                            16)
  

+#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

+#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x01000000 +#define CONFIG_SYS_LOAD_ADDR 0x20000000

+/*-----------------------------------------------------------------------

• • Video Configuration
• */

+#define CONFIG_VIDEO +#define CONFIG_VIDEO_SW_CURSOR +#define VIDEO_FB_16BPP_WORD_SWAP +#define CONFIG_I8042_KBD +#define CONFIG_CFB_CONSOLE

+/*-----------------------------------------------------------------------

• • CPU Features
• */

+#define CONFIG_SYS_X86_TSC_TIMER +#define CONFIG_SYS_PCAT_INTERRUPTS +#define CONFIG_SYS_PCAT_TIMER +#define CONFIG_SYS_NUM_IRQS 16

+#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN 0x200000 +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)

+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE

+/*-----------------------------------------------------------------------

• • FLASH configuration
• */

+#define CONFIG_ICH_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_GIGADEVICE

Should we include all the avaliable SPI flash here?

+#define CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_SF +#define CONFIG_CMD_SF_TEST +#define CONFIG_CMD_SPI +#define CONFIG_SPI

+/*-----------------------------------------------------------------------

• • Environment configuration
• */

+#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x01000

+/*-----------------------------------------------------------------------

• • PCI configuration
• */

+#define CONFIG_PCI

+#define CONFIG_CROS_EC +#define CONFIG_CROS_EC_LPC +#define CONFIG_CMD_CROS_EC

The CROS_XXX should be board specific?

+#define CONFIG_ARCH_EARLY_INIT_R

+/*-----------------------------------------------------------------------

• • USB configuration
• */

+#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_PCI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL

+#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_TFTP_TSIZE +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME

+#define CONFIG_CMD_USB

+#define CONFIG_EXTRA_ENV_SETTINGS \

•   CONFIG_STD_DEVICES_SETTINGS
  

+#endif /* __CONFIG_H */

Regards, Bin

Hi Bin,

On 6 November 2014 17:14, Bin Meng bmeng.cn@gmail.com wrote:

Hi Simon,

On Fri, Nov 7, 2014 at 4:19 AM, Simon Glass sjg@chromium.org wrote:

...

Add some functions to access cpuid from C in various useful ways. Also add a function to get the stack pointer and another to halt the CPU.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/include/asm/processor.h | 121 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index bb3172f..30d7d48 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -30,4 +30,125 @@ enum {

#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)

+#ifndef __ASSEMBLY__

+static inline __attribute__((always_inline)) void cpu_hlt(void) +{

•   asm("hlt");
  

+}

+struct cpuid_result {

•   uint32_t eax;
  

•   uint32_t ebx;
  

•   uint32_t ecx;
  

•   uint32_t edx;
  

+};

+/*

• • Generic CPUID function
• */

+static inline struct cpuid_result cpuid(int op) +{

•   struct cpuid_result result;
  

•   asm volatile(
  

•           "mov %%ebx, %%edi;"
  

•           "cpuid;"
  

•           "mov %%ebx, %%esi;"
  

•           "mov %%edi, %%ebx;"
  

•           : "=a" (result.eax),
  

•             "=S" (result.ebx),
  

•             "=c" (result.ecx),
  

•             "=d" (result.edx)
  

•           : "0" (op)
  

•           : "edi");
  

•   return result;
  

+}

+/*

• • Generic Extended CPUID function
• */

+static inline struct cpuid_result cpuid_ext(int op, unsigned ecx) +{

•   struct cpuid_result result;
  

•   asm volatile(
  

•           "mov %%ebx, %%edi;"
  

•           "cpuid;"
  

•           "mov %%ebx, %%esi;"
  

•           "mov %%edi, %%ebx;"
  

•           : "=a" (result.eax),
  

•             "=S" (result.ebx),
  

•             "=c" (result.ecx),
  

•             "=d" (result.edx)
  

•           : "0" (op), "2" (ecx)
  

•           : "edi");
  

•   return result;
  

+}

+static inline ulong cpu_get_sp(void) +{

•   ulong result;
  

•   asm volatile(
  

•           "mov %%esp, %%eax"
  

•           : "=a" (result));
  

•   return result;
  

+}

+/*

• • CPUID functions returning a single datum
• */

+static inline unsigned int cpuid_eax(unsigned int op) +{

•   unsigned int eax;
  

•   __asm__("mov %%ebx, %%edi;"
  

•           "cpuid;"
  

•           "mov %%edi, %%ebx;"
  

•           : "=a" (eax)
  

•           : "0" (op)
  

•           : "ecx", "edx", "edi");
  

•   return eax;
  

+}

+static inline unsigned int cpuid_ebx(unsigned int op) +{

•   unsigned int eax, ebx;
  

•   __asm__("mov %%ebx, %%edi;"
  

•           "cpuid;"
  

•           "mov %%ebx, %%esi;"
  

•           "mov %%edi, %%ebx;"
  

•           : "=a" (eax), "=S" (ebx)
  

•           : "0" (op)
  

•           : "ecx", "edx", "edi");
  

•   return ebx;
  

+}

+static inline unsigned int cpuid_ecx(unsigned int op) +{

•   unsigned int eax, ecx;
  

•   __asm__("mov %%ebx, %%edi;"
  

•           "cpuid;"
  

•           "mov %%edi, %%ebx;"
  

•           : "=a" (eax), "=c" (ecx)
  

•           : "0" (op)
  

•           : "edx", "edi");
  

•   return ecx;
  

+}

+static inline unsigned int cpuid_edx(unsigned int op) +{

•   unsigned int eax, edx;
  

•   __asm__("mov %%ebx, %%edi;"
  

•           "cpuid;"
  

•           "mov %%edi, %%ebx;"
  

•           : "=a" (eax), "=d" (edx)
  

•           : "0" (op)
  

•           : "ecx", "edi");
  

•   return edx;
  

+} +#endif /* __ASSEMBLY__ */

#endif

My previous patch (http://patchwork.ozlabs.org/patch/406636/) introduced these cpuid_xxx functions already. Would you consider merging the two patches?

Yes I saw your patch, thank you. I will sort it out once I get a chance to test your series. Have been travelling.

Regards, Simon

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

This was missed when the real mode support was dropped. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/config.mk | 1 - 1 file changed, 1 deletion(-)

diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 3e7fedb..bb2da46 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -15,7 +15,6 @@ PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ $(call cc-option, -mpreferred-stack-boundary=2) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm -PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0 PLATFORM_CPPFLAGS += -march=i386 -m32

# Support generic board on x86

Reviewed-by: Bin Meng bmeng.cn@gmail.com

On 6 November 2014 19:57, Bin Meng bmeng.cn@gmail.com wrote:

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

...

This allows a board to do very early init, but no boards need to do this. We may as well drop this feature.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/cpu/start16.S | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 6968fda..e718d4b 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -24,15 +24,7 @@ start16: /* Set the Cold Boot / Hard Reset flag */ movl $GD_FLG_COLD_BOOT, %ebx

•   /*
  

•    * First we let the BSP do some early initialization
  

•    * this code have to map the flash to its final position
  

•    */
  

•   jmp     board_init16
  

-.globl board_init16_ret -board_init16_ret:

•   /* Turn of cache (this might require a 486-class CPU) */
  

•   /* Turn off cache (this might require a 486-class CPU) */
    movl    %cr0, %eax
    orl     $(X86_CR0_NW | X86_CR0_CD), %eax
    movl    %eax, %cr0
  

--

Reviewed-by: Bin Meng bmeng.cn@gmail.com

Applied to u-boot-x86.

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

This allows early board init before board_init_f() is called. We already have a standard U-Boot board call, and no boards use this, so drop it.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/cpu/start.S | 5 ----- board/chromebook-x86/coreboot/Makefile | 2 +- board/chromebook-x86/coreboot/coreboot_start.S | 13 ------------- 3 files changed, 1 insertion(+), 19 deletions(-) delete mode 100644 board/chromebook-x86/coreboot/coreboot_start.S

diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 338bab1..62ac4cd 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -61,11 +61,6 @@ _start: /* Clear the interrupt vectors */ lidt blank_idt_ptr

•   /* Early platform init (setup gpio, etc ) */
  

•   jmp     early_board_init
  

-.globl early_board_init_ret -early_board_init_ret:

•   /* Initialise Cache-As-RAM */
    jmp     car_init
  

.globl car_init_ret diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile index 27ebe78..071bdc4 100644 --- a/board/chromebook-x86/coreboot/Makefile +++ b/board/chromebook-x86/coreboot/Makefile @@ -12,4 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y += coreboot_start.o coreboot.o +obj-y += coreboot.o diff --git a/board/chromebook-x86/coreboot/coreboot_start.S b/board/chromebook-x86/coreboot/coreboot_start.S deleted file mode 100644 index 932fe6c..0000000 --- a/board/chromebook-x86/coreboot/coreboot_start.S +++ /dev/null @@ -1,13 +0,0 @@ -/*

• • Copyright (c) 2011 The Chromium OS Authors.
• • (C) Copyright 2008
• • Graeme Russ, graeme.russ@gmail.com.
• • SPDX-License-Identifier: GPL-2.0+
• */

-/* board early intialization */ -.globl early_board_init -early_board_init:

•   /* No 32-bit board specific initialisation */
  

•   jmp     early_board_init_ret
  

--

Reviewed-by: Bin Meng bmeng.cn@gmail.com

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

We should invalidate the TLB right at the start to ensure that we don't get false address translations even though paging is disabled.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/cpu/start16.S | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index e718d4b..445d5a1 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -24,6 +24,9 @@ start16: /* Set the Cold Boot / Hard Reset flag */ movl $GD_FLG_COLD_BOOT, %ebx

•   xorl    %eax, %eax
  

•   movl    %eax, %cr3    /* Invalidate TLB */
  

•   /* Turn off cache (this might require a 486-class CPU) */
    movl    %cr0, %eax
    orl     $(X86_CR0_NW | X86_CR0_CD), %eax
  

--

Reviewed-by: Bin Meng bmeng.cn@gmail.com

On 7 November 2014 02:37, Bin Meng bmeng.cn@gmail.com wrote:

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

...

This code is a little muddled, so tidy it up. Make sure that we put the GDT in the right place and set it up properly.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/cpu/start.S | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 62ac4cd..c41e1ae 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -69,6 +69,16 @@ car_init_ret: * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, * or fully initialised SDRAM - we really don't care which) * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack

•    * and early malloc area.
  

•    *
  

•    * Stack grows down from top of CAR. We have:
  

•    *
  

•    * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE
  

•    *      global_data
  

•    *      x86 global descriptor table
  

•    *      early malloc area
  

•    *      stack
  

•    * bottom-> CONFIG_SYS_CAR_ADDR
     */
  
    /* Stack grows down from top of CAR */
  

@@ -86,12 +96,16 @@ car_init_ret: movl %esp, %edi rep stosb

•   /* Setup first parameter to setup_gdt */
  

•   /* Setup first parameter to setup_gdt, pointer to global_data */
    movl    %esp, %eax
  
    /* Reserve space for global descriptor table */
    subl    $X86_GDT_SIZE, %esp
  
  

•   /* Align temporary global descriptor table to 16-byte boundary */
  

•   andl    $0xfffffff0, %esp
  

•   movl    %esp, %ecx
  

#if defined(CONFIG_SYS_MALLOC_F_LEN) subl $CONFIG_SYS_MALLOC_F_LEN, %esp movl %eax, %edx @@ -103,14 +117,13 @@ car_init_ret: andl $0xfffffff0, %esp

    /* Set second parameter to setup_gdt */

•   movl    %esp, %edx
  

•   movl    %ecx, %edx
  
    /* Setup global descriptor table so gd->xyz works */
    call    setup_gdt
  
    /* Set parameter to board_init_f() to boot flags */
    xorl    %eax, %eax
  

•   movw    %bx, %ax
  
    /* Enter, U-boot! */
    call    board_init_f
  

--

Reviewed-by: Bin Meng bmeng.cn@gmail.com

Applied to u-boot-x86.

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

Instead of having an x86-specific DRAM init function, adjust things so we can use the normal one.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/cpu/coreboot/sdram.c | 11 ++++------- arch/x86/include/asm/u-boot-x86.h | 4 ++-- common/board_f.c | 6 +----- 3 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index 959feaa..ca651c7 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -11,6 +11,7 @@ #include <asm/e820.h> #include <asm/u-boot-x86.h> #include <asm/global_data.h> +#include <asm/init_helpers.h> #include <asm/processor.h> #include <asm/sections.h> #include <asm/arch/sysinfo.h> @@ -79,7 +80,7 @@ ulong board_get_usable_ram_top(ulong total_size) return (ulong)dest_addr; }

-int dram_init_f(void) +int dram_init(void) { int i; phys_size_t ram_size = 0; @@ -94,7 +95,8 @@ int dram_init_f(void) gd->ram_size = ram_size; if (ram_size == 0) return -1;

•   return 0;
  

•   return calculate_relocation_address();
  

}

int dram_init_banksize(void) @@ -116,8 +118,3 @@ int dram_init_banksize(void) } return 0; }

-int dram_init(void) -{

•   return dram_init_banksize();
  

-} diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 9e525dd..89618c7 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -27,8 +27,8 @@ unsigned long get_tbclk_mhz(void); void timer_set_base(uint64_t base); int pcat_timer_init(void);

-/* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */ -int dram_init_f(void); +/* Architecture specific DRAM init */ +int dram_init(void);

/* cpu/.../interrupts.c */ int cpu_init_interrupts(void); diff --git a/common/board_f.c b/common/board_f.c index 31f1d5c..df02ca5 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -903,13 +903,9 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_HARD_SPI) init_func_spi, #endif -#ifdef CONFIG_X86

•   dram_init_f,            /* configure available RAM banks */
  

•   calculate_relocation_address,
  

-#endif announce_dram_init, /* TODO: unify all these dram functions? */ -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_X86) dram_init, /* configure available RAM banks */ #endif

#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)

Reviewed-by: Bin Meng bmeng.cn@gmail.com

On 7 November 2014 02:49, Bin Meng bmeng.cn@gmail.com wrote:

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

...

Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one for this purpose. Also remove a useless/misleading comment.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/cpu/coreboot/coreboot.c | 5 +---- arch/x86/cpu/cpu.c | 1 - arch/x86/include/asm/u-boot-x86.h | 1 + common/board_f.c | 1 - 4 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index e24f13a..b640f35 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -20,10 +20,7 @@

DECLARE_GLOBAL_DATA_PTR;

-/*

• • Miscellaneous platform dependent initializations
• */

-int cpu_init_f(void) +int arch_cpu_init(void) { int ret = get_coreboot_info(&lib_sysinfo); if (ret != 0) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 2e25253..d6ba246 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -130,7 +130,6 @@ int x86_cpu_init_f(void)

    return 0;

} -int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));

int x86_cpu_init_r(void) { diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 89618c7..fdb8a6c 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -9,6 +9,7 @@ #define _U_BOOT_I386_H_ 1

/* cpu/.../cpu.c */ +int arch_cpu_init(void); int x86_cpu_init_r(void); int cpu_init_r(void); int x86_cpu_init_f(void); diff --git a/common/board_f.c b/common/board_f.c index df02ca5..f81f70d 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -819,7 +819,6 @@ static init_fnc_t init_sequence_f[] = { #endif arch_cpu_init, /* basic arch cpu dependent setup */ #ifdef CONFIG_X86

•   cpu_init_f,             /* TODO(sjg@chromium.org): remove */
  

# ifdef CONFIG_OF_CONTROL find_fdt, /* TODO(sjg@chromium.org): remove */

# endif

Reviewed-by: Bin Meng bmeng.cn@gmail.com

Applied to u-boot-x86.

On 7 November 2014 03:07, Bin Meng bmeng.cn@gmail.com wrote:

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

...

Some functions are missing prototypes. Fix those that are specific to x86.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/cpu/coreboot/coreboot.c | 4 +--- arch/x86/cpu/coreboot/sdram.c | 4 ++-- arch/x86/cpu/cpu.c | 3 +-- arch/x86/cpu/interrupts.c | 2 +- arch/x86/include/asm/u-boot-x86.h | 9 +++++++++ 5 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index b640f35..c430ab1 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -95,7 +95,7 @@ int board_eth_init(bd_t *bis) #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)

-int board_final_cleanup(void) +void board_final_cleanup(void) { /* Un-cache the ROM so the kernel has one * more MTRR available. @@ -117,8 +117,6 @@ int board_final_cleanup(void) /* Issue SMI to Coreboot to lock down ME and registers */ printf("Finalizing Coreboot\n"); outb(0xcb, 0xb2);

•   return 0;
  

}

void panic_puts(const char *str) diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index ca651c7..342ff30 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -14,6 +14,7 @@ #include <asm/init_helpers.h> #include <asm/processor.h> #include <asm/sections.h> +#include <asm/zimage.h> #include <asm/arch/sysinfo.h> #include <asm/arch/tables.h>

@@ -99,7 +100,7 @@ int dram_init(void) return calculate_relocation_address(); }

-int dram_init_banksize(void) +void dram_init_banksize(void) { int i, j;

@@ -116,5 +117,4 @@ int dram_init_banksize(void) } } }

•   return 0;
  

} diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index d6ba246..6441dde 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -197,14 +197,13 @@ asm(".globl generate_gpf\n" "generate_gpf:\n" "ljmp $0x70, $0x47114711\n");

-void __reset_cpu(ulong addr) +__weak void reset_cpu(ulong addr) { printf("Resetting using x86 Triple Fault\n"); set_vector(13, generate_gpf); /* general protection fault handler */ set_vector(8, generate_gpf); /* double fault handler */ generate_gpf(); /* start the show */ } -void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu")));

int dcache_status(void) { diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 6f3d85f..51e2c59 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; "pushl $"#x"\n" \ "jmp irq_common_entry\n"

-void dump_regs(struct irq_regs *regs) +static void dump_regs(struct irq_regs *regs) { unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; unsigned long d0, d1, d2, d3, d6, d7; diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index fdb8a6c..8d5b438 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -37,6 +37,15 @@ int cpu_init_interrupts(void); /* board/.../... */ int dram_init(void);

+int cleanup_before_linux(void); +int x86_cleanup_before_linux(void); +void x86_enable_caches(void); +void x86_disable_caches(void); +int x86_init_cache(void); +void reset_cpu(ulong addr); +ulong board_get_usable_ram_top(ulong total_size); +void dram_init_banksize(void);

void setup_pcat_compatibility(void);

void isa_unmap_rom(u32 addr);

Reviewed-by: Bin Meng bmeng.cn@gmail.com

Applied to u-boot-x86.

Hi Simon,

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector.

This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/Kconfig | 23 +++++ arch/x86/cpu/coreboot/coreboot.c | 8 ++ arch/x86/cpu/cpu.c | 32 ++++-- arch/x86/cpu/ivybridge/Kconfig | 157 +++++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/Makefile | 9 ++ arch/x86/cpu/ivybridge/car.S | 20 ++++ arch/x86/cpu/ivybridge/cpu.c | 41 ++++++++ arch/x86/cpu/ivybridge/sdram.c | 20 ++++ arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/include/asm/arch-ivybridge/gpio.h | 10 ++ arch/x86/include/asm/processor.h | 12 +++ board/google/chromebook_link/Kconfig | 15 +++ board/google/chromebook_link/MAINTAINERS | 6 ++ board/google/chromebook_link/Makefile | 15 +++ board/google/chromebook_link/link.c | 17 ++++ configs/chromebook_link_defconfig | 10 ++ include/configs/chromebook_link.h | 53 ++++++++++ 18 files changed, 443 insertions(+), 7 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/Kconfig create mode 100644 arch/x86/cpu/ivybridge/Makefile create mode 100644 arch/x86/cpu/ivybridge/car.S create mode 100644 arch/x86/cpu/ivybridge/cpu.c create mode 100644 arch/x86/cpu/ivybridge/sdram.c create mode 120000 arch/x86/dts/chromebook_link.dts create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h create mode 100644 board/google/chromebook_link/Kconfig create mode 100644 board/google/chromebook_link/MAINTAINERS create mode 100644 board/google/chromebook_link/Makefile create mode 100644 board/google/chromebook_link/link.c create mode 100644 configs/chromebook_link_defconfig create mode 100644 include/configs/chromebook_link.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0dba8ac..07ff149 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -12,9 +12,32 @@ choice

config TARGET_COREBOOT bool "Support coreboot"

•   help
  

•     This target is used for running U-Boot on top of Coreboot. In
  

•     this case Coreboot does the early inititalisation, and U-Boot
  

•     takes over once the RAM, video and CPU are fully running.
  

•     U-Boot is loaded as a fallback payload from Coreboot, in
  

•     Coreboot terminology. This method was used for the Chromebook
  

•     Pixel when launched.
  

+config TARGET_CHROMEBOOK_LINK

•   bool "Support Chromebook link"
  

•   help
  

•     This is the Chromebook Pixel released in 2013. It uses an Intel
  

•     i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
  

•     SDRAM. It has a Panther Point peripheral controller hub, PCIe
  

Intel official name is 'platform controller hub'.

•     WiFi and Bluetooth. It also includes a 720p webcam, USB SD
  

•     reader, microphone and speakers, display port and 32GB SATA
  

•     solid state drive. There is a Chrome OS EC connected on LPC,
  

•     and it provides a 2560x1700 high resolution touch-enabled LCD
  

•     display.
  
  

endchoice

+source "arch/x86/cpu/ivybridge/Kconfig"

source "board/chromebook-x86/coreboot/Kconfig"

Not related to this patch, but do you consider renaming 'board/chromebook-x86/' to something like 'board/generic-x86/' since this build of U-Boot is supposed to run as a payload from coreboot on every board that coreboot supports in theory.

+source "board/google/chromebook_link/Kconfig"

endmenu diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index c430ab1..257faa1 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -13,6 +13,7 @@ #include <ns16550.h> #include <asm/msr.h> #include <asm/cache.h> +#include <asm/cpu.h> #include <asm/io.h> #include <asm/arch-coreboot/tables.h> #include <asm/arch-coreboot/sysinfo.h> @@ -127,3 +128,10 @@ void panic_puts(const char *str) while (*str) NS16550_putc(port, *str++); }

+int print_cpuinfo(void) +{

•   printf("CPU:   %s\n", cpu_has_64bit() ? "x86_64" : "x86");
  

•   return 0;
  

+} diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 6441dde..61c198e 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -334,13 +334,6 @@ int cpu_has_64bit(void) has_long_mode(); }

-int print_cpuinfo(void) -{

•   printf("CPU:   %s\n", cpu_has_64bit() ? "x86_64" : "x86");
  

•   return 0;
  

-}

#define PAGETABLE_SIZE (6 * 4096)

/** @@ -382,3 +375,28 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target)

    return -EFAULT;

}

+char *cpu_get_name(char *name) +{

•   unsigned int *name_as_ints = (unsigned int *)name;
  

•   struct cpuid_result regs;
  

•   char *ptr;
  

•   int i;
  

•   /* This bit adds up to 48 bytes */
  

•   for (i = 0; i < 3; i++) {
  

•           regs = cpuid(0x80000002 + i);
  

•           name_as_ints[i * 4 + 0] = regs.eax;
  

•           name_as_ints[i * 4 + 1] = regs.ebx;
  

•           name_as_ints[i * 4 + 2] = regs.ecx;
  

•           name_as_ints[i * 4 + 3] = regs.edx;
  

•   }
  

•   name[CPU_MAX_NAME_LEN - 1] = '\0';
  

•   /* Skip leading spaces. */
  

•   ptr = name;
  

•   while (*ptr == ' ')
  

•           ptr++;
  

•   return ptr;
  

+} diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig new file mode 100644 index 0000000..030d813 --- /dev/null +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -0,0 +1,157 @@ +# +# From Coreboot src/northbridge/intel/sandybridge/Kconfig +# +# Copyright (C) 2010 Google Inc. +# +# SPDX-License-Identifier: GPL-2.0

+config NORTHBRIDGE_INTEL_SANDYBRIDGE

•   bool
  

•   select CACHE_MRC_BIN
  

•   select CPU_INTEL_MODEL_206AX
  

+config NORTHBRIDGE_INTEL_IVYBRIDGE

•   bool
  

•   select CACHE_MRC_BIN
  

•   select CPU_INTEL_MODEL_306AX
  

+if NORTHBRIDGE_INTEL_SANDYBRIDGE

+config VGA_BIOS_ID

•   string
  

•   default "8086,0106"
  

+config CACHE_MRC_SIZE_KB

•   int
  

•   default 256
  

+config MRC_CACHE_BASE

•   hex
  

•   default 0xff800000
  

+config MRC_CACHE_LOCATION

•   hex
  

•   depends on !CHROMEOS
  

•   default 0x1ec000
  

+config MRC_CACHE_SIZE

•   hex
  

•   depends on !CHROMEOS
  

•   default 0x10000
  

+config DCACHE_RAM_BASE

•   hex
  

•   default 0xff7f0000
  

+config DCACHE_RAM_SIZE

•   hex
  

•   default 0x10000
  

+endif

+if NORTHBRIDGE_INTEL_IVYBRIDGE

+config VGA_BIOS_ID

•   string
  

•   default "8086,0166"
  

+config EXTERNAL_MRC_BLOB

•   bool
  

•   default n
  

+config CACHE_MRC_SIZE_KB

•   int
  

•   default 512
  

+config MRC_CACHE_BASE

•   hex
  

•   default 0xff800000
  

+config MRC_CACHE_LOCATION

•   hex
  

•   depends on !CHROMEOS
  

•   default 0x370000
  

+config MRC_CACHE_SIZE

•   hex
  

•   depends on !CHROMEOS
  

•   default 0x10000
  

+config DCACHE_RAM_BASE

•   hex
  

•   default 0xff7e0000
  

+config DCACHE_RAM_SIZE

•   hex
  

•   default 0x20000
  

+endif

+if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE

+config HAVE_MRC

•    bool "Add a System Agent binary"
  

•    help
  

•      Select this option to add a System Agent binary to
  

•      the resulting U-Boot image. MRC stands for Memory Reference Code.
  

•      It is a binary blob which U-Boot uses to set up SDRAM.
  

•      Note: Without this binary U-Boot will not be able to set up its
  

•      SDRAM so will not boot.
  

+config DCACHE_RAM_MRC_VAR_SIZE

•   hex
  

•   default 0x4000
  

•   help
  

•     This is the amount of CAR (Cache as RAM) reserved for use by the
  

•     memory reference code. This should be set to 16KB (0x4000 hex)
  

•     so that MRC has enough space to run.
  

+config MRC_FILE

•   string "Intel System Agent path and filename"
  

•   depends on HAVE_MRC
  

•   default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE
  

•   default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE
  

•   help
  

•     The path and filename of the file to use as System Agent
  

•     binary.
  

+config CPU_SPECIFIC_OPTIONS

•   def_bool y
  

•   select SMM_TSEG
  

•   select ARCH_BOOTBLOCK_X86_32
  

•   select ARCH_ROMSTAGE_X86_32
  

•   select ARCH_RAMSTAGE_X86_32
  

•   select SMP
  

•   select SSE2
  

•   select UDELAY_LAPIC
  

•   select CPU_MICROCODE_IN_CBFS
  

•   select TSC_SYNC_MFENCE
  

+config SMM_TSEG_SIZE

•   hex
  

•   default 0x800000
  

+config ENABLE_VMX

•   bool "Enable VMX for virtualization"
  

•   default n
  

+endif

+config CPU_INTEL_SOCKET_RPGA989

•   bool
  

+if CPU_INTEL_SOCKET_RPGA989

+config SOCKET_SPECIFIC_OPTIONS # dummy

•   def_bool y
  

•   select MMX
  

•   select SSE
  

•   select CACHE_AS_RAM
  

+config CACHE_MRC_BIN

•   bool
  

•   default n
  

+endif diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile new file mode 100644 index 0000000..dbcd4bd --- /dev/null +++ b/arch/x86/cpu/ivybridge/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y += car.o +obj-y += cpu.o +obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S new file mode 100644 index 0000000..0480813 --- /dev/null +++ b/arch/x86/cpu/ivybridge/car.S @@ -0,0 +1,20 @@ +/*

• • Copyright (c) 2014 Google, Inc
• • From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
• • Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com
• • Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
• • Copyright (C) 2007-2008 coresystems GmbH
• • Copyright (C) 2012 Kyösti Mälkki kyosti.malkki@gmail.com
• • SPDX-License-Identifier: GPL-2.0
• */

+#include <common.h>

•   /* Note: ebp must not be touched in this code */
  

+.globl car_init +car_init:

•   /* TODO: Add cache-as-RAM init here */
  

•   jmp     car_init_ret
  

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c new file mode 100644 index 0000000..7e77be6 --- /dev/null +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -0,0 +1,41 @@ +/*

• • Copyright (c) 2014 Google, Inc
• • (C) Copyright 2008
• • Graeme Russ, graeme.russ@gmail.com.
• • Some portions from coreboot src/mainboard/google/link/romstage.c
• • Copyright (C) 2007-2010 coresystems GmbH
• • Copyright (C) 2011 Google Inc.
• • SPDX-License-Identifier: GPL-2.0
• */

+#include <common.h> +#include <asm/processor.h>

+DECLARE_GLOBAL_DATA_PTR;

+int arch_cpu_init(void) +{

•   int ret;
  

•   timer_set_base(rdtsc());
  

•   ret = x86_cpu_init_f();
  

•   if (ret)
  

•           return ret;
  

•   return 0;
  

+}

+int print_cpuinfo(void) +{

•   char processor_name[CPU_MAX_NAME_LEN];
  

•   const char *name;
  

•   /* Print processor name */
  

•   name = cpu_get_name(processor_name);
  

•   printf("CPU:   %s\n", name);
  

•   return 0;
  

+} diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c new file mode 100644 index 0000000..5f9ae5e --- /dev/null +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -0,0 +1,20 @@ +/*

• • Copyright (c) 2011 The Chromium OS Authors.
• • (C) Copyright 2010,2011
• • Graeme Russ, graeme.russ@gmail.com
• • Portions from Coreboot mainboard/google/link/romstage.c
• • Copyright (C) 2007-2010 coresystems GmbH
• • Copyright (C) 2011 Google Inc.
• • SPDX-License-Identifier: GPL-2.0
• */

+#include <common.h>

+int dram_init(void) +{

•   /* TODO: Set up DRAM */
  

•   return 0;
  

+} diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 48265ef..bb3b116 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,4 +1,5 @@ dtb-y += link.dtb \

•   chromebook_link.dtb \
    alex.dtb
  
  

targets += $(dtb-y) diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts new file mode 120000 index 0000000..6f8c5cd --- /dev/null +++ b/arch/x86/dts/chromebook_link.dts @@ -0,0 +1 @@ +link.dts \ No newline at end of file diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h new file mode 100644 index 0000000..4951a8c --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/gpio.h @@ -0,0 +1,10 @@ +/*

• • Copyright (c) 2014, Google Inc.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_

+#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 30d7d48..2c33723 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -149,6 +149,18 @@ static inline unsigned int cpuid_edx(unsigned int op) : "ecx", "edi"); return edx; }

+#define CPU_MAX_NAME_LEN 49

+/**

• • cpu_get_name() - Get the name of the current cpu
• • @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including
• • @return pointer to name, which will likely be a few bytes after the start
• • of @name
• • \0 terminator
• */

+char *cpu_get_name(char *name); #endif /* __ASSEMBLY__ */

#endif diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig new file mode 100644 index 0000000..975d557 --- /dev/null +++ b/board/google/chromebook_link/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CHROMEBOOK_LINK

+config SYS_BOARD

•   default "chromebook_link"
  

+config SYS_VENDOR

•   default "google"
  

+config SYS_SOC

•   default "ivybridge"
  

+config SYS_CONFIG_NAME

•   default "chromebook_link"
  

+endif diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS new file mode 100644 index 0000000..bc253a2 --- /dev/null +++ b/board/google/chromebook_link/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK LINK BOARD +M: Simon Glass sjg@chromium.org +S: Maintained +F: board/google/chromebook_link/ +F: include/configs/chromebook_link.h +F: configs/chromebook_link_defconfig diff --git a/board/google/chromebook_link/Makefile b/board/google/chromebook_link/Makefile new file mode 100644 index 0000000..a133c2e --- /dev/null +++ b/board/google/chromebook_link/Makefile @@ -0,0 +1,15 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y += link.o diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c new file mode 100644 index 0000000..ffa9d60 --- /dev/null +++ b/board/google/chromebook_link/link.c @@ -0,0 +1,17 @@ +/*

• • Copyright (C) 2014 Google, Inc
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h>

+int arch_early_init_r(void) +{

•   return 0;
  

+}

+int board_early_init_r(void) +{

•   return 0;
  

+} diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig new file mode 100644 index 0000000..b83803e --- /dev/null +++ b/configs/chromebook_link_defconfig @@ -0,0 +1,10 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_CHROMEBOOK_LINK=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" +CONFIG_HAVE_MRC=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h new file mode 100644 index 0000000..1d6f55b --- /dev/null +++ b/include/configs/chromebook_link.h @@ -0,0 +1,53 @@ +/*

• • Copyright (c) 2011 The Chromium OS Authors.
• • (C) Copyright 2008
• • Graeme Russ, graeme.russ@gmail.com.
• • SPDX-License-Identifier: GPL-2.0+
• */

+/*

• • board/config.h - configuration options, board specific
• */

+#ifndef __CONFIG_H +#define __CONFIG_H

+#include <configs/x86-common.h>

+#define CONFIG_SYS_CAR_ADDR 0xff7e0000 +#define CONFIG_SYS_CAR_SIZE (128 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_R

+#define CONFIG_NR_DRAM_BANKS 8

+/*

• • These common x86 features are not yet supported, but are added in
• • follow-on patches in this series. Add undefs here to avoid every patch
• • having to put things back into x86-common.h
• */

+#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_DM_GPIO +#undef CONFIG_CMD_GPIO +#undef CONFIG_CROS_EC +#undef CONFIG_CROS_EC_LPC +#undef CONFIG_CMD_CROS_EC +#undef CONFIG_ARCH_EARLY_INIT_R +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE +#undef CONFIG_SYS_EARLY_PCI_INIT +#undef CONFIG_PCI +#undef CONFIG_ICH_SPI +#undef CONFIG_SPI +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_SF +#undef CONFIG_USB_EHCI +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_SCSI

+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \

•                                   "stdout=vga,serial\0" \
  

•                                   "stderr=vga,serial\0"
  

+#endif /* __CONFIG_H */

Regards, Bin

On 7 November 2014 03:21, Bin Meng bmeng.cn@gmail.com wrote:

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

...

The built in self test value is available in register eax on start-up. Save it so that it can be accessed later. Unfortunately we must wait until the global_data is available before we can do this, so there is a little bit of shuffling to keep it around.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/cpu/start.S | 9 ++++++--- arch/x86/cpu/start16.S | 7 ++++++- arch/x86/include/asm/global_data.h | 1 + lib/asm-offsets.c | 3 +++ 4 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index c41e1ae..7f41475 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -49,6 +49,8 @@ _start: */ movw $GD_FLG_COLD_BOOT, %bx 1:

•   /* Save BIST */
  

•   movl    %eax, %ebp
  
    /* Load the segement registes to match the gdt loaded in start16.S */
    movl    $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
  

@@ -112,9 +114,10 @@ car_init_ret: addl $GD_MALLOC_BASE, %edx movl %esp, (%edx) #endif

•   /* Align temporary global descriptor table to 16-byte boundary */
  

•   andl    $0xfffffff0, %esp
  

•   /* Store BIST */
  

•   movl    %eax, %edx
  

•   addl    $GD_BIST, %edx
  

•   movl    %ebp, (%edx)
  
    /* Set second parameter to setup_gdt */
    movl    %ecx, %edx
  

diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 445d5a1..9550502 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -21,6 +21,9 @@ .code16 .globl start16 start16:

•   /* Save BIST */
  

•   movl    %eax, %ecx
  

•   /* Set the Cold Boot / Hard Reset flag */
    movl    $GD_FLG_COLD_BOOT, %ebx
  
  

@@ -45,9 +48,11 @@ o32 cs lgdt gdt_ptr /* Flush the prefetch queue */ jmp ff ff:

•   /* Finally jump to the 32bit initialization code */
  

•   /* Finally restore BIST and jump to the 32bit initialization code */
    movw    $code32start, %ax
    movw    %ax, %bp
  

•   movl    %ecx, %eax
  

o32 cs ljmp *(%bp)

    /* 48-bit far pointer */

diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 3e8e2cd..9eae228 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -17,6 +17,7 @@ struct arch_global_data { uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */ uint32_t tsc_prev; /* For show_boot_progress() */ void *new_fdt; /* Relocated FDT */

•   uint32_t bist;                  /* Built-in self test value */
  

};

#endif diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c index 129bc3e..580f763 100644 --- a/lib/asm-offsets.c +++ b/lib/asm-offsets.c @@ -31,6 +31,9 @@ int main(void) #ifdef CONFIG_SYS_MALLOC_F_LEN DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base)); #endif +#ifdef CONFIG_X86

•   DEFINE(GD_BIST, offsetof(struct global_data, arch.bist));
  

+#endif

#if defined(CONFIG_ARM)

--

Reviewed-by: Bin Meng bmeng.cn@gmail.com

Applied to u-boot-x86.

Hi Simon,

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

On x86 machines U-Boot needs to be added to a large ROM image which is then flashed onto the target board. The ROM has a particular format so it makes sense for U-Boot to build this image automatically. Unfortunately it relies on binary blobs so we cannot require this for the default build as yet.

Create a u-boot.rom output file for this purpose.

Signed-off-by: Simon Glass sjg@chromium.org

Makefile | 27 ++++++++++++++++++++++++++- arch/x86/Kconfig | 4 ++++ include/configs/chromebook_link.h | 2 ++ 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile index 9c8a580..86d0510 100644 --- a/Makefile +++ b/Makefile @@ -743,6 +743,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf

+# We can't do this yet due to the need for binary blobs +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom

# enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) ifeq ($(CONFIG_SPL),y) @@ -804,7 +807,8 @@ OBJCOPYFLAGS_u-boot.srec := -O srec u-boot.hex u-boot.srec: u-boot FORCE $(call if_changed,objcopy)

-OBJCOPYFLAGS_u-boot.bin := -O binary +OBJCOPYFLAGS_u-boot.bin := -O binary \

•           $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
  
  

binary_size_check: u-boot.bin FORCE @file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \ @@ -943,6 +947,27 @@ u-boot-nand.gph: u-boot.bin FORCE $(call if_changed,mkimage) @dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@

+# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including +# reset vector) at the top, Intel ME at the bottom, and U-Boot in the middle. +ifneq ($(CONFIG_X86_RESET_VECTOR),) +rom: u-boot.rom FORCE

+u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \

The u-boot-dtb.bin means we have to use device tree for all x86 board port. Is this a must-have?

•           $(srctree)/board/$(BOARDDIR)/descriptor.bin
  

I don't see where the descriptor.bin is created?

•   $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \
  

•           -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp
  

•   $(objtree)/tools/ifdtool -w \
  

•           $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp
  

•   $(objtree)/tools/ifdtool -w \
  

•           $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
  

•           u-boot.tmp
  

•   mv u-boot.tmp $@
  

+OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec +u-boot-x86-16bit.bin: u-boot FORCE

•   $(call if_changed,objcopy)
  

+endif

[snip]

Regards, Bin

Hi Bin,

On 7 November 2014 06:37, Bin Meng bmeng.cn@gmail.com wrote:

Hi Simon,

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

...

On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died.

On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/cpu/coreboot/coreboot.c | 3 ++- arch/x86/cpu/start.S | 25 +++++++++++++++++++++++++ arch/x86/include/asm/post.h | 32 ++++++++++++++++++++++++++++++++ board/google/chromebook_link/Kconfig | 4 ++++ 4 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/asm/post.h

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 257faa1..cc7398f 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -15,6 +15,7 @@ #include <asm/cache.h> #include <asm/cpu.h> #include <asm/io.h> +#include <asm/post.h> #include <asm/arch-coreboot/tables.h> #include <asm/arch-coreboot/sysinfo.h> #include <asm/arch/timestamp.h> @@ -68,7 +69,7 @@ void show_boot_progress(int val) gd->arch.tsc_prev = now; } #endif

•   outb(val, 0x80);
  

•   outb(val, POST_PORT);
  

}

int last_stage_init(void) diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 7f41475..f62ffeb 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -13,6 +13,7 @@ #include <config.h> #include <version.h> #include <asm/global_data.h> +#include <asm/post.h> #include <asm/processor.h> #include <asm/processor-flags.h> #include <generated/generic-asm-offsets.h> @@ -60,6 +61,28 @@ _start: movw %ax, %es movw %ax, %ss

•   /* Enable post codes to EC */
  

+#ifdef CONFIG_EARLY_POST_CROS_EC

•   mov    $0x1b, %ecx
  

•   rdmsr
  

•   and    $0x100, %eax
  

•   test   %eax, %eax
  

•   je     2f
  

•   mov    $0x8000f8f0, %eax
  

•   mov    $0xcf8, %dx
  

•   out    %eax, (%dx)
  

•   mov    $0xfed1c001, %eax
  

•   mov    $0xcfc, %dx
  

•   out    %eax, (%dx)
  

•   mov    $0xfed1f410, %esp
  

•   mov    (%esp), %eax
  

•   and    $0xfffffffb, %eax
  

•   mov    %eax, (%esp)
  

+2: +#endif

IMHO the early_board_init() removal should be rolled back, and the enable post codes is better to put there.

Yes I was thinking about that, I'll make that change.

...

•   post_code(POST_START)
  

•   /* Clear the interrupt vectors */
    lidt    blank_idt_ptr
  
  

@@ -91,6 +114,7 @@ car_init_ret:

    /* Align global data to 16-byte boundary */
    andl    $0xfffffff0, %esp

•   post_code(POST_START_STACK)
  
    /* Zero the global data since it won't happen later */
    xorl    %eax, %eax
  

@@ -126,6 +150,7 @@ car_init_ret: call setup_gdt

    /* Set parameter to board_init_f() to boot flags */

•   post_code(POST_START_DONE)
    xorl    %eax, %eax
  
    /* Enter, U-boot! */
  

diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h new file mode 100644 index 0000000..3371185 --- /dev/null +++ b/arch/x86/include/asm/post.h @@ -0,0 +1,32 @@ +/*

• • Copyright (c) 2014 Google, Inc
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef _post_h +#define _post_h

+/* port to use for post codes */ +#define POST_PORT 0x80

+/* post codes which represent various stages of init */ +#define POST_START 0x1e +#define POST_CAR_START 0x1f

+#define POST_START_STACK 0x29 +#define POST_START_DONE 0x2a

Do we follow some specification about post codes values, or are them just some random numbers?

Just random - they're all in one place so we can change them pretty easily.

...

+/* Output a post code using al - value must be 0 to 0xff */ +#ifdef __ASSEMBLY__ +#define post_code(value) \

•   movb    $value, %al; \
  

•   outb    %al, $POST_PORT
  

+#else +static inline void post_code(int code) +{

•   outb(code, POST_PORT);
  

+} +#endif

+#endif diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 975d557..9c715ba 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -12,4 +12,8 @@ config SYS_SOC config SYS_CONFIG_NAME default "chromebook_link"

+config EARLY_POST_CROS_EC

•   bool "Enable early post to Chrome OS EC"
  

•   default y
  

endif

Regards, Bin

Regards, Simon

Hi Simon,

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code.

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/Kconfig | 16 ++++ arch/x86/cpu/ivybridge/car.S | 156 ++++++++++++++++++++++++++++++++++- arch/x86/cpu/ivybridge/cpu.c | 2 + arch/x86/include/asm/mtrr.h | 121 +++++++++++++++++++++++++++ arch/x86/include/asm/post.h | 13 ++- board/google/chromebook_link/Kconfig | 12 +++ 6 files changed, 318 insertions(+), 2 deletions(-) create mode 100644 arch/x86/include/asm/mtrr.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d9ce129..73fe8b2 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -34,6 +34,22 @@ config TARGET_CHROMEBOOK_LINK

endchoice

+config RAMBASE

•   hex
  

•   default 0x100000
  

+config RAMTOP

•   hex
  

•   default 0x200000
  

+config XIP_ROM_SIZE

•   hex
  

•   default 0x10000
  

+config CPU_ADDR_BITS

•   int
  

•   default 36
  

config ROM_SIZE hex default 0x800000 diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S index 0480813..391f6df 100644 --- a/arch/x86/cpu/ivybridge/car.S +++ b/arch/x86/cpu/ivybridge/car.S @@ -12,9 +12,163 @@ */

#include <common.h> +#include <asm/mtrr.h> +#include <asm/post.h> +#include <asm/processor-flags.h>

+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)

Should these macros be all capital?

+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

+/* Cache 4GB - MRC_SIZE_KB for MRC */ +#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) +#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)

+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)

+#define NoEvictMod_MSR 0x2e0

Ditto.

    /* Note: ebp must not be touched in this code */

I think mentioning ebp holds the value of BIST would help more?

.globl car_init car_init:

•   /* TODO: Add cache-as-RAM init here */
  

•   post_code(POST_CAR_START)
  

•   /* Send INIT IPI to all excluding ourself */
  

•   movl    $0x000C4500, %eax
  

•   movl    $0xFEE00300, %esi
  

•   movl    %eax, (%esi)
  

•   /* All CPUs need to be in Wait for SIPI state */
  

+wait_for_sipi:

•   movl    (%esi), %eax
  

•   bt      $12, %eax
  

•   jc      wait_for_sipi
  

Is this a must to send INIT IPI before CAR initialization?

•   post_code(POST_CAR_SIPI)
  

•   /* Zero out all fixed range and variable range MTRRs */
  

•   movl    $mtrr_table, %esi
  

•   movl    $((mtrr_table_end - mtrr_table) / 2), %edi
  

•   xorl    %eax, %eax
  

•   xorl    %edx, %edx
  

+clear_mtrrs:

•   movw    (%esi), %bx
  

•   movzx   %bx, %ecx
  

•   wrmsr
  

•   add     $2, %esi
  

•   dec     %edi
  

•   jnz     clear_mtrrs
  

•   post_code(POST_CAR_MTRR)
  

•   /* Configure the default memory type to uncacheable */
  

•   movl    $MTRRdefType_MSR, %ecx
  

•   rdmsr
  

•   andl    $(~0x00000cff), %eax
  

•   wrmsr
  

•   post_code(POST_CAR_UNCACHEABLE)
  

•   /* Set Cache-as-RAM base address */
  

•   movl    $(MTRRphysBase_MSR(0)), %ecx
  

•   movl    $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
  

•   xorl    %edx, %edx
  

•   wrmsr
  

•   post_code(POST_CAR_BASE_ADDRESS)
  

•   /* Set Cache-as-RAM mask */
  

•   movl    $(MTRRphysMask_MSR(0)), %ecx
  

•   movl    $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
  

•   movl    $CPU_PHYSMASK_HI, %edx
  

•   wrmsr
  

•   post_code(POST_CAR_MASK)
  

•   /* Enable MTRR */
  

•   movl    $MTRRdefType_MSR, %ecx
  

•   rdmsr
  

•   orl     $MTRRdefTypeEn, %eax
  

•   wrmsr
  

•   /* Enable cache (CR0.CD = 0, CR0.NW = 0) */
  

•    movl   %cr0, %eax
  

•   andl    $(~(X86_CR0_CD | X86_CR0_NW)), %eax
  

•   invd
  

•   movl    %eax, %cr0
  

•   /* enable the 'no eviction' mode */
  

•   movl    $NoEvictMod_MSR, %ecx
  

•   rdmsr
  

•   orl     $1, %eax
  

•   andl    $~2, %eax
  

•   wrmsr
  

•   /* Clear the cache memory region. This will also fill up the cache */
  

•   movl    $CACHE_AS_RAM_BASE, %esi
  

•   movl    %esi, %edi
  

•   movl    $(CACHE_AS_RAM_SIZE / 4), %ecx
  

•   xorl    %eax, %eax
  

•   rep     stosl
  

•   /* enable the 'no eviction run' state */
  

•   movl    $NoEvictMod_MSR, %ecx
  

•   rdmsr
  

•   orl     $3, %eax
  

•   wrmsr
  

•   post_code(POST_CAR_FILL)
  

•   /* Enable Cache-as-RAM mode by disabling cache */
  

•   movl    %cr0, %eax
  

•   orl     $X86_CR0_CD, %eax
  

•   movl    %eax, %cr0
  

•   /* Enable cache for our code in Flash because we do XIP here */
  

•   movl    $MTRRphysBase_MSR(1), %ecx
  

•   xorl    %edx, %edx
  

•   movl    $car_init_ret, %eax
  

•   andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
  

•   orl     $MTRR_TYPE_WRPROT, %eax
  

•   wrmsr
  

•   movl    $MTRRphysMask_MSR(1), %ecx
  

•   movl    $CPU_PHYSMASK_HI, %edx
  

•   movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
  

•   wrmsr
  

•   post_code(POST_CAR_ROM_CACHE)
  

+#ifdef CONFIG_CACHE_MRC_BIN

•   /* Enable caching for ram init code to run faster */
  

•   movl    $MTRRphysBase_MSR(2), %ecx
  

•   movl    $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
  

•   xorl    %edx, %edx
  

•   wrmsr
  

•   movl    $MTRRphysMask_MSR(2), %ecx
  

•   movl    $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
  

•   movl    $CPU_PHYSMASK_HI, %edx
  

•   wrmsr
  

+#endif

•   post_code(POST_CAR_MRC_CACHE)
  

•   /* Enable cache */
  

•   movl    %cr0, %eax
  

•   andl    $(~(X86_CR0_CD | X86_CR0_NW)), %eax
  

•   movl    %eax, %cr0
  

•   post_code(POST_CAR_CPU_CACHE)
  

•   /* return */
    jmp     car_init_ret
  

+mtrr_table:

•   /* Fixed MTRRs */
  

•   .word 0x250, 0x258, 0x259
  

•   .word 0x268, 0x269, 0x26A
  

•   .word 0x26B, 0x26C, 0x26D
  

•   .word 0x26E, 0x26F
  

•   /* Variable MTRRs */
  

•   .word 0x200, 0x201, 0x202, 0x203
  

•   .word 0x204, 0x205, 0x206, 0x207
  

•   .word 0x208, 0x209, 0x20A, 0x20B
  

•   .word 0x20C, 0x20D, 0x20E, 0x20F
  

•   .word 0x210, 0x211, 0x212, 0x213
  

+mtrr_table_end: diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 7e77be6..a9884ca 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -11,6 +11,7 @@ */

#include <common.h> +#include <asm/post.h> #include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR; @@ -19,6 +20,7 @@ int arch_cpu_init(void) { int ret;

•   post_code(POST_CPU_INIT);
    timer_set_base(rdtsc());
  
    ret = x86_cpu_init_f();
  

diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h new file mode 100644 index 0000000..5f05a48 --- /dev/null +++ b/arch/x86/include/asm/mtrr.h @@ -0,0 +1,121 @@ +/*

• • Copyright (c) 2014 Google, Inc
• • From Coreboot file of the same name
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef _ASM_MTRR_H +#define _ASM_MTRR_H

+/* These are the region types */ +#define MTRR_TYPE_UNCACHEABLE 0 +#define MTRR_TYPE_WRCOMB 1 +/*#define MTRR_TYPE_ 2*/ +/*#define MTRR_TYPE_ 3*/ +#define MTRR_TYPE_WRTHROUGH 4 +#define MTRR_TYPE_WRPROT 5 +#define MTRR_TYPE_WRBACK 6 +#define MTRR_NUM_TYPES 7

+#define MTRRcap_MSR 0x0fe +#define MTRRdefType_MSR 0x2ff

+#define MTRRdefTypeEn (1 << 11) +#define MTRRdefTypeFixEn (1 << 10)

+#define SMRRphysBase_MSR 0x1f2 +#define SMRRphysMask_MSR 0x1f3

+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)

+#define MTRRphysMaskValid (1 << 11)

+#define NUM_FIXED_RANGES 88 +#define RANGES_PER_FIXED_MTRR 8 +#define MTRRfix64K_00000_MSR 0x250 +#define MTRRfix16K_80000_MSR 0x258 +#define MTRRfix16K_A0000_MSR 0x259 +#define MTRRfix4K_C0000_MSR 0x268 +#define MTRRfix4K_C8000_MSR 0x269 +#define MTRRfix4K_D0000_MSR 0x26a +#define MTRRfix4K_D8000_MSR 0x26b +#define MTRRfix4K_E0000_MSR 0x26c +#define MTRRfix4K_E8000_MSR 0x26d +#define MTRRfix4K_F0000_MSR 0x26e +#define MTRRfix4K_F8000_MSR 0x26f

Ditto.

+#if !defined(__ASSEMBLER__)

+/*

• • The MTRR code has some side effects that the callers should be aware for.
• • 1. The call sequence matters. x86_setup_mtrrs() calls
• • x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent
• • of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers
• • want to call the components of x86_setup_mtrrs() because of other
• • rquirements the ordering should still preserved.
• • 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because
• • of the nature of the global MTRR enable flag. Therefore, all direct
• • or indirect callers of enable_fixed_mtrr() should ensure that the
• • variable MTRR MSRs do not contain bad ranges.
• • 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling
• • the caching of the ROM. However, it is set to uncacheable (UC). It
• • is the responsiblity of the caller to enable it by calling
• • x86_mtrr_enable_rom_caching().
• */

+void x86_setup_mtrrs(void); +/*

• • x86_setup_var_mtrrs() parameters:
• • address_bits - number of physical address bits supported by cpu
• • above4gb - 2 means dynamically detect number of variable MTRRs available.

• •        non-zero means handle memory ranges above 4GiB.
    

• •        0 means ignore memory ranges above 4GiB
    

• */

+void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); +void enable_fixed_mtrr(void); +void x86_setup_fixed_mtrrs(void); +/* Set up fixed MTRRs but do not enable them. */ +void x86_setup_fixed_mtrrs_no_enable(void); +int x86_mtrr_check(void); +/* ROM caching can be used after variable MTRRs are set up. Beware that

• • enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on
• • one's IO hole size and WRCOMB resources. Be sure to check the console
• • log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that
• • on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the
• • rom caching will be disabled if all threads run the MTRR code. Therefore,
• • one needs to call x86_mtrr_enable_rom_caching() after all threads of the
• • same core have run the MTRR code. */

+#if CONFIG_CACHE_ROM +void x86_mtrr_enable_rom_caching(void); +void x86_mtrr_disable_rom_caching(void); +/* Return the variable range MTRR index of the ROM cache. */ +long x86_mtrr_rom_cache_var_index(void); +#else +static inline void x86_mtrr_enable_rom_caching(void) {} +static inline void x86_mtrr_disable_rom_caching(void) {} +static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } +#endif /* CONFIG_CACHE_ROM */

+#endif

+#if !defined(CONFIG_RAMTOP) +# error "CONFIG_RAMTOP not defined" +#endif

+#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) +# error "CONFIG_XIP_ROM_SIZE is not a power of 2" +#endif

+#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) +# error "CONFIG_CACHE_ROM_SIZE is not a power of 2" +#endif

+#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)

+#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 +# error "CONFIG_RAMTOP must be a power of 2" +#endif

+#endif diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h index 3371185..b203dc9 100644 --- a/arch/x86/include/asm/post.h +++ b/arch/x86/include/asm/post.h @@ -13,9 +13,18 @@ /* post codes which represent various stages of init */ #define POST_START 0x1e #define POST_CAR_START 0x1f

+#define POST_CAR_SIPI 0x20 +#define POST_CAR_MTRR 0x21 +#define POST_CAR_UNCACHEABLE 0x22 +#define POST_CAR_BASE_ADDRESS 0x23 +#define POST_CAR_MASK 0x24 +#define POST_CAR_FILL 0x25 +#define POST_CAR_ROM_CACHE 0x26 +#define POST_CAR_MRC_CACHE 0x27 +#define POST_CAR_CPU_CACHE 0x28 #define POST_START_STACK 0x29 #define POST_START_DONE 0x2a +#define POST_CPU_INIT 0x2b

/* Output a post code using al - value must be 0 to 0xff */ #ifdef __ASSEMBLY__ @@ -23,6 +32,8 @@ movb $value, %al; \ outb %al, $POST_PORT #else +#include <asm/io.h>

static inline void post_code(int code) { outb(code, POST_PORT); diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 9c715ba..3a4f557 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -12,6 +12,18 @@ config SYS_SOC config SYS_CONFIG_NAME default "chromebook_link"

+config BOARD_SPECIFIC_OPTIONS # dummy

•   def_bool y
  

•   select CPU_INTEL_SOCKET_RPGA989
  

•   select NORTHBRIDGE_INTEL_IVYBRIDGE
  

•   select SOUTHBRIDGE_INTEL_C216
  

•   select HAVE_ACPI_RESUME
  

•   select MARK_GRAPHICS_MEM_WRCOMB
  

+config MMCONF_BASE_ADDRESS

•   hex
  

•   default 0xf0000000
  

config EARLY_POST_CROS_EC bool "Enable early post to Chrome OS EC" default y --

Regards, Bin

Hi Bin,

On 6 November 2014 17:07, Bin Meng bmeng.cn@gmail.com wrote:

Hi Simon,

On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass sjg@chromium.org wrote:

...

This code is not really Coreboot-specific, so move it into the common area and rename it.

OK, but current coreboot pci codes are broken, thus need to be fixed before making it common.

...

Signed-off-by: Simon Glass sjg@chromium.org

arch/x86/cpu/Makefile | 1 + arch/x86/cpu/coreboot/Makefile | 1 - arch/x86/cpu/{coreboot => }/pci.c | 24 +++++++++++++----------- 3 files changed, 14 insertions(+), 12 deletions(-) rename arch/x86/cpu/{coreboot => }/pci.c (63%)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 9d38ef7..97f36d5 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -11,3 +11,4 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o obj-y += interrupts.o cpu.o call64.o +obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index cd0bf4e..65cf2cb 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -19,4 +19,3 @@ obj-$(CONFIG_SYS_COREBOOT) += tables.o obj-$(CONFIG_SYS_COREBOOT) += ipchecksum.o obj-$(CONFIG_SYS_COREBOOT) += sdram.o obj-$(CONFIG_SYS_COREBOOT) += timestamp.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/pci.c similarity index 63% rename from arch/x86/cpu/coreboot/pci.c rename to arch/x86/cpu/pci.c index 33f16a3..f35c8b3 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/pci.c @@ -13,7 +13,7 @@ #include <pci.h> #include <asm/pci.h>

-static struct pci_controller coreboot_hose; +static struct pci_controller x86_hose;

static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *table) @@ -24,7 +24,7 @@ static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, pci_hose_scan_bus(hose, secondary); }

-static struct pci_config_table pci_coreboot_config_table[] = { +static struct pci_config_table pci_x86_config_table[] = { /* vendor, device, class, bus, dev, func */ { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, @@ -33,17 +33,19 @@ static struct pci_config_table pci_coreboot_config_table[] = {

Use this config_table will cause infinite loop when doing pci_hose_scan later. I do not use config_table on my Crown Bay port, instead using CONFIG_PCI_PNP which works very well.

OK, so are you saying that we should leave this separate for each board?

...

void pci_init_board(void) {

•   coreboot_hose.config_table = pci_coreboot_config_table;
  

•   coreboot_hose.first_busno = 0;
  

•   coreboot_hose.last_busno = 0;
  

•   struct pci_controller *hose = &x86_hose;
  
  

•   pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
  

•           PCI_REGION_MEM);
  

•   coreboot_hose.region_count = 1;
  

•   hose->config_table = pci_x86_config_table;
  

•   hose->first_busno = 0;
  

•   hose->last_busno = 0;
  
  

•   pci_setup_type1(&coreboot_hose);
  

•   pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff,
  

•                  PCI_REGION_MEM);
  

•   hose->region_count = 1;
  

There are 3 issues with the pci_set_region here: 1). The whole 4GiB PCI memory region creats conflicts with the systeam RAM memory map. This is a programming effor and normally causes undefined behaviour from chipset perspective. 2). There is no IO region configured, that means any device behind the PCI/PCIe bridge with only IO bar will fail to work. 3). There is no systeam RAM region configured, that means any device driver behind the PCI/PCIe bridge will fail to create pci addr <-> cpu physical addr mappings.

Actually this is not real setup - for the coreboot case it is scan-only, there is no memory or I/O allocation going on.

...

•   pci_register_hose(&coreboot_hose);
  

•   pci_setup_type1(hose);
  
  

•   pci_hose_scan(&coreboot_hose);
  

•   pci_register_hose(hose);
  

•   pci_hose_scan(hose);
  

}

Regards, Bin

Regards, Simon

Hi Bin,

On 6 November 2014 18:39, Bin Meng bmeng.cn@gmail.com wrote:

Hi Simon,

On Fri, Nov 7, 2014 at 8:26 AM, Simon Glass sjg@chromium.org wrote:

...

Hi Bin,

On 6 November 2014 17:07, Bin Meng bmeng.cn@gmail.com wrote:

...

Hi Simon,

...

-static struct pci_config_table pci_coreboot_config_table[] = { +static struct pci_config_table pci_x86_config_table[] = { /* vendor, device, class, bus, dev, func */ { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, @@ -33,17 +33,19 @@ static struct pci_config_table pci_coreboot_config_table[] = {

Use this config_table will cause infinite loop when doing pci_hose_scan later. I do not use config_table on my Crown Bay port, instead using CONFIG_PCI_PNP which works very well.

OK, so are you saying that we should leave this separate for each board?

Not really. But we can make this code really generic. So far it is broken.

I think the issue is that booting from Coreboot is quite a different use case from everything else.

...

...

...

void pci_init_board(void) {

•   coreboot_hose.config_table = pci_coreboot_config_table;
  

•   coreboot_hose.first_busno = 0;
  

•   coreboot_hose.last_busno = 0;
  

•   struct pci_controller *hose = &x86_hose;
  
  

•   pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
  

•           PCI_REGION_MEM);
  

•   coreboot_hose.region_count = 1;
  

•   hose->config_table = pci_x86_config_table;
  

•   hose->first_busno = 0;
  

•   hose->last_busno = 0;
  
  

•   pci_setup_type1(&coreboot_hose);
  

•   pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff,
  

•                  PCI_REGION_MEM);
  

•   hose->region_count = 1;
  

There are 3 issues with the pci_set_region here: 1). The whole 4GiB PCI memory region creats conflicts with the systeam RAM memory map. This is a programming effor and normally causes undefined behaviour from chipset perspective. 2). There is no IO region configured, that means any device behind the PCI/PCIe bridge with only IO bar will fail to work. 3). There is no systeam RAM region configured, that means any device driver behind the PCI/PCIe bridge will fail to create pci addr <-> cpu physical addr mappings.

Actually this is not real setup - for the coreboot case it is scan-only, there is no memory or I/O allocation going on.

OK, so if U-Boot boots from coreboot, the issue #1 and #2 disappear because coreboot has already enumerated the buses and devices and have memory/io allocation setup. That's fine. But this code is assumed to be used in U-Boot without coreboot too, thus U-Boot has to do the same thing as coreboot. And in the latter case, issue #1 and #2 do matter. About the issue #3, even when U-Boot is booting from coreboot, the system RAM region still needs to be set up otherwise you won't get any PCI device driver in U-Boot work. You can try adding CONFIG_E1000 to test an Intel Pro/1000 NIC in U-Boot and see what's happening.

If I do that, then Coreboot will find the device and allocate space for it, then U-Boot will juts use the allocated space.

Actually I think the region is completely misleading in the Coreboot case and should juts be remove.

Issue 3 is not a problem either I think, since again Coreboot will allocate it.

Regards, Simon

Hi Bin,

On 6 November 2014 19:12, Bin Meng bmeng.cn@gmail.com wrote:

Hi Simon,

On Fri, Nov 7, 2014 at 9:53 AM, Simon Glass sjg@chromium.org wrote:

...

Hi Bin,

On 6 November 2014 18:39, Bin Meng bmeng.cn@gmail.com wrote:

...

Hi Simon,

On Fri, Nov 7, 2014 at 8:26 AM, Simon Glass sjg@chromium.org wrote:

...

Hi Bin,

On 6 November 2014 17:07, Bin Meng bmeng.cn@gmail.com wrote:

...

Hi Simon,

...

-static struct pci_config_table pci_coreboot_config_table[] = { +static struct pci_config_table pci_x86_config_table[] = { /* vendor, device, class, bus, dev, func */ { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, @@ -33,17 +33,19 @@ static struct pci_config_table pci_coreboot_config_table[] = {

Use this config_table will cause infinite loop when doing pci_hose_scan later. I do not use config_table on my Crown Bay port, instead using CONFIG_PCI_PNP which works very well.

OK, so are you saying that we should leave this separate for each board?

Not really. But we can make this code really generic. So far it is broken.

I think the issue is that booting from Coreboot is quite a different use case from everything else.

We can use #ifdef CONFIG_SYS_COREBOOT in avoid re-allocating memory resources in U-Boot.

Hmm in that case I'd rather keep the files separate, since I'd like to minimise the use of #ifdef.

Can we just leave off CONFIG_PCI_PNP?

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void pci_init_board(void) {

•   coreboot_hose.config_table = pci_coreboot_config_table;
  

•   coreboot_hose.first_busno = 0;
  

•   coreboot_hose.last_busno = 0;
  

•   struct pci_controller *hose = &x86_hose;
  
  

•   pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
  

•           PCI_REGION_MEM);
  

•   coreboot_hose.region_count = 1;
  

•   hose->config_table = pci_x86_config_table;
  

•   hose->first_busno = 0;
  

•   hose->last_busno = 0;
  
  

•   pci_setup_type1(&coreboot_hose);
  

•   pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff,
  

•                  PCI_REGION_MEM);
  

•   hose->region_count = 1;
  

There are 3 issues with the pci_set_region here: 1). The whole 4GiB PCI memory region creats conflicts with the systeam RAM memory map. This is a programming effor and normally causes undefined behaviour from chipset perspective. 2). There is no IO region configured, that means any device behind the PCI/PCIe bridge with only IO bar will fail to work. 3). There is no systeam RAM region configured, that means any device driver behind the PCI/PCIe bridge will fail to create pci addr <-> cpu physical addr mappings.

Actually this is not real setup - for the coreboot case it is scan-only, there is no memory or I/O allocation going on.

OK, so if U-Boot boots from coreboot, the issue #1 and #2 disappear because coreboot has already enumerated the buses and devices and have memory/io allocation setup. That's fine. But this code is assumed to be used in U-Boot without coreboot too, thus U-Boot has to do the same thing as coreboot. And in the latter case, issue #1 and #2 do matter. About the issue #3, even when U-Boot is booting from coreboot, the system RAM region still needs to be set up otherwise you won't get any PCI device driver in U-Boot work. You can try adding CONFIG_E1000 to test an Intel Pro/1000 NIC in U-Boot and see what's happening.

If I do that, then Coreboot will find the device and allocate space for it, then U-Boot will juts use the allocated space.

Yes, I understand this.

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Actually I think the region is completely misleading in the Coreboot case and should juts be remove.

I am not sure if memory and IO can be removed completely for the coreboot case. I will need look into the pci.c/pci_auto.c and PCI device driver to confirm.

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Issue 3 is not a problem either I think, since again Coreboot will allocate it.

No, it does matter for coreboot. If the pci hose does not have the system RAM region setup, the pci_mem_to_phys will fail when PCI device driver wants to do DMA to RAM.

Good point, that is not supported at present.

So perhaps we should always set up suitable memory/I/O/bus-master regions and for Coreboot they will just not be used.

Regards, Simon