ping.

On Mon, Sep 30, 2013 at 4:50 PM, Ajay Kumar ajaykumar.rs@samsung.comwrote:

Previously, we used to statically assign values for vl_col, vl_row and vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.

Introducing the function exynos_lcd_early_init() would take care of this assignment on the fly by parsing FIMD DT properties, thereby allowing us to remove LCD_XRES and LCD_YRES from the main config file.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com

arch/arm/include/asm/arch-exynos/system.h | 1 + board/samsung/common/board.c | 15 +++++++++++++++ drivers/video/exynos_fb.c | 20 ++++++-------------- include/configs/exynos5250-dt.h | 2 -- 4 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index 7e2057c..4968d3d 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -39,5 +39,6 @@ struct exynos5_sysreg {

void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); +int exynos_lcd_early_init(const void *blob);

#endif /* _EXYNOS4_SYSTEM_H */ diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index ce85ddb..ae89c94 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -17,6 +17,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/power.h> +#include <asm/arch/system.h> #include <power/pmic.h> #include <power/max77686_pmic.h>

@@ -130,6 +131,20 @@ int board_early_init_f(void) #ifdef CONFIG_SYS_I2C_INIT_BOARD board_i2c_init(gd->fdt_blob); #endif

+#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB) +/*

• • board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
• • panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve
• • FB memory at a very early stage. So, we need to fill panel_info.vl_col,
• • panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called.
• */

•   err = exynos_lcd_early_init(gd->fdt_blob);
  

•   if (err) {
  

•           debug("LCD early init failed\n");
  

•           return err;
  

•   }
  

+#endif return err; } #endif diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 5c7ec91..686870f 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -27,17 +27,12 @@ DECLARE_GLOBAL_DATA_PTR;

static unsigned int panel_width, panel_height;

-/*

• • board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
• • panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
• • FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
• • is called. So, we are forced to statically assign it.
• */

#ifdef CONFIG_OF_CONTROL vidinfo_t panel_info = {

•   .vl_col = LCD_XRES,
  

•   .vl_row = LCD_YRES,
  

•   .vl_bpix = LCD_COLOR16,
  

•   /* Insert a value here so that we don't end up in the BSS
  

•    * Reference: drivers/video/tegra.c
  

•    */
  

•   .vl_col = -1,
  

}; #endif

@@ -159,7 +154,7 @@ static void lcd_panel_on(vidinfo_t *vid) }

#ifdef CONFIG_OF_CONTROL -int exynos_fimd_parse_dt(const void *blob) +int exynos_lcd_early_init(const void *blob) { unsigned int node; node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD); @@ -303,10 +298,7 @@ void lcd_ctrl_init(void *lcdbase) set_system_display_ctrl(); set_lcd_clk();

-#ifdef CONFIG_OF_CONTROL

•   if (exynos_fimd_parse_dt(gd->fdt_blob))
  

•           debug("Can't get proper panel info\n");
  

-#else +#ifndef CONFIG_OF_CONTROL /* initialize parameters which is specific to panel. */ init_panel_info(&panel_info); #endif diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 689919d..508962c 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -50,8 +50,6 @@ #ifdef CONFIG_LCD #define CONFIG_EXYNOS_FB #define CONFIG_EXYNOS_DP -#define LCD_XRES 2560 -#define LCD_YRES 1600 #define LCD_BPP LCD_COLOR16 #endif

#endif /* __CONFIG_5250_H */

1.7.12.4

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On Mon, Sep 30, 2013 at 4:50 PM, Ajay Kumar ajaykumar.rs@samsung.comwrote:

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com

arch/arm/cpu/armv7/exynos/clock.c | 74 +++++++++++++++++++++++++++++-- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/include/asm/arch-exynos/clk.h | 1 + 3 files changed, 73 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index bc06995..e953ddc 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) * VPLL_CON: MIDV [24:16] * BPLL_CON: MIDV [25:16]: Exynos5 */

•   if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
  

•   if (pllreg == APLL || pllreg == MPLL ||
  

•                                   pllreg == BPLL || pllreg == SPLL)
            mask = 0x3ff;
    else
            mask = 0x1ff;
  

@@ -388,6 +389,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg) r = readl(&clk->rpll_con0); k = readl(&clk->rpll_con1); break;

•   case SPLL:
  

•           r = readl(&clk->spll_con0);
  

•           break;
    default:
            printf("Unsupported PLL (%d)\n", pllreg);
            return 0;
  

@@ -1035,6 +1039,40 @@ static unsigned long exynos5_get_lcd_clk(void) return pclk; }

+static unsigned long exynos5420_get_lcd_clk(void) +{

•   struct exynos5420_clock *clk =
  

•           (struct exynos5420_clock *)samsung_get_base_clock();
  

•   unsigned long pclk, sclk;
  

•   unsigned int sel;
  

•   unsigned int ratio;
  

•   /*
  

•    * CLK_SRC_DISP10
  

•    * FIMD1_SEL [4]
  

•    * 0: SCLK_RPLL
  

•    * 1: SCLK_SPLL
  

•    */
  

•   sel = readl(&clk->src_disp10);
  

•   sel &= (1 << 4);
  

•   if (sel)
  

•           sclk = get_pll_clk(SPLL);
  

•   else
  

•           sclk = get_pll_clk(RPLL);
  

•   /*
  

•    * CLK_DIV_DISP10
  

•    * FIMD1_RATIO [3:0]
  

•    */
  

•   ratio = readl(&clk->div_disp10);
  

•   ratio = ratio & 0xf;
  

•   pclk = sclk / (ratio + 1);
  

•   return pclk;
  

+}

void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1159,6 +1197,33 @@ void exynos5_set_lcd_clk(void) writel(cfg, &clk->div_disp1_0); }

+void exynos5420_set_lcd_clk(void) +{

•   struct exynos5420_clock *clk =
  

•           (struct exynos5420_clock *)samsung_get_base_clock();
  

•   unsigned int cfg;
  

•   /*
  

•    * CLK_SRC_DISP10
  

•    * FIMD1_SEL [4]
  

•    * 0: SCLK_RPLL
  

•    * 1: SCLK_SPLL
  

•    */
  

•   cfg = readl(&clk->src_disp10);
  

•   cfg &= ~(0x1 << 4);
  

•   cfg |= (0 << 4);
  

•   writel(cfg, &clk->src_disp10);
  

•   /*
  

•    * CLK_DIV_DISP10
  

•    * FIMD1_RATIO          [3:0]
  

•    */
  

•   cfg = readl(&clk->div_disp10);
  

•   cfg &= ~(0xf << 0);
  

•   cfg |= (0 << 0);
  

•   writel(cfg, &clk->div_disp10);
  

+}

void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1628,14 +1693,17 @@ unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) return exynos4_get_lcd_clk();

•   else
  

•           return exynos5_get_lcd_clk();
  

•   else if (proid_is_exynos5420())
  

•           return exynos5420_get_lcd_clk();
  

•   return exynos5_get_lcd_clk();
  

}

void set_lcd_clk(void) { if (cpu_is_exynos4()) exynos4_set_lcd_clk();

•   else if (proid_is_exynos5420())
  

•           exynos5420_set_lcd_clk();
    else
            exynos5_set_lcd_clk();
  

} diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 8e05a00..70b1c04 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -780,7 +780,7 @@ #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 #define CLK_SRC_TOP4_VAL 0x11110111 -#define CLK_SRC_TOP5_VAL 0x11111100 +#define CLK_SRC_TOP5_VAL 0x11111101 #define CLK_SRC_TOP6_VAL 0x11110111 #define CLK_SRC_TOP7_VAL 0x00022200

diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index abce246..f0b4d70 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -15,6 +15,7 @@ #define VPLL 4 #define BPLL 5 #define RPLL 6 +#define SPLL 7

enum pll_src_bit { EXYNOS_SRC_MPLL = 6, -- 1.7.12.4

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On Mon, Sep 30, 2013 at 4:50 PM, Ajay Kumar ajaykumar.rs@samsung.comwrote:

Add callbacks to set up DP-HPD, backlight and LCD power on SMDK5420.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com

board/samsung/smdk5420/smdk5420.c | 118 +++++++++++--------------------------- 1 file changed, 34 insertions(+), 84 deletions(-)

diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index cf76455..3f29ce0 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -137,98 +137,48 @@ int board_mmc_init(bd_t *bis) #endif

#ifdef CONFIG_LCD -void cfg_lcd_gpio(void) +void exynos_cfg_lcd_gpio(void) {

•   struct exynos5_gpio_part1 *gpio1 =
  

•           (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
  

•   struct exynos5420_gpio_part2 *gpio2 =
  

•           (struct exynos5420_gpio_part2
  

*)samsung_get_base_gpio_part2();

•   /* For Backlight */
  

•   /* Set Hotplug detect for DP */
  

•   s5p_gpio_cfg_pin(&gpio2->x0, 7, GPIO_FUNC(0x3));
  

+}

+void exynos_backlight_on(unsigned int onoff) +{

•   struct exynos5420_gpio_part1 *gpio1 =
  

•           (struct exynos5420_gpio_part1
  

*)samsung_get_base_gpio_part1();

•   struct exynos5420_gpio_part2 *gpio2 =
  

•           (struct exynos5420_gpio_part2
  

*)samsung_get_base_gpio_part2();

•   /* For PWM */
    s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
    s5p_gpio_set_value(&gpio1->b2, 0, 1);
  
  

•   /* LCD power on */
  

•   s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
  

•   s5p_gpio_set_value(&gpio1->x1, 5, 1);
  

•   /* Set Hotplug detect for DP */
  

•   s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
  

•   /* BL_EN */
  

•   s5p_gpio_cfg_pin(&gpio2->x1, 5, GPIO_OUTPUT);
  

•   s5p_gpio_set_value(&gpio2->x1, 5, 1);
  

}

-vidinfo_t panel_info = {

•   .vl_freq        = 60,
  

•   .vl_col         = 2560,
  

•   .vl_row         = 1600,
  

•   .vl_width       = 2560,
  

•   .vl_height      = 1600,
  

•   .vl_clkp        = CONFIG_SYS_LOW,
  

•   .vl_hsp         = CONFIG_SYS_LOW,
  

•   .vl_vsp         = CONFIG_SYS_LOW,
  

•   .vl_dp          = CONFIG_SYS_LOW,
  

•   .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on
  

LCD */

•   /* wDP panel timing infomation */
  

•   .vl_hspw        = 32,
  

•   .vl_hbpd        = 80,
  

•   .vl_hfpd        = 48,
  

•   .vl_vspw        = 6,
  

•   .vl_vbpd        = 37,
  

•   .vl_vfpd        = 3,
  

•   .vl_cmd_allow_len = 0xf,
  

•   .win_id         = 3,
  

•   .cfg_gpio       = cfg_lcd_gpio,
  

•   .backlight_on   = NULL,
  

•   .lcd_power_on   = NULL,
  

•   .reset_lcd      = NULL,
  

•   .dual_lcd_enabled = 0,
  

•   .init_delay     = 0,
  

•   .power_on_delay = 0,
  

•   .reset_delay    = 0,
  

•   .interface_mode = FIMD_RGB_INTERFACE,
  

•   .dp_enabled     = 1,
  

-};

-static struct edp_device_info edp_info = {

•   .disp_info = {
  

•           .h_res = 2560,
  

•           .h_sync_width = 32,
  

•           .h_back_porch = 80,
  

•           .h_front_porch = 48,
  

•           .v_res = 1600,
  

•           .v_sync_width  = 6,
  

•           .v_back_porch = 37,
  

•           .v_front_porch = 3,
  

•           .v_sync_rate = 60,
  

•   },
  

•   .lt_info = {
  

•           .lt_status = DP_LT_NONE,
  

•   },
  

•   .video_info = {
  

•           .master_mode = 0,
  

•           .bist_mode = DP_DISABLE,
  

•           .bist_pattern = NO_PATTERN,
  

•           .h_sync_polarity = 0,
  

•           .v_sync_polarity = 0,
  

•           .interlaced = 0,
  

•           .color_space = COLOR_RGB,
  

•           .dynamic_range = VESA,
  

•           .ycbcr_coeff = COLOR_YCBCR601,
  

•           .color_depth = COLOR_8,
  

•   },
  

-};

-static struct exynos_dp_platform_data dp_platform_data = {

•   .phy_enable     = set_dp_phy_ctrl,
  

•   .edp_dev_info   = &edp_info,
  

-};

-void init_panel_info(vidinfo_t *vid) +void exynos_lcd_power_on(void) {

•   vid->rgb_mode   = MODE_RGB_P,
  

•   exynos_set_dp_platform_data(&dp_platform_data);
  

•   int pmic_bus, pmic_i2caddr, ldo38_reg, old_bus;
  

•   u8 value;
  

•   /* enable VDD_28IO_DP: LDO38 should be at 2.8V */
  

•   pmic_bus = 4;
  

•   pmic_i2caddr = 0x66;
  

•   ldo38_reg = 0x62;
  

•   value = 0x78;
  

•   old_bus = i2c_get_bus_num();
  

•   i2c_set_bus_num(pmic_bus);
  

•   if (i2c_write(pmic_i2caddr, ldo38_reg, 1, &value, 1))
  

•           printf("i2c write fail. Failed to enable VDD_28IO_DP\n");
  

•   i2c_set_bus_num(old_bus);
  

} #endif

-- 1.7.12.4

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